Lines Matching refs:Hexagon
44 #include "Hexagon.h"
84 return "Hexagon Packetizer";
174 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
180 INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
268 return ((MI->getOpcode() == Hexagon::CALLR) ||
269 (MI->getOpcode() == Hexagon::CALLRv3));
277 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
295 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
307 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
342 if (RC == &Hexagon::PredRegsRegClass) {
370 return (MI->getOpcode() == Hexagon::JMP);
375 case Hexagon::BARRIER:
386 return (MI->getOpcode() == Hexagon::LOOP0_i ||
387 MI->getOpcode() == Hexagon::LOOP0_r);
439 if (RC == &Hexagon::PredRegsRegClass)
567 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
568 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
572 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
614 if (predRegClass == &Hexagon::PredRegsRegClass) {
618 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
626 if (predRegClass == &Hexagon::PredRegsRegClass) {
630 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
763 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
765 else if (RC != &Hexagon::PredRegsRegClass &&
852 Hexagon::PredRegsRegClass.contains(Op.getReg()))
912 Hexagon::PredRegsRegClass.contains(
937 Hexagon::PredRegsRegClass.contains(PReg1) &&
938 Hexagon::PredRegsRegClass.contains(PReg2) &&
985 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
1014 if (I->getOpcode() == Hexagon::INLINEASM)
1121 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
1285 && J->getOpcode() == Hexagon::ALLOCFRAME
1286 && (I->getOpcode() == Hexagon::STrid
1287 || I->getOpcode() == Hexagon::STriw
1288 || I->getOpcode() == Hexagon::STrib)