Cross Reference: /external/qemu/hw/mips

Lines Matching defs:env
8 uint32_t cpu_mips_get_random (CPUState *env)
16         idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
23 uint32_t cpu_mips_get_count (CPUState *env)
25     if (env->CP0_Cause & (1 << CP0Ca_DC))
26         return env->CP0_Count;
28         return env->CP0_Count +
33 static void cpu_mips_timer_update(CPUState *env)
39     wait = env->CP0_Compare - env->CP0_Count -
42     qemu_mod_timer(env->timer, next);
45 void cpu_mips_store_count (CPUState *env, uint32_t count)
47     if (env->CP0_Cause & (1 << CP0Ca_DC))
48         env->CP0_Count = count;
51         env->CP0_Count =
55         cpu_mips_timer_update(env);
59 void cpu_mips_store_compare (CPUState *env, uint32_t value)
61     env->CP0_Compare = value;
62     if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
63         cpu_mips_timer_update(env);
64     if (env->insn_flags & ISA_MIPS32R2)
65         env->CP0_Cause &= ~(1 << CP0Ca_TI);
66     qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
69 void cpu_mips_start_count(CPUState *env)
71     cpu_mips_store_count(env, env->CP0_Count);
74 void cpu_mips_stop_count(CPUState *env)
77     env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock),
83     CPUState *env;
85     env = opaque;
90     if (env->CP0_Cause & (1 << CP0Ca_DC))
96     env->CP0_Count++;
97     cpu_mips_timer_update(env);
98     env->CP0_Count--;
99     if (env->insn_flags & ISA_MIPS32R2)
100         env->CP0_Cause |= 1 << CP0Ca_TI;
101     qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
104 void cpu_mips_clock_init (CPUState *env)
106     env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
107     env->CP0_Compare = 0;
108     cpu_mips_store_count(env, 1);