Cross Reference: /external/valgrind/main/VEX/priv/guest_arm

Lines Matching defs:dD
10962       UInt dD      = (INSN(22,22) << 4) | INSN(15,12);
10987       if (dD + nRegs - 1 >= 32)
11034             putDReg(dD + i, loadLE(Ity_F64, addr), IRTemp_INVALID);
11036             storeLE(addr, getDReg(dD + i));
11053                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
11056                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
11059                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
11099       UInt dD      = (INSN(22,22) << 4) | INSN(15,12);
11124       if (dD + nRegs - 1 >= 32)
11171             putDReg(dD + i, loadLE(Ity_F64, addr), IRTemp_INVALID);
11173             storeLE(addr, getDReg(dD + i));
11190                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
11193                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
11196                       nm, nCC(conq), rN, dD, dD + nRegs - 1);
11460    // VMOV.F64 dD, #imm
11461    // FCONSTD dD, #imm
11477    // VDUP dD, rT
11533       UInt dD     = INSN(15,12) | (INSN(22,22) << 4);
11552          putDReg(dD, loadLE(Ity_F64,mkexpr(ea)), IRTemp_INVALID);
11554          storeLE(mkexpr(ea), getDReg(dD));
11557           bL ? "ld" : "st", nCC(conq), dD, rN,
11567       UInt    dD  = INSN(15,12) | (INSN(22,22) << 4);   /* dst/acc */
11577             putDReg(dD, triop(Iop_AddF64, rm,
11578                               getDReg(dD),
11582             DIP("fmacd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11585             putDReg(dD, triop(Iop_AddF64, rm,
11586                               getDReg(dD),
11591             DIP("fnmacd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11594             putDReg(dD, triop(Iop_AddF64, rm,
11595                               unop(Iop_NegF64, getDReg(dD)),
11599             DIP("fmscd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11602             putDReg(dD, triop(Iop_AddF64, rm,
11603                               unop(Iop_NegF64, getDReg(dD)),
11608             DIP("fnmscd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11611             putDReg(dD, triop(Iop_MulF64, rm, getDReg(dN), getDReg(dM)),
11613             DIP("fmuld%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11616             putDReg(dD, unop(Iop_NegF64,
11620             DIP("fnmuld%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11623             putDReg(dD, triop(Iop_AddF64, rm, getDReg(dN), getDReg(dM)),
11625             DIP("faddd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11628             putDReg(dD, triop(Iop_SubF64, rm, getDReg(dN), getDReg(dM)),
11630             DIP("fsubd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11633             putDReg(dD, triop(Iop_DivF64, rm, getDReg(dN), getDReg(dM)),
11635             DIP("fdivd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
11664       UInt dD = INSN(15,12) | (INSN(22,22) << 4);
11672          assign(argL, getDReg(dD));
11705             DIP("fcmpz%sd%s d%u\n", bN ? "e" : "", nCC(conq), dD);
11707             DIP("fcmp%sd%s d%u, d%u\n", bN ? "e" : "", nCC(conq), dD, dM);
11719       UInt dD  = INSN(15,12) | (INSN(22,22) << 4);
11725          putDReg(dD, getDReg(dM), condT);
11726          DIP("fcpyd%s d%u, d%u\n", nCC(conq), dD, dM);
11731          putDReg(dD, unop(Iop_AbsF64, getDReg(dM)), condT);
11732          DIP("fabsd%s d%u, d%u\n", nCC(conq), dD, dM);
11737          putDReg(dD, unop(Iop_NegF64, getDReg(dM)), condT);
11738          DIP("fnegd%s d%u, d%u\n", nCC(conq), dD, dM);
11744          putDReg(dD, binop(Iop_SqrtF64, rm, getDReg(dM)), condT);
11745          DIP("fsqrtd%s d%u, d%u\n", nCC(conq), dD, dM);
11756    // F{S,U}ITOD dD, fM
11763       UInt dD    = INSN(15,12) | (INSN(22,22) << 4);
11767          putDReg(dD, unop(Iop_I32StoF64,
11770          DIP("fsitod%s d%u, s%u\n", nCC(conq), dD, fM);
11773          putDReg(dD, unop(Iop_I32UtoF64,
11776          DIP("fuitod%s d%u, s%u\n", nCC(conq), dD, fM);
12306       UInt dD = INSN(15,12) | (INSN(22,22) << 4);
12309       putDReg(dD, unop(Iop_F32toF64, getFReg(fM)), condT);
12310       DIP("fcvtds%s d%u, s%u\n", nCC(conq), dD, fM);