| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCFGOptimizer.cpp | 75 int NewOpcode = 0; local
78 NewOpcode = Hexagon::JMP_f;
82 NewOpcode = Hexagon::JMP_t;
86 NewOpcode = Hexagon::JMP_fnew_t;
90 NewOpcode = Hexagon::JMP_tnew_t;
97 MI->setDesc(QII->get(NewOpcode));
|
| H A D | HexagonVLIWPacketizer.cpp | 438 int NewOpcode; local
440 NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
442 NewOpcode = QII->GetDotNewOp(MI);
443 MI->setDesc(QII->get(NewOpcode));
450 int NewOpcode = QII->GetDotOldOp(MI->getOpcode()); local
451 MI->setDesc(QII->get(NewOpcode));
771 int NewOpcode = QII->GetDotNewOp(MI); local
772 const MCInstrDesc &desc = QII->get(NewOpcode);
|
| H A D | HexagonInstrInfo.cpp | 1581 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); local
1582 if (NewOpcode >= 0) // Valid predicate new instruction
1583 return NewOpcode;
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreRegisterInfo.cpp | 219 int NewOpcode; local
221 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
222 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
226 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
227 BuildMI(MBB, II, dl, TII.get(NewOpcode))
232 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
233 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
|
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZFrameLowering.cpp | 436 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); local
440 if (!NewOpcode) {
445 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
446 assert(NewOpcode && "No restore instruction available");
449 MBBI->setDesc(ZII->get(NewOpcode));
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| H A D | SystemZInstrInfo.cpp | 37 // each having the opcode given by NewOpcode.
39 unsigned NewOpcode) const {
61 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
62 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
79 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); local
80 assert(NewOpcode && "No support for huge argument lists yet");
81 MI->setDesc(get(NewOpcode));
503 unsigned NewOpcode; local
505 NewOpcode = SystemZ::RISBG;
507 NewOpcode
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 260 unsigned NewOpcode = 0; local
267 NewOpcode = X86::CBW;
271 NewOpcode = X86::CWDE;
275 NewOpcode = X86::CDQE;
279 if (NewOpcode != 0) {
281 Inst.setOpcode(NewOpcode);
|
| H A D | X86InstrInfo.cpp | 3366 unsigned NewOpcode = 0; local
3389 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
3390 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
3391 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
3392 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
3393 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
3394 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
3395 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
3396 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
3397 case X86::SUB64ri32: NewOpcode
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCAsmPrinter.cpp | 672 unsigned NewOpcode = local
676 OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode)
686 unsigned NewOpcode = local
692 OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode)
|
| H A D | PPCRegisterInfo.cpp | 671 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; local
672 MI.setDesc(TII.get(NewOpcode));
|
| /external/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 1041 unsigned NewOpcode = N->getMachineOpcode(); local
1046 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1049 if (NewOpcode == N->getMachineOpcode()) {
1050 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1055 if (NewOpcode == N->getMachineOpcode()) {
1056 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1068 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
|
| H A D | AMDILCFGStructurizer.cpp | 224 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
226 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
228 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
229 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
232 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
234 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
465 int NewOpcode, DebugLoc DL) {
467 ->CreateMachineInstr(TII->get(NewOpcode), DL);
474 int NewOpcode, DebugLoc DL) {
476 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), D
464 insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, DebugLoc DL) argument
473 insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, DebugLoc DL) argument
485 insertInstrBefore( MachineBasicBlock::iterator I, int NewOpcode) argument
497 insertCondBranchBefore( MachineBasicBlock::iterator I, int NewOpcode, DebugLoc DL) argument
510 insertCondBranchBefore(MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, DebugLoc DL) argument
521 insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum) argument
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 1201 std::string NewOpcode; local
1204 NewOpcode = Name;
1205 NewOpcode += '+';
1206 Name = NewOpcode;
1210 NewOpcode = Name;
1211 NewOpcode += '-';
1212 Name = NewOpcode;
1218 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1226 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 3487 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local
3491 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3499 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local
3503 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
|