/external/llvm/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 89 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 90 MVT VT = Outs[i].VT; 91 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 103 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 104 MVT VT = Outs[i].VT; 105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 120 unsigned NumOps = Outs [all...] |
H A D | TargetLoweringBase.cpp | 1124 SmallVectorImpl<ISD::OutputArg> &Outs, 1165 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0)); 1123 GetReturnInfo(Type* ReturnType, AttributeSet attr, SmallVectorImpl<ISD::OutputArg> &Outs, const TargetLowering &TLI) argument
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.cpp | 94 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 116 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 117 EVT VT = Outs[i].VT; 118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 132 &Outs, 136 unsigned NumOps = Outs.size(); 147 EVT ArgVT = Outs[i].VT; 148 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 131 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, Hexagon_CCAssignFn Fn, int NonVarArgsParams, unsigned SretValueSize) argument
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H A D | HexagonISelLowering.cpp | 303 const SmallVectorImpl<ISD::OutputArg> &Outs, 315 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon); 386 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local 395 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 421 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg); 423 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon); 432 Outs, OutVals, Ins, DAG); 460 ISD::ArgFlagsTy Flags = Outs[ 301 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument 1669 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 68 const SmallVectorImpl<ISD::OutputArg> &Outs, 64 LowerReturn( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc DL, SelectionDAG &DAG) const argument
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 66 SmallVector<ISD::OutputArg, 4> Outs; local 67 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI); 70 Outs, Fn->getContext());
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H A D | SelectionDAGBuilder.cpp | 1192 SmallVector<ISD::OutputArg, 8> Outs; local 1200 // Leave Outs empty so that LowerReturn won't try to load return 1270 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1282 Outs, OutVals, getCurSDLoc(), 5230 SmallVector<ISD::OutputArg, 4> Outs; local 5232 GetReturnInfo(RetTy, CS.getAttributes(), Outs, *TLI); 5236 FTy->isVarArg(), Outs, 6453 CLI.Outs.clear(); 6538 CLI.Outs.push_back(MyFlags);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 68 const SmallVectorImpl<ISD::OutputArg> &Outs, 64 LowerReturn( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc DL, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 115 SmallVectorImpl<MachineInstr*> &Outs); 368 SmallVectorImpl<MachineInstr*> &Outs) { 402 Outs.push_back(MI); 367 elideCopiesAndPHIs(MachineInstr *MI, SmallVectorImpl<MachineInstr*> &Outs) argument
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H A D | ARMFastISel.cpp | 2111 SmallVector<ISD::OutputArg, 4> Outs; local 2112 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI); 2117 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */, 2152 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { 2153 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
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H A D | ARMISelLowering.cpp | 1400 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local 1411 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1421 Outs, OutVals, Ins, DAG); 1434 CCInfo.AnalyzeCallOperands(Outs, 1463 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1510 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) { 1920 const SmallVectorImpl<ISD::OutputArg> &Outs, 1933 if (isVarArg && !Outs 1915 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument 2054 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument 2065 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 161 const SmallVectorImpl<ISD::OutputArg> &Outs, 157 LowerReturn( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 282 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local 300 Outs, OutVals, Ins, dl, DAG, InVals); 410 const SmallVectorImpl<ISD::OutputArg> &Outs, 418 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) 426 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430); 465 &Outs, 475 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430); 524 ISD::ArgFlagsTy Flags = Outs[i].Flags; 408 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument 461 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 74 /// same number of types as the Ins/Outs arrays in LowerFormalArguments, 346 const SmallVectorImpl<ISD::OutputArg> &Outs, 417 if (Outs[OIdx].Flags.isByVal() == false) { 429 // update the index for Outs 437 assert((getValueType(Ty) == Outs[OIdx].VT || 438 (getValueType(Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) && 458 unsigned align = Outs[OIdx].Flags.getByValAlign(); 496 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local 521 // Args.size() and Outs 345 getPrototype(Type *retTy, const ArgListTy &Args, const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment, const ImmutableCallSite *CS) const argument 1670 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 165 const SmallVectorImpl<ISD::OutputArg> &Outs, 169 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 170 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 176 const SmallVectorImpl<ISD::OutputArg> &Outs, 189 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 239 const SmallVectorImpl<ISD::OutputArg> &Outs, 250 CCInfo.AnalyzeReturn(Outs, CC_Sparc64); 657 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local 673 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc3 163 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument 174 LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument 237 LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument 944 fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs, ArrayRef<ISD::OutputArg> Outs) argument [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 697 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local 714 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); 841 const SmallVectorImpl<ISD::OutputArg> &Outs, 849 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ); 839 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 755 SmallVector<ISD::OutputArg, 4> Outs; local 756 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI); 762 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 795 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) 801 if (Outs[0].Flags.isSExt()) 806 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : 1863 SmallVector<ISD::OutputArg, 4> Outs; 1864 GetReturnInfo(I->getType(), CS.getAttributes(), Outs, TLI); 1867 Outs, FT [all...] |
H A D | X86ISelLowering.cpp | 1762 const SmallVectorImpl<ISD::OutputArg> &Outs, 1767 return CCInfo.CheckReturn(Outs, RetCC_X86); 1773 const SmallVectorImpl<ISD::OutputArg> &Outs, 1782 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 2016 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { argument 2017 if (Outs.empty()) 2020 const ISD::ArgFlagsTy &Flags = Outs[0].Flags; 2473 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local 2486 StructReturnType SR = callIsStructReturn(Outs); 1760 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument 1771 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument 3019 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 853 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local 873 Outs, OutVals, Ins, dl, DAG, InVals); 885 const SmallVectorImpl<ISD::OutputArg> &Outs, 900 CCInfo.AnalyzeCallOperands(Outs, CC_XCore); 1235 const SmallVectorImpl<ISD::OutputArg> &Outs, 1239 return CCInfo.CheckReturn(Outs, RetCC_XCore); 1245 const SmallVectorImpl<ISD::OutputArg> &Outs, 1258 CCInfo.AnalyzeReturn(Outs, RetCC_XCore); 882 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1233 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument 1243 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1063 const SmallVectorImpl<ISD::OutputArg> &Outs, 1074 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv)); 1139 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local 1152 bool IsStructRet = !Outs.empty() && Outs[0].Flags.isSRet(); 1158 Outs, OutVals, Ins, DAG); 1169 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); 1215 ISD::ArgFlagsTy Flags = Outs[i].Flags; 1449 const SmallVectorImpl<ISD::OutputArg> &Outs, 1061 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument 1444 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg, bool IsCalleeStructRet, bool IsCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 2330 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local 2352 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, 2392 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2721 const SmallVectorImpl<ISD::OutputArg> &Outs, 2726 return CCInfo.CheckReturn(Outs, RetCC_Mips); 2732 const SmallVectorImpl<ISD::OutputArg> &Outs, 2746 MipsCCInfo.analyzeReturn(Outs, getTargetMachine().Options.UseSoftFloat, 3247 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat, argument 3249 analyzeReturn(Outs, IsSoftFloa 2719 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument 2730 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 2830 &Outs, 2837 unsigned NumOps = Outs.size(); 2848 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2849 EVT ArgVT = Outs[i].VT; 3481 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; local 3497 isTailCall, Outs, OutVals, Ins, 3501 isTailCall, Outs, OutVals, Ins, 3506 isTailCall, Outs, OutVals, Ins, 3514 const SmallVectorImpl<ISD::OutputArg> &Outs, 2825 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, bool isPPC64, bool isVarArg, unsigned CC, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, unsigned &nAltivecParamsAtEnd) argument 3511 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3746 LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 4118 LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 4467 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument 4478 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const argument [all...] |