| /external/smack/src/org/xbill/DNS/ |
| H A D | Flags.java | 29 public static final byte RA = 8; field in class:Flags
49 flags.add(RA, "ra");
|
| /external/clang/test/CodeGenCXX/ |
| H A D | devirtualize-virtual-function-calls-final.cpp | 164 struct RA { struct in namespace:Test9
169 struct RC final : public RA {
185 return static_cast<RA*>(x)->f();
|
| /external/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 43 const MCReadAdvanceEntry *RA,
54 ReadAdvanceTable = RA;
37 InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, const SubtargetFeatureKV *PF, const SubtargetFeatureKV *PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP, unsigned NF, unsigned NP) argument
|
| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16FrameLowering.cpp | 68 unsigned RA = MRI->getDwarfRegNum(Mips::RA, true); local
69 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, RA, -4));
107 // Registers RA, S0,S1 are the callee saved registers and they
113 // RA and return address is taken, because it has already been added in
115 // It's killed at the spill, unless the register is RA and return address
118 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
132 // Registers RA,S0,S1 are the callee saved registers and they will be restored
171 MF.getRegInfo().setPhysRegUsed(Mips::RA);
|
| H A D | MipsSEInstrInfo.cpp | 387 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
516 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA; local
528 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
532 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
|
| H A D | MipsISelLowering.cpp | 1837 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; local
1840 // Return RA, which contains the return address. Mark it an implicit live-in.
1841 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCMCTargetDesc.cpp | 48 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local
51 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 253 unsigned RA = (TheTriple.getArch() == Triple::x86_64) local
258 InitX86MCRegisterInfo(X, RA,
261 RA);
|
| /external/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 721 APInt RA = Rem->getValue().abs(); local
722 if (RA.isPowerOf2()) {
723 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
726 APInt LowBits = RA - 1;
|
| /external/llvm/lib/Transforms/IPO/ |
| H A D | DeadArgumentElimination.cpp | 158 void MarkValue(const RetOrArg &RA, Liveness L,
160 void MarkLive(const RetOrArg &RA);
162 void PropagateLiveness(const RetOrArg &RA);
638 /// MarkValue - This function marks the liveness of RA depending on L. If L is
640 /// such that RA will be marked live if any use in MaybeLiveUses gets marked
642 void DAE::MarkValue(const RetOrArg &RA, Liveness L, argument
645 case Live: MarkLive(RA); break;
652 Uses.insert(std::make_pair(*UI, RA));
677 void DAE::MarkLive(const RetOrArg &RA) { argument
678 if (LiveFunctions.count(RA
690 PropagateLiveness(const RetOrArg &RA) argument
[all...] |
| /external/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 239 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument
252 RAReg = RA;
|
| /external/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 548 APInt RA = Rem->getValue().abs(); local
549 if (RA.isPowerOf2()) {
550 APInt LowBits = RA - 1;
585 APInt RA = Rem->getValue(); local
586 if (RA.isPowerOf2()) {
587 APInt LowBits = (RA - 1);
|
| H A D | ScalarEvolution.cpp | 509 const Argument *RA = cast<Argument>(RV); local
510 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo();
544 const APInt &RA = RC->getValue()->getValue(); local
545 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth();
548 return LA.ult(RA) ? -1 : 1;
553 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS); local
556 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop();
565 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands();
571 long X = compare(LA->getOperand(i), RA->getOperand(i));
3889 const SCEV *RA
[all...] |
| /external/qemu/tcg/ppc/ |
| H A D | tcg-target.c | 397 #define RA(r) ((r)<<16) macro
407 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
408 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
449 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
451 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
461 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
464 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
493 tcg_out32 (s, LWZ | RT (0) | RA (reg));
494 tcg_out32 (s, MTSPR | RA (
[all...] |
| /external/qemu/tcg/ppc64/ |
| H A D | tcg-target.c | 394 #define RA(r) ((r)<<16) macro
405 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
406 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
453 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
455 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
477 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
478 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
521 tcg_out32 (s, LD | RT (0) | RA (re
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| H A D | LoopStrengthReduce.cpp | 477 const APInt &RA = RC->getValue()->getValue(); local
480 if (RA.isAllOnesValue())
483 if (RA == 1)
492 const APInt &RA = RC->getValue()->getValue(); local
493 if (LA.srem(RA) != 0)
495 return SE.getConstant(LA.sdiv(RA));
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 2054 const APInt &RA = Rem->getAPIntValue().abs(); local
2055 if (RA.isPowerOf2()) {
2056 APInt LowBits = RA - 1;
2079 const APInt &RA = Rem->getAPIntValue(); local
2080 if (RA.isPowerOf2()) {
2081 APInt LowBits = (RA - 1);
|
| /external/qemu/ |
| H A D | ppc-dis.c | 688 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
689 #define RA NSI + 1
693 /* As above, but 0 in the RA field means zero, not r0. */
694 #define RA0 RA + 1
697 /* The RA field in the DQ form lq instruction, which has special
702 /* The RA field in a D or X form instruction which is an updating
703 load, which means that the RA field may not be zero and may not
708 /* The RA field in an lmw instruction, which has special value
713 /* The RA field in a D or X form instruction which is an updating
714 store or an updating floating point load, which means that the RA
685 #define RA macro
[all...] |
| /external/robolectric/lib/main/ |
| H A D | sqlite-jdbc-3.7.2.jar | META-INF/ META-INF/MANIFEST.MF META-INF/maven/ META-INF/maven/org. ... |