Searched defs:Reg (Results 1 - 25 of 214) sorted by relevance

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/external/llvm/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { argument
31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
/external/llvm/include/llvm/MC/
H A DMCInstBuilder.h32 MCInstBuilder &addReg(unsigned Reg) { argument
33 Inst.addOperand(MCOperand::CreateReg(Reg));
H A DMCWin64EH.h36 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg) argument
37 : Operation(Op), Label(L), Offset(0), Register(Reg) {
43 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg, unsigned Off) argument
44 : Operation(Op), Label(L), Offset(Off), Register(Reg) {
/external/llvm/lib/CodeGen/
H A DAllocationOrder.h52 unsigned Reg = Order[Pos++]; local
53 if (!isHint(Reg))
54 return Reg;
H A DRegAllocBase.cpp71 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
72 if (MRI->reg_nodbg_empty(Reg))
74 enqueue(&LIS->getInterval(Reg));
H A DDeadMachineInstructionElim.cpp69 unsigned Reg = MO.getReg(); local
70 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
72 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
75 if (!MRI->use_nodbg_empty(Reg))
127 unsigned Reg = MO.getReg(); local
128 if (!TargetRegisterInfo::isVirtualRegister(Reg))
131 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
155 unsigned Reg = MO.getReg(); local
156 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
174 unsigned Reg = MO.getReg(); local
[all...]
H A DProcessImplicitDefs.cpp78 unsigned Reg = MI->getOperand(0).getReg(); local
80 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
84 MRI->use_nodbg_begin(Reg),
110 !TRI->regsOverlap(Reg, UserReg))
112 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
H A DCalcSpillWeights.cpp53 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
54 if (MRI.reg_nodbg_empty(Reg))
56 VRAI.CalculateWeightAndHint(LIS.getInterval(Reg));
H A DCallingConvLower.cpp59 void CCState::MarkAllocated(unsigned Reg) { argument
60 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
H A DLiveRangeCalc.cpp39 void LiveRangeCalc::createDeadDefs(LiveInterval *LI, unsigned Reg) { argument
42 // Visit all def operands. If the same instruction has multiple defs of Reg,
45 I = MRI->def_begin(Reg), E = MRI->def_end(); I != E; ++I) {
63 void LiveRangeCalc::extendToUses(LiveInterval *LI, unsigned Reg) { argument
66 // Visit all operands that read Reg. This may include partial defs.
67 for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg),
76 // MI is reading Reg. We may have visited MI before if it happens to be
77 // reading Reg multiple times. That is OK, extend() is idempotent.
84 // PHI operands are paired: (Reg, PredMBB).
102 extend(LI, Idx, Reg);
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H A DMachineCopyPropagation.cpp51 void SourceNoLongerAvailable(unsigned Reg,
65 MachineCopyPropagation::SourceNoLongerAvailable(unsigned Reg, argument
68 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
241 unsigned Reg = MO.getReg(); local
242 if (!Reg)
245 if (TargetRegisterInfo::isVirtualRegister(Reg))
250 Defs.push_back(Reg);
254 // If 'Reg' is defined by a copy, the copy is no longer a candidate
256 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
273 unsigned Reg local
290 unsigned Reg = Defs[i]; local
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/external/llvm/lib/Target/R600/
H A DSIFixSGPRCopies.cpp84 unsigned Reg) const;
106 /// \p Reg until it finds an Instruction that isn't a COPY returns
111 unsigned Reg) const {
112 // The Reg parameter to the function must always be defined by either a PHI
114 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
115 "Reg cannot be a physical register");
117 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
118 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg),
144 unsigned Reg = MI.getOperand(0).getReg(); local
145 const TargetRegisterClass *RC = inferRegClass(TRI, MRI, Reg);
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/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { argument
40 switch (Reg) {
53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { argument
55 switch (Reg) {
64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { argument
66 switch (Reg) {
128 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
156 bool isLowRegister(unsigned Reg) const;
H A DARMCallingConv.h34 if (unsigned Reg = State.AllocateReg(RegList, 4))
35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
49 if (unsigned Reg = State.AllocateReg(RegList, 4))
50 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); local
80 if (Reg == 0) {
83 Reg = State.AllocateReg(GPRArgRegs, 4);
84 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64");
99 if (HiRegList[i] == Reg)
129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); local
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/external/llvm/lib/Target/Sparc/
H A DSparcMachineFunctionInfo.h43 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
49 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/external/qemu/target-i386/
H A Dops_sse_header.h21 #define Reg MMXReg macro
24 #define Reg XMMReg macro
31 #define dh_ctype_Reg Reg *
38 DEF_HELPER_2(glue(psrlw, SUFFIX), void, Reg, Reg) variable
39 DEF_HELPER_2(glue(psraw, SUFFIX), void, Reg, Reg) variable
40 DEF_HELPER_2(glue(psllw, SUFFIX), void, Reg, Reg) variable
41 DEF_HELPER_2(glue(psrld, SUFFIX), void, Reg, Re variable
42 DEF_HELPER_2(glue(psrad, SUFFIX), void, Reg, Reg) variable
43 DEF_HELPER_2(glue(pslld, SUFFIX), void, Reg, Reg) variable
44 DEF_HELPER_2(glue(psrlq, SUFFIX), void, Reg, Reg) variable
45 DEF_HELPER_2(glue(psllq, SUFFIX), void, Reg, Reg) variable
48 DEF_HELPER_2(glue(psrldq, SUFFIX), void, Reg, Reg) variable
49 DEF_HELPER_2(glue(pslldq, SUFFIX), void, Reg, Reg) variable
113 DEF_HELPER_2(glue(pmuludq, SUFFIX), void, Reg, Reg) variable
114 DEF_HELPER_2(glue(pmaddwd, SUFFIX), void, Reg, Reg) variable
116 DEF_HELPER_2(glue(psadbw, SUFFIX), void, Reg, Reg) variable
117 DEF_HELPER_3(glue(maskmov, SUFFIX), void, Reg, Reg, tl) variable
118 DEF_HELPER_2(glue(movl_mm_T0, SUFFIX), void, Reg, i32) variable
120 DEF_HELPER_2(glue(movq_mm_T0, SUFFIX), void, Reg, i64) variable
124 DEF_HELPER_3(glue(pshufw, SUFFIX), void, Reg, Reg, int) variable
225 DEF_HELPER_2(glue(packsswb, SUFFIX), void, Reg, Reg) variable
226 DEF_HELPER_2(glue(packuswb, SUFFIX), void, Reg, Reg) variable
227 DEF_HELPER_2(glue(packssdw, SUFFIX), void, Reg, Reg) variable
237 DEF_HELPER_2(glue(punpcklqdq, SUFFIX), void, Reg, Reg) variable
238 DEF_HELPER_2(glue(punpckhqdq, SUFFIX), void, Reg, Reg) variable
265 DEF_HELPER_2(glue(phaddw, SUFFIX), void, Reg, Reg) variable
266 DEF_HELPER_2(glue(phaddd, SUFFIX), void, Reg, Reg) variable
267 DEF_HELPER_2(glue(phaddsw, SUFFIX), void, Reg, Reg) variable
268 DEF_HELPER_2(glue(phsubw, SUFFIX), void, Reg, Reg) variable
269 DEF_HELPER_2(glue(phsubd, SUFFIX), void, Reg, Reg) variable
270 DEF_HELPER_2(glue(phsubsw, SUFFIX), void, Reg, Reg) variable
271 DEF_HELPER_2(glue(pabsb, SUFFIX), void, Reg, Reg) variable
272 DEF_HELPER_2(glue(pabsw, SUFFIX), void, Reg, Reg) variable
273 DEF_HELPER_2(glue(pabsd, SUFFIX), void, Reg, Reg) variable
274 DEF_HELPER_2(glue(pmaddubsw, SUFFIX), void, Reg, Reg) variable
275 DEF_HELPER_2(glue(pmulhrsw, SUFFIX), void, Reg, Reg) variable
276 DEF_HELPER_2(glue(pshufb, SUFFIX), void, Reg, Reg) variable
277 DEF_HELPER_2(glue(psignb, SUFFIX), void, Reg, Reg) variable
278 DEF_HELPER_2(glue(psignw, SUFFIX), void, Reg, Reg) variable
279 DEF_HELPER_2(glue(psignd, SUFFIX), void, Reg, Reg) variable
280 DEF_HELPER_3(glue(palignr, SUFFIX), void, Reg, Reg, s32) variable
284 DEF_HELPER_2(glue(pblendvb, SUFFIX), void, Reg, Reg) variable
285 DEF_HELPER_2(glue(blendvps, SUFFIX), void, Reg, Reg) variable
286 DEF_HELPER_2(glue(blendvpd, SUFFIX), void, Reg, Reg) variable
287 DEF_HELPER_2(glue(ptest, SUFFIX), void, Reg, Reg) variable
288 DEF_HELPER_2(glue(pmovsxbw, SUFFIX), void, Reg, Reg) variable
289 DEF_HELPER_2(glue(pmovsxbd, SUFFIX), void, Reg, Reg) variable
290 DEF_HELPER_2(glue(pmovsxbq, SUFFIX), void, Reg, Reg) variable
291 DEF_HELPER_2(glue(pmovsxwd, SUFFIX), void, Reg, Reg) variable
292 DEF_HELPER_2(glue(pmovsxwq, SUFFIX), void, Reg, Reg) variable
293 DEF_HELPER_2(glue(pmovsxdq, SUFFIX), void, Reg, Reg) variable
294 DEF_HELPER_2(glue(pmovzxbw, SUFFIX), void, Reg, Reg) variable
295 DEF_HELPER_2(glue(pmovzxbd, SUFFIX), void, Reg, Reg) variable
296 DEF_HELPER_2(glue(pmovzxbq, SUFFIX), void, Reg, Reg) variable
297 DEF_HELPER_2(glue(pmovzxwd, SUFFIX), void, Reg, Reg) variable
298 DEF_HELPER_2(glue(pmovzxwq, SUFFIX), void, Reg, Reg) variable
299 DEF_HELPER_2(glue(pmovzxdq, SUFFIX), void, Reg, Reg) variable
300 DEF_HELPER_2(glue(pmuldq, SUFFIX), void, Reg, Reg) variable
301 DEF_HELPER_2(glue(pcmpeqq, SUFFIX), void, Reg, Reg) variable
302 DEF_HELPER_2(glue(packusdw, SUFFIX), void, Reg, Reg) variable
303 DEF_HELPER_2(glue(pminsb, SUFFIX), void, Reg, Reg) variable
304 DEF_HELPER_2(glue(pminsd, SUFFIX), void, Reg, Reg) variable
305 DEF_HELPER_2(glue(pminuw, SUFFIX), void, Reg, Reg) variable
306 DEF_HELPER_2(glue(pminud, SUFFIX), void, Reg, Reg) variable
307 DEF_HELPER_2(glue(pmaxsb, SUFFIX), void, Reg, Reg) variable
308 DEF_HELPER_2(glue(pmaxsd, SUFFIX), void, Reg, Reg) variable
309 DEF_HELPER_2(glue(pmaxuw, SUFFIX), void, Reg, Reg) variable
310 DEF_HELPER_2(glue(pmaxud, SUFFIX), void, Reg, Reg) variable
311 DEF_HELPER_2(glue(pmulld, SUFFIX), void, Reg, Reg) variable
312 DEF_HELPER_2(glue(phminposuw, SUFFIX), void, Reg, Reg) variable
313 DEF_HELPER_3(glue(roundps, SUFFIX), void, Reg, Reg, i32) variable
314 DEF_HELPER_3(glue(roundpd, SUFFIX), void, Reg, Reg, i32) variable
315 DEF_HELPER_3(glue(roundss, SUFFIX), void, Reg, Reg, i32) variable
316 DEF_HELPER_3(glue(roundsd, SUFFIX), void, Reg, Reg, i32) variable
317 DEF_HELPER_3(glue(blendps, SUFFIX), void, Reg, Reg, i32) variable
318 DEF_HELPER_3(glue(blendpd, SUFFIX), void, Reg, Reg, i32) variable
319 DEF_HELPER_3(glue(pblendw, SUFFIX), void, Reg, Reg, i32) variable
320 DEF_HELPER_3(glue(dpps, SUFFIX), void, Reg, Reg, i32) variable
321 DEF_HELPER_3(glue(dppd, SUFFIX), void, Reg, Reg, i32) variable
322 DEF_HELPER_3(glue(mpsadbw, SUFFIX), void, Reg, Reg, i32) variable
327 DEF_HELPER_2(glue(pcmpgtq, SUFFIX), void, Reg, Reg) variable
328 DEF_HELPER_3(glue(pcmpestri, SUFFIX), void, Reg, Reg, i32) variable
329 DEF_HELPER_3(glue(pcmpestrm, SUFFIX), void, Reg, Reg, i32) variable
330 DEF_HELPER_3(glue(pcmpistri, SUFFIX), void, Reg, Reg, i32) variable
331 DEF_HELPER_3(glue(pcmpistrm, SUFFIX), void, Reg, Reg, i32) variable
337 #undef Reg macro
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsMachineFunction.h69 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
92 int getEhDataRegFI(unsigned Reg) const { return EhDataRegFI[Reg]; }
H A DMipsSERegisterInfo.cpp124 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm); local
125 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
126 .addReg(Reg, RegState::Kill);
128 FrameReg = Reg;
/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.cpp84 unsigned Reg = Op.getReg(); local
85 printRegName(O, Reg);
/external/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
118 unsigned Reg = *I; local
119 if (Reg < X86::FP0 || Reg > X86::FP6)
121 Mask |= 1 << (Reg - X86::FP0);
228 void pushReg(unsigned Reg) {
229 assert(Reg < NumFPRegs && "Register number out of range!");
232 Stack[StackTop] = Reg;
233 RegMap[Reg] = StackTop++;
289 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
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/external/llvm/include/llvm/CodeGen/
H A DLiveVariables.h106 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
107 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
110 unsigned Reg,
150 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
165 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
170 MachineInstr *FindLastPartialDef(unsigned Reg,
281 isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) argument
299 isPHIJoin(unsigned Reg) argument
302 setPHIJoin(unsigned Reg) argument
[all...]
H A DRegisterScavenging.h45 ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(NULL) {}
52 unsigned Reg; member in struct:llvm::RegScavenger::ScavengedInfo
162 void setUsed(unsigned Reg);
165 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
171 bool isUsed(unsigned Reg, bool CheckReserved = true) const { argument
172 return !RegsAvailable.test(Reg) || (CheckReserved && isReserved(Reg));
175 /// isAliasUsed - Is Reg or an alias currently in use?
176 bool isAliasUsed(unsigned Reg) cons
[all...]
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp255 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); local
256 if (MRC.contains(Reg)) {
263 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
283 unsigned Reg = Op.getReg(); local
284 printRegName(O, Reg);
738 unsigned Reg = MI->getOperand(OpNum).getReg();
739 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
741 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
1031 unsigned Reg = MO1.getReg();
1032 printRegName(O, Reg);
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp57 void Hexagon_CCState::MarkAllocated(unsigned Reg) { argument
59 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
101 unsigned Reg = Hexagon::R0; local
102 addLoc(CCValAssign::getReg(0, MVT::i32, Reg, MVT::i32,
107 unsigned Reg = Hexagon::D0; local
108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
H A DHexagonCallingConvLower.h73 bool isAllocated(unsigned Reg) const {
74 return UsedRegs[Reg/32] & (1 << (Reg&31));
120 unsigned AllocateReg(unsigned Reg) { argument
121 if (isAllocated(Reg)) return 0;
122 MarkAllocated(Reg);
123 return Reg;
127 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument
128 if (isAllocated(Reg)) return 0;
129 MarkAllocated(Reg);
143 unsigned Reg = Regs[FirstUnalloc]; local
156 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local
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