| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 339 EVT ShiftTy, SelectionDAG &DAG) {
354 DAG.getConstant(Log2_64(C), ShiftTy));
364 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
365 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
371 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
372 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
338 genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG) argument
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 1476 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? local
1483 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1491 DAG.getConstant(C1.logBase2(), ShiftTy)));
1506 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? local
1510 DAG.getConstant(ShiftBits, ShiftTy));
1534 EVT ShiftTy = DCI.isBeforeLegalizeOps() ? local
1538 DAG.getConstant(ShiftBits, ShiftTy));
|
| H A D | LegalizeIntegerTypes.cpp | 2107 EVT ShiftTy = TLI.getShiftAmountTy(VT); local
2108 assert(ShiftTy.getScalarType().getSizeInBits() >=
2111 if (ShiftOp.getValueType() != ShiftTy)
2112 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
|
| H A D | SelectionDAGBuilder.cpp | 2664 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType()); local
2667 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2668 unsigned ShiftSize = ShiftTy.getSizeInBits();
2674 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2681 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 175 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2770 ARM_AM::ShiftOpc ShiftTy) {
2813 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2816 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2769 SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy) argument
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 395 ARM_AM::ShiftOpc ShiftTy; member in struct:__anon21372::ARMOperand::PostIdxRegOp
405 ARM_AM::ShiftOpc ShiftTy; member in struct:__anon21372::ARMOperand::RegShiftedRegOp
412 ARM_AM::ShiftOpc ShiftTy; member in struct:__anon21372::ARMOperand::RegShiftedImmOp
963 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1025 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1544 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1555 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2078 PostIdxReg.ShiftTy);
2265 Op->RegShiftedReg.ShiftTy = ShTy;
2279 Op->RegShiftedImm.ShiftTy
2414 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
2665 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) local
3998 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; local
6869 ARM_AM::ShiftOpc ShiftTy; local
6894 ARM_AM::ShiftOpc ShiftTy; local
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