Searched defs:SubRegs (Results 1 - 4 of 4) sorted by relevance

/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h103 /// register. The SubRegs field is a zero terminated array of registers that
111 uint32_t SubRegs; // Sub-register set, described above member in struct:llvm::MCRegisterDesc
115 // sub-register in SubRegs.
445 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.h141 return SubRegs;
234 SubRegMap SubRegs; member in struct:llvm::CodeGenRegister
H A DCodeGenRegisters.cpp119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
123 "SubRegs and SubRegIndices must have the same size");
213 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
226 return SubRegs;
233 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
252 if (!SubRegs.insert(*SI).second)
265 CodeGenRegister *SR = SubRegs[Idx];
277 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
280 SubRegs
556 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); local
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/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp682 unsigned SubRegs = 0; local
687 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
689 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
692 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
694 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
696 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
698 Opc = ARM::MOVr, BeginIdx = ARM::gsub_0, SubRegs = 2;
701 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
703 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
705 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs
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