Searched defs:disp (Results 1 - 7 of 7) sorted by relevance

/art/compiler/dex/quick/arm/
H A Dassemble_arm.cc1226 int disp = target_disp - ((lir->offset + 4) & ~3); local
1227 if (disp < 4096) {
1228 lir->operands[1] = disp;
1252 // operands[1] should hold disp, [2] has add, [3] has tab_rec
1260 // operands[1] should hold disp, [2] has add, [3] has tab_rec
H A Dutility_arm.cc1037 LIR* ArmMir2Lir::OpMem(OpKind op, int rBase, int disp) { argument
/art/compiler/utils/x86/
H A Dassembler_x86.h105 void SetDisp8(int8_t disp) { argument
107 encoding_[length_++] = static_cast<uint8_t>(disp);
110 void SetDisp32(int32_t disp) { argument
112 int disp_size = sizeof(disp);
113 memmove(&encoding_[length_], &disp, disp_size);
139 Address(Register base, int32_t disp) { argument
140 Init(base, disp);
143 Address(Register base, Offset disp) { argument
144 Init(base, disp.Int32Value());
147 Address(Register base, FrameOffset disp) { argument
152 Address(Register base, MemberOffset disp) argument
156 Init(Register base, int32_t disp) argument
172 Address(Register index, ScaleFactor scale, int32_t disp) argument
179 Address(Register base, Register index, ScaleFactor scale, int32_t disp) argument
[all...]
/art/compiler/dex/quick/mips/
H A Dutility_mips.cc640 LIR* MipsMir2Lir::OpMem(OpKind op, int rBase, int disp) { argument
/art/compiler/dex/quick/x86/
H A Dassemble_x86.cc375 case kMem: // lir operands - 0: base, 1: disp
377 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp
379 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg
381 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
383 case kThreadReg: // lir operands - 0: disp, 1: reg
389 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp
391 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
393 case kRegThread: // lir operands - 0: reg, 1: disp
405 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate
407 case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp
491 ModrmForDisp(int base, int disp) argument
502 EmitDisp(int base, int disp) argument
551 EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp) argument
572 EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg) argument
615 EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp) argument
621 EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, int scale, int disp) argument
660 EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, uint8_t reg) argument
666 EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp) argument
849 EmitThreadImm(const X86EncodingMap* entry, int disp, int imm) argument
1028 EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp) argument
1060 EmitCallThread(const X86EncodingMap* entry, int disp) argument
1090 int disp; local
[all...]
H A Dutility_x86.cc230 r_src2 /* index */, 0 /* scale */, 0 /* disp */);
233 r_src1 /* index */, 0 /* scale */, 0 /* disp */);
283 // TODO: fix bug in LEA encoding when disp == 0
285 r_src /* index */, value /* scale */, 0 /* disp */);
288 r4sib_no_index /* index */, 0 /* scale */, value /* disp */);
306 LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp) { argument
314 return NewLIR2(opcode, rBase, disp);
/art/compiler/dex/quick/
H A Dcodegen_util.cc427 int disp = tab_rec->targets[elems]->offset - bx_offset; local
430 << std::hex << keys[elems] << ", disp: 0x"
431 << std::hex << disp; local
441 int disp = tab_rec->targets[elems]->offset - bx_offset; local
443 LOG(INFO) << " Case[" << elems << "] disp: 0x"
444 << std::hex << disp; local

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