Searched defs:rINST (Results 1 - 19 of 19) sorted by relevance

/dalvik/vm/compiler/template/ia32/
H A Dheader.S23 #define rINST %ebx define
/dalvik/vm/compiler/template/armv5te/
H A Dheader.S65 r7 rINST first 16-bit code unit of current instruction
77 #define rINST r7 define
/dalvik/vm/compiler/template/out/
H A DCompilerTemplateAsm-ia32.S30 #define rINST %ebx define
H A DCompilerTemplateAsm-armv5te.S72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7 define
H A DCompilerTemplateAsm-armv7-a-neon.S72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7 define
H A DCompilerTemplateAsm-armv7-a.S72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7 define
H A DCompilerTemplateAsm-armv5te-vfp.S72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7 define
H A DCompilerTemplateAsm-mips.S49 s4 rINST first 16-bit code unit of current instruction
123 #define rINST s4 define
162 #define FETCH_INST() lhu rINST, (rPC)
164 #define FETCH_ADVANCE_INST(_count) lhu rINST, (_count*2)(rPC); \
168 lhu rINST, (rPC)
185 #define GET_INST_OPCODE(rd) and rd, rINST, 0xFF
217 #define GET_OPA(rd) srl rd, rINST, 8
223 #define GET_OPB(rd) srl rd, rINST, 12
738 la rINST, .LdvmICHitCount
742 lw t2, 0(rINST)
[all...]
/dalvik/vm/mterp/armv5te/
H A Dheader.S60 r7 rINST first 16-bit code unit of current instruction
72 #define rINST r7 define
104 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
106 #define FETCH_INST() ldrh rINST, [rPC]
120 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
124 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
134 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
139 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
160 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
/dalvik/vm/mterp/x86/
H A Dheader.S71 #define rINST %ebx define
176 movzwl (rPC),rINST
200 movzwl \_count*2(rPC),rINST
208 movzwl (rPC,\_reg,2),rINST
227 movzbl rINSTbh,rINST
236 movzbl 1(rPC),rINST
/dalvik/vm/mterp/out/
H A DInterpAsm-x86.S78 #define rINST %ebx define
183 movzwl (rPC),rINST
207 movzwl \_count*2(rPC),rINST
215 movzwl (rPC,\_reg,2),rINST
234 movzbl rINSTbh,rINST
243 movzbl 1(rPC),rINST
343 shrl $4,rINST # rINST<- B
344 GET_VREG_R rINST rINST
[all...]
H A DInterpAsm-armv5te-vfp.S67 r7 rINST first 16-bit code unit of current instruction
79 #define rINST r7 define
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
315 FETCH_INST() @ load rINST fro
[all...]
H A DInterpAsm-armv5te.S67 r7 rINST first 16-bit code unit of current instruction
79 #define rINST r7 define
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
315 FETCH_INST() @ load rINST fro
[all...]
H A DInterpAsm-armv7-a-neon.S67 r7 rINST first 16-bit code unit of current instruction
79 #define rINST r7 define
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
329 FETCH_INST() @ load rINST fro
[all...]
H A DInterpAsm-armv7-a.S67 r7 rINST first 16-bit code unit of current instruction
79 #define rINST r7 define
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]!
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
329 FETCH_INST() @ load rINST fro
[all...]
H A DInterpAsm-mips.S30 s4 rINST first 16-bit code unit of current instruction
39 #define rINST s4 define
84 #define FETCH_INST() lhu rINST, (rPC)
86 #define FETCH_ADVANCE_INST(_count) lhu rINST, ((_count)*2)(rPC); \
94 lhu rINST, (rPC)
111 #define GET_INST_OPCODE(rd) and rd, rINST, 0xFF
147 #define GET_OPA(rd) srl rd, rINST, 8
151 #define GET_OPA4(rd) ext rd, rINST, 8, 4
153 #define GET_OPB(rd) srl rd, rINST, 12
446 FETCH_INST() # load rINST fro
[all...]
/dalvik/vm/mterp/mips/
H A Dheader.S23 s4 rINST first 16-bit code unit of current instruction
32 #define rINST s4 define
77 #define FETCH_INST() lhu rINST, (rPC)
79 #define FETCH_ADVANCE_INST(_count) lhu rINST, ((_count)*2)(rPC); \
87 lhu rINST, (rPC)
104 #define GET_INST_OPCODE(rd) and rd, rINST, 0xFF
140 #define GET_OPA(rd) srl rd, rINST, 8
144 #define GET_OPA4(rd) ext rd, rINST, 8, 4
146 #define GET_OPB(rd) srl rd, rINST, 12
/dalvik/vm/compiler/template/mips/
H A Dheader.S42 s4 rINST first 16-bit code unit of current instruction
116 #define rINST s4 define
155 #define FETCH_INST() lhu rINST, (rPC)
157 #define FETCH_ADVANCE_INST(_count) lhu rINST, (_count*2)(rPC); \
161 lhu rINST, (rPC)
178 #define GET_INST_OPCODE(rd) and rd, rINST, 0xFF
210 #define GET_OPA(rd) srl rd, rINST, 8
216 #define GET_OPB(rd) srl rd, rINST, 12
/dalvik/vm/compiler/codegen/mips/
H A DMipsLIR.h33 * s2 (rINST) is scratch for Jit
342 #define rINST r_S4 macro

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