| /art/compiler/dex/quick/x86/ |
| H A D | assemble_x86.cc | 703 void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) { argument
724 if (X86_FPREG(reg1)) {
725 reg1 = reg1 & X86_FP_REG_MASK;
730 DCHECK_LT(reg1, 8);
732 uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2;
740 uint8_t reg1, uint8_t reg2, int32_t imm) {
761 if (X86_FPREG(reg1)) {
762 reg1 = reg1
739 EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm) argument
[all...] |
| H A D | int_x86.cc | 30 int reg1, int base, int offset, ThrowKind kind) {
32 current_dalvik_offset_, reg1, base, offset);
33 OpRegMem(kOpCmp, reg1, base, offset);
239 void X86Mir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) { argument
240 NewLIR5(kX86Lea32RA, rBase, reg1, reg2, scale, offset);
29 GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset, ThrowKind kind) argument
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| H A D | target_x86.cc | 104 bool X86Mir2Lir::SameRegType(int reg1, int reg2) { argument
105 return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
316 void X86Mir2Lir::FlushRegWide(int reg1, int reg2) { argument
317 RegisterInfo* info1 = GetRegInfo(reg1);
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| /art/compiler/dex/quick/arm/ |
| H A D | target_arm.cc | 94 bool ArmMir2Lir::SameRegType(int reg1, int reg2) { argument
95 return (ARM_REGTYPE(reg1) == ARM_REGTYPE(reg2));
612 void ArmMir2Lir::FlushRegWide(int reg1, int reg2) { argument
613 RegisterInfo* info1 = GetRegInfo(reg1);
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| H A D | int_arm.cc | 463 int reg1, int base, int offset, ThrowKind kind) {
468 RegLocation ArmMir2Lir::GenDivRemLit(RegLocation rl_dest, int reg1, int lit, argument
474 RegLocation ArmMir2Lir::GenDivRem(RegLocation rl_dest, int reg1, int reg2, argument
497 void ArmMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) { argument
462 GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset, ThrowKind kind) argument
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| /art/compiler/dex/quick/mips/ |
| H A D | int_mips.cc | 221 int reg1, int base, int offset, ThrowKind kind) {
226 RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, int reg1, int reg2, argument
228 NewLIR4(kMipsDiv, r_HI, r_LO, reg1, reg2);
238 RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, int reg1, int lit, argument
242 NewLIR4(kMipsDiv, r_HI, r_LO, reg1, t_reg);
253 void MipsMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) { argument
220 GenRegMemCheck(ConditionCode c_code, int reg1, int base, int offset, ThrowKind kind) argument
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| H A D | target_mips.cc | 95 bool MipsMir2Lir::SameRegType(int reg1, int reg2) { argument
96 return (MIPS_REGTYPE(reg1) == MIPS_REGTYPE(reg2));
312 void MipsMir2Lir::FlushRegWide(int reg1, int reg2) { argument
313 RegisterInfo* info1 = GetRegInfo(reg1);
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| /art/compiler/dex/quick/ |
| H A D | gen_common.cc | 76 LIR* Mir2Lir::GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, argument
78 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_, reg1, reg2);
79 LIR* branch = OpCmpBranch(c_code, reg1, reg2, tgt);
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| /art/compiler/utils/x86/ |
| H A D | assembler_x86.cc | 762 void X86Assembler::cmpl(Register reg0, Register reg1) { argument
765 EmitOperand(reg0, Operand(reg1));
803 void X86Assembler::testl(Register reg1, Register reg2) { argument
806 EmitRegisterOperand(reg1, reg2);
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