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Searched defs:rs (Results 1 - 3 of 3) sorted by relevance

/art/runtime/
H A D	disassembler_mips.cc	`174 uint32_t rs = (instruction >> 21) & 0x1f; // I-type, R-type. local 234 case 'O': // +x(rs) 237 args << StringPrintf("%+d(r%d)", offset, rs); 238 if (rs == 17) { 244 case 'S': args << 'r' << rs; break; local 245 case 's': args << 'f' << rs; break; local`
/art/compiler/utils/mips/
H A D	assembler_mips.cc	53 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { argument 54 CHECK_NE(rs, kNoRegister); 58 static_cast<int32_t>(rs) << kRsShift \| 66 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { argument 67 CHECK_NE(rs, kNoRegister); 70 static_cast<int32_t>(rs) << kRsShift \| 104 void MipsAssembler::EmitBranch(Register rt, Register rs, Label* label, bool equal) { argument 114 Beq(rt, rs, (offset >> 2) & kBranchOffsetMask); 116 Bne(rt, rs, (offset >> 2) & kBranchOffsetMask); 174 void MipsAssembler::Add(Register rd, Register rs, Registe argument 178 Addu(Register rd, Register rs, Register rt) argument 182 Addi(Register rt, Register rs, uint16_t imm16) argument 186 Addiu(Register rt, Register rs, uint16_t imm16) argument 190 Sub(Register rd, Register rs, Register rt) argument 194 Subu(Register rd, Register rs, Register rt) argument 198 Mult(Register rs, Register rt) argument 202 Multu(Register rs, Register rt) argument 206 Div(Register rs, Register rt) argument 210 Divu(Register rs, Register rt) argument 214 And(Register rd, Register rs, Register rt) argument 218 Andi(Register rt, Register rs, uint16_t imm16) argument 222 Or(Register rd, Register rs, Register rt) argument 226 Ori(Register rt, Register rs, uint16_t imm16) argument 230 Xor(Register rd, Register rs, Register rt) argument 234 Xori(Register rt, Register rs, uint16_t imm16) argument 238 Nor(Register rd, Register rs, Register rt) argument 242 Sll(Register rd, Register rs, int shamt) argument 246 Srl(Register rd, Register rs, int shamt) argument 250 Sra(Register rd, Register rs, int shamt) argument 254 Sllv(Register rd, Register rs, Register rt) argument 258 Srlv(Register rd, Register rs, Register rt) argument 262 Srav(Register rd, Register rs, Register rt) argument 266 Lb(Register rt, Register rs, uint16_t imm16) argument 270 Lh(Register rt, Register rs, uint16_t imm16) argument 274 Lw(Register rt, Register rs, uint16_t imm16) argument 278 Lbu(Register rt, Register rs, uint16_t imm16) argument 282 Lhu(Register rt, Register rs, uint16_t imm16) argument 298 Sb(Register rt, Register rs, uint16_t imm16) argument 302 Sh(Register rt, Register rs, uint16_t imm16) argument 306 Sw(Register rt, Register rs, uint16_t imm16) argument 310 Slt(Register rd, Register rs, Register rt) argument 314 Sltu(Register rd, Register rs, Register rt) argument 318 Slti(Register rt, Register rs, uint16_t imm16) argument 322 Sltiu(Register rt, Register rs, uint16_t imm16) argument 326 Beq(Register rt, Register rs, uint16_t imm16) argument 331 Bne(Register rt, Register rs, uint16_t imm16) argument 346 Jr(Register rs) argument 351 Jalr(Register rs) argument 405 Mtc1(FRegister ft, Register rs) argument 409 Lwc1(FRegister ft, Register rs, uint16_t imm16) argument 413 Ldc1(DRegister ft, Register rs, uint16_t imm16) argument 417 Swc1(FRegister ft, Register rs, uint16_t imm16) argument 421 Sdc1(DRegister ft, Register rs, uint16_t imm16) argument 434 Move(Register rt, Register rs) argument 442 Not(Register rt, Register rs) argument 446 Mul(Register rd, Register rs, Register rt) argument 451 Div(Register rd, Register rs, Register rt) argument 456 Rem(Register rd, Register rs, Register rt) argument 461 AddConstant(Register rt, Register rs, int32_t value) argument [all...]
/art/compiler/utils/arm/
H A D	assembler_arm.cc	419 Register rm, Register rs) { 423 CHECK_NE(rs, kNoRegister); 429 (static_cast<int32_t>(rs) << kRsShift) \| 437 // Assembler registers rd, rn, rm are encoded as rn, rm, rs. 444 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 451 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 458 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. 417 EmitMulOp(Condition cond, int32_t opcode, Register rd, Register rn, Register rm, Register rs) argument

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