/external/llvm/include/llvm/Support/ |
H A D | TargetFolder.h | 245 Constant *Mask) const { 246 return Fold(ConstantExpr::getShuffleVector(V1, V2, Mask));
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H A D | NoFolder.h | 281 Constant *Mask) const { 282 return new ShuffleVectorInst(V1, V2, Mask);
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/external/llvm/lib/IR/ |
H A D | Instructions.cpp | 1528 ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, argument 1532 cast<VectorType>(Mask->getType())->getNumElements()), 1537 assert(isValidOperands(V1, V2, Mask) && 1541 Op<2>() = Mask; 1545 ShuffleVectorInst::ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, argument 1549 cast<VectorType>(Mask->getType())->getNumElements()), 1554 assert(isValidOperands(V1, V2, Mask) && 1559 Op<2>() = Mask; 1564 const Value *Mask) { 1569 // Mask mus 1563 isValidOperands(const Value *V1, const Value *V2, const Value *Mask) argument 1614 getMaskValue(Constant *Mask, unsigned i) argument 1626 getShuffleMask(Constant *Mask, SmallVectorImpl<int> &Result) argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 96 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a 98 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask, 356 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, argument 373 if (isShiftMask) Mask = Mask << Shift; 378 if (isShiftMask) Mask = Mask >> Shift; 390 if (Mask && !(Mask & Indeterminant)) { 393 return isRunOfOnes(Mask, M [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/state_trackers/d3d1x/d3dapi/ |
H A D | d3d11shader.idl | 54 BYTE Mask;
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/external/clang/lib/CodeGen/ |
H A D | CGExpr.cpp | 1079 llvm::Constant *Mask[] = { local 1085 llvm::Value *MaskV = llvm::ConstantVector::get(Mask); 1180 SmallVector<llvm::Constant*, 4> Mask; local 1181 Mask.push_back(llvm::ConstantInt::get( 1184 Mask.push_back(llvm::ConstantInt::get( 1187 Mask.push_back(llvm::ConstantInt::get( 1190 Mask.push_back(llvm::UndefValue::get(llvm::Type::getInt32Ty(VMContext))); 1192 llvm::Value *MaskV = llvm::ConstantVector::get(Mask); 1328 SmallVector<llvm::Constant*, 4> Mask; local 1330 Mask 1544 SmallVector<llvm::Constant*, 4> Mask; local [all...] |
/external/libnfc-nxp/src/ |
H A D | phFriNfc_NdefRecord.c | 381 static uint8_t phFriNfc_NdefRecord_NdefFlag(uint8_t Flags,uint8_t Mask) argument 384 check_flag = Flags & Mask;
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 149 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const { 150 MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
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H A D | SelectionDAGNodes.h | 1179 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and 1181 const int *Mask; member in class:llvm::ShuffleVectorSDNode 1186 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) { 1193 return makeArrayRef(Mask, VT.getVectorNumElements()); 1197 return Mask[Idx]; 1200 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); } 1205 if (Mask[i] >= 0) 1206 return Mask[i]; 1210 static bool isSplatMask(const int *Mask, EVT VT);
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/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 739 int &Mask, int &Value) const { 748 int Mask, int Value, 737 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument 746 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const argument
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/external/mesa3d/src/gallium/state_trackers/d3d1x/d3dapi/ |
H A D | d3d11shader.idl | 54 BYTE Mask;
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/external/chromium_org/rlz/win/lib/ |
H A D | rlz_lib_win.cc | 98 DWORD mask = ace->Mask;
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/external/chromium_org/third_party/leveldatabase/src/table/ |
H A D | table_builder.cc | 187 EncodeFixed32(trailer+1, crc32c::Mask(crc));
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
H A D | brw_cc.c | 210 cc->cc2.depth_write_enable = ctx->Depth.Mask;
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/nouveau/ |
H A D | nv10_state_raster.c | 101 PUSH_DATAb(push, ctx->Depth.Mask);
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/external/chromium_org/v8/src/ |
H A D | utils.h | 1064 bool Contains(E element) const { return (bits_ & Mask(element)) != 0; } 1068 void Add(E element) { bits_ |= Mask(element); } 1070 void Remove(E element) { bits_ &= ~Mask(element); } 1082 T Mask(E element) const {
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.h | 73 int &Mask, int &Value) const;
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/external/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 714 unsigned Mask = 1; local 716 if (ErrorInfo & Mask) { 718 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 720 Mask <<= 1;
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_cc.c | 210 cc->cc2.depth_write_enable = ctx->Depth.Mask;
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/external/mesa3d/src/mesa/drivers/dri/nouveau/ |
H A D | nv10_state_raster.c | 101 PUSH_DATAb(push, ctx->Depth.Mask);
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/external/v8/src/ |
H A D | utils.h | 933 bool Contains(E element) const { return (bits_ & Mask(element)) != 0; } 937 void Add(E element) { bits_ |= Mask(element); } 939 void Remove(E element) { bits_ &= ~Mask(element); } 947 T Mask(E element) const {
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/external/chromium_org/third_party/openssl/openssl/crypto/bn/asm/ |
H A D | pa-risc2.s | 478 DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L 505 AND m_0,high_mask,tmp_0 ; m[0] & Mask 506 AND m_1,high_mask,tmp_1 ; m[1] & Mask 512 EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m[0]&Mask >> 32-1 513 EXTRD,U tmp_1,32,33,tmp_1 ; tmp_1 = m[1]&Mask >> 32-1 553 AND m_0,high_mask,tmp_0 ; m & Mask 558 EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m&Mask >> 32-1 1031 AND m,high_mask,temp2 ; m & Mask 1036 EXTRD,U temp2,32,33,temp1 ; temp1 = m&Mask >> 32-1 1114 DEPDI,Z -1,32,33,high_mask ; Create Mask [all...] |
H A D | pa-risc2W.s | 467 DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L 494 AND m_0,high_mask,tmp_0 ; m[0] & Mask 495 AND m_1,high_mask,tmp_1 ; m[1] & Mask 501 EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m[0]&Mask >> 32-1 502 EXTRD,U tmp_1,32,33,tmp_1 ; tmp_1 = m[1]&Mask >> 32-1 542 AND m_0,high_mask,tmp_0 ; m & Mask 547 EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m&Mask >> 32-1 1018 AND m,high_mask,temp2 ; m & Mask 1023 EXTRD,U temp2,32,33,temp1 ; temp1 = m&Mask >> 32-1 1101 DEPDI,Z -1,32,33,high_mask ; Create Mask [all...] |
/external/openssl/crypto/bn/asm/ |
H A D | pa-risc2.s | 478 DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L 505 AND m_0,high_mask,tmp_0 ; m[0] & Mask 506 AND m_1,high_mask,tmp_1 ; m[1] & Mask 512 EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m[0]&Mask >> 32-1 513 EXTRD,U tmp_1,32,33,tmp_1 ; tmp_1 = m[1]&Mask >> 32-1 553 AND m_0,high_mask,tmp_0 ; m & Mask 558 EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m&Mask >> 32-1 1031 AND m,high_mask,temp2 ; m & Mask 1036 EXTRD,U temp2,32,33,temp1 ; temp1 = m&Mask >> 32-1 1114 DEPDI,Z -1,32,33,high_mask ; Create Mask [all...] |
H A D | pa-risc2W.s | 467 DEPDI,Z -1,32,33,high_mask ; Create Mask 0xffffffff80000000L 494 AND m_0,high_mask,tmp_0 ; m[0] & Mask 495 AND m_1,high_mask,tmp_1 ; m[1] & Mask 501 EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m[0]&Mask >> 32-1 502 EXTRD,U tmp_1,32,33,tmp_1 ; tmp_1 = m[1]&Mask >> 32-1 542 AND m_0,high_mask,tmp_0 ; m & Mask 547 EXTRD,U tmp_0,32,33,tmp_0 ; tmp_0 = m&Mask >> 32-1 1018 AND m,high_mask,temp2 ; m & Mask 1023 EXTRD,U temp2,32,33,temp1 ; temp1 = m&Mask >> 32-1 1101 DEPDI,Z -1,32,33,high_mask ; Create Mask [all...] |