/external/chromium_org/third_party/mesa/src/src/glsl/ |
H A D | opt_array_splitting.cpp | 101 bool get_split_list(exec_list *instructions, bool linked); 195 * so just look at the body instructions and not the parameter 203 ir_array_reference_visitor::get_split_list(exec_list *instructions, argument 206 visit_list_elements(this, instructions); 212 foreach_list(node, instructions) { 356 optimize_split_arrays(exec_list *instructions, bool linked) argument 359 if (!refs.get_split_list(instructions, linked)) 396 visit_list_elements(&split, instructions); 399 _mesa_print_ir(instructions, NULL);
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H A D | opt_if_simplification.cpp | 50 /* We only care about the top level "if" instructions, so don't 61 do_if_simplification(exec_list *instructions) argument 65 v.run(instructions);
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H A D | opt_redundant_jumps.cpp | 49 /* We only care about the top level instructions, so don't descend 118 optimize_redundant_jumps(exec_list *instructions) argument 122 v.run(instructions);
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H A D | opt_swizzle_swizzle.cpp | 90 do_swizzle_swizzle(exec_list *instructions) argument 94 v.run(instructions);
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H A D | ir_function_detect_recursion.cpp | 328 exec_list *instructions) 335 v.run(instructions); 354 exec_list *instructions) 361 v.run(instructions); 327 detect_recursion_unlinked(struct _mesa_glsl_parse_state *state, exec_list *instructions) argument 353 detect_recursion_linked(struct gl_shader_program *prog, exec_list *instructions) argument
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H A D | ir_print_visitor.h | 36 extern void _mesa_print_ir(exec_list *instructions,
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H A D | lower_if_to_cond_assign.cpp | 36 * lower_if_to_cond_assign(instructions) 43 * lower_if_to_cond_assign(instructions, N) 80 lower_if_to_cond_assign(exec_list *instructions, unsigned max_depth) argument 87 visit_list_elements(&v, instructions); 112 exec_list *instructions, 115 foreach_list_safe(node, instructions) { 190 /* Store the condition to a variable. Move all of the instructions from 215 /* If there are instructions in the else-clause, store the inverse of the 216 * condition to a variable. Move all of the instructions from the 110 move_block_to_cond_assign(void *mem_ctx, ir_if *if_ir, ir_rvalue *cond_expr, exec_list *instructions, struct hash_table *ht) argument
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H A D | opt_constant_variable.cpp | 169 do_constant_variable(exec_list *instructions) argument 174 v.run(instructions); 193 do_constant_variable_unlinked(exec_list *instructions) argument 197 foreach_iter(exec_list_iterator, iter, *instructions) {
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/external/mesa3d/src/glsl/ |
H A D | ir_basic_block.cpp | 52 void call_for_basic_blocks(exec_list *instructions, argument 61 foreach_iter(exec_list_iterator, iter, *instructions) { 89 * maximal BBs between the instructions that precede main() 90 * and the body of main(). Perhaps those instructions ought
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H A D | lower_texture_projection.cpp | 92 do_lower_texture_projection(exec_list *instructions) argument 96 visit_list_elements(&v, instructions);
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H A D | opt_array_splitting.cpp | 101 bool get_split_list(exec_list *instructions, bool linked); 195 * so just look at the body instructions and not the parameter 203 ir_array_reference_visitor::get_split_list(exec_list *instructions, argument 206 visit_list_elements(this, instructions); 212 foreach_list(node, instructions) { 356 optimize_split_arrays(exec_list *instructions, bool linked) argument 359 if (!refs.get_split_list(instructions, linked)) 396 visit_list_elements(&split, instructions); 399 _mesa_print_ir(instructions, NULL);
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H A D | opt_if_simplification.cpp | 50 /* We only care about the top level "if" instructions, so don't 61 do_if_simplification(exec_list *instructions) argument 65 v.run(instructions);
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H A D | opt_redundant_jumps.cpp | 49 /* We only care about the top level instructions, so don't descend 118 optimize_redundant_jumps(exec_list *instructions) argument 122 v.run(instructions);
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H A D | opt_swizzle_swizzle.cpp | 90 do_swizzle_swizzle(exec_list *instructions) argument 94 v.run(instructions);
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/external/oprofile/events/mips/25K/ |
H A D | events | 7 event:0x1 counters:0,1 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions 8 event:0x2 counters:0,1 um:zero minimum:500 name:FP_INSNS_ISSUED : FPU instructions issued 9 event:0x3 counters:0,1 um:zero minimum:500 name:INT_INSNS_ISSUED : Integer instructions issued 10 event:0x4 counters:0,1 um:zero minimum:500 name:LOAD_INSNS_ISSUED : Load instructions issued 11 event:0x5 counters:0,1 um:zero minimum:500 name:STORE_INSNS_ISSUED : Store instructions issued 12 event:0x6 counters:0,1 um:zero minimum:500 name:BRANCHES_JUMPS_ISSUED : Branch/Jump instructions issued 20 event:0xa counters:0,1 um:zero minimum:500 name:INSN_FP_DATAPATH_COMPLETED : Instructions completed in FPU datapath (computational instructions only) 29 event:0xf counters:0,1 um:zero minimum:500 name:JR_RPD_MISSPREDICTED : JR instructions that mispredicted using the Return Prediction Stack 50 event:0x18 counters:0,1 um:zero minimum:500 name:INSNS_FETCHED_FROM_ICACHE : Total number of instructions fetched from the I-Cache 81 event:0x27 counters:0,1 um:zero minimum:500 name:LOAD_STORE_ISSUED : Load/store instructions issue [all...] |
/external/oprofile/events/mips/1004K/ |
H A D | events | 21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted) 22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed 23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict) 32 event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed 33 event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (including FP) 34 event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed 35 event:0x11 counters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0 37 event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions completed 38 event:0x14 counters:0 um:zero minimum:500 name:PREFETCH_INSNS : 20-0 PREFETCH instructions completed 44 event:0x1a counters:0 um:zero minimum:500 name:DSP_INSNS : 26-0 DSP instructions complete [all...] |
/external/oprofile/events/mips/74K/ |
H A D | events | 20 event:0x2 counters:0,2 um:zero minimum:500 name:PREDICTED_JR_31 : 2-0 JR $31 (return) instructions predicted including speculative instructions 21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception 24 event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions 35 event:0x11 counters:0,2 um:zero minimum:500 name:ALU_OPERANDS_NOT_READY_CYCLES : 17-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready 36 event:0x12 counters:0,2 um:zero minimum:500 name:ALU_NO_ISSUES_CYCLES : 18-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, MDU busy, or CorExt resource busy 40 event:0x16 counters:0,2 um:zero minimum:500 name:JALR_JALR_HB_INSNS : 22-0 Graduated JALR/JALR.HB instructions 41 event:0x17 counters:0,2 um:zero minimum:500 name:DCACHE_LOAD_ACCESSES : 23-0 Counts all accesses to the data cache caused by load instructions 53 event:0x24 counters:0,2 um:zero minimum:500 name:JR_NON_31_INSNS : 36-0 jr $xx (not $31) instructions graduated (at same cost as a mispredict) 54 event:0x25 counters:0,2 um:zero minimum:500 name:BRANCH_INSNS : 37-0 Branch instructions graduate [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
H A D | brw_fs_schedule_instructions.cpp | 35 * List scheduling of FS instructions. 120 this->instructions.make_empty(); 142 exec_list instructions; member in class:instruction_scheduler 157 instructions.push_tail(n); 266 schedule_node *last = (schedule_node *)instructions.get_tail(); 273 foreach_list(node, &instructions) { 355 for (node = instructions.get_tail(), prev = node->prev; 436 foreach_list_safe(node, &instructions) { 442 while (!instructions.is_empty()) { 446 foreach_list(node, &instructions) { [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_fs_schedule_instructions.cpp | 35 * List scheduling of FS instructions. 120 this->instructions.make_empty(); 142 exec_list instructions; member in class:instruction_scheduler 157 instructions.push_tail(n); 266 schedule_node *last = (schedule_node *)instructions.get_tail(); 273 foreach_list(node, &instructions) { 355 for (node = instructions.get_tail(), prev = node->prev; 436 foreach_list_safe(node, &instructions) { 442 while (!instructions.is_empty()) { 446 foreach_list(node, &instructions) { [all...] |
/external/oprofile/events/mips/rm9000/ |
H A D | events | 6 event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued 7 event:0x03 counters:0,1 um:zero minimum:500 name:INT_INSTRUCTIONS_ISSUED : Integer instructions issued 8 event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued 9 event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued 21 event:0x12 counters:0,1 um:zero minimum:500 name:BRANCHES_ISSUED : Branch instructions issued 31 event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES : Stall cycles due to cache instructions
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/external/chromium_org/third_party/WebKit/ManualTests/inspector-wrappers/ |
H A D | inspector-wrappers-test-utils.js | 27 function instructions(params) { function
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/external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
H A D | FillArrayDataPayloadDecodedInstruction.java | 17 package com.android.dx.io.instructions;
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H A D | FiveRegisterDecodedInstruction.java | 17 package com.android.dx.io.instructions;
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H A D | FourRegisterDecodedInstruction.java | 17 package com.android.dx.io.instructions;
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H A D | ThreeRegisterDecodedInstruction.java | 17 package com.android.dx.io.instructions;
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