| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDGPUSubtarget.h | 40 InstrItineraryData InstrItins; member in class:llvm::AMDGPUSubtarget
46 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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| H A D | AMDGPUTargetMachine.h | 37 const InstrItineraryData* InstrItins; member in class:llvm::AMDGPUTargetMachine
62 return InstrItins;
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| H A D | AMDGPUSubtarget.cpp | 25 InstrItins = getInstrItineraryForCPU(CPU);
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| /external/llvm/lib/Target/R600/ |
| H A D | AMDGPUSubtarget.h | 52 InstrItineraryData InstrItins; member in class:llvm::AMDGPUSubtarget
57 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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| H A D | AMDGPUTargetMachine.h | 36 const InstrItineraryData *InstrItins; member in class:llvm::AMDGPUTargetMachine
60 return InstrItins;
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| H A D | AMDGPUSubtarget.cpp | 27 InstrItins = getInstrItineraryForCPU(CPU);
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDGPUSubtarget.h | 40 InstrItineraryData InstrItins; member in class:llvm::AMDGPUSubtarget
46 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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| H A D | AMDGPUTargetMachine.h | 37 const InstrItineraryData* InstrItins; member in class:llvm::AMDGPUTargetMachine
62 return InstrItins;
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| H A D | AMDGPUSubtarget.cpp | 25 InstrItins = getInstrItineraryForCPU(CPU);
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | TargetSchedule.h | 36 InstrItineraryData InstrItins; member in class:llvm::TargetSchedModel
77 return &InstrItins;
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| H A D | DFAPacketizer.h | 46 const InstrItineraryData *InstrItins; member in class:llvm::DFAPacketizer
82 const InstrItineraryData *getInstrItins() const { return InstrItins; }
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| H A D | ResourcePriorityQueue.h | 63 const InstrItineraryData* InstrItins; member in class:llvm::ResourcePriorityQueue
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| /external/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 36 return EnableSchedItins && !InstrItins.isEmpty();
60 STI->initInstrItins(InstrItins);
80 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
81 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
165 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx,
170 OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
176 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
179 // Rather than directly querying InstrItins stage latency, we call a TII
181 // applicable to the InstrItins model. InstrSchedModel should model all
231 return TII->getInstrLatency(&InstrItins, M
[all...] |
| H A D | DFAPacketizer.cpp | 36 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
68 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
80 const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.h | 41 InstrItineraryData InstrItins; member in class:llvm::HexagonSubtarget
48 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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| H A D | HexagonTargetMachine.h | 36 const InstrItineraryData* InstrItins; member in class:llvm::HexagonTargetMachine
55 return InstrItins;
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| H A D | HexagonSubtarget.cpp | 73 InstrItins = getInstrItineraryForCPU(CPUString);
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetMachine.h | 38 InstrItineraryData InstrItins; member in class:llvm::PPCTargetMachine
64 return &InstrItins;
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| H A D | PPCSubtarget.h | 67 InstrItineraryData InstrItins; member in class:llvm::PPCSubtarget
123 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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| /external/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 115 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
116 InstrItins =
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.h | 38 InstrItineraryData InstrItins; member in class:llvm::ARMBaseTargetMachine
54 return &InstrItins;
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| H A D | ARMSubtarget.h | 191 InstrItineraryData InstrItins; member in class:llvm::ARMSubtarget
320 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSubtarget.h | 116 InstrItineraryData InstrItins; member in class:llvm::MipsSubtarget
197 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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| H A D | MipsTargetMachine.h | 47 const InstrItineraryData &InstrItins; member in class:llvm::MipsTargetMachine
71 return Subtarget.inMips16Mode() ? 0 : &InstrItins;
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| /external/llvm/lib/Target/X86/ |
| H A D | X86TargetMachine.h | 35 InstrItineraryData InstrItins; member in class:llvm::X86TargetMachine
64 return &InstrItins;
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