Searched refs:NextVA (Results 1 - 6 of 6) sorted by relevance

/external/clang/lib/AST/
H A DStmtIterator.cpp33 void StmtIteratorBase::NextVA() { function in class:StmtIteratorBase
/external/clang/include/clang/AST/
H A DStmtIterator.h63 void NextVA();
91 NextVA();
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.h421 CCValAssign &VA, CCValAssign &NextVA,
425 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
H A DARMFastISel.cpp2017 CCValAssign &NextVA = ArgLocs[++i]; local
2019 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2024 .addReg(NextVA.getLocReg(), RegState::Define)
2027 RegArgs.push_back(NextVA.getLocReg());
H A DARMISelLowering.cpp1370 CCValAssign &VA, CCValAssign &NextVA,
1379 if (NextVA.isRegLoc())
1380 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1382 assert(NextVA.isMemLoc());
1387 dl, DAG, NextVA,
2653 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, argument
2670 if (NextVA.isMemLoc()) {
2672 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2680 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1367 PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVectorImpl<SDValue> &MemOpChains, ISD::ArgFlagsTy Flags) const argument
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp372 CCValAssign &NextVA = ArgLocs[++i]; local
375 if (NextVA.isMemLoc()) {
377 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
383 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
791 CCValAssign &NextVA = ArgLocs[++i]; local
792 if (NextVA.isRegLoc()) {
793 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
796 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;

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