/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 17 const MCOperand &Op = MI->getOperand(OpNo); local 18 if (Op.isReg()) { 19 O << getRegisterName(Op.getReg()); 20 } else if (Op.isImm()) { 21 O << Op.getImm(); 22 } else if (Op.isFPImm()) { 23 O << Op.getFPImm();
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/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.cpp | 17 const MCOperand &Op = MI->getOperand(OpNo); local 18 if (Op.isReg()) { 19 O << getRegisterName(Op.getReg()); 20 } else if (Op.isImm()) { 21 O << Op.getImm(); 22 } else if (Op.isFPImm()) { 23 O << Op.getFPImm();
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/external/llvm/include/llvm/MC/ |
H A D | MCInst.h | 112 MCOperand Op; local 113 Op.Kind = kRegister; 114 Op.RegVal = Reg; 115 return Op; 118 MCOperand Op; local 119 Op.Kind = kImmediate; 120 Op.ImmVal = Val; 121 return Op; 124 MCOperand Op; local 125 Op 130 MCOperand Op; local 136 MCOperand Op; local 157 setOpcode(unsigned Op) argument 167 addOperand(const MCOperand &Op) argument 177 insert(iterator I, const MCOperand &Op) argument [all...] |
H A D | MCWin64EH.h | 36 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg) argument 37 : Operation(Op), Label(L), Offset(0), Register(Reg) { 38 assert(Op == Win64EH::UOP_PushNonVol); 43 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg, unsigned Off) argument 44 : Operation(Op), Label(L), Offset(Off), Register(Reg) { 45 assert(Op == Win64EH::UOP_SetFPReg || 46 Op == Win64EH::UOP_SaveNonVol || 47 Op == Win64EH::UOP_SaveNonVolBig || 48 Op == Win64EH::UOP_SaveXMM128 || 49 Op 51 MCWin64EHInstruction(OpType Op, MCSymbol *L, bool Code) argument [all...] |
/external/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86IntelInstPrinter.cpp | 52 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op, argument 54 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; 76 void X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op, argument 78 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; 120 const MCOperand &Op = MI->getOperand(OpNo); local 121 if (Op.isImm()) 122 O << formatImm(Op.getImm()); 124 assert(Op.isExpr() && "unknown pcrel immediate operand"); 127 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 134 O << *Op 141 const MCOperand &Op = MI->getOperand(OpNo); local 152 printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O) argument [all...] |
H A D | X86ATTInstPrinter.cpp | 62 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op, argument 64 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; 86 void X86ATTInstPrinter::printAVXCC(const MCInst *MI, unsigned Op, argument 88 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; 132 const MCOperand &Op = MI->getOperand(OpNo); local 133 if (Op.isImm()) 134 O << formatImm(Op.getImm()); 136 assert(Op.isExpr() && "unknown pcrel immediate operand"); 139 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 146 O << *Op 153 const MCOperand &Op = MI->getOperand(OpNo); local 173 printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O) argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 543 MachineOperand Op(MachineOperand::MO_Immediate); 544 Op.setImm(Val); 545 return Op; 549 MachineOperand Op(MachineOperand::MO_CImmediate); 550 Op.Contents.CI = CI; 551 return Op; 555 MachineOperand Op(MachineOperand::MO_FPImmediate); 556 Op.Contents.CFP = CFP; 557 return Op; 567 MachineOperand Op(MachineOperan [all...] |
H A D | MachineRegisterInfo.h | 524 MachineOperand *Op; member in class:llvm::MachineRegisterInfo::defusechain_iterator 525 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 542 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 543 defusechain_iterator() : Op(0) {} 546 return Op == x.Op; 553 bool atEnd() const { return Op == 0; } 557 assert(Op && "Cannot increment end iterator!"); 558 Op [all...] |
/external/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 36 const MCOperand &Op = MI->getOperand(OpNo); local 37 if (Op.isImm()) 38 O << Op.getImm(); 40 assert(Op.isExpr() && "unknown pcrel immediate operand"); 41 O << *Op.getExpr(); 48 const MCOperand &Op = MI->getOperand(OpNo); local 49 if (Op.isReg()) { 50 O << getRegisterName(Op.getReg()); 51 } else if (Op.isImm()) { 52 O << '#' << Op [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) argument 82 switch (Op.getOpcode()) { 84 Op.getNode()->dump(); 89 case ISD::SDIV: return LowerSDIV(Op, DAG); 90 case ISD::SREM: return LowerSREM(Op, DAG); 91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 93 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 95 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 96 case ISD::UDIVREM: return LowerUDIVREM(Op, DA 101 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const argument 149 LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const argument 163 LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const argument 180 LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const argument [all...] |
H A D | AMDGPUISelLowering.h | 27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 38 bool isHWTrueValue(SDValue Op) const; 39 bool isHWFalseValue(SDValue Op) const; 56 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 57 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; 58 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; 67 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 84 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const; 85 SDValue LowerSREM8(SDValue Op, SelectionDA [all...] |
H A D | R600ISelLowering.h | 29 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 44 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 47 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; 49 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 50 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUISelLowering.cpp | 79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) argument 82 switch (Op.getOpcode()) { 84 Op.getNode()->dump(); 89 case ISD::SDIV: return LowerSDIV(Op, DAG); 90 case ISD::SREM: return LowerSREM(Op, DAG); 91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 93 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 95 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 96 case ISD::UDIVREM: return LowerUDIVREM(Op, DA 101 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const argument 149 LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const argument 163 LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const argument 180 LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const argument [all...] |
H A D | AMDGPUISelLowering.h | 27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 38 bool isHWTrueValue(SDValue Op) const; 39 bool isHWFalseValue(SDValue Op) const; 56 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 57 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; 58 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; 67 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 84 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const; 85 SDValue LowerSREM8(SDValue Op, SelectionDA [all...] |
H A D | R600ISelLowering.h | 29 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 44 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 47 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; 49 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 50 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.h | 28 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 29 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 40 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 43 bool isHWTrueValue(SDValue Op) const; 44 bool isHWFalseValue(SDValue Op) const; 66 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 67 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; 68 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; 69 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const; 82 virtual void computeMaskedBitsForTargetNode(const SDValue Op, [all...] |
H A D | R600ISelLowering.h | 29 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 56 SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const; 58 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 59 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 60 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 61 SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const; 62 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 63 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const; 64 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 70 bool isZero(SDValue Op) cons [all...] |
H A D | AMDGPUISelLowering.cpp | 171 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) argument 173 switch (Op.getOpcode()) { 175 Op.getNode()->dump(); 180 case ISD::SDIV: return LowerSDIV(Op, DAG); 181 case ISD::SREM: return LowerSREM(Op, DAG); 182 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); 183 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 185 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 186 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); 188 return Op; 191 LowerGlobalAddress(AMDGPUMachineFunction* MFI, SDValue Op, SelectionDAG &DAG) const argument 211 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const argument 251 LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const argument 264 LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const argument 279 LowerMinMax(SDValue Op, SelectionDAG &DAG) const argument 340 LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 54 SDValue LegalizeOp(SDValue Op); 56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result); 58 SDValue UnrollVSETCC(SDValue Op); 63 SDValue ExpandUINT_TO_FLOAT(SDValue Op); 65 SDValue ExpandSEXTINREG(SDValue Op); 68 SDValue ExpandVSELECT(SDValue Op); 69 SDValue ExpandSELECT(SDValue Op); 70 SDValue ExpandLoad(SDValue Op); 71 SDValue ExpandStore(SDValue Op); 72 SDValue ExpandFNEG(SDValue Op); 131 TranslateLegalizeResults(SDValue Op, SDValue Result) argument 138 LegalizeOp(SDValue Op) argument 315 PromoteVectorOp(SDValue Op) argument 338 PromoteVectorOpINT_TO_FP(SDValue Op) argument 377 ExpandLoad(SDValue Op) argument 521 ExpandStore(SDValue Op) argument 572 ExpandSELECT(SDValue Op) argument 632 ExpandSEXTINREG(SDValue Op) argument 652 ExpandVSELECT(SDValue Op) argument 699 ExpandUINT_TO_FLOAT(SDValue Op) argument 739 ExpandFNEG(SDValue Op) argument 748 UnrollVSETCC(SDValue Op) argument [all...] |
/external/llvm/lib/Target/XCore/InstPrinter/ |
H A D | XCoreInstPrinter.cpp | 73 const MCOperand &Op = MI->getOperand(OpNo); local 74 if (Op.isReg()) { 75 printRegName(O, Op.getReg()); 79 if (Op.isImm()) { 80 O << Op.getImm(); 84 assert(Op.isExpr() && "unknown operand kind in printOperand"); 85 printExpr(Op.getExpr(), O);
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/external/chromium_org/third_party/skia/src/utils/ |
H A D | SkCanvasStack.h | 29 virtual void addCanvas(SkCanvas*) SK_OVERRIDE { SkASSERT(!"Invalid Op"); } 30 virtual void removeCanvas(SkCanvas*) SK_OVERRIDE { SkASSERT(!"Invalid Op"); } 33 virtual bool clipRect(const SkRect&, SkRegion::Op, bool) SK_OVERRIDE; 34 virtual bool clipRRect(const SkRRect&, SkRegion::Op, bool) SK_OVERRIDE; 35 virtual bool clipPath(const SkPath&, SkRegion::Op, bool) SK_OVERRIDE; 37 SkRegion::Op) SK_OVERRIDE;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.h | 100 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 103 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 104 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 105 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; 106 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const; 107 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 113 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const; 114 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 127 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 128 SDValue LowerFRAMEADDR(SDValue Op, SelectionDA [all...] |
/external/skia/src/utils/ |
H A D | SkCanvasStack.h | 29 virtual void addCanvas(SkCanvas*) SK_OVERRIDE { SkASSERT(!"Invalid Op"); } 30 virtual void removeCanvas(SkCanvas*) SK_OVERRIDE { SkASSERT(!"Invalid Op"); } 33 virtual bool clipRect(const SkRect&, SkRegion::Op, bool) SK_OVERRIDE; 34 virtual bool clipRRect(const SkRRect&, SkRegion::Op, bool) SK_OVERRIDE; 35 virtual bool clipPath(const SkPath&, SkRegion::Op, bool) SK_OVERRIDE; 37 SkRegion::Op) SK_OVERRIDE;
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 563 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 584 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const; 601 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 609 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 632 virtual void LowerAsmOperandForConstraint(SDValue Op, 755 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 830 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 836 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 837 SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const; 838 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDA [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 172 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 203 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 227 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 228 SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 229 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 230 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 231 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 232 SDValue LowerF128ToCall(SDValue Op, SelectionDAG &DAG, 234 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 235 SDValue LowerFP_ROUND(SDValue Op, SelectionDA [all...] |