Searched refs:Operands (Results 1 - 25 of 57) sorted by relevance

123

/external/llvm/utils/TableGen/
H A DAsmWriterInst.h87 std::vector<AsmWriterOperand> Operands; member in class:llvm::AsmWriterInst
104 if (!Operands.empty() &&
105 Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
106 Operands.back().Str.append(Str);
108 Operands.push_back(AsmWriterOperand(Str));
H A DFastISelEmitter.cpp116 SmallVector<OpKind, 3> Operands;
119 return Operands < O.Operands;
122 return Operands == O.Operands;
125 bool empty() const { return Operands.empty(); }
128 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
129 if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
138 for (unsigned i = 0, e = Operands
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H A DAsmWriterInst.cpp87 Operands.push_back(
119 Operands.push_back(
196 Operands.push_back(AsmWriterOperand("PrintSpecial",
202 unsigned OpNo = CGI.Operands.getOperandNamed(VarName);
203 CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo];
206 Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName,
213 Operands.push_back(AsmWriterOperand("return;",
222 if (Operands.size() != Other.Operands.size()) return ~1;
225 for (unsigned i = 0, e = Operands
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H A DPseudoLoweringEmitter.cpp92 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
96 Insn.Operands[BaseIdx + i].Rec->getName() + "'");
100 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
102 OpsAdded += Insn.Operands[i].MINumOperands;
145 if (Insn.Operands.size() != Dag->getNumArgs())
150 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
151 NumMIOperands += Insn.Operands[i].MINumOperands;
159 // Operands that are a sublass of OperandWithDefaultOp have default values.
170 for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i)
171 SourceOperands[SourceInsn.Operands[
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H A DInstrInfoEmitter.cpp63 std::map<std::string, unsigned> &Operands,
90 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
99 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
103 OperandList.push_back(Inst.Operands[i]);
105 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
106 OperandList.push_back(Inst.Operands[i]);
136 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
141 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
146 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.");
147 Res += Inst.Operands[
201 initOperandMapData( const std::vector<const CodeGenInstruction *> NumberedInstructions, const std::string &Namespace, std::map<std::string, unsigned> &Operands, OpNameMapTy &OperandMap) argument
247 std::map<std::string, unsigned> Operands; local
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H A DAsmWriterEmitter.cpp108 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
111 O << " " << FirstInst.Operands[i].getCode();
119 FirstInst.Operands[i]));
125 AWI.Operands[i]));
155 if (Inst->Operands.empty())
158 Command = " " + Inst->Operands[0].getCode() + "\n";
197 if (!FirstInst || FirstInst->Operands.size() == Op)
205 size_t MaxSize = FirstInst->Operands.size();
216 OtherInst->Operands.size() > FirstInst->Operands
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H A DCodeEmitterGen.cpp131 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
133 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
134 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
137 unsigned NumberOps = CGI.Operands.size();
141 CGI.Operands.isFlatOperandNotEmitted(NumberedOp))
147 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
148 std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
H A DCodeGenInstruction.cpp292 : TheDef(R), Operands(R), InferredFrom(0) {
306 isPredicable = Operands.isPredicable || R->getValueAsBit("isPredicable");
335 ParseConstraints(R->getValueAsString("Constraints"), Operands);
338 Operands.ProcessDisableEncoding(R->getValueAsString("DisableEncoding"));
501 // If both are Operands with the same MVT, allow the conversion. It's
549 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
554 if (ResultInst->Operands[i].MINumOperands == 1 &&
555 ResultInst->Operands[i].getTiedRegister() != -1)
561 Record *InstOpRec = ResultInst->Operands[i].Rec;
562 unsigned NumSubOps = ResultInst->Operands[
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H A DX86RecognizableInstr.h103 const std::vector<CGIOperandList::OperandInfo>* Operands; member in class:llvm::X86Disassembler::RecognizableInstr
/external/llvm/include/llvm/MC/
H A DMCInst.h153 SmallVector<MCOperand, 8> Operands; member in class:llvm::MCInst
163 const MCOperand &getOperand(unsigned i) const { return Operands[i]; }
164 MCOperand &getOperand(unsigned i) { return Operands[i]; }
165 unsigned getNumOperands() const { return Operands.size(); }
168 Operands.push_back(Op);
171 void clear() { Operands.clear(); }
172 size_t size() { return Operands.size(); }
175 iterator begin() { return Operands.begin(); }
176 iterator end() { return Operands.end(); }
178 return Operands
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H A DMCTargetAsmParser.h125 /// \param Operands [out] - The list of parsed operands, this returns
130 SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;
156 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
176 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;
/external/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp314 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
322 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
326 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
344 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
348 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
354 parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument
355 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
358 parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument
359 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
362 parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument
366 parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
370 parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
374 parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
378 parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
382 parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
386 parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
390 parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
394 parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
398 parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
402 parseBDLAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
411 parsePCRel16(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
415 parsePCRel32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
489 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands, RegisterGroup Group, const unsigned *Regs, RegisterKind Kind) argument
558 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands, const unsigned *Regs, RegisterKind RegKind, MemoryKind MemKind) argument
615 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
648 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Mnemonic) argument
693 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument
746 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
761 parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands, int64_t MinVal, int64_t MaxVal) argument
[all...]
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp69 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
76 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
84 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
92 ParseNEONLane(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
96 ParseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
100 ParseImmWithLSLOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
103 ParseCondCodeOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
106 ParseCRxOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
109 ParseFPImmOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
112 ParseNamedImmOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument
1172 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Mnemonic) argument
1281 ParseNEONLane(SmallVectorImpl<MCParsedAsmOperand*> &Operands, uint32_t NumLanes) argument
1385 ParseImmWithLSLOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1437 ParseCondCodeOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1457 ParseCRxOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1489 ParseFPImmOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1582 ParseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands, uint32_t &NumLanes) argument
1639 ParseNamedImmOperand(const NamedImmMapper &Mapper, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1686 ParseSysRegOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1706 ParseLSXAddressOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1756 ParseShiftExtend( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1829 validateInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1917 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
2056 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument
[all...]
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp71 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
79 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
84 parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
88 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
91 parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
94 parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
97 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
100 parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
103 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
106 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
727 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument
921 tryParseRegisterOperand( SmallVectorImpl<MCParsedAsmOperand*> &Operands, bool is64BitReg) argument
1270 parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands, int RegKind) argument
1306 parseGPR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1314 parseGPR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1319 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1330 parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1340 parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1347 parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1380 parseACRegsDSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1412 searchSymbolAlias( SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) argument
1474 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1501 parseHW64Regs( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1531 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
1581 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
[all...]
/external/llvm/include/llvm/Analysis/
H A DScalarEvolutionExpressions.h139 const SCEV *const *Operands; member in class:llvm::SCEVNAryExpr
144 : SCEV(ID, T), Operands(O), NumOperands(N) {}
150 return Operands[i];
154 op_iterator op_begin() const { return Operands; }
155 op_iterator op_end() const { return Operands + NumOperands; }
293 const SCEV *getStart() const { return Operands[0]; }
581 SmallVector<const SCEV *, 2> Operands; local
583 Operands.push_back(visit(Expr->getOperand(i)));
584 return SE.getAddExpr(Operands);
588 SmallVector<const SCEV *, 2> Operands; local
599 SmallVector<const SCEV *, 2> Operands; local
607 SmallVector<const SCEV *, 2> Operands; local
614 SmallVector<const SCEV *, 2> Operands; local
672 SmallVector<const SCEV *, 2> Operands; local
[all...]
H A DConstantFolding.h98 Constant *ConstantFoldCall(Function *F, ArrayRef<Constant *> Operands,
/external/llvm/lib/Analysis/
H A DScalarEvolutionNormalization.cpp109 SmallVector<const SCEV *, 8> Operands; local
116 Operands.push_back(TransformSubExpr(*I, LUser, 0));
119 const SCEV *Result = SE.getAddRecExpr(Operands, L, SCEV::FlagAnyWrap);
160 SmallVector<const SCEV *, 8> Operands; local
168 Operands.push_back(N);
173 case scAddExpr: return SE.getAddExpr(Operands);
174 case scMulExpr: return SE.getMulExpr(Operands);
175 case scSMaxExpr: return SE.getSMaxExpr(Operands);
176 case scUMaxExpr: return SE.getUMaxExpr(Operands);
H A DTargetTransformInfo.cpp58 const Value *Ptr, ArrayRef<const Value *> Operands) const {
59 return PrevTTI->getGEPCost(Ptr, Operands);
299 ArrayRef<const Value *> Operands) const {
302 for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
303 if (!isa<Constant>(Operands[Idx]))
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp524 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
568 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
1856 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1924 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
1927 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1946 Operands.push_back(X86Operand::CreateToken("*", Loc));
1952 Operands.push_back(Op);
1963 Operands.push_back(Op);
1983 Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
1989 Operands
1855 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
2226 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument
[all...]
/external/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp229 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
231 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
270 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
277 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2659 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2682 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2742 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2746 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2760 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument
2766 Operands
2658 tryParseShiftRegister( SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
2846 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
2883 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
2902 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
2920 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
2998 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3180 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3431 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3493 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3544 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3578 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3706 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, int Low, int High) argument
3754 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3783 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3853 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3899 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
3967 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4016 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4089 cvtThumbMultiply(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4108 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4357 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4432 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Mnemonic) argument
4734 shouldOmitCCOutOperand(StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
4860 shouldOmitPredicateOperand( StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) argument
4906 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
5215 validateInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
5652 processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
7468 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument
8014 SmallVector<MCParsedAsmOperand *, 1> Operands; member in struct:__anon21372::CleanupObject
[all...]
/external/llvm/lib/Transforms/IPO/
H A DArgumentPromotion.cpp372 IndicesVector Operands; local
376 Operands.clear();
382 Operands.push_back(0);
399 Operands.push_back(C->getSExtValue());
419 // is safe if Operands, or a prefix of Operands, is marked as safe.
420 if (!PrefixIn(Operands, SafeToUnconditionallyLoad))
426 if (ToPromote.find(Operands) == ToPromote.end()) {
435 ToPromote.insert(Operands);
833 IndicesVector Operands; local
[all...]
/external/llvm/test/MC/X86/
H A Dx86_operands.s30 # Indirect Memory Operands
/external/llvm/lib/CodeGen/
H A DMachineInstr.cpp534 : MCID(&tid), Parent(0), Operands(0), NumOperands(0),
541 Operands = MF.allocateOperandArray(CapOperands);
551 : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0),
556 Operands = MF.allocateOperandArray(CapOperands);
580 if (Operands[i].isReg())
581 MRI.removeRegOperandFromUseList(&Operands[i]);
589 if (Operands[i].isReg())
590 MRI.addRegOperandToUseList(&Operands[i]);
626 if (&Op >= Operands && &Op < Operands
[all...]
/external/llvm/lib/IR/
H A DMetadata.cpp253 // Coallocate space for the node and Operands together, then placement new.
523 static SmallVector<TrackingVH<MDNode>, 4> &getNMDOps(void *Operands) { argument
524 return *(SmallVector<TrackingVH<MDNode>, 4>*)Operands;
529 Operands(new SmallVector<TrackingVH<MDNode>, 4>()) {
534 delete &getNMDOps(Operands);
539 return (unsigned)getNMDOps(Operands).size();
545 return dyn_cast<MDNode>(&*getNMDOps(Operands)[i]);
552 getNMDOps(Operands).push_back(TrackingVH<MDNode>(M));
563 getNMDOps(Operands).clear();
/external/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp197 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
204 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
233 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
570 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
852 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
857 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
861 ProcessInstruction(Inst, Operands);
872 if (ErrorInfo >= Operands.size())
875 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
1095 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { argument
569 ProcessInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
851 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out, unsigned &ErrorInfo, bool MatchingInlineAsm) argument
1196 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument
[all...]

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