| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 705 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
731 SETGE, // 1 X 0 1 1 True if greater than or equal enumerator in enum:llvm::ISD::CondCode
743 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
|
| /external/llvm/lib/Target/R600/ |
| H A D | AMDGPUISelLowering.cpp | 322 case ISD::SETGE:
395 ISD::SETGE);
401 ISD::SETGE);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDGPUISelLowering.cpp | 236 ISD::SETGE);
242 ISD::SETGE);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDGPUISelLowering.cpp | 236 ISD::SETGE);
242 ISD::SETGE);
|
| /external/llvm/lib/CodeGen/ |
| H A D | Analysis.cpp | 179 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE;
193 case ICmpInst::ICMP_SGE: return ISD::SETGE;
|
| H A D | TargetLoweringBase.cpp | 599 CCs[RTLIB::OGE_F32] = ISD::SETGE;
600 CCs[RTLIB::OGE_F64] = ISD::SETGE;
601 CCs[RTLIB::OGE_F128] = ISD::SETGE;
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1599 case ISD::SETGE: return A64CC::GE;
1647 case ISD::SETGE:
1663 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1695 case ISD::SETGE:
2350 case ISD::SETGE:
2439 case ISD::SETGE:
2440 CC = ISD::SETGE;
2458 CC = ISD::SETGE;
2474 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGE));
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 588 case ISD::SETGE: return PPC::PRED_GE;
612 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
651 case ISD::SETGE:
820 case ISD::SETGE:
|
| H A D | PPCISelLowering.cpp | 4689 case ISD::SETGE:
4725 case ISD::SETGE:
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 303 case ISD::SETGE: return "setge";
|
| H A D | TargetLowering.cpp | 122 case ISD::SETGE:
1251 case ISD::SETGE:
1407 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1412 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1425 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1805 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
|
| H A D | LegalizeIntegerTypes.cpp | 849 case ISD::SETGE:
2031 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2032 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2037 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2559 case ISD::SETGE:
2587 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
|
| H A D | LegalizeDAG.cpp | 1651 case ISD::SETGE:
3424 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3425 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3430 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
|
| H A D | LegalizeFloatTypes.cpp | 1383 ISD::SETGE);
|
| H A D | SelectionDAG.cpp | 259 case ISD::SETGE: return 1;
1596 case ISD::SETGE: return getConstant(C1.sge(C2), VT);
1627 case ISD::SETGE: if (R==APFloat::cmpUnordered)
|
| H A D | DAGCombiner.cpp | 4237 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
9800 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
10032 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 453 case ISD::SETGE: return IsV216;
|
| H A D | MipsISelLowering.cpp | 469 case ISD::SETGE:
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1203 case ISD::SETGE: return SPCC::ICC_GE;
1226 case ISD::SETGE:
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1185 case ISD::SETGE: return ARMCC::GE;
1205 case ISD::SETGE:
3048 case ISD::SETGE:
3064 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3750 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3784 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
4032 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4065 case ISD::SETGE: Opc = ARMISD::VCGE; break;
9746 case ISD::SETGE:
9758 if ((CC == ISD::SETGE || C
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 751 case ISD::SETGE:
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 3418 case ISD::SETGE: return X86::COND_GE;
3463 case ISD::SETGE: return X86::COND_AE;
9618 case ISD::SETGE: Swap = true; // Fallthrough
9725 case ISD::SETGE: Swap = true;
10803 CC = ISD::SETGE;
10833 CC = ISD::SETGE;
15892 case ISD::SETGE:
15910 case ISD::SETGE:
16002 case ISD::SETGE:
16036 case ISD::SETGE
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/x86/ |
| H A D | assyntax.h | 620 #define SETGE(a) CHOICE(setge a, setge a, setge a) macro
1341 #define SETGE(a) setge a macro
|
| /external/mesa3d/src/mesa/x86/ |
| H A D | assyntax.h | 620 #define SETGE(a) CHOICE(setge a, setge a, setge a) macro
1341 #define SETGE(a) setge a macro
|