| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 50 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
54 GenericValue Src2, Type *Ty) {
65 GenericValue Src2, Type *Ty) {
76 GenericValue Src2, Type *Ty) {
87 GenericValue Src2, Type *Ty) {
98 GenericValue Src2, Type *Ty) {
101 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
104 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
114 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
119 assert(Src1.AggregateVal.size() == Src2
53 executeFAddInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument
64 executeFSubInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument
75 executeFMulInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument
86 executeFDivInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument
97 executeFRemInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument
136 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument
150 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument
164 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 160 MachineOperand &Src2 = MI->getOperand(2); local
164 unsigned SrcReg = Src2.getReg();
177 MachineOperand &Src2 = MI->getOperand(2); local
178 if (Src2.getImm() != 32)
|
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1501 SDValue Src2 = Node->getVal(); local
1508 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Src2)) {
1510 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
1534 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
1538 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
1543 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
1870 // Src2 ca
1874 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3)); local
1996 unsigned Src2 = MI->getOperand(3).getReg(); local
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 1902 unsigned Src2 = MI->getOperand(2).getReg(); local
1906 if (Src == Src2) {
1921 .addReg(Src2, getKillRegState(isKill2));
1925 LV->replaceKillInstruction(Src2, MI, InsMI2);
2151 const MachineOperand &Src2 = MI->getOperand(2); local
2155 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2172 if (LV && Src2.isKill())
2181 unsigned Src2 = MI->getOperand(2).getReg(); local
2185 Src.getReg(), Src.isKill(), Src2, isKill2);
2194 LV->replaceKillInstruction(Src2, M
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 2896 SDValue Src2 = getValue(I.getOperand(1)); local
2908 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2919 // First check for Src1 in low and Src2 in high
2924 VT, Src1, Src2));
2927 // Then check for Src2 in low and Src1 in high
2932 VT, Src2, Src1));
2940 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2946 MOps2[0] = Src2;
2951 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2964 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 6661 unsigned Src2 = MI->getOperand(2).getReg(); local
6675 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
|