Searched refs:cycles (Results 1 - 25 of 70) sorted by relevance

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/external/antlr/antlr-3.4/tool/src/main/java/org/antlr/tool/
H A DLeftRecursionCyclesMessage.java35 * cycles found by walking rules without decisions; the other msg is
39 public Collection cycles; field in class:LeftRecursionCyclesMessage
41 public LeftRecursionCyclesMessage(Collection cycles) { argument
43 this.cycles = cycles;
48 st.add("listOfCycles", cycles);
/external/oprofile/events/mips/rm7000/
H A Devents4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Clock cycles
13 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
25 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache miss stall cycles (cycles where both cache miss tokens taken and a third try is requested)
27 event:0x17 counters:0,1 um:zero minimum:500 name:FP_EXCEPTION_STALL_CYCLES : FP possible exception cycles
29 event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Coprocessor 0 slip cycles
30 event:0x1a counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_PENDING_NON_BLKING_LOAD : Slip cycles due to pending non-blocking loads
31 event:0x1c counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Write buffer full stall cycles
32 event:0x1d counters:0,1 um:zero minimum:500 name:CACHE_INSTRUCTION_STALL_CYCLES : Cache instruction stall cycles
33 event:0x1e counters:0,1 um:zero minimum:500 name:MULTIPLIER_STALL_CYCLES : Multiplier stall cycles
[all...]
/external/oprofile/events/mips/rm9000/
H A Devents4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
12 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
24 event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache-miss stall cycles
26 event:0x17 counters:0,1 um:zero minimum:500 name:FP_POSSIBLE_EXCEPTION_CYCLES : Floating-point possible exception cycles
27 event:0x18 counters:0,1 um:zero minimum:500 name:MULTIPLIER_BUSY_SLIP_CYCLES : Slip cycles due to busy multiplier
28 event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Co-processor 0 slip cycles
29 event:0x1a counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_SLIP_CYCLES : Slip cycles due to pending non-blocking loads
30 event:0x1b counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Stall cycles due to a full write buffer
31 event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES : Stall cycles due to cache instructions
32 event:0x1e counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_PENDING_EXCEPTION_STALL_CYCLES : Stall cycles du
[all...]
/external/oprofile/events/mips/24K/
H A Devents36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 24K family microarchitecture)
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
53 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
55 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
56 event:0x26 counters:0 um:zero minimum:500 name:SYNC_STALLS : 38-0 SYNC stall cycles
58 event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
59 event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
60 event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
[all...]
/external/oprofile/events/mips/34K/
H A Devents36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
57 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
59 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
62 event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
63 event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
64 event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
65 event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles
[all...]
/external/oprofile/events/mips/1004K/
H A Devents36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
55 event:0x24 counters:0 um:zero minimum:500 name:INTERVENTION_STALLS : 36-0 Cache coherence intervention processing stall cycles
58 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
60 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
63 event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
64 event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
65 event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
[all...]
/external/chromium/chrome/browser/ui/gtk/
H A Dhover_controller_gtk.h27 // Throb for |cycles| cycles. This will override the current remaining
28 // number of cycles. Note that a "cycle" is (somewhat unintuitively) half of
30 void StartThrobbing(int cycles);
H A Dhover_controller_gtk.cc39 void HoverControllerGtk::StartThrobbing(int cycles) { argument
40 throb_animation_.StartThrobbing(cycles);
/external/chromium_org/chrome/browser/ui/gtk/
H A Dhover_controller_gtk.h27 // Throb for |cycles| cycles. This will override the current remaining
28 // number of cycles. Note that a "cycle" is (somewhat unintuitively) half of
30 void StartThrobbing(int cycles);
H A Dhover_controller_gtk.cc40 void HoverControllerGtk::StartThrobbing(int cycles) { argument
41 throb_animation_.StartThrobbing(cycles);
/external/oprofile/events/mips/74K/
H A Devents21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
26 event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles
31 event:0xd counters:0,2 um:zero minimum:500 name:DDQ0_FULL_DR_STALLS : 13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full
32 event:0xe counters:0,2 um:zero minimum:500 name:ALCB_FULL_DR_STALLS : 14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full
33 event:0xf counters:0,2 um:zero minimum:500 name:CLDQ_FULL_DR_STALLS : 15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) full
34 event:0x10 counters:0,2 um:zero minimum:500 name:ALU_EMPTY_CYCLES : 16-0 DDQ0 (ALU out-of-order dispatch queue) empty cycles
35 event:0x11 counters:0,2 um:zero minimum:500 name:ALU_OPERANDS_NOT_READY_CYCLES : 17-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready
36 event:0x12 counters:0,2 um:zero minimum:500 name:ALU_NO_ISSUES_CYCLES : 18-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, MDU busy, or CorExt resource busy
38 event:0x14 counters:0,2 um:zero minimum:500 name:SINGLE_ISSUE_CYCLES : 20-0 Either DDQ0 (ALU out-of-order dispatch queue) or DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/llvmpipe/
H A Dlp_test_conv.c66 double cycles,
71 fprintf(fp, "%.1f\t", cycles / MAX2(src_type.length, dst_type.length));
163 int64_t cycles[LP_TEST_NUM_SAMPLES]; local
246 cycles[i] = end_counter - start_counter;
299 sum += cycles[i];
300 sum2 += cycles[i]*cycles[i];
309 if(fabs(cycles[i] - avg) <= 4.0*std) {
310 sum += cycles[i];
63 write_tsv_row(FILE *fp, struct lp_type src_type, struct lp_type dst_type, double cycles, boolean success) argument
/external/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_test_conv.c66 double cycles,
71 fprintf(fp, "%.1f\t", cycles / MAX2(src_type.length, dst_type.length));
163 int64_t cycles[LP_TEST_NUM_SAMPLES]; local
246 cycles[i] = end_counter - start_counter;
299 sum += cycles[i];
300 sum2 += cycles[i]*cycles[i];
309 if(fabs(cycles[i] - avg) <= 4.0*std) {
310 sum += cycles[i];
63 write_tsv_row(FILE *fp, struct lp_type src_type, struct lp_type dst_type, double cycles, boolean success) argument
/external/chromium_org/third_party/mesa/src/src/mesa/math/
H A Dm_debug_norm.c196 static int test_norm_function( normal_func func, int mtype, long *cycles )
209 (void) cycles;
285 BEGIN_RACE( *cycles );
287 END_RACE( *cycles );
349 printf( "counter overhead: %ld cycles\n\n", counter_overhead );
359 long *cycles = &benchmark_tab[mtype]; local
361 if ( test_norm_function( func, mtype, cycles ) == 0 ) {
H A Dm_debug_xform.c48 /* Overhead of profiling counter in cycles. Automatically adjusted to
169 int mtype, unsigned long *cycles )
179 (void) cycles;
246 BEGIN_RACE( *cycles );
248 END_RACE( *cycles );
295 printf("counter overhead: %lu cycles\n\n", counter_overhead );
314 unsigned long *cycles = &(benchmark_tab[psize-1][mtype]); local
316 if ( test_transform_function( func, psize, mtype, cycles ) == 0 ) {
H A Dm_debug_clip.c230 int psize, long *cycles )
241 (void) cycles;
282 BEGIN_RACE( *cycles );
284 END_RACE( *cycles );
365 printf( "counter overhead: %ld cycles\n\n", counter_overhead );
384 long *cycles = &(benchmark_tab[np][psize-1]); local
386 if ( test_cliptest_function( func, np, psize, cycles ) == 0 ) {
/external/mesa3d/src/mesa/math/
H A Dm_debug_norm.c196 static int test_norm_function( normal_func func, int mtype, long *cycles )
209 (void) cycles;
285 BEGIN_RACE( *cycles );
287 END_RACE( *cycles );
349 printf( "counter overhead: %ld cycles\n\n", counter_overhead );
359 long *cycles = &benchmark_tab[mtype]; local
361 if ( test_norm_function( func, mtype, cycles ) == 0 ) {
H A Dm_debug_xform.c48 /* Overhead of profiling counter in cycles. Automatically adjusted to
169 int mtype, unsigned long *cycles )
179 (void) cycles;
246 BEGIN_RACE( *cycles );
248 END_RACE( *cycles );
295 printf("counter overhead: %lu cycles\n\n", counter_overhead );
314 unsigned long *cycles = &(benchmark_tab[psize-1][mtype]); local
316 if ( test_transform_function( func, psize, mtype, cycles ) == 0 ) {
H A Dm_debug_clip.c230 int psize, long *cycles )
241 (void) cycles;
282 BEGIN_RACE( *cycles );
284 END_RACE( *cycles );
365 printf( "counter overhead: %ld cycles\n\n", counter_overhead );
384 long *cycles = &(benchmark_tab[np][psize-1]); local
386 if ( test_cliptest_function( func, np, psize, cycles ) == 0 ) {
/external/chromium_org/third_party/smhasher/src/
H A DSpeedTest.cpp220 double cycles = SpeedTest(hash,seed,trials,blocksize,align); local
222 double bestbpc = double(blocksize)/cycles;
237 double cycles = SpeedTest(hash,seed,trials,keysize,0); local
239 printf("%8.2f cycles/hash\n",cycles);
/external/chromium_org/base/test/
H A Dtest_launcher.cc432 int cycles = 1; local
434 StringToInt(command_line->GetSwitchValueASCII(kGTestRepeatFlag), &cycles);
437 while (cycles != 0) {
444 if (cycles != -1)
445 cycles--;
/external/chromium-trace/trace-viewer/src/tracing/importer/linux_perf/
H A Dbus_parser.js38 'w_bytes=(\\d+) cycles=(\\d+) ns=(\\d+)');
45 var cycles = parseInt(event[5]);
/external/oprofile/events/mips/vr5432/
H A Devents4 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
/external/oprofile/events/mips/vr5500/
H A Devents6 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
/external/oprofile/events/i386/westmere/
H A Dunit_masks62 0x01 ref_p Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
66 0x04 walk_cycles DTLB load miss page walk cycles
73 0x04 walk_cycles DTLB miss page walk cycles
95 0x01 lcp Length Change Prefix stall cycles
96 0x02 mru Stall cycles due to BPU MRU bypass
97 0x04 iq_full Instruction Queue full stall cycles
98 0x08 regen Regen stall cycles
99 0x0f any Any Instruction Length Decoder stall cycles
107 0x04 walk_cycles ITLB miss page walk cycles
128 0x04 cycles_stalled L1I instruction fetch stall cycles
[all...]

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