Searched refs:inw (Results 1 - 25 of 50) sorted by relevance

12

/external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/gas64/
H A Dgas-inout.asm2 inw $10, %ax label
5 inw $10 label
/external/grub/netboot/
H A Dsmc9000.c117 bank = inw(ioaddr + BANK_SELECT);
124 bank = inw(ioaddr + BANK_SELECT);
133 base_address_register = inw(ioaddr + BASE);
151 revision_register = inw(ioaddr + REVISION);
290 packet_no = inw(smc9000_base + FIFO_PORTS);
299 tx_status = inw( smc9000_base + DATA_1 );
307 _outw(inw(smc9000_base + TCR ) | TCR_ENABLE, smc9000_base + TCR );
332 if (inw(smc9000_base + FIFO_PORTS) & FP_RXEMPTY)
339 if (!(inw(smc9000_base + DATA_1) & RS_ERRORS)) {
341 nic->packetlen = (inw(smc9000_bas
[all...]
H A Dlance.c218 (void)inw(ioaddr+LANCE_RESET);
228 outw(inw(ioaddr+LANCE_BUS_IF) | 0x2, ioaddr+LANCE_BUS_IF);
238 media = inw(ioaddr+0x16) ;
252 check = inw(ioaddr+0x16) ;
275 (void)inw(ioaddr+LANCE_ADDR);
278 (void)inw(ioaddr+LANCE_ADDR);
281 (void)inw(ioaddr+LANCE_ADDR);
284 (void)inw(ioaddr+LANCE_ADDR);
288 if (inw(ioaddr+LANCE_DATA) & 0x100)
312 inw(ioadd
[all...]
H A D3c90x.c269 while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
303 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
307 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
308 val = inw(ioaddr + regEepromData_0_w);
326 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
330 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
334 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
339 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
343 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
412 while (inw(INF_3C90
[all...]
H A D3c509.c74 while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
89 while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
193 while (inw(BASE + EP_W1_FREE_TX) < (unsigned short)len + pad + 4)
211 while((inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS) != 0)
226 cst=inw(BASE + EP_STATUS);
241 status = inw(BASE + EP_W1_RX_STATUS);
265 status = inw(BASE + EP_W1_RX_STATUS);
289 while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS)
332 return (inw(IS_BASE + EP_W0_EEPROM_DATA));
370 data = (data << 1) | (inw(id_por
[all...]
H A Dsmc9000.h199 #define SMC_DELAY(x) { inw( x + RCR );\
200 inw( x + RCR );\
201 inw( x + RCR ); }
H A D3c595.c202 while (inw(BASE + VX_W1_FREE_TX) < len + pad + 4) {
221 while((inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) != 0)
236 cst=inw(BASE + VX_STATUS);
251 status = inw(BASE + VX_W1_RX_STATUS);
275 status = inw(BASE + VX_W1_RX_STATUS);
301 while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS);
346 return (inw(BASE + VX_W0_EEPROM_DATA));
355 vx_connectors = inw(BASE + VX_W3_RESET_OPT) & 0x7f;
H A Dcs89x0.c86 return inw(eth_nic_base + DATA_PORT);
424 status = inw(eth_nic_base + RX_FRAME_PORT);
425 nic->packetlen = inw(eth_nic_base + RX_FRAME_PORT);
428 nic->packet[nic->packetlen-1] = inw(eth_nic_base + RX_FRAME_PORT);
466 if ((inw(ioaddr + ADD_PORT) & ADD_MASK) != ADD_SIG)
471 if (inw(ioaddr + DATA_PORT) != CHIP_EISA_ID_SIG)
H A Dtiara.c145 len = inw(ioaddr + BMPR_MEM_PORT); /* throw away status */
146 len = inw(ioaddr + BMPR_MEM_PORT);
H A Deepro100.c334 retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0);
385 status = inw(ioaddr + SCBStatus);
391 t, s, status, inw (ioaddr + SCBCmd));
420 s1 = inw (ioaddr + SCBStatus);
424 s2 = inw (ioaddr + SCBStatus);
H A Deepro.c356 rcv_event = inw(ioaddr + IO_PORT);
359 rcv_status = inw(ioaddr + IO_PORT);
360 rcv_next_frame = inw(ioaddr + IO_PORT);
361 rcv_size = inw(ioaddr + IO_PORT);
425 status = inw(ioaddr + IO_PORT);
435 if (((status = inw(ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) {
H A D3c595.h296 #define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS)
425 #define is_eeprom_busy(b) (inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY)
H A Ddepca.c521 for (i = 0; i < 100 && !(inw(DEPCA_DATA) & IDON); i++)
545 if (inw(DEPCA_DATA) != STOP)
693 if (inw(DEPCA_DATA) != STOP)
H A Drtl8139.c213 fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex;
364 status = inw(ioaddr + IntrStatus);
399 status = inw(ioaddr + IntrStatus);
H A Depic100.c180 *ap++ = inw(lan0 + i*4);
480 return inw(mmdata);
/external/chromium_org/third_party/openssl/openssl/crypto/evp/
H A De_xcbc_d.c78 DES_cblock inw; member in struct:__anon13161
110 memcpy(&data(ctx)->inw[0],&key[8],8);
123 &data(ctx)->inw,
133 &data(ctx)->inw,
/external/openssl/crypto/evp/
H A De_xcbc_d.c78 DES_cblock inw; member in struct:__anon23648
110 memcpy(&data(ctx)->inw[0],&key[8],8);
123 &data(ctx)->inw,
133 &data(ctx)->inw,
/external/qemu-pc-bios/bochs/bios/
H A Drombios32start.S101 inw %dx, %ax
113 inw %dx, %ax
/external/chromium_org/third_party/openssl/openssl/crypto/des/
H A Ddes_old.c111 _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc)
114 length, (DES_key_schedule *)schedule, ivec, inw, outw, enc);
109 _ossl_old_des_xcbc_encrypt(_ossl_old_des_cblock *input,_ossl_old_des_cblock *output,long length, des_key_schedule schedule,_ossl_old_des_cblock *ivec, _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc) argument
H A Dxcbc_enc.c114 DES_cblock *ivec, const_DES_cblock *inw,
125 in2 = &(*inw)[0];
112 DES_xcbc_encrypt(const unsigned char *in, unsigned char *out, long length, DES_key_schedule *schedule, DES_cblock *ivec, const_DES_cblock *inw, const_DES_cblock *outw, int enc) argument
H A Ddes_old.h156 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\
157 DES_xcbc_encrypt((i),(o),(l),&(k),(iv),(inw),(outw),(e))
259 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\
260 _ossl_old_des_xcbc_encrypt((i),(o),(l),(k),(iv),(inw),(outw),(e))
347 _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc);
/external/openssl/crypto/des/
H A Ddes_old.c111 _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc)
114 length, (DES_key_schedule *)schedule, ivec, inw, outw, enc);
109 _ossl_old_des_xcbc_encrypt(_ossl_old_des_cblock *input,_ossl_old_des_cblock *output,long length, des_key_schedule schedule,_ossl_old_des_cblock *ivec, _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc) argument
H A Dxcbc_enc.c114 DES_cblock *ivec, const_DES_cblock *inw,
125 in2 = &(*inw)[0];
112 DES_xcbc_encrypt(const unsigned char *in, unsigned char *out, long length, DES_key_schedule *schedule, DES_cblock *ivec, const_DES_cblock *inw, const_DES_cblock *outw, int enc) argument
H A Ddes_old.h156 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\
157 DES_xcbc_encrypt((i),(o),(l),&(k),(iv),(inw),(outw),(e))
259 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\
260 _ossl_old_des_xcbc_encrypt((i),(o),(l),(k),(iv),(inw),(outw),(e))
347 _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc);
/external/chromium_org/third_party/openssl/openssl/include/openssl/
H A Ddes_old.h156 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\
157 DES_xcbc_encrypt((i),(o),(l),&(k),(iv),(inw),(outw),(e))
259 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\
260 _ossl_old_des_xcbc_encrypt((i),(o),(l),(k),(iv),(inw),(outw),(e))
347 _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc);

Completed in 216 milliseconds

12