Searched refs:um (Results 1 - 25 of 68) sorted by relevance

123

/external/oprofile/events/mips/5K/
H A Devents8 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
9 event:0x2 counters:0,1 um:zero minimum:500 name:LOADS_EXECED : Load/pref(x)/sync/cache-ops executed
10 event:0x3 counters:0,1 um:zero minimum:500 name:STORES_EXECED : Stores (including conditional stores) executed
11 event:0x4 counters:0,1 um:zero minimum:500 name:COND_STORES_EXECED : Conditional stores executed
16 event:0x1 counters:0 um:zero minimum:500 name:INSN_FETCHED : Instructions fetched
17 event:0x5 counters:0 um:zero minimum:500 name:FAILED_COND_STORES : Failed conditional stores
18 event:0x6 counters:0 um:zero minimum:500 name:BRANCHES_EXECED : Branches executed
19 event:0x7 counters:0 um:zero minimum:500 name:ITLB_MISSES : ITLB miss
20 event:0x8 counters:0 um:zero minimum:500 name:DTLB_MISSES : DTLB miss
21 event:0x9 counters:0 um
[all...]
/external/oprofile/events/mips/34K/
H A Devents14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um
[all...]
/external/oprofile/events/i386/atom/
H A Devents5 event:0x3c counters:0,1 um:cpu_clk_unhalted minimum:6000 name:CPU_CLK_UNHALTED : Clock cycles when not halted
6 event:0x3c counters:0,1 um:one minimum:6000 name:UNHALTED_REFERENCE_CYCLES : Unhalted reference cycles
7 event:0xc0 counters:0,1 um:one minimum:6000 name:INST_RETIRED : number of instructions retired
8 event:0x2e counters:0,1 um:x41 minimum:6000 name:LLC_MISSES : Last level cache demand requests from this core that missed the LLC
9 event:0x2e counters:0,1 um:x4f minimum:6000 name:LLC_REFS : Last level cache demand requests from this core
10 event:0xc4 counters:0,1 um:br_inst_retired minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
11 event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired (precise)
13 event:0x02 counters:0,1 um:store_forwards minimum:6000 name:STORE_FORWARDS : Good store forwards
14 event:0x06 counters:0,1 um:segment_reg_loads minimum:6000 name:SEGMENT_REG_LOADS : Number of segment register loads
15 event:0x07 counters:0,1 um
[all...]
/external/oprofile/events/mips/sb1/
H A Devents5 event:0x10 counters:0,1,2,3 um:zero minimum:500 name:CYCLES :Elapsed cycles
8 event:0x28 counters:1,2,3 um:zero minimum:500 name:ISSUE_L0 :Issue to L0
9 event:0x29 counters:1,2,3 um:zero minimum:500 name:ISSUE_L1 :Issue to L0
10 event:0x2a counters:1,2,3 um:zero minimum:500 name:ISSUE_E0 :Issue to E0
11 event:0x2b counters:1,2,3 um:zero minimum:500 name:ISSUE_E1 :Issue to E1
14 event:0x2f counters:1,2,3 um:zero minimum:500 name:BRANCH_MISSPREDICTS :Branch mispredicts
15 event:0x1d counters:1,2,3 um:zero minimum:500 name:MBOX_REPLAY :MBOX replay
16 event:0x1c counters:1,2,3 um:zero minimum:500 name:DCFIFO :DCFIFO
17 event:0x1e counters:1,2,3 um:zero minimum:500 name:DATA_DEPENDENCY_REPLAY :Data dependency replay
18 event:0x1b counters:1,2,3 um
[all...]
/external/dropbear/libtommath/
H A Dbn_mp_reduce.c25 int res, um = m->used; local
33 mp_rshd (&q, um - 1);
36 if (((unsigned long) um) > (((mp_digit)1) << (DIGIT_BIT - 1))) {
42 if ((res = s_mp_mul_high_digs (&q, mu, &q, um)) != MP_OKAY) {
46 if ((res = fast_s_mp_mul_high_digs (&q, mu, &q, um)) != MP_OKAY) {
58 mp_rshd (&q, um + 1);
61 if ((res = mp_mod_2d (x, DIGIT_BIT * (um + 1), x)) != MP_OKAY) {
66 if ((res = s_mp_mul_digs (&q, m, &q, um + 1)) != MP_OKAY) {
78 if ((res = mp_lshd (&q, um + 1)) != MP_OKAY)
/external/oprofile/events/mips/r10000/
H A Devents6 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
7 event:0x01 counters:0 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
8 event:0x01 counters:1 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated
9 event:0x02 counters:0 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_ISSUED : Load / prefetch / sync / CacheOp issued
10 event:0x02 counters:1 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_GRADUATED : Load / prefetch / sync / CacheOp graduated
11 event:0x03 counters:0 um:zero minimum:500 name:STORES_ISSUED : Stores issued
12 event:0x03 counters:1 um:zero minimum:500 name:STORES_GRADUATED : Stores graduated
13 event:0x04 counters:0 um:zero minimum:500 name:STORE_COND_ISSUED : Store conditional issued
14 event:0x04 counters:1 um:zero minimum:500 name:STORE_COND_GRADUATED : Store conditional graduated
15 event:0x05 counters:0 um
[all...]
/external/oprofile/events/mips/r12000/
H A Devents4 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : Cycles
5 event:0x1 counters:0,1,2,3 um:zero minimum:500 name:DECODED_INSTRUCTIONS : Decoded instructions
6 event:0x2 counters:0,1,2,3 um:zero minimum:500 name:DECODED_LOADS : Decoded loads
7 event:0x3 counters:0,1,2,3 um:zero minimum:500 name:DECODED_STORES : Decoded stores
8 event:0x4 counters:0,1,2,3 um:zero minimum:500 name:MISS_TABLE_OCCUPANCY : Miss Handling Table Occupancy
9 event:0x5 counters:0,1,2,3 um:zero minimum:500 name:FAILED_STORE_CONDITIONAL : Failed store conditional
10 event:0x6 counters:0,1,2,3 um:zero minimum:500 name:RESOLVED_BRANCH_CONDITIONAL : Resolved conditional branches
11 event:0x7 counters:0,1,2,3 um:zero minimum:500 name:QUADWORRDS_WRITEBACK_FROM_SC : Quadwords written back from secondary cache
12 event:0x8 counters:0,1,2,3 um:zero minimum:500 name:CORRECTABLE_ECC_ERRORS : Correctable ECC errors on secondary cache data
13 event:0x9 counters:0,1,2,3 um
[all...]
/external/oprofile/events/mips/rm7000/
H A Devents4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Clock cycles
5 event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Total instructions issued
6 event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
7 event:0x03 counters:0,1 um:zero minimum:500 name:INTEGER_INSTRUCTIONS_ISSUED : Integer instructions issued
8 event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
9 event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
10 event:0x06 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual issued pairs
11 event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_PREFETCHES : Branch prefetches
12 event:0x08 counters:0,1 um:zero minimum:500 name:EXTERNAL_CACHE_MISSES : External Cache Misses
13 event:0x09 counters:0,1 um
[all...]
/external/oprofile/events/mips/24K/
H A Devents14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um
[all...]
/external/oprofile/events/mips/vr5432/
H A Devents4 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
5 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : (Instructions executed)/2 and truncated
6 event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync)
7 event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Store execution
8 event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Branch execution (no jumps or jump registers)
9 event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : (FP instruction execution) / 2 and truncated excluding cp1 loads and stores
10 event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doublewords flushed to main memory (no uncached stores)
11 event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : JTLB refills
12 event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
13 event:0x9 counters:0,1 um
[all...]
/external/oprofile/events/mips/vr5500/
H A Devents6 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
7 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed
8 event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Execution of load/prefetch/cache instruction
9 event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Execution of store instruction
10 event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Execution of branch instruction
11 event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : Execution of floating-point instruction
12 event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doubleword flush to main memory
13 event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : TLB refill
14 event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache miss
15 event:0x9 counters:0,1 um
[all...]
/external/oprofile/events/x86-64/family11h/
H A Devents24 event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops
25 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles in which the FPU is empty
26 event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
29 event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads
30 event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
31 event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
32 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
33 event:0x24 counters:0,1,2,3 um:locked_ops minimum:500 name:LOCKED_OPS : Locked operations
38 event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
39 event:0x41 counters:0,1,2,3 um
[all...]
/external/oprofile/events/x86-64/hammer/
H A Devents22 event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops
23 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles with no FPU ops retired
24 event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
27 event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads
28 event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
29 event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
30 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
31 event:0x24 counters:0,1,2,3 um:locked_ops minimum:500 name:LOCKED_OPS : Locked operations
34 event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CLFLUSH_INSTRUCTIONS : Retired CLFLUSH instructions
35 event:0x27 counters:0,1,2,3 um
[all...]
/external/oprofile/events/mips/rm9000/
H A Devents4 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
5 event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
6 event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
7 event:0x03 counters:0,1 um:zero minimum:500 name:INT_INSTRUCTIONS_ISSUED : Integer instructions issued
8 event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
9 event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
10 event:0x06 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_DUAL_ISSUED : Dual-issued instruction pairs
11 event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_MISSPREDICTS : Branch mispredictions
12 event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
13 event:0x0a counters:0,1 um
[all...]
/external/oprofile/events/mips/1004K/
H A Devents14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
16 event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
21 event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
22 event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
23 event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um
[all...]
/external/oprofile/events/mips/20K/
H A Devents6 event:0x0 counters:0 um:zero minimum:500 name:CYCLES : CPU cycles
7 event:0x1 counters:0 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
8 event:0x2 counters:0 um:zero minimum:500 name:FETCH_GROUPS : Fetch groups entering CPU execution pipes
9 event:0x3 counters:0 um:zero minimum:500 name:FP_INSNS_COMPLETED : Instructions completed in FPU datapath (computational event:instructions only)
10 event:0x4 counters:0 um:zero minimum:500 name:TLB_REFILLS_TAKEN : Taken TLB refill exceptions
11 event:0x5 counters:0 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branches that mispredicted before completing execution
12 event:0x6 counters:0 um:zero minimum:500 name:BRANCHES_COMPLETED : Branches that completed execution
13 event:0x7 counters:0 um:zero minimum:500 name:JTLB_EXCEPTIONS : Taken Joint-TLB exceptions
14 event:0x8 counters:0 um:zero minimum:500 name:REPLAY_DUE_TO_LOAD_DEPENDENT_SPEC_DISPATCH : Replays due to load-dependent speculative dispatch
15 event:0x9 counters:0 um
[all...]
/external/oprofile/events/mips/25K/
H A Devents6 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : CPU cycles
7 event:0x1 counters:0,1 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
8 event:0x2 counters:0,1 um:zero minimum:500 name:FP_INSNS_ISSUED : FPU instructions issued
9 event:0x3 counters:0,1 um:zero minimum:500 name:INT_INSNS_ISSUED : Integer instructions issued
10 event:0x4 counters:0,1 um:zero minimum:500 name:LOAD_INSNS_ISSUED : Load instructions issued
11 event:0x5 counters:0,1 um:zero minimum:500 name:STORE_INSNS_ISSUED : Store instructions issued
12 event:0x6 counters:0,1 um:zero minimum:500 name:BRANCHES_JUMPS_ISSUED : Branch/Jump instructions issued
13 event:0x7 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual-issued pairs
14 event:0x8 counters:0,1 um:zero minimum:500 name:INSNS_COMPLETE : Instruction that completed execution (with or without exception)
15 event:0x9 counters:0,1 um
[all...]
/external/oprofile/events/i386/westmere/
H A Devents10 event:0x03 counters:0,1,2,3 um:x02 minimum:200000 name:LOAD_BLOCK : Loads that partially overlap an earlier store
11 event:0x04 counters:0,1,2,3 um:x07 minimum:200000 name:SB_DRAIN : All Store buffer stall cycles
12 event:0x05 counters:0,1,2,3 um:x02 minimum:200000 name:MISALIGN_MEM_REF : Misaligned store references
13 event:0x06 counters:0,1,2,3 um:store_blocks minimum:200000 name:STORE_BLOCKS : Loads delayed with at-Retirement block code
14 event:0x07 counters:0,1,2,3 um:x01 minimum:200000 name:PARTIAL_ADDRESS_ALIAS : False dependencies due to partial address aliasing
15 event:0x08 counters:0,1,2,3 um:dtlb_load_misses minimum:200000 name:DTLB_LOAD_MISSES : DTLB load misses
16 event:0x0b counters:0,1,2,3 um:mem_inst_retired minimum:2000000 name:MEM_INST_RETIRED : Memory instructions retired above 0 clocks (Precise Event)
17 event:0x0c counters:0,1,2,3 um:x01 minimum:200000 name:MEM_STORE_RETIRED : Retired stores that miss the DTLB (Precise Event)
18 event:0x0e counters:0,1,2,3 um:uops_issued minimum:2000000 name:UOPS_ISSUED : Uops issued
19 event:0x0f counters:0,1,2,3 um
[all...]
/external/oprofile/events/mips/74K/
H A Devents14 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : 0-0 Cycles
15 event:0x1 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions graduated
20 event:0x2 counters:0,2 um:zero minimum:500 name:PREDICTED_JR_31 : 2-0 JR $31 (return) instructions predicted including speculative instructions
21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
22 event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB accesses
24 event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions
25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
26 event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles
27 event:0x9 counters:0,2 um:zero minimum:500 name:IFU_REPLAYS : 9-0 Replays within the IFU due to full Instruction Buffer
29 event:0xb counters:0,2 um
[all...]
/external/oprofile/libop/
H A Dop_events.c34 static void free_unit_mask(struct op_unit_mask * um);
110 static void parse_um(struct op_unit_mask * um, char const * line) argument
136 free_unit_mask(um);
145 um->name = op_xstrndup(tagend, valueend - tagend);
151 um->unit_type_mask = utm_mandatory;
153 um->unit_type_mask = utm_bitmask;
155 um->unit_type_mask = utm_exclusive;
163 um->default_mask = parse_hex(tagend);
173 if (!um->name)
203 struct op_unit_mask * um local
210 free_unit_mask(struct op_unit_mask * um) argument
222 struct op_unit_mask * um = NULL; local
289 struct op_unit_mask * um = list_entry(pos, struct op_unit_mask, um_next); local
300 struct op_unit_mask * um = try_find_um(value); local
312 struct op_unit_mask *new, *um; local
537 check_unit_mask(struct op_unit_mask const * um, char const * cpu_name) argument
620 struct op_unit_mask * um = list_entry(pos, struct op_unit_mask, um_next); local
691 find_event_um(u32 nr, u32 um) argument
847 match_event(int i, struct op_event *event, unsigned um) argument
863 find_event_by_name(char const * name, unsigned um, int um_valid) argument
886 op_find_event(op_cpu cpu_type, u32 nr, u32 um) argument
904 op_check_events(int ctr, u32 nr, u32 um, op_cpu cpu_type) argument
[all...]
H A Dop_events.h44 } um[MAX_UNIT_MASK]; member in struct:op_unit_mask
45 struct list_head um_next; /**< next um in list */
68 struct op_event * op_find_event(op_cpu cpu_type, u32 nr, u32 um);
72 struct op_event * find_event_by_name(char const * name, unsigned um,
94 * @param um unit mask for counter
103 int op_check_events(int ctr, u32 event, u32 um, op_cpu cpu_type);
113 unsigned long um; member in struct:op_default_event_descr
/external/oprofile/events/i386/nehalem/
H A Devents10 event:0x3c counters:0,1,2,3 um:zero minimum:6000 name:CPU_CLK_UNHALTED : Clock cycles when not halted
11 event:0x3c counters:0,1,2,2 um:one minimum:6000 name:UNHALTED_REFERENCE_CYCLES : Unhalted reference cycles
12 event:0x2e counters:0,1,2,3 um:x41 minimum:6000 name:LLC_MISSES : Last level cache demand requests from this core that missed the LLC
13 event:0x2e counters:0,1,2,3 um:x4f minimum:6000 name:LLC_REFS : Last level cache demand requests from this core
14 event:0xc0 counters:0,1,2,3 um:inst_retired minimum:6000 name:INST_RETIRED : number of instructions retired
15 event:0xc4 counters:0,1,2,3 um:br_inst_retired minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
16 event:0xc5 counters:0,1,2,3 um:br_misp_retired minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired (precise)
18 event:0x02 counters:0,1,2,3 um:sb_forward minimum:6000 name:SB_FORWARD : Counts the number of store forwards.
19 event:0x03 counters:0,1,2,3 um:load_block minimum:6000 name:LOAD_BLOCK : Counts the number of loads blocked
20 event:0x04 counters:0,1,2,3 um
[all...]
/external/oprofile/daemon/
H A Dopd_events.h25 unsigned long um; member in struct:opd_event
/external/oprofile/libpp/
H A Dop_header.cpp169 string const op_print_event(op_cpu cpu_type, u32 type, u32 um, u32 count) argument
178 struct op_event * event = op_find_event(cpu_type, type, um);
192 if (event->unit->um[i].value == um)
193 um_desc = event->unit->um[i].desc;
203 ss << hex << setw(2) << setfill('0') << unsigned(um);
215 string const op_xml_print_event(op_cpu cpu_type, u32 type, u32 um, u32 count) argument
222 struct op_event * event = op_find_event(cpu_type, type, um);
233 str_out << um; local
/external/skia/gm/
H A Dshadertext3.cpp30 SkUnitMapper* um = NULL; local
32 um = new SkCosineMapper;
34 SkAutoUnref au(um);
37 SK_ARRAY_COUNT(kColors0), SkShader::kClamp_TileMode, um))->unref();

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