Searched refs:opc (Results 1 - 11 of 11) sorted by relevance

/dalvik/dexopt/
H A DOptMain.cpp133 const char* opc; local
136 opc = strstr(dexoptFlagStr, "v="); /* verification */
137 if (opc != NULL) {
138 switch (*(opc+2)) {
146 opc = strstr(dexoptFlagStr, "o="); /* optimization */
147 if (opc != NULL) {
148 switch (*(opc+2)) {
157 opc = strstr(dexoptFlagStr, "m=y"); /* register map */
158 if (opc != NULL) {
162 opc
[all...]
/dalvik/vm/compiler/codegen/mips/Mips32/
H A DFactory.cpp171 static MipsLIR *opCompareBranch(CompilationUnit *cUnit, MipsOpCode opc, int rs, int rt) argument
175 assert(opc >= kMipsBeqz && opc <= kMipsBnez);
176 res = newLIR1(cUnit, opc, rs);
178 assert(opc == kMipsBeq || opc == kMipsBne);
179 res = newLIR2(cUnit, opc, rs, rt);
914 MipsOpCode opc = kMipsNop; local
916 opc = kMipsBeqz;
918 opc
[all...]
H A DGen.cpp120 static void withCarryHelper(CompilationUnit *cUnit, MipsOpCode opc, argument
125 newLIR3(cUnit, opc, rlDest.lowReg, rlSrc1.lowReg, rlSrc2.lowReg);
127 newLIR3(cUnit, opc, rlDest.highReg, rlSrc1.highReg, rlSrc2.highReg);
128 newLIR3(cUnit, opc, rlDest.highReg, rlDest.highReg, tReg);
/dalvik/vm/compiler/codegen/x86/
H A DLowerAlu.cpp428 int common_alu_int(ALU_Opcode opc, u2 vA, u2 v1, u2 v2) { //except div and rem argument
433 alu_binary_VR_reg(OpndSize_32, opc, v2, 1, false);
442 int common_shift_int(ALU_Opcode opc, u2 vA, u2 v1, u2 v2) { argument
448 alu_binary_reg_reg(OpndSize_32, opc, PhysicalReg_ECX, true, 1, false);
767 int common_alu_int_lit(ALU_Opcode opc, u2 vA, u2 vB, s2 imm) { //except div and rem argument
769 alu_binary_imm_reg(OpndSize_32, opc, imm, 1, false);
774 int common_shift_int_lit(ALU_Opcode opc, u2 vA, u2 vB, s2 imm) { argument
775 return common_alu_int_lit(opc, vA, vB, imm);
790 int alu_rsub_int(ALU_Opcode opc, u2 vA, s2 imm, u2 vB) { argument
793 alu_binary_reg_reg(OpndSize_32, opc,
1133 common_alu_long(ALU_Opcode opc, u2 vA, u2 v1, u2 v2) argument
1512 common_alu_float(ALU_Opcode opc, u2 vA, u2 v1, u2 v2) argument
1623 common_alu_double(ALU_Opcode opc, u2 vA, u2 v1, u2 v2) argument
[all...]
H A DLower.h630 void fpu_VR(ALU_Opcode opc, OpndSize size, int vA);
688 void alu_unary_reg(OpndSize size, ALU_Opcode opc, int reg, bool isPhysical);
689 void alu_unary_mem(LowOp* op, OpndSize size, ALU_Opcode opc, int disp, int base_reg, bool isBasePhysical);
691 void alu_binary_imm_mem(OpndSize size, ALU_Opcode opc,
693 void alu_binary_imm_reg(OpndSize size, ALU_Opcode opc, int imm, int reg, bool isPhysical);
694 void alu_binary_mem_reg(OpndSize size, ALU_Opcode opc,
697 void alu_binary_VR_reg(OpndSize size, ALU_Opcode opc, int vA, int reg, bool isPhysical);
698 void alu_sd_binary_VR_reg(ALU_Opcode opc, int vA, int reg, bool isPhysical, bool isSD);
699 void alu_binary_reg_reg(OpndSize size, ALU_Opcode opc,
702 void alu_binary_reg_mem(OpndSize size, ALU_Opcode opc,
[all...]
H A DLowerHelper.cpp1048 void fpu_VR(ALU_Opcode opc, OpndSize size, int vA) { argument
1049 Mnemonic m = map_of_fpu_opcode_2_mnemonic[opc];
1212 void alu_unary_reg(OpndSize size, ALU_Opcode opc, int reg, bool isPhysical) { argument
1215 m = map_of_64_opcode_2_mnemonic[opc];
1217 m = map_of_alu_opcode_2_mnemonic[opc];
1223 void alu_unary_mem(LowOp* op, OpndSize size, ALU_Opcode opc, int disp, int base_reg, bool isBasePhysical) { argument
1226 m = map_of_64_opcode_2_mnemonic[opc];
1228 m = map_of_alu_opcode_2_mnemonic[opc];
1234 void alu_binary_imm_mem(OpndSize size, ALU_Opcode opc, int imm, int disp, int base_reg, bool isBasePhysical) { argument
1237 m = map_of_64_opcode_2_mnemonic[opc];
1245 alu_binary_imm_reg(OpndSize size, ALU_Opcode opc, int imm, int reg, bool isPhysical) argument
1256 alu_binary_mem_reg(OpndSize size, ALU_Opcode opc, int disp, int base_reg, bool isBasePhysical, int reg, bool isPhysical) argument
1267 alu_sd_binary_VR_reg(ALU_Opcode opc, int vA, int reg, bool isPhysical, bool isSD) argument
1320 alu_binary_VR_reg(OpndSize size, ALU_Opcode opc, int vA, int reg, bool isPhysical) argument
1369 alu_binary_reg_reg(OpndSize size, ALU_Opcode opc, int reg1, bool isPhysical1, int reg2, bool isPhysical2) argument
1382 alu_binary_reg_mem(OpndSize size, ALU_Opcode opc, int reg, bool isPhysical, int disp, int base_reg, bool isBasePhysical) argument
1395 fpu_mem(LowOp* op, ALU_Opcode opc, OpndSize size, int disp, int base_reg, bool isBasePhysical) argument
1402 alu_ss_binary_reg_reg(ALU_Opcode opc, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
1410 alu_sd_binary_reg_reg(ALU_Opcode opc, int reg, bool isPhysical, int reg2, bool isPhysical2) argument
[all...]
/dalvik/vm/compiler/codegen/x86/libenc/
H A Dencoder.h485 ENCODER_DECLARE_EXPORT char * alu(char * stream, ALU_Opcode opc, const RM_Opnd & rm, const Imm_Opnd & imm, Opnd_Size sz = size_platf);
486 ENCODER_DECLARE_EXPORT char * alu(char * stream, ALU_Opcode opc, const M_Opnd & m, const R_Opnd & r, Opnd_Size sz = size_platf);
487 ENCODER_DECLARE_EXPORT char * alu(char * stream, ALU_Opcode opc, const R_Opnd & r, const RM_Opnd & rm, Opnd_Size sz = size_platf);
494 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode opc, const RM_Opnd & rm, const Imm_Opnd & imm, Opnd_Size sz = size_platf);
495 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode opc, const RM_Opnd & rm, Opnd_Size sz = size_platf);
496 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode opc, const RM_Opnd & rm, const R_Opnd & r, const Imm_Opnd & imm, Opnd_Size sz = size_platf);
497 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode opc, const RM_Opnd & rm, const R_Opnd & r, Opnd_Size sz = size_platf);
617 //!char * fp_op_mem(char * stream, FP_Opcode opc,const M_Opnd& mem,int is_double);
620 //!char *fp_op(char * stream, FP_Opcode opc,unsigned i);
623 //!char * fp_op(char * stream, FP_Opcode opc,unsigne
[all...]
H A Dencoder.inl186 ENCODER_DECLARE_EXPORT char * alu(char * stream, ALU_Opcode opc, const RM_Opnd & rm, const Imm_Opnd & imm, Opnd_Size sz) {
190 return (char*)EncoderBase::encode(stream, map_alu(opc), args);
193 ENCODER_DECLARE_EXPORT char * alu(char * stream, ALU_Opcode opc, const M_Opnd & m, const R_Opnd & r, Opnd_Size sz) {
197 return (char*)EncoderBase::encode(stream, map_alu(opc), args);
200 ENCODER_DECLARE_EXPORT char * alu(char * stream, ALU_Opcode opc, const R_Opnd & r, const RM_Opnd & rm, Opnd_Size sz) {
204 return (char*)EncoderBase::encode(stream, map_alu(opc), args);
/dalvik/vm/compiler/codegen/mips/
H A DCodegenDriver.cpp350 MipsOpCode opc, int rs, int rt,
353 MipsLIR *branch = opCompareBranch(cUnit, opc, rs, rt);
838 MipsOpCode opc; local
866 opc = kMipsMflo;
873 opc = kMipsMfhi;
921 newLIR2(cUnit, opc, rlResult.lowReg, divReg);
2158 MipsOpCode opc = kMipsNop; local
2173 opc = kMipsBeqz;
2176 opc = kMipsBne;
2180 opc
349 genConditionalBranchMips(CompilationUnit *cUnit, MipsOpCode opc, int rs, int rt, MipsLIR *target) argument
2402 MipsOpCode opc; local
2666 MipsOpCode opc = kMipsNop; local
[all...]
/dalvik/vm/analysis/
H A DOptimize.cpp164 Opcode opc, quickOpc, volatileOpc; local
168 opc = dexOpcodeFromCodeUnit(*insns);
201 switch (opc) {
303 switch (opc) {
/dalvik/dx/etc/
H A Djasmin.jarMETA-INF/ META-INF/MANIFEST.MF jas/ jas/AnnotDefAttr.class AnnotDefAttr.java package jas ...

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