| /art/runtime/arch/arm/ |
| H A D | jni_entrypoints_arm.S | 24 push {r0, r1, r2, r3, lr} @ spill regs
25 .save {r0, r1, r2, r3, lr}
36 pop {r0, r1, r2, r3, lr} @ restore regs
41 pop {r0, r1, r2, r3, pc} @ restore regs and return to caller to handle exception
56 .cfi_rel_offset r2, 8
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| H A D | quick_entrypoints_arm.S | 91 .cfi_rel_offset r2, 4
107 ldrd r2, [sp, #12] @ restore non-callee saves r2-r3
153 mov r2, sp @ pass SP
162 mov r2, r9 @ pass Thread::Current
220 ldr r2, [sp, #48] @ pass caller Method*
251 * r2 = size of argument array in bytes
271 add r5, r2, #16 @ create space for method pointer in frame
278 ldr r2, [sp, #8] @ copy arg value for r2
[all...] |
| H A D | portable_entrypoints_arm.S | 24 * r2 = size of argument array in bytes
44 add r5, r2, #16 @ create space for method pointer in frame
51 ldr r2, [sp, #8] @ copy arg value for r2
74 .cfi_rel_offset r2, 4
88 mov r2, r9 @ pass Thread::Current
106 .cfi_rel_offset r2, 4
118 mov r2, r9 @ pass Thread::Current
126 ldrd r2, [sp, #12] @ restore non-callee saves r2
[all...] |
| /art/compiler/dex/quick/x86/ |
| H A D | int_x86.cc | 51 LoadValueDirectWideFixed(rl_src2, r2, r3);
52 // Compute (r1:r0) = (r1:r0) - (r3:r2)
53 OpRegReg(kOpSub, r0, r2); // r0 = r0 - r2
55 NewLIR2(kX86Set8R, r2, kX86CondL); // r2 = (r1:r0) < (r3:r2) ? 1 : 0
56 NewLIR2(kX86Movzx8RR, r2, r2);
57 OpReg(kOpNeg, r2); // r
[all...] |
| H A D | x86_lir.h | 39 * r2/edx: caller save | caller save, arg3 | caller, arg2, scratch, high half of long return
153 r2 = 2, enumerator in enum:art::X86NativeRegisterPool
154 rDX = r2,
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| /art/compiler/dex/quick/arm/ |
| H A D | call_arm.cc | 449 * r2 -> intial contents of object->lock, later result of strex
473 LoadWordDisp(rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2);
477 OpRegImm(kOpLsl, r2, LW_LOCK_OWNER_SHIFT);
479 NewLIR4(kThumb2Bfi, r2, r1, 0, LW_LOCK_OWNER_SHIFT - 1);
483 NewLIR4(kThumb2Strex, r1, r2, r0,
508 LoadWordDisp(rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2);
513 OpRegImm(kOpLsl, r2, LW_LOCK_OWNER_SHIFT);
515 OpRegReg(kOpSub, r1, r2);
557 * On entry, r0, r1, r2 & r3 are live. Let the register allocation
564 LockTemp(r2);
[all...] |
| H A D | target_arm.cc | 26 static int core_regs[] = {r0, r1, r2, r3, rARM_SUSPEND, r5, r6, r7, r8, rARM_SELF, r10,
33 static int core_temps[] = {r0, r1, r2, r3, r12};
225 "r2",
567 // Start allocation at r2 in an attempt to avoid clobbering return values
568 reg_pool_->next_core_reg = r2;
652 Clobber(r2);
676 res.low_reg = r2;
678 Clobber(r2);
680 MarkInUse(r2);
703 LockTemp(r2);
[all...] |
| H A D | arm_lir.h | 45 * 5 core temps that codegen can use (r0, r1, r2, r3, r12)
147 r2 = 2, enumerator in enum:art::ArmNativeRegisterPool
217 #define rARM_ARG2 r2
221 #define rARM_FARG2 r2
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