18d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers/* 28d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * Copyright (C) 2013 The Android Open Source Project 38d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * 48d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * Licensed under the Apache License, Version 2.0 (the "License"); 58d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * you may not use this file except in compliance with the License. 68d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * You may obtain a copy of the License at 78d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * 88d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * http://www.apache.org/licenses/LICENSE-2.0 98d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * 108d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * Unless required by applicable law or agreed to in writing, software 118d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * distributed under the License is distributed on an "AS IS" BASIS, 128d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 138d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * See the License for the specific language governing permissions and 148d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * limitations under the License. 158d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers */ 168d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 17fc0e3219edc9a5bf81b166e82fd5db2796eb6a0dBrian Carlstrom#ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_INL_H_ 18fc0e3219edc9a5bf81b166e82fd5db2796eb6a0dBrian Carlstrom#define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_INL_H_ 198d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 208d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers#include "mir_to_lir.h" 218d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 227940e44f4517de5e2634a7e07d58d0fb26160513Brian Carlstrom#include "dex/compiler_internals.h" 238d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 248d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogersnamespace art { 258d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 268d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers/* Mark a temp register as dead. Does not affect allocation state. */ 278d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogersinline void Mir2Lir::ClobberBody(RegisterInfo* p) { 288d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (p->is_temp) { 298d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers DCHECK(!(p->live && p->dirty)) << "Live & dirty temp in clobber"; 308d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers p->live = false; 318d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers p->s_reg = INVALID_SREG; 328d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers p->def_start = NULL; 338d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers p->def_end = NULL; 348d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (p->pair) { 358d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers p->pair = false; 368d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers Clobber(p->partner); 378d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 388d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 398d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers} 408d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 418d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogersinline LIR* Mir2Lir::RawLIR(int dalvik_offset, int opcode, int op0, 428d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers int op1, int op2, int op3, int op4, LIR* target) { 43f6c4b3ba3825de1dbb3e747a68b809c6cc8eb4dbMathieu Chartier LIR* insn = static_cast<LIR*>(arena_->Alloc(sizeof(LIR), ArenaAllocator::kAllocLIR)); 448d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers insn->dalvik_offset = dalvik_offset; 458d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers insn->opcode = opcode; 468d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers insn->operands[0] = op0; 478d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers insn->operands[1] = op1; 488d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers insn->operands[2] = op2; 498d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers insn->operands[3] = op3; 508d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers insn->operands[4] = op4; 518d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers insn->target = target; 528d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers SetupResourceMasks(insn); 538d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if ((opcode == kPseudoTargetLabel) || (opcode == kPseudoSafepointPC) || 548d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers (opcode == kPseudoExportedPC)) { 558d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers // Always make labels scheduling barriers 568d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers insn->use_mask = insn->def_mask = ENCODE_ALL; 578d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 588d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers return insn; 598d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers} 608d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 618d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers/* 628d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * The following are building blocks to construct low-level IRs with 0 - 4 638d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * operands. 648d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers */ 658d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogersinline LIR* Mir2Lir::NewLIR0(int opcode) { 668d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & NO_OPERAND)) 678d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << GetTargetInstName(opcode) << " " << opcode << " " 688d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " 698d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << current_dalvik_offset_; 708d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers LIR* insn = RawLIR(current_dalvik_offset_, opcode); 718d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers AppendLIR(insn); 728d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers return insn; 738d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers} 748d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 758d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogersinline LIR* Mir2Lir::NewLIR1(int opcode, int dest) { 768d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & IS_UNARY_OP)) 778d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << GetTargetInstName(opcode) << " " << opcode << " " 788d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " 798d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << current_dalvik_offset_; 808d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest); 818d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers AppendLIR(insn); 828d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers return insn; 838d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers} 848d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 858d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogersinline LIR* Mir2Lir::NewLIR2(int opcode, int dest, int src1) { 868d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & IS_BINARY_OP)) 878d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << GetTargetInstName(opcode) << " " << opcode << " " 888d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " 898d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << current_dalvik_offset_; 908d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1); 918d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers AppendLIR(insn); 928d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers return insn; 938d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers} 948d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 958d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogersinline LIR* Mir2Lir::NewLIR3(int opcode, int dest, int src1, int src2) { 968d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & IS_TERTIARY_OP)) 978d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << GetTargetInstName(opcode) << " " << opcode << " " 988d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " 998d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << current_dalvik_offset_; 1008d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2); 1018d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers AppendLIR(insn); 1028d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers return insn; 1038d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers} 1048d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1058d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogersinline LIR* Mir2Lir::NewLIR4(int opcode, int dest, int src1, int src2, int info) { 1068d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & IS_QUAD_OP)) 1078d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << GetTargetInstName(opcode) << " " << opcode << " " 1088d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " 1098d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << current_dalvik_offset_; 1108d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info); 1118d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers AppendLIR(insn); 1128d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers return insn; 1138d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers} 1148d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1158d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogersinline LIR* Mir2Lir::NewLIR5(int opcode, int dest, int src1, int src2, int info1, 1168d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers int info2) { 1178d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers DCHECK(is_pseudo_opcode(opcode) || (GetTargetInstFlags(opcode) & IS_QUIN_OP)) 1188d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << GetTargetInstName(opcode) << " " << opcode << " " 1198d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << PrettyMethod(cu_->method_idx, *cu_->dex_file) << " " 1208d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers << current_dalvik_offset_; 1218d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info1, info2); 1228d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers AppendLIR(insn); 1238d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers return insn; 1248d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers} 1258d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1268d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers/* 1278d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * Mark the corresponding bit(s). 1288d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers */ 1298d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogersinline void Mir2Lir::SetupRegMask(uint64_t* mask, int reg) { 1308d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers *mask |= GetRegMaskCommon(reg); 1318d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers} 1328d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1338d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers/* 1348d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * Set up the proper fields in the resource mask 1358d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers */ 1368d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogersinline void Mir2Lir::SetupResourceMasks(LIR* lir) { 1378d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers int opcode = lir->opcode; 1388d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1398d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (opcode <= 0) { 1408d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers lir->use_mask = lir->def_mask = 0; 1418d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers return; 1428d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 1438d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1448d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers uint64_t flags = GetTargetInstFlags(opcode); 1458d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1468d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (flags & NEEDS_FIXUP) { 1478d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers lir->flags.pcRelFixup = true; 1488d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 1498d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1508d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers /* Get the starting size of the instruction's template */ 1518d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers lir->flags.size = GetInsnSize(lir); 1528d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1538d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers /* Set up the mask for resources that are updated */ 1548d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (flags & (IS_LOAD | IS_STORE)) { 1558d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers /* Default to heap - will catch specialized classes later */ 1568d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers SetMemRefType(lir, flags & IS_LOAD, kHeapRef); 1578d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 1588d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1598d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers /* 1608d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * Conservatively assume the branch here will call out a function that in 1618d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers * turn will trash everything. 1628d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers */ 1638d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (flags & IS_BRANCH) { 1648d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers lir->def_mask = lir->use_mask = ENCODE_ALL; 1658d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers return; 1668d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 1678d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1688d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (flags & REG_DEF0) { 1698d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers SetupRegMask(&lir->def_mask, lir->operands[0]); 1708d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 1718d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1728d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (flags & REG_DEF1) { 1738d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers SetupRegMask(&lir->def_mask, lir->operands[1]); 1748d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 1758d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1768d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1778d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (flags & SETS_CCODES) { 1788d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers lir->def_mask |= ENCODE_CCODE; 1798d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 1808d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1818d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (flags & (REG_USE0 | REG_USE1 | REG_USE2 | REG_USE3)) { 1828d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers int i; 1838d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1848d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers for (i = 0; i < 4; i++) { 1858d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (flags & (1 << (kRegUse0 + i))) { 1868d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers SetupRegMask(&lir->use_mask, lir->operands[i]); 1878d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 1888d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 1898d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 1908d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1918d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers if (flags & USES_CCODES) { 1928d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers lir->use_mask |= ENCODE_CCODE; 1938d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers } 1948d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1958d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers // Handle target-specific actions 1968d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers SetupTargetResourceMasks(lir); 1978d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers} 1988d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 1998d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers} // namespace art 2008d3a117b374352a1853fae9b7306afeaaa9e3b91Ian Rogers 201fc0e3219edc9a5bf81b166e82fd5db2796eb6a0dBrian Carlstrom#endif // ART_COMPILER_DEX_QUICK_MIR_TO_LIR_INL_H_ 202