1a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham%verify "executed" 2a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham /* 3a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham * Long integer shift. This is different from the generic 32/64-bit 4a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham * binary operations because vAA/vBB are 64-bit but vCC (the shift 5a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham * distance) is 32-bit. Also, Dalvik requires us to mask off the low 6a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham * 6 bits of the shift distance. 7a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham */ 8a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham /* shl-long vAA, vBB, vCC */ 9a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham FETCH(a0, 1) # a0 <- CCBB 10a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham GET_OPA(t2) # t2 <- AA 11a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham and a3, a0, 255 # a3 <- BB 12a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham srl a0, a0, 8 # a0 <- CC 13a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham EAS2(a3, rFP, a3) # a3 <- &fp[BB] 14a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham GET_VREG(a2, a0) # a2 <- vCC 15a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 16a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham 17a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham EAS2(t2, rFP, t2) # t2 <- &fp[AA] 18a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham FETCH_ADVANCE_INST(2) # advance rPC, load rINST 19a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham 20a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham sll v0, a0, a2 # rlo<- alo << (shift&31) 21a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham not v1, a2 # rhi<- 31-shift (shift is 5b) 22a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham srl a0, 1 23a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham srl a0, v1 # alo<- alo >> (32-(shift&31)) 24a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham sll v1, a1, a2 # rhi<- ahi << (shift&31) 25a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham or v1, a0 # rhi<- rhi | alo 26a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham andi a2, 0x20 # shift< shift & 0x20 27a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham movn v1, v0, a2 # rhi<- rlo (if shift&0x20) 28a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham movn v0, zero, a2 # rlo<- 0 (if shift&0x20) 29a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham 30a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham GET_INST_OPCODE(t0) # extract opcode from rINST 31a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham STORE64(v0, v1, t2) # vAA/vAA+1 <- a0/a1 32a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham GOTO_OPCODE(t0) # jump to next instruction 33a8b91c52fd8a90b784835dfe1f8898035266c4ddRaghu Gandham 34