MCRegisterInfo.h revision e26e8a64ab37e98c69801ac2028b187773bc1d1f
1//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_MC_MCREGISTERINFO_H 17#define LLVM_MC_MCREGISTERINFO_H 18 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/Support/ErrorHandling.h" 21#include <cassert> 22 23namespace llvm { 24 25/// An unsigned integer type large enough to represent all physical registers, 26/// but not necessarily virtual registers. 27typedef uint16_t MCPhysReg; 28 29/// MCRegisterClass - Base class of TargetRegisterClass. 30class MCRegisterClass { 31public: 32 typedef const MCPhysReg* iterator; 33 typedef const MCPhysReg* const_iterator; 34 35 const char *Name; 36 const iterator RegsBegin; 37 const uint8_t *const RegSet; 38 const uint16_t RegsSize; 39 const uint16_t RegSetSize; 40 const uint16_t ID; 41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes 42 const int8_t CopyCost; 43 const bool Allocatable; 44 45 /// getID() - Return the register class ID number. 46 /// 47 unsigned getID() const { return ID; } 48 49 /// getName() - Return the register class name for debugging. 50 /// 51 const char *getName() const { return Name; } 52 53 /// begin/end - Return all of the registers in this class. 54 /// 55 iterator begin() const { return RegsBegin; } 56 iterator end() const { return RegsBegin + RegsSize; } 57 58 /// getNumRegs - Return the number of registers in this class. 59 /// 60 unsigned getNumRegs() const { return RegsSize; } 61 62 /// getRegister - Return the specified register in the class. 63 /// 64 unsigned getRegister(unsigned i) const { 65 assert(i < getNumRegs() && "Register number out of range!"); 66 return RegsBegin[i]; 67 } 68 69 /// contains - Return true if the specified register is included in this 70 /// register class. This does not include virtual registers. 71 bool contains(unsigned Reg) const { 72 unsigned InByte = Reg % 8; 73 unsigned Byte = Reg / 8; 74 if (Byte >= RegSetSize) 75 return false; 76 return (RegSet[Byte] & (1 << InByte)) != 0; 77 } 78 79 /// contains - Return true if both registers are in this class. 80 bool contains(unsigned Reg1, unsigned Reg2) const { 81 return contains(Reg1) && contains(Reg2); 82 } 83 84 /// getSize - Return the size of the register in bytes, which is also the size 85 /// of a stack slot allocated to hold a spilled copy of this register. 86 unsigned getSize() const { return RegSize; } 87 88 /// getAlignment - Return the minimum required alignment for a register of 89 /// this class. 90 unsigned getAlignment() const { return Alignment; } 91 92 /// getCopyCost - Return the cost of copying a value between two registers in 93 /// this class. A negative number means the register class is very expensive 94 /// to copy e.g. status flag register classes. 95 int getCopyCost() const { return CopyCost; } 96 97 /// isAllocatable - Return true if this register class may be used to create 98 /// virtual registers. 99 bool isAllocatable() const { return Allocatable; } 100}; 101 102/// MCRegisterDesc - This record contains all of the information known about 103/// a particular register. The Overlaps field contains a pointer to a zero 104/// terminated array of registers that this register aliases, starting with 105/// itself. This is needed for architectures like X86 which have AL alias AX 106/// alias EAX. The SubRegs field is a zero terminated array of registers that 107/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of 108/// AX. The SuperRegs field is a zero terminated array of registers that are 109/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 110/// of AX. 111/// 112struct MCRegisterDesc { 113 uint32_t Name; // Printable name for the reg (for debugging) 114 uint32_t Overlaps; // Overlapping registers, described above 115 uint32_t SubRegs; // Sub-register set, described above 116 uint32_t SuperRegs; // Super-register set, described above 117 118 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each 119 // sub-register in SubRegs. 120 uint32_t SubRegIndices; 121 122 // RegUnits - Points to the list of register units. The low 4 bits holds the 123 // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. 124 uint32_t RegUnits; 125}; 126 127/// MCRegisterInfo base class - We assume that the target defines a static 128/// array of MCRegisterDesc objects that represent all of the machine 129/// registers that the target has. As such, we simply have to track a pointer 130/// to this array so that we can turn register number into a register 131/// descriptor. 132/// 133/// Note this class is designed to be a base class of TargetRegisterInfo, which 134/// is the interface used by codegen. However, specific targets *should never* 135/// specialize this class. MCRegisterInfo should only contain getters to access 136/// TableGen generated physical register data. It must not be extended with 137/// virtual methods. 138/// 139class MCRegisterInfo { 140public: 141 typedef const MCRegisterClass *regclass_iterator; 142 143 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 144 /// performed with a binary search. 145 struct DwarfLLVMRegPair { 146 unsigned FromReg; 147 unsigned ToReg; 148 149 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } 150 }; 151private: 152 const MCRegisterDesc *Desc; // Pointer to the descriptor array 153 unsigned NumRegs; // Number of entries in the array 154 unsigned RAReg; // Return address register 155 const MCRegisterClass *Classes; // Pointer to the regclass array 156 unsigned NumClasses; // Number of entries in the array 157 unsigned NumRegUnits; // Number of regunits. 158 const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table. 159 const MCPhysReg *DiffLists; // Pointer to the difflists array 160 const char *RegStrings; // Pointer to the string table. 161 const uint16_t *SubRegIndices; // Pointer to the subreg lookup 162 // array. 163 unsigned NumSubRegIndices; // Number of subreg indices. 164 const uint16_t *RegEncodingTable; // Pointer to array of register 165 // encodings. 166 167 unsigned L2DwarfRegsSize; 168 unsigned EHL2DwarfRegsSize; 169 unsigned Dwarf2LRegsSize; 170 unsigned EHDwarf2LRegsSize; 171 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping 172 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 173 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping 174 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 175 DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 176 177public: 178 /// DiffListIterator - Base iterator class that can traverse the 179 /// differentially encoded register and regunit lists in DiffLists. 180 /// Don't use this class directly, use one of the specialized sub-classes 181 /// defined below. 182 class DiffListIterator { 183 uint16_t Val; 184 const MCPhysReg *List; 185 186 protected: 187 /// Create an invalid iterator. Call init() to point to something useful. 188 DiffListIterator() : Val(0), List(0) {} 189 190 /// init - Point the iterator to InitVal, decoding subsequent values from 191 /// DiffList. The iterator will initially point to InitVal, sub-classes are 192 /// responsible for skipping the seed value if it is not part of the list. 193 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { 194 Val = InitVal; 195 List = DiffList; 196 } 197 198 /// advance - Move to the next list position, return the applied 199 /// differential. This function does not detect the end of the list, that 200 /// is the caller's responsibility (by checking for a 0 return value). 201 unsigned advance() { 202 assert(isValid() && "Cannot move off the end of the list."); 203 MCPhysReg D = *List++; 204 Val += D; 205 return D; 206 } 207 208 public: 209 210 /// isValid - returns true if this iterator is not yet at the end. 211 bool isValid() const { return List; } 212 213 /// Dereference the iterator to get the value at the current position. 214 unsigned operator*() const { return Val; } 215 216 /// Pre-increment to move to the next position. 217 void operator++() { 218 // The end of the list is encoded as a 0 differential. 219 if (!advance()) 220 List = 0; 221 } 222 }; 223 224 // These iterators are allowed to sub-class DiffListIterator and access 225 // internal list pointers. 226 friend class MCSubRegIterator; 227 friend class MCSuperRegIterator; 228 friend class MCRegAliasIterator; 229 friend class MCRegUnitIterator; 230 friend class MCRegUnitRootIterator; 231 232 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen 233 /// auto-generated routines. *DO NOT USE*. 234 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 235 const MCRegisterClass *C, unsigned NC, 236 const uint16_t (*RURoots)[2], 237 unsigned NRU, 238 const MCPhysReg *DL, 239 const char *Strings, 240 const uint16_t *SubIndices, 241 unsigned NumIndices, 242 const uint16_t *RET) { 243 Desc = D; 244 NumRegs = NR; 245 RAReg = RA; 246 Classes = C; 247 DiffLists = DL; 248 RegStrings = Strings; 249 NumClasses = NC; 250 RegUnitRoots = RURoots; 251 NumRegUnits = NRU; 252 SubRegIndices = SubIndices; 253 NumSubRegIndices = NumIndices; 254 RegEncodingTable = RET; 255 } 256 257 /// mapLLVMRegsToDwarfRegs - Used to initialize LLVM register to Dwarf 258 /// register number mapping. Called by TableGen auto-generated routines. 259 /// *DO NOT USE*. 260 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, 261 bool isEH) { 262 if (isEH) { 263 EHL2DwarfRegs = Map; 264 EHL2DwarfRegsSize = Size; 265 } else { 266 L2DwarfRegs = Map; 267 L2DwarfRegsSize = Size; 268 } 269 } 270 271 /// mapDwarfRegsToLLVMRegs - Used to initialize Dwarf register to LLVM 272 /// register number mapping. Called by TableGen auto-generated routines. 273 /// *DO NOT USE*. 274 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, 275 bool isEH) { 276 if (isEH) { 277 EHDwarf2LRegs = Map; 278 EHDwarf2LRegsSize = Size; 279 } else { 280 Dwarf2LRegs = Map; 281 Dwarf2LRegsSize = Size; 282 } 283 } 284 285 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 286 /// number mapping. By default the SEH register number is just the same 287 /// as the LLVM register number. 288 /// FIXME: TableGen these numbers. Currently this requires target specific 289 /// initialization code. 290 void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 291 L2SEHRegs[LLVMReg] = SEHReg; 292 } 293 294 /// getRARegister - This method should return the register where the return 295 /// address can be found. 296 unsigned getRARegister() const { 297 return RAReg; 298 } 299 300 const MCRegisterDesc &operator[](unsigned RegNo) const { 301 assert(RegNo < NumRegs && 302 "Attempting to access record for invalid register number!"); 303 return Desc[RegNo]; 304 } 305 306 /// Provide a get method, equivalent to [], but more useful if we have a 307 /// pointer to this object. 308 /// 309 const MCRegisterDesc &get(unsigned RegNo) const { 310 return operator[](RegNo); 311 } 312 313 /// getSubReg - Returns the physical register number of sub-register "Index" 314 /// for physical register RegNo. Return zero if the sub-register does not 315 /// exist. 316 unsigned getSubReg(unsigned Reg, unsigned Idx) const; 317 318 /// getMatchingSuperReg - Return a super-register of the specified register 319 /// Reg so its sub-register of index SubIdx is Reg. 320 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 321 const MCRegisterClass *RC) const; 322 323 /// getSubRegIndex - For a given register pair, return the sub-register index 324 /// if the second register is a sub-register of the first. Return zero 325 /// otherwise. 326 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const; 327 328 /// getName - Return the human-readable symbolic target-specific name for the 329 /// specified physical register. 330 const char *getName(unsigned RegNo) const { 331 return RegStrings + get(RegNo).Name; 332 } 333 334 /// getNumRegs - Return the number of registers this target has (useful for 335 /// sizing arrays holding per register information) 336 unsigned getNumRegs() const { 337 return NumRegs; 338 } 339 340 /// getNumSubRegIndices - Return the number of sub-register indices 341 /// understood by the target. Index 0 is reserved for the no-op sub-register, 342 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers. 343 unsigned getNumSubRegIndices() const { 344 return NumSubRegIndices; 345 } 346 347 /// getNumRegUnits - Return the number of (native) register units in the 348 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They 349 /// can be accessed through MCRegUnitIterator defined below. 350 unsigned getNumRegUnits() const { 351 return NumRegUnits; 352 } 353 354 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 355 /// number. Returns -1 if there is no equivalent value. The second 356 /// parameter allows targets to use different numberings for EH info and 357 /// debugging info. 358 int getDwarfRegNum(unsigned RegNum, bool isEH) const; 359 360 /// getLLVMRegNum - Map a dwarf register back to a target register. 361 /// 362 int getLLVMRegNum(unsigned RegNum, bool isEH) const; 363 364 /// getSEHRegNum - Map a target register to an equivalent SEH register 365 /// number. Returns LLVM register number if there is no equivalent value. 366 int getSEHRegNum(unsigned RegNum) const; 367 368 regclass_iterator regclass_begin() const { return Classes; } 369 regclass_iterator regclass_end() const { return Classes+NumClasses; } 370 371 unsigned getNumRegClasses() const { 372 return (unsigned)(regclass_end()-regclass_begin()); 373 } 374 375 /// getRegClass - Returns the register class associated with the enumeration 376 /// value. See class MCOperandInfo. 377 const MCRegisterClass& getRegClass(unsigned i) const { 378 assert(i < getNumRegClasses() && "Register Class ID out of range"); 379 return Classes[i]; 380 } 381 382 /// getEncodingValue - Returns the encoding for RegNo 383 uint16_t getEncodingValue(unsigned RegNo) const { 384 assert(RegNo < NumRegs && 385 "Attempting to get encoding for invalid register number!"); 386 return RegEncodingTable[RegNo]; 387 } 388 389}; 390 391//===----------------------------------------------------------------------===// 392// Register List Iterators 393//===----------------------------------------------------------------------===// 394 395// MCRegisterInfo provides lists of super-registers, sub-registers, and 396// aliasing registers. Use these iterator classes to traverse the lists. 397 398/// MCSubRegIterator enumerates all sub-registers of Reg. 399class MCSubRegIterator : public MCRegisterInfo::DiffListIterator { 400public: 401 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 402 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs); 403 ++*this; 404 } 405}; 406 407/// MCSuperRegIterator enumerates all super-registers of Reg. 408class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator { 409public: 410 MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 411 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs); 412 ++*this; 413 } 414}; 415 416/// MCRegAliasIterator enumerates all registers aliasing Reg. 417/// If IncludeSelf is set, Reg itself is included in the list. 418class MCRegAliasIterator : public MCRegisterInfo::DiffListIterator { 419public: 420 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, 421 bool IncludeSelf) { 422 init(Reg, MCRI->DiffLists + MCRI->get(Reg).Overlaps); 423 // Initially, the iterator points to Reg itself. 424 if (!IncludeSelf) 425 ++*this; 426 } 427}; 428 429//===----------------------------------------------------------------------===// 430// Register Units 431//===----------------------------------------------------------------------===// 432 433// Register units are used to compute register aliasing. Every register has at 434// least one register unit, but it can have more. Two registers overlap if and 435// only if they have a common register unit. 436// 437// A target with a complicated sub-register structure will typically have many 438// fewer register units than actual registers. MCRI::getNumRegUnits() returns 439// the number of register units in the target. 440 441// MCRegUnitIterator enumerates a list of register units for Reg. The list is 442// in ascending numerical order. 443class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator { 444public: 445 /// MCRegUnitIterator - Create an iterator that traverses the register units 446 /// in Reg. 447 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 448 // Decode the RegUnits MCRegisterDesc field. 449 unsigned RU = MCRI->get(Reg).RegUnits; 450 unsigned Scale = RU & 15; 451 unsigned Offset = RU >> 4; 452 453 // Initialize the iterator to Reg * Scale, and the List pointer to 454 // DiffLists + Offset. 455 init(Reg * Scale, MCRI->DiffLists + Offset); 456 457 // That may not be a valid unit, we need to advance by one to get the real 458 // unit number. The first differential can be 0 which would normally 459 // terminate the list, but since we know every register has at least one 460 // unit, we can allow a 0 differential here. 461 advance(); 462 } 463}; 464 465// Each register unit has one or two root registers. The complete set of 466// registers containing a register unit is the union of the roots and their 467// super-registers. All registers aliasing Unit can be visited like this: 468// 469// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { 470// unsigned Root = *RI; 471// visit(Root); 472// for (MCSuperRegIterator SI(Root, MCRI); SI.isValid(); ++SI) 473// visit(*SI); 474// } 475 476/// MCRegUnitRootIterator enumerates the root registers of a register unit. 477class MCRegUnitRootIterator { 478 uint16_t Reg0; 479 uint16_t Reg1; 480public: 481 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { 482 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); 483 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; 484 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; 485 } 486 487 /// Dereference to get the current root register. 488 unsigned operator*() const { 489 return Reg0; 490 } 491 492 /// isValid - Check if the iterator is at the end of the list. 493 bool isValid() const { 494 return Reg0; 495 } 496 497 /// Preincrement to move to the next root register. 498 void operator++() { 499 assert(isValid() && "Cannot move off the end of the list."); 500 Reg0 = Reg1; 501 Reg1 = 0; 502 } 503}; 504 505} // End llvm namespace 506 507#endif 508