LiveVariables.cpp revision ef09c63e7ba5dd5410655f71d35eb7245893b1f1
1//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveVariable analysis pass. For each machine 11// instruction in the function, this pass calculates the set of registers that 12// are immediately dead after the instruction (i.e., the instruction calculates 13// the value, but it is never used) and the set of registers that are used by 14// the instruction, but are never used after the instruction (i.e., they are 15// killed). 16// 17// This class computes live variables using are sparse implementation based on 18// the machine code SSA form. This class computes live variable information for 19// each virtual and _register allocatable_ physical register in a function. It 20// uses the dominance properties of SSA form to efficiently compute live 21// variables for virtual registers, and assumes that physical registers are only 22// live within a single basic block (allowing it to do a single local analysis 23// to resolve physical register lifetimes in each basic block). If a physical 24// register is not register allocatable, it is not tracked. This is useful for 25// things like the stack pointer and condition codes. 26// 27//===----------------------------------------------------------------------===// 28 29#include "llvm/CodeGen/LiveVariables.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Target/TargetMachine.h" 33#include "llvm/Support/CFG.h" 34#include "Support/DepthFirstIterator.h" 35using namespace llvm; 36 37static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis"); 38 39const std::pair<MachineBasicBlock*, unsigned> & 40LiveVariables::getMachineBasicBlockInfo(MachineBasicBlock *MBB) const{ 41 return BBMap.find(MBB->getBasicBlock())->second; 42} 43 44/// getIndexMachineBasicBlock() - Given a block index, return the 45/// MachineBasicBlock corresponding to it. 46MachineBasicBlock *LiveVariables::getIndexMachineBasicBlock(unsigned Idx) { 47 if (BBIdxMap.empty()) { 48 BBIdxMap.resize(BBMap.size()); 49 for (std::map<const BasicBlock*, std::pair<MachineBasicBlock*, unsigned> > 50 ::iterator I = BBMap.begin(), E = BBMap.end(); I != E; ++I) { 51 assert(BBIdxMap.size() > I->second.second &&"Indices are not sequential"); 52 assert(BBIdxMap[I->second.second] == 0 && "Multiple idx collision!"); 53 BBIdxMap[I->second.second] = I->second.first; 54 } 55 } 56 assert(Idx < BBIdxMap.size() && "BB Index out of range!"); 57 return BBIdxMap[Idx]; 58} 59 60LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { 61 assert(MRegisterInfo::isVirtualRegister(RegIdx) && 62 "getVarInfo: not a virtual register!"); 63 RegIdx -= MRegisterInfo::FirstVirtualRegister; 64 if (RegIdx >= VirtRegInfo.size()) { 65 if (RegIdx >= 2*VirtRegInfo.size()) 66 VirtRegInfo.resize(RegIdx*2); 67 else 68 VirtRegInfo.resize(2*VirtRegInfo.size()); 69 } 70 return VirtRegInfo[RegIdx]; 71} 72 73 74 75void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, 76 const BasicBlock *BB) { 77 const std::pair<MachineBasicBlock*,unsigned> &Info = BBMap.find(BB)->second; 78 MachineBasicBlock *MBB = Info.first; 79 unsigned BBNum = Info.second; 80 81 // Check to see if this basic block is one of the killing blocks. If so, 82 // remove it... 83 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 84 if (VRInfo.Kills[i].first == MBB) { 85 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry 86 break; 87 } 88 89 if (MBB == VRInfo.DefBlock) return; // Terminate recursion 90 91 if (VRInfo.AliveBlocks.size() <= BBNum) 92 VRInfo.AliveBlocks.resize(BBNum+1); // Make space... 93 94 if (VRInfo.AliveBlocks[BBNum]) 95 return; // We already know the block is live 96 97 // Mark the variable known alive in this bb 98 VRInfo.AliveBlocks[BBNum] = true; 99 100 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) 101 MarkVirtRegAliveInBlock(VRInfo, *PI); 102} 103 104void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB, 105 MachineInstr *MI) { 106 // Check to see if this basic block is already a kill block... 107 if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) { 108 // Yes, this register is killed in this basic block already. Increase the 109 // live range by updating the kill instruction. 110 VRInfo.Kills.back().second = MI; 111 return; 112 } 113 114#ifndef NDEBUG 115 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 116 assert(VRInfo.Kills[i].first != MBB && "entry should be at end!"); 117#endif 118 119 assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!"); 120 121 // Add a new kill entry for this basic block. 122 VRInfo.Kills.push_back(std::make_pair(MBB, MI)); 123 124 // Update all dominating blocks to mark them known live. 125 const BasicBlock *BB = MBB->getBasicBlock(); 126 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); 127 PI != E; ++PI) 128 MarkVirtRegAliveInBlock(VRInfo, *PI); 129} 130 131void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { 132 PhysRegInfo[Reg] = MI; 133 PhysRegUsed[Reg] = true; 134} 135 136void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { 137 // Does this kill a previous version of this register? 138 if (MachineInstr *LastUse = PhysRegInfo[Reg]) { 139 if (PhysRegUsed[Reg]) 140 RegistersKilled.insert(std::make_pair(LastUse, Reg)); 141 else 142 RegistersDead.insert(std::make_pair(LastUse, Reg)); 143 } 144 PhysRegInfo[Reg] = MI; 145 PhysRegUsed[Reg] = false; 146 147 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); 148 *AliasSet; ++AliasSet) { 149 if (MachineInstr *LastUse = PhysRegInfo[*AliasSet]) { 150 if (PhysRegUsed[*AliasSet]) 151 RegistersKilled.insert(std::make_pair(LastUse, *AliasSet)); 152 else 153 RegistersDead.insert(std::make_pair(LastUse, *AliasSet)); 154 } 155 PhysRegInfo[*AliasSet] = MI; 156 PhysRegUsed[*AliasSet] = false; 157 } 158} 159 160bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { 161 // First time though, initialize AllocatablePhysicalRegisters for the target 162 if (AllocatablePhysicalRegisters.empty()) { 163 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); 164 assert(&MRI && "Target doesn't have register information?"); 165 166 // Make space, initializing to false... 167 AllocatablePhysicalRegisters.resize(MRegisterInfo::FirstVirtualRegister); 168 169 // Loop over all of the register classes... 170 for (MRegisterInfo::regclass_iterator RCI = MRI.regclass_begin(), 171 E = MRI.regclass_end(); RCI != E; ++RCI) 172 // Loop over all of the allocatable registers in the function... 173 for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(MF), 174 E = (*RCI)->allocation_order_end(MF); I != E; ++I) 175 AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable! 176 } 177 178 // Build BBMap... 179 unsigned BBNum = 0; 180 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) 181 BBMap[I->getBasicBlock()] = std::make_pair(I, BBNum++); 182 183 // PhysRegInfo - Keep track of which instruction was the last use of a 184 // physical register. This is a purely local property, because all physical 185 // register references as presumed dead across basic blocks. 186 // 187 MachineInstr *PhysRegInfoA[MRegisterInfo::FirstVirtualRegister]; 188 bool PhysRegUsedA[MRegisterInfo::FirstVirtualRegister]; 189 std::fill(PhysRegInfoA, PhysRegInfoA+MRegisterInfo::FirstVirtualRegister, 190 (MachineInstr*)0); 191 PhysRegInfo = PhysRegInfoA; 192 PhysRegUsed = PhysRegUsedA; 193 194 const TargetInstrInfo &TII = MF.getTarget().getInstrInfo(); 195 RegInfo = MF.getTarget().getRegisterInfo(); 196 197 /// Get some space for a respectable number of registers... 198 VirtRegInfo.resize(64); 199 200 // Calculate live variable information in depth first order on the CFG of the 201 // function. This guarantees that we will see the definition of a virtual 202 // register before its uses due to dominance properties of SSA (except for PHI 203 // nodes, which are treated as a special case). 204 // 205 const BasicBlock *Entry = MF.getFunction()->begin(); 206 for (df_iterator<const BasicBlock*> DFI = df_begin(Entry), E = df_end(Entry); 207 DFI != E; ++DFI) { 208 const BasicBlock *BB = *DFI; 209 std::pair<MachineBasicBlock*, unsigned> &BBRec = BBMap.find(BB)->second; 210 MachineBasicBlock *MBB = BBRec.first; 211 unsigned BBNum = BBRec.second; 212 213 // Loop over all of the instructions, processing them. 214 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 215 I != E; ++I) { 216 MachineInstr *MI = *I; 217 const TargetInstrDescriptor &MID = TII.get(MI->getOpcode()); 218 219 // Process all of the operands of the instruction... 220 unsigned NumOperandsToProcess = MI->getNumOperands(); 221 222 // Unless it is a PHI node. In this case, ONLY process the DEF, not any 223 // of the uses. They will be handled in other basic blocks. 224 if (MI->getOpcode() == TargetInstrInfo::PHI) 225 NumOperandsToProcess = 1; 226 227 // Loop over implicit uses, using them. 228 for (const unsigned *ImplicitUses = MID.ImplicitUses; 229 *ImplicitUses; ++ImplicitUses) 230 HandlePhysRegUse(*ImplicitUses, MI); 231 232 // Process all explicit uses... 233 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 234 MachineOperand &MO = MI->getOperand(i); 235 if (MO.isUse()) { 236 if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) { 237 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI); 238 } else if (MO.isPhysicalRegister() && 239 AllocatablePhysicalRegisters[MO.getReg()]) { 240 HandlePhysRegUse(MO.getReg(), MI); 241 } 242 } 243 } 244 245 // Loop over implicit defs, defining them. 246 for (const unsigned *ImplicitDefs = MID.ImplicitDefs; 247 *ImplicitDefs; ++ImplicitDefs) 248 HandlePhysRegDef(*ImplicitDefs, MI); 249 250 // Process all explicit defs... 251 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 252 MachineOperand &MO = MI->getOperand(i); 253 if (MO.isDef()) { 254 if (MO.isVirtualRegister()) { 255 VarInfo &VRInfo = getVarInfo(MO.getReg()); 256 257 assert(VRInfo.DefBlock == 0 && "Variable multiply defined!"); 258 VRInfo.DefBlock = MBB; // Created here... 259 VRInfo.DefInst = MI; 260 VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead 261 } else if (MO.isPhysicalRegister() && 262 AllocatablePhysicalRegisters[MO.getReg()]) { 263 HandlePhysRegDef(MO.getReg(), MI); 264 } 265 } 266 } 267 } 268 269 // Handle any virtual assignments from PHI nodes which might be at the 270 // bottom of this basic block. We check all of our successor blocks to see 271 // if they have PHI nodes, and if so, we simulate an assignment at the end 272 // of the current block. 273 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); 274 SI != E; ++SI) { 275 MachineBasicBlock *Succ = BBMap.find(*SI)->second.first; 276 277 // PHI nodes are guaranteed to be at the top of the block... 278 for (MachineBasicBlock::iterator I = Succ->begin(), E = Succ->end(); 279 I != E && (*I)->getOpcode() == TargetInstrInfo::PHI; ++I) { 280 MachineInstr *MI = *I; 281 for (unsigned i = 1; ; i += 2) 282 if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) { 283 MachineOperand &MO = MI->getOperand(i); 284 if (!MO.getVRegValueOrNull()) { 285 VarInfo &VRInfo = getVarInfo(MO.getReg()); 286 287 // Only mark it alive only in the block we are representing... 288 MarkVirtRegAliveInBlock(VRInfo, BB); 289 break; // Found the PHI entry for this block... 290 } 291 } 292 } 293 } 294 295 // Loop over PhysRegInfo, killing any registers that are available at the 296 // end of the basic block. This also resets the PhysRegInfo map. 297 for (unsigned i = 0, e = MRegisterInfo::FirstVirtualRegister; i != e; ++i) 298 if (PhysRegInfo[i]) 299 HandlePhysRegDef(i, 0); 300 } 301 302 // Convert the information we have gathered into VirtRegInfo and transform it 303 // into a form usable by RegistersKilled. 304 // 305 for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i) 306 for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) { 307 if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst) 308 RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second, 309 i + MRegisterInfo::FirstVirtualRegister)); 310 311 else 312 RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second, 313 i + MRegisterInfo::FirstVirtualRegister)); 314 } 315 316 return false; 317} 318