1//===-- RegAllocBasic.cpp - Basic Register Allocator ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the RABasic function pass, which provides a minimal 11// implementation of the basic register allocator. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "regalloc" 16#include "llvm/CodeGen/Passes.h" 17#include "AllocationOrder.h" 18#include "LiveDebugVariables.h" 19#include "RegAllocBase.h" 20#include "Spiller.h" 21#include "llvm/Analysis/AliasAnalysis.h" 22#include "llvm/CodeGen/CalcSpillWeights.h" 23#include "llvm/CodeGen/LiveIntervalAnalysis.h" 24#include "llvm/CodeGen/LiveRangeEdit.h" 25#include "llvm/CodeGen/LiveRegMatrix.h" 26#include "llvm/CodeGen/LiveStackAnalysis.h" 27#include "llvm/CodeGen/MachineBlockFrequencyInfo.h" 28#include "llvm/CodeGen/MachineFunctionPass.h" 29#include "llvm/CodeGen/MachineInstr.h" 30#include "llvm/CodeGen/MachineLoopInfo.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/CodeGen/RegAllocRegistry.h" 33#include "llvm/CodeGen/VirtRegMap.h" 34#include "llvm/PassAnalysisSupport.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/Target/TargetMachine.h" 38#include "llvm/Target/TargetRegisterInfo.h" 39#include <cstdlib> 40#include <queue> 41 42using namespace llvm; 43 44static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator", 45 createBasicRegisterAllocator); 46 47namespace { 48 struct CompSpillWeight { 49 bool operator()(LiveInterval *A, LiveInterval *B) const { 50 return A->weight < B->weight; 51 } 52 }; 53} 54 55namespace { 56/// RABasic provides a minimal implementation of the basic register allocation 57/// algorithm. It prioritizes live virtual registers by spill weight and spills 58/// whenever a register is unavailable. This is not practical in production but 59/// provides a useful baseline both for measuring other allocators and comparing 60/// the speed of the basic algorithm against other styles of allocators. 61class RABasic : public MachineFunctionPass, public RegAllocBase 62{ 63 // context 64 MachineFunction *MF; 65 66 // state 67 OwningPtr<Spiller> SpillerInstance; 68 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>, 69 CompSpillWeight> Queue; 70 71 // Scratch space. Allocated here to avoid repeated malloc calls in 72 // selectOrSplit(). 73 BitVector UsableRegs; 74 75public: 76 RABasic(); 77 78 /// Return the pass name. 79 virtual const char* getPassName() const { 80 return "Basic Register Allocator"; 81 } 82 83 /// RABasic analysis usage. 84 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 85 86 virtual void releaseMemory(); 87 88 virtual Spiller &spiller() { return *SpillerInstance; } 89 90 virtual float getPriority(LiveInterval *LI) { return LI->weight; } 91 92 virtual void enqueue(LiveInterval *LI) { 93 Queue.push(LI); 94 } 95 96 virtual LiveInterval *dequeue() { 97 if (Queue.empty()) 98 return 0; 99 LiveInterval *LI = Queue.top(); 100 Queue.pop(); 101 return LI; 102 } 103 104 virtual unsigned selectOrSplit(LiveInterval &VirtReg, 105 SmallVectorImpl<LiveInterval*> &SplitVRegs); 106 107 /// Perform register allocation. 108 virtual bool runOnMachineFunction(MachineFunction &mf); 109 110 // Helper for spilling all live virtual registers currently unified under preg 111 // that interfere with the most recently queried lvr. Return true if spilling 112 // was successful, and append any new spilled/split intervals to splitLVRs. 113 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 114 SmallVectorImpl<LiveInterval*> &SplitVRegs); 115 116 static char ID; 117}; 118 119char RABasic::ID = 0; 120 121} // end anonymous namespace 122 123RABasic::RABasic(): MachineFunctionPass(ID) { 124 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry()); 125 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); 126 initializeSlotIndexesPass(*PassRegistry::getPassRegistry()); 127 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry()); 128 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry()); 129 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry()); 130 initializeLiveStacksPass(*PassRegistry::getPassRegistry()); 131 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry()); 132 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry()); 133 initializeVirtRegMapPass(*PassRegistry::getPassRegistry()); 134 initializeLiveRegMatrixPass(*PassRegistry::getPassRegistry()); 135} 136 137void RABasic::getAnalysisUsage(AnalysisUsage &AU) const { 138 AU.setPreservesCFG(); 139 AU.addRequired<AliasAnalysis>(); 140 AU.addPreserved<AliasAnalysis>(); 141 AU.addRequired<LiveIntervals>(); 142 AU.addPreserved<LiveIntervals>(); 143 AU.addPreserved<SlotIndexes>(); 144 AU.addRequired<LiveDebugVariables>(); 145 AU.addPreserved<LiveDebugVariables>(); 146 AU.addRequired<CalculateSpillWeights>(); 147 AU.addRequired<LiveStacks>(); 148 AU.addPreserved<LiveStacks>(); 149 AU.addRequired<MachineBlockFrequencyInfo>(); 150 AU.addPreserved<MachineBlockFrequencyInfo>(); 151 AU.addRequiredID(MachineDominatorsID); 152 AU.addPreservedID(MachineDominatorsID); 153 AU.addRequired<MachineLoopInfo>(); 154 AU.addPreserved<MachineLoopInfo>(); 155 AU.addRequired<VirtRegMap>(); 156 AU.addPreserved<VirtRegMap>(); 157 AU.addRequired<LiveRegMatrix>(); 158 AU.addPreserved<LiveRegMatrix>(); 159 MachineFunctionPass::getAnalysisUsage(AU); 160} 161 162void RABasic::releaseMemory() { 163 SpillerInstance.reset(0); 164} 165 166 167// Spill or split all live virtual registers currently unified under PhysReg 168// that interfere with VirtReg. The newly spilled or split live intervals are 169// returned by appending them to SplitVRegs. 170bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 171 SmallVectorImpl<LiveInterval*> &SplitVRegs) { 172 // Record each interference and determine if all are spillable before mutating 173 // either the union or live intervals. 174 SmallVector<LiveInterval*, 8> Intfs; 175 176 // Collect interferences assigned to any alias of the physical register. 177 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 178 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); 179 Q.collectInterferingVRegs(); 180 if (Q.seenUnspillableVReg()) 181 return false; 182 for (unsigned i = Q.interferingVRegs().size(); i; --i) { 183 LiveInterval *Intf = Q.interferingVRegs()[i - 1]; 184 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) 185 return false; 186 Intfs.push_back(Intf); 187 } 188 } 189 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) << 190 " interferences with " << VirtReg << "\n"); 191 assert(!Intfs.empty() && "expected interference"); 192 193 // Spill each interfering vreg allocated to PhysReg or an alias. 194 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) { 195 LiveInterval &Spill = *Intfs[i]; 196 197 // Skip duplicates. 198 if (!VRM->hasPhys(Spill.reg)) 199 continue; 200 201 // Deallocate the interfering vreg by removing it from the union. 202 // A LiveInterval instance may not be in a union during modification! 203 Matrix->unassign(Spill); 204 205 // Spill the extracted interval. 206 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM); 207 spiller().spill(LRE); 208 } 209 return true; 210} 211 212// Driver for the register assignment and splitting heuristics. 213// Manages iteration over the LiveIntervalUnions. 214// 215// This is a minimal implementation of register assignment and splitting that 216// spills whenever we run out of registers. 217// 218// selectOrSplit can only be called once per live virtual register. We then do a 219// single interference test for each register the correct class until we find an 220// available register. So, the number of interference tests in the worst case is 221// |vregs| * |machineregs|. And since the number of interference tests is 222// minimal, there is no value in caching them outside the scope of 223// selectOrSplit(). 224unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, 225 SmallVectorImpl<LiveInterval*> &SplitVRegs) { 226 // Populate a list of physical register spill candidates. 227 SmallVector<unsigned, 8> PhysRegSpillCands; 228 229 // Check for an available register in this class. 230 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); 231 while (unsigned PhysReg = Order.next()) { 232 // Check for interference in PhysReg 233 switch (Matrix->checkInterference(VirtReg, PhysReg)) { 234 case LiveRegMatrix::IK_Free: 235 // PhysReg is available, allocate it. 236 return PhysReg; 237 238 case LiveRegMatrix::IK_VirtReg: 239 // Only virtual registers in the way, we may be able to spill them. 240 PhysRegSpillCands.push_back(PhysReg); 241 continue; 242 243 default: 244 // RegMask or RegUnit interference. 245 continue; 246 } 247 } 248 249 // Try to spill another interfering reg with less spill weight. 250 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(), 251 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) { 252 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) 253 continue; 254 255 assert(!Matrix->checkInterference(VirtReg, *PhysRegI) && 256 "Interference after spill."); 257 // Tell the caller to allocate to this newly freed physical register. 258 return *PhysRegI; 259 } 260 261 // No other spill candidates were found, so spill the current VirtReg. 262 DEBUG(dbgs() << "spilling: " << VirtReg << '\n'); 263 if (!VirtReg.isSpillable()) 264 return ~0u; 265 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM); 266 spiller().spill(LRE); 267 268 // The live virtual register requesting allocation was spilled, so tell 269 // the caller not to allocate anything during this round. 270 return 0; 271} 272 273bool RABasic::runOnMachineFunction(MachineFunction &mf) { 274 DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n" 275 << "********** Function: " 276 << mf.getName() << '\n'); 277 278 MF = &mf; 279 RegAllocBase::init(getAnalysis<VirtRegMap>(), 280 getAnalysis<LiveIntervals>(), 281 getAnalysis<LiveRegMatrix>()); 282 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM)); 283 284 allocatePhysRegs(); 285 286 // Diagnostic output before rewriting 287 DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n"); 288 289 releaseMemory(); 290 return true; 291} 292 293FunctionPass* llvm::createBasicRegisterAllocator() 294{ 295 return new RABasic(); 296} 297