SelectionDAGBuilder.cpp revision 1a54c57cf654e001c078c7064123d30e6c03e349
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SelectionDAGBuilder.h" 16#include "SDNodeDbgValue.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/Optional.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/ConstantFolding.h" 23#include "llvm/Analysis/ValueTracking.h" 24#include "llvm/CodeGen/Analysis.h" 25#include "llvm/CodeGen/FastISel.h" 26#include "llvm/CodeGen/FunctionLoweringInfo.h" 27#include "llvm/CodeGen/GCMetadata.h" 28#include "llvm/CodeGen/GCStrategy.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/DebugInfo.h" 37#include "llvm/IR/CallingConv.h" 38#include "llvm/IR/Constants.h" 39#include "llvm/IR/DataLayout.h" 40#include "llvm/IR/DerivedTypes.h" 41#include "llvm/IR/Function.h" 42#include "llvm/IR/GlobalVariable.h" 43#include "llvm/IR/InlineAsm.h" 44#include "llvm/IR/Instructions.h" 45#include "llvm/IR/IntrinsicInst.h" 46#include "llvm/IR/Intrinsics.h" 47#include "llvm/IR/LLVMContext.h" 48#include "llvm/IR/Module.h" 49#include "llvm/Support/CommandLine.h" 50#include "llvm/Support/Debug.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/IntegersSubsetMapping.h" 53#include "llvm/Support/MathExtras.h" 54#include "llvm/Support/raw_ostream.h" 55#include "llvm/Target/TargetFrameLowering.h" 56#include "llvm/Target/TargetInstrInfo.h" 57#include "llvm/Target/TargetIntrinsicInfo.h" 58#include "llvm/Target/TargetLibraryInfo.h" 59#include "llvm/Target/TargetLowering.h" 60#include "llvm/Target/TargetOptions.h" 61#include <algorithm> 62using namespace llvm; 63 64/// LimitFloatPrecision - Generate low-precision inline sequences for 65/// some float libcalls (6, 8 or 12 bits). 66static unsigned LimitFloatPrecision; 67 68static cl::opt<unsigned, true> 69LimitFPPrecision("limit-float-precision", 70 cl::desc("Generate low-precision inline sequences " 71 "for some float libcalls"), 72 cl::location(LimitFloatPrecision), 73 cl::init(0)); 74 75// Limit the width of DAG chains. This is important in general to prevent 76// prevent DAG-based analysis from blowing up. For example, alias analysis and 77// load clustering may not complete in reasonable time. It is difficult to 78// recognize and avoid this situation within each individual analysis, and 79// future analyses are likely to have the same behavior. Limiting DAG width is 80// the safe approach, and will be especially important with global DAGs. 81// 82// MaxParallelChains default is arbitrarily high to avoid affecting 83// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 84// sequence over this should have been converted to llvm.memcpy by the 85// frontend. It easy to induce this behavior with .ll code such as: 86// %buffer = alloca [4096 x i8] 87// %data = load [4096 x i8]* %argPtr 88// store [4096 x i8] %data, [4096 x i8]* %buffer 89static const unsigned MaxParallelChains = 64; 90 91static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL, 92 const SDValue *Parts, unsigned NumParts, 93 MVT PartVT, EVT ValueVT, const Value *V); 94 95/// getCopyFromParts - Create a value that contains the specified legal parts 96/// combined into the value they represent. If the parts combine to a type 97/// larger then ValueVT then AssertOp can be used to specify whether the extra 98/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 99/// (ISD::AssertSext). 100static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL, 101 const SDValue *Parts, 102 unsigned NumParts, MVT PartVT, EVT ValueVT, 103 const Value *V, 104 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 105 if (ValueVT.isVector()) 106 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, 107 PartVT, ValueVT, V); 108 109 assert(NumParts > 0 && "No parts to assemble!"); 110 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 111 SDValue Val = Parts[0]; 112 113 if (NumParts > 1) { 114 // Assemble the value from multiple parts. 115 if (ValueVT.isInteger()) { 116 unsigned PartBits = PartVT.getSizeInBits(); 117 unsigned ValueBits = ValueVT.getSizeInBits(); 118 119 // Assemble the power of 2 part. 120 unsigned RoundParts = NumParts & (NumParts - 1) ? 121 1 << Log2_32(NumParts) : NumParts; 122 unsigned RoundBits = PartBits * RoundParts; 123 EVT RoundVT = RoundBits == ValueBits ? 124 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 125 SDValue Lo, Hi; 126 127 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 128 129 if (RoundParts > 2) { 130 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 131 PartVT, HalfVT, V); 132 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 133 RoundParts / 2, PartVT, HalfVT, V); 134 } else { 135 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 136 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 137 } 138 139 if (TLI.isBigEndian()) 140 std::swap(Lo, Hi); 141 142 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 143 144 if (RoundParts < NumParts) { 145 // Assemble the trailing non-power-of-2 part. 146 unsigned OddParts = NumParts - RoundParts; 147 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 148 Hi = getCopyFromParts(DAG, DL, 149 Parts + RoundParts, OddParts, PartVT, OddVT, V); 150 151 // Combine the round and odd parts. 152 Lo = Val; 153 if (TLI.isBigEndian()) 154 std::swap(Lo, Hi); 155 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 156 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 157 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 158 DAG.getConstant(Lo.getValueType().getSizeInBits(), 159 TLI.getPointerTy())); 160 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 161 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 162 } 163 } else if (PartVT.isFloatingPoint()) { 164 // FP split into multiple FP parts (for ppcf128) 165 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && 166 "Unexpected split"); 167 SDValue Lo, Hi; 168 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 169 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 170 if (TLI.isBigEndian()) 171 std::swap(Lo, Hi); 172 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 173 } else { 174 // FP split into integer parts (soft fp) 175 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 176 !PartVT.isVector() && "Unexpected split"); 177 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 178 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V); 179 } 180 } 181 182 // There is now one part, held in Val. Correct it to match ValueVT. 183 EVT PartEVT = Val.getValueType(); 184 185 if (PartEVT == ValueVT) 186 return Val; 187 188 if (PartEVT.isInteger() && ValueVT.isInteger()) { 189 if (ValueVT.bitsLT(PartEVT)) { 190 // For a truncate, see if we have any information to 191 // indicate whether the truncated bits will always be 192 // zero or sign-extension. 193 if (AssertOp != ISD::DELETED_NODE) 194 Val = DAG.getNode(AssertOp, DL, PartEVT, Val, 195 DAG.getValueType(ValueVT)); 196 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 197 } 198 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 199 } 200 201 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 202 // FP_ROUND's are always exact here. 203 if (ValueVT.bitsLT(Val.getValueType())) 204 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 205 DAG.getTargetConstant(1, TLI.getPointerTy())); 206 207 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 208 } 209 210 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits()) 211 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 212 213 llvm_unreachable("Unknown mismatch!"); 214} 215 216/// getCopyFromPartsVector - Create a value that contains the specified legal 217/// parts combined into the value they represent. If the parts combine to a 218/// type larger then ValueVT then AssertOp can be used to specify whether the 219/// extra bits are known to be zero (ISD::AssertZext) or sign extended from 220/// ValueVT (ISD::AssertSext). 221static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL, 222 const SDValue *Parts, unsigned NumParts, 223 MVT PartVT, EVT ValueVT, const Value *V) { 224 assert(ValueVT.isVector() && "Not a vector value"); 225 assert(NumParts > 0 && "No parts to assemble!"); 226 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 227 SDValue Val = Parts[0]; 228 229 // Handle a multi-element vector. 230 if (NumParts > 1) { 231 EVT IntermediateVT; 232 MVT RegisterVT; 233 unsigned NumIntermediates; 234 unsigned NumRegs = 235 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 236 NumIntermediates, RegisterVT); 237 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 238 NumParts = NumRegs; // Silence a compiler warning. 239 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 240 assert(RegisterVT == Parts[0].getSimpleValueType() && 241 "Part type doesn't match part!"); 242 243 // Assemble the parts into intermediate operands. 244 SmallVector<SDValue, 8> Ops(NumIntermediates); 245 if (NumIntermediates == NumParts) { 246 // If the register was not expanded, truncate or copy the value, 247 // as appropriate. 248 for (unsigned i = 0; i != NumParts; ++i) 249 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 250 PartVT, IntermediateVT, V); 251 } else if (NumParts > 0) { 252 // If the intermediate type was expanded, build the intermediate 253 // operands from the parts. 254 assert(NumParts % NumIntermediates == 0 && 255 "Must expand into a divisible number of parts!"); 256 unsigned Factor = NumParts / NumIntermediates; 257 for (unsigned i = 0; i != NumIntermediates; ++i) 258 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 259 PartVT, IntermediateVT, V); 260 } 261 262 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 263 // intermediate operands. 264 Val = DAG.getNode(IntermediateVT.isVector() ? 265 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 266 ValueVT, &Ops[0], NumIntermediates); 267 } 268 269 // There is now one part, held in Val. Correct it to match ValueVT. 270 EVT PartEVT = Val.getValueType(); 271 272 if (PartEVT == ValueVT) 273 return Val; 274 275 if (PartEVT.isVector()) { 276 // If the element type of the source/dest vectors are the same, but the 277 // parts vector has more elements than the value vector, then we have a 278 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 279 // elements we want. 280 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) { 281 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 282 "Cannot narrow, it would be a lossy transformation"); 283 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 284 DAG.getIntPtrConstant(0)); 285 } 286 287 // Vector/Vector bitcast. 288 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) 289 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 290 291 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 292 "Cannot handle this kind of promotion"); 293 // Promoted vector extract 294 bool Smaller = ValueVT.bitsLE(PartEVT); 295 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 296 DL, ValueVT, Val); 297 298 } 299 300 // Trivial bitcast if the types are the same size and the destination 301 // vector type is legal. 302 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() && 303 TLI.isTypeLegal(ValueVT)) 304 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 305 306 // Handle cases such as i8 -> <1 x i1> 307 if (ValueVT.getVectorNumElements() != 1) { 308 LLVMContext &Ctx = *DAG.getContext(); 309 Twine ErrMsg("non-trivial scalar-to-vector conversion"); 310 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 311 if (const CallInst *CI = dyn_cast<CallInst>(I)) 312 if (isa<InlineAsm>(CI->getCalledValue())) 313 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 314 Ctx.emitError(I, ErrMsg); 315 } else { 316 Ctx.emitError(ErrMsg); 317 } 318 return DAG.getUNDEF(ValueVT); 319 } 320 321 if (ValueVT.getVectorNumElements() == 1 && 322 ValueVT.getVectorElementType() != PartEVT) { 323 bool Smaller = ValueVT.bitsLE(PartEVT); 324 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 325 DL, ValueVT.getScalarType(), Val); 326 } 327 328 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 329} 330 331static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl, 332 SDValue Val, SDValue *Parts, unsigned NumParts, 333 MVT PartVT, const Value *V); 334 335/// getCopyToParts - Create a series of nodes that contain the specified value 336/// split into legal parts. If the parts contain more bits than Val, then, for 337/// integers, ExtendKind can be used to specify how to generate the extra bits. 338static void getCopyToParts(SelectionDAG &DAG, SDLoc DL, 339 SDValue Val, SDValue *Parts, unsigned NumParts, 340 MVT PartVT, const Value *V, 341 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 342 EVT ValueVT = Val.getValueType(); 343 344 // Handle the vector case separately. 345 if (ValueVT.isVector()) 346 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V); 347 348 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 349 unsigned PartBits = PartVT.getSizeInBits(); 350 unsigned OrigNumParts = NumParts; 351 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 352 353 if (NumParts == 0) 354 return; 355 356 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 357 EVT PartEVT = PartVT; 358 if (PartEVT == ValueVT) { 359 assert(NumParts == 1 && "No-op copy with multiple parts!"); 360 Parts[0] = Val; 361 return; 362 } 363 364 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 365 // If the parts cover more bits than the value has, promote the value. 366 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 367 assert(NumParts == 1 && "Do not know what to promote to!"); 368 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 369 } else { 370 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 371 ValueVT.isInteger() && 372 "Unknown mismatch!"); 373 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 374 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 375 if (PartVT == MVT::x86mmx) 376 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 377 } 378 } else if (PartBits == ValueVT.getSizeInBits()) { 379 // Different types of the same size. 380 assert(NumParts == 1 && PartEVT != ValueVT); 381 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 382 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 383 // If the parts cover less bits than value has, truncate the value. 384 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 385 ValueVT.isInteger() && 386 "Unknown mismatch!"); 387 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 388 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 389 if (PartVT == MVT::x86mmx) 390 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 391 } 392 393 // The value may have changed - recompute ValueVT. 394 ValueVT = Val.getValueType(); 395 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 396 "Failed to tile the value with PartVT!"); 397 398 if (NumParts == 1) { 399 if (PartEVT != ValueVT) { 400 LLVMContext &Ctx = *DAG.getContext(); 401 Twine ErrMsg("scalar-to-vector conversion failed"); 402 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 403 if (const CallInst *CI = dyn_cast<CallInst>(I)) 404 if (isa<InlineAsm>(CI->getCalledValue())) 405 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 406 Ctx.emitError(I, ErrMsg); 407 } else { 408 Ctx.emitError(ErrMsg); 409 } 410 } 411 412 Parts[0] = Val; 413 return; 414 } 415 416 // Expand the value into multiple parts. 417 if (NumParts & (NumParts - 1)) { 418 // The number of parts is not a power of 2. Split off and copy the tail. 419 assert(PartVT.isInteger() && ValueVT.isInteger() && 420 "Do not know what to expand to!"); 421 unsigned RoundParts = 1 << Log2_32(NumParts); 422 unsigned RoundBits = RoundParts * PartBits; 423 unsigned OddParts = NumParts - RoundParts; 424 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 425 DAG.getIntPtrConstant(RoundBits)); 426 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V); 427 428 if (TLI.isBigEndian()) 429 // The odd parts were reversed by getCopyToParts - unreverse them. 430 std::reverse(Parts + RoundParts, Parts + NumParts); 431 432 NumParts = RoundParts; 433 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 434 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 435 } 436 437 // The number of parts is a power of 2. Repeatedly bisect the value using 438 // EXTRACT_ELEMENT. 439 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 440 EVT::getIntegerVT(*DAG.getContext(), 441 ValueVT.getSizeInBits()), 442 Val); 443 444 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 445 for (unsigned i = 0; i < NumParts; i += StepSize) { 446 unsigned ThisBits = StepSize * PartBits / 2; 447 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 448 SDValue &Part0 = Parts[i]; 449 SDValue &Part1 = Parts[i+StepSize/2]; 450 451 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 452 ThisVT, Part0, DAG.getIntPtrConstant(1)); 453 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 454 ThisVT, Part0, DAG.getIntPtrConstant(0)); 455 456 if (ThisBits == PartBits && ThisVT != PartVT) { 457 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 458 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 459 } 460 } 461 } 462 463 if (TLI.isBigEndian()) 464 std::reverse(Parts, Parts + OrigNumParts); 465} 466 467 468/// getCopyToPartsVector - Create a series of nodes that contain the specified 469/// value split into legal parts. 470static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL, 471 SDValue Val, SDValue *Parts, unsigned NumParts, 472 MVT PartVT, const Value *V) { 473 EVT ValueVT = Val.getValueType(); 474 assert(ValueVT.isVector() && "Not a vector"); 475 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 476 477 if (NumParts == 1) { 478 EVT PartEVT = PartVT; 479 if (PartEVT == ValueVT) { 480 // Nothing to do. 481 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 482 // Bitconvert vector->vector case. 483 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 484 } else if (PartVT.isVector() && 485 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() && 486 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 487 EVT ElementVT = PartVT.getVectorElementType(); 488 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 489 // undef elements. 490 SmallVector<SDValue, 16> Ops; 491 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 492 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 493 ElementVT, Val, DAG.getIntPtrConstant(i))); 494 495 for (unsigned i = ValueVT.getVectorNumElements(), 496 e = PartVT.getVectorNumElements(); i != e; ++i) 497 Ops.push_back(DAG.getUNDEF(ElementVT)); 498 499 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 500 501 // FIXME: Use CONCAT for 2x -> 4x. 502 503 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 504 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 505 } else if (PartVT.isVector() && 506 PartEVT.getVectorElementType().bitsGE( 507 ValueVT.getVectorElementType()) && 508 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 509 510 // Promoted vector extract 511 bool Smaller = PartEVT.bitsLE(ValueVT); 512 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 513 DL, PartVT, Val); 514 } else{ 515 // Vector -> scalar conversion. 516 assert(ValueVT.getVectorNumElements() == 1 && 517 "Only trivial vector-to-scalar conversions should get here!"); 518 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 519 PartVT, Val, DAG.getIntPtrConstant(0)); 520 521 bool Smaller = ValueVT.bitsLE(PartVT); 522 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 523 DL, PartVT, Val); 524 } 525 526 Parts[0] = Val; 527 return; 528 } 529 530 // Handle a multi-element vector. 531 EVT IntermediateVT; 532 MVT RegisterVT; 533 unsigned NumIntermediates; 534 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 535 IntermediateVT, 536 NumIntermediates, RegisterVT); 537 unsigned NumElements = ValueVT.getVectorNumElements(); 538 539 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 540 NumParts = NumRegs; // Silence a compiler warning. 541 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 542 543 // Split the vector into intermediate operands. 544 SmallVector<SDValue, 8> Ops(NumIntermediates); 545 for (unsigned i = 0; i != NumIntermediates; ++i) { 546 if (IntermediateVT.isVector()) 547 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 548 IntermediateVT, Val, 549 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 550 else 551 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 552 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 553 } 554 555 // Split the intermediate operands into legal parts. 556 if (NumParts == NumIntermediates) { 557 // If the register was not expanded, promote or copy the value, 558 // as appropriate. 559 for (unsigned i = 0; i != NumParts; ++i) 560 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V); 561 } else if (NumParts > 0) { 562 // If the intermediate type was expanded, split each the value into 563 // legal parts. 564 assert(NumParts % NumIntermediates == 0 && 565 "Must expand into a divisible number of parts!"); 566 unsigned Factor = NumParts / NumIntermediates; 567 for (unsigned i = 0; i != NumIntermediates; ++i) 568 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V); 569 } 570} 571 572namespace { 573 /// RegsForValue - This struct represents the registers (physical or virtual) 574 /// that a particular set of values is assigned, and the type information 575 /// about the value. The most common situation is to represent one value at a 576 /// time, but struct or array values are handled element-wise as multiple 577 /// values. The splitting of aggregates is performed recursively, so that we 578 /// never have aggregate-typed registers. The values at this point do not 579 /// necessarily have legal types, so each value may require one or more 580 /// registers of some legal type. 581 /// 582 struct RegsForValue { 583 /// ValueVTs - The value types of the values, which may not be legal, and 584 /// may need be promoted or synthesized from one or more registers. 585 /// 586 SmallVector<EVT, 4> ValueVTs; 587 588 /// RegVTs - The value types of the registers. This is the same size as 589 /// ValueVTs and it records, for each value, what the type of the assigned 590 /// register or registers are. (Individual values are never synthesized 591 /// from more than one type of register.) 592 /// 593 /// With virtual registers, the contents of RegVTs is redundant with TLI's 594 /// getRegisterType member function, however when with physical registers 595 /// it is necessary to have a separate record of the types. 596 /// 597 SmallVector<MVT, 4> RegVTs; 598 599 /// Regs - This list holds the registers assigned to the values. 600 /// Each legal or promoted value requires one register, and each 601 /// expanded value requires multiple registers. 602 /// 603 SmallVector<unsigned, 4> Regs; 604 605 RegsForValue() {} 606 607 RegsForValue(const SmallVector<unsigned, 4> ®s, 608 MVT regvt, EVT valuevt) 609 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 610 611 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 612 unsigned Reg, Type *Ty) { 613 ComputeValueVTs(tli, Ty, ValueVTs); 614 615 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 616 EVT ValueVT = ValueVTs[Value]; 617 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 618 MVT RegisterVT = tli.getRegisterType(Context, ValueVT); 619 for (unsigned i = 0; i != NumRegs; ++i) 620 Regs.push_back(Reg + i); 621 RegVTs.push_back(RegisterVT); 622 Reg += NumRegs; 623 } 624 } 625 626 /// areValueTypesLegal - Return true if types of all the values are legal. 627 bool areValueTypesLegal(const TargetLowering &TLI) { 628 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 629 MVT RegisterVT = RegVTs[Value]; 630 if (!TLI.isTypeLegal(RegisterVT)) 631 return false; 632 } 633 return true; 634 } 635 636 /// append - Add the specified values to this one. 637 void append(const RegsForValue &RHS) { 638 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 639 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 640 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 641 } 642 643 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 644 /// this value and returns the result as a ValueVTs value. This uses 645 /// Chain/Flag as the input and updates them for the output Chain/Flag. 646 /// If the Flag pointer is NULL, no flag is used. 647 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 648 SDLoc dl, 649 SDValue &Chain, SDValue *Flag, 650 const Value *V = 0) const; 651 652 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 653 /// specified value into the registers specified by this object. This uses 654 /// Chain/Flag as the input and updates them for the output Chain/Flag. 655 /// If the Flag pointer is NULL, no flag is used. 656 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, 657 SDValue &Chain, SDValue *Flag, const Value *V) const; 658 659 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 660 /// operand list. This adds the code marker, matching input operand index 661 /// (if applicable), and includes the number of values added into it. 662 void AddInlineAsmOperands(unsigned Kind, 663 bool HasMatching, unsigned MatchingIdx, 664 SelectionDAG &DAG, 665 std::vector<SDValue> &Ops) const; 666 }; 667} 668 669/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 670/// this value and returns the result as a ValueVT value. This uses 671/// Chain/Flag as the input and updates them for the output Chain/Flag. 672/// If the Flag pointer is NULL, no flag is used. 673SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 674 FunctionLoweringInfo &FuncInfo, 675 SDLoc dl, 676 SDValue &Chain, SDValue *Flag, 677 const Value *V) const { 678 // A Value with type {} or [0 x %t] needs no registers. 679 if (ValueVTs.empty()) 680 return SDValue(); 681 682 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 683 684 // Assemble the legal parts into the final values. 685 SmallVector<SDValue, 4> Values(ValueVTs.size()); 686 SmallVector<SDValue, 8> Parts; 687 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 688 // Copy the legal parts from the registers. 689 EVT ValueVT = ValueVTs[Value]; 690 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 691 MVT RegisterVT = RegVTs[Value]; 692 693 Parts.resize(NumRegs); 694 for (unsigned i = 0; i != NumRegs; ++i) { 695 SDValue P; 696 if (Flag == 0) { 697 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 698 } else { 699 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 700 *Flag = P.getValue(2); 701 } 702 703 Chain = P.getValue(1); 704 Parts[i] = P; 705 706 // If the source register was virtual and if we know something about it, 707 // add an assert node. 708 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 709 !RegisterVT.isInteger() || RegisterVT.isVector()) 710 continue; 711 712 const FunctionLoweringInfo::LiveOutInfo *LOI = 713 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 714 if (!LOI) 715 continue; 716 717 unsigned RegSize = RegisterVT.getSizeInBits(); 718 unsigned NumSignBits = LOI->NumSignBits; 719 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 720 721 if (NumZeroBits == RegSize) { 722 // The current value is a zero. 723 // Explicitly express that as it would be easier for 724 // optimizations to kick in. 725 Parts[i] = DAG.getConstant(0, RegisterVT); 726 continue; 727 } 728 729 // FIXME: We capture more information than the dag can represent. For 730 // now, just use the tightest assertzext/assertsext possible. 731 bool isSExt = true; 732 EVT FromVT(MVT::Other); 733 if (NumSignBits == RegSize) 734 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 735 else if (NumZeroBits >= RegSize-1) 736 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 737 else if (NumSignBits > RegSize-8) 738 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 739 else if (NumZeroBits >= RegSize-8) 740 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 741 else if (NumSignBits > RegSize-16) 742 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 743 else if (NumZeroBits >= RegSize-16) 744 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 745 else if (NumSignBits > RegSize-32) 746 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 747 else if (NumZeroBits >= RegSize-32) 748 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 749 else 750 continue; 751 752 // Add an assertion node. 753 assert(FromVT != MVT::Other); 754 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 755 RegisterVT, P, DAG.getValueType(FromVT)); 756 } 757 758 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 759 NumRegs, RegisterVT, ValueVT, V); 760 Part += NumRegs; 761 Parts.clear(); 762 } 763 764 return DAG.getNode(ISD::MERGE_VALUES, dl, 765 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 766 &Values[0], ValueVTs.size()); 767} 768 769/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 770/// specified value into the registers specified by this object. This uses 771/// Chain/Flag as the input and updates them for the output Chain/Flag. 772/// If the Flag pointer is NULL, no flag is used. 773void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, 774 SDValue &Chain, SDValue *Flag, 775 const Value *V) const { 776 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 777 778 // Get the list of the values's legal parts. 779 unsigned NumRegs = Regs.size(); 780 SmallVector<SDValue, 8> Parts(NumRegs); 781 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 782 EVT ValueVT = ValueVTs[Value]; 783 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 784 MVT RegisterVT = RegVTs[Value]; 785 ISD::NodeType ExtendKind = 786 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND; 787 788 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 789 &Parts[Part], NumParts, RegisterVT, V, ExtendKind); 790 Part += NumParts; 791 } 792 793 // Copy the parts into the registers. 794 SmallVector<SDValue, 8> Chains(NumRegs); 795 for (unsigned i = 0; i != NumRegs; ++i) { 796 SDValue Part; 797 if (Flag == 0) { 798 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 799 } else { 800 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 801 *Flag = Part.getValue(1); 802 } 803 804 Chains[i] = Part.getValue(0); 805 } 806 807 if (NumRegs == 1 || Flag) 808 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 809 // flagged to it. That is the CopyToReg nodes and the user are considered 810 // a single scheduling unit. If we create a TokenFactor and return it as 811 // chain, then the TokenFactor is both a predecessor (operand) of the 812 // user as well as a successor (the TF operands are flagged to the user). 813 // c1, f1 = CopyToReg 814 // c2, f2 = CopyToReg 815 // c3 = TokenFactor c1, c2 816 // ... 817 // = op c3, ..., f2 818 Chain = Chains[NumRegs-1]; 819 else 820 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 821} 822 823/// AddInlineAsmOperands - Add this value to the specified inlineasm node 824/// operand list. This adds the code marker and includes the number of 825/// values added into it. 826void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 827 unsigned MatchingIdx, 828 SelectionDAG &DAG, 829 std::vector<SDValue> &Ops) const { 830 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 831 832 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 833 if (HasMatching) 834 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 835 else if (!Regs.empty() && 836 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 837 // Put the register class of the virtual registers in the flag word. That 838 // way, later passes can recompute register class constraints for inline 839 // assembly as well as normal instructions. 840 // Don't do this for tied operands that can use the regclass information 841 // from the def. 842 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 843 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 844 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 845 } 846 847 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 848 Ops.push_back(Res); 849 850 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 851 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 852 MVT RegisterVT = RegVTs[Value]; 853 for (unsigned i = 0; i != NumRegs; ++i) { 854 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 855 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 856 } 857 } 858} 859 860void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 861 const TargetLibraryInfo *li) { 862 AA = &aa; 863 GFI = gfi; 864 LibInfo = li; 865 TD = DAG.getTarget().getDataLayout(); 866 Context = DAG.getContext(); 867 LPadToCallSiteMap.clear(); 868} 869 870/// clear - Clear out the current SelectionDAG and the associated 871/// state and prepare this SelectionDAGBuilder object to be used 872/// for a new block. This doesn't clear out information about 873/// additional blocks that are needed to complete switch lowering 874/// or PHI node updating; that information is cleared out as it is 875/// consumed. 876void SelectionDAGBuilder::clear() { 877 NodeMap.clear(); 878 UnusedArgNodeMap.clear(); 879 PendingLoads.clear(); 880 PendingExports.clear(); 881 CurInst = NULL; 882 HasTailCall = false; 883} 884 885/// clearDanglingDebugInfo - Clear the dangling debug information 886/// map. This function is separated from the clear so that debug 887/// information that is dangling in a basic block can be properly 888/// resolved in a different basic block. This allows the 889/// SelectionDAG to resolve dangling debug information attached 890/// to PHI nodes. 891void SelectionDAGBuilder::clearDanglingDebugInfo() { 892 DanglingDebugInfoMap.clear(); 893} 894 895/// getRoot - Return the current virtual root of the Selection DAG, 896/// flushing any PendingLoad items. This must be done before emitting 897/// a store or any other node that may need to be ordered after any 898/// prior load instructions. 899/// 900SDValue SelectionDAGBuilder::getRoot() { 901 if (PendingLoads.empty()) 902 return DAG.getRoot(); 903 904 if (PendingLoads.size() == 1) { 905 SDValue Root = PendingLoads[0]; 906 DAG.setRoot(Root); 907 PendingLoads.clear(); 908 return Root; 909 } 910 911 // Otherwise, we have to make a token factor node. 912 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, 913 &PendingLoads[0], PendingLoads.size()); 914 PendingLoads.clear(); 915 DAG.setRoot(Root); 916 return Root; 917} 918 919/// getControlRoot - Similar to getRoot, but instead of flushing all the 920/// PendingLoad items, flush all the PendingExports items. It is necessary 921/// to do this before emitting a terminator instruction. 922/// 923SDValue SelectionDAGBuilder::getControlRoot() { 924 SDValue Root = DAG.getRoot(); 925 926 if (PendingExports.empty()) 927 return Root; 928 929 // Turn all of the CopyToReg chains into one factored node. 930 if (Root.getOpcode() != ISD::EntryToken) { 931 unsigned i = 0, e = PendingExports.size(); 932 for (; i != e; ++i) { 933 assert(PendingExports[i].getNode()->getNumOperands() > 1); 934 if (PendingExports[i].getNode()->getOperand(0) == Root) 935 break; // Don't add the root if we already indirectly depend on it. 936 } 937 938 if (i == e) 939 PendingExports.push_back(Root); 940 } 941 942 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, 943 &PendingExports[0], 944 PendingExports.size()); 945 PendingExports.clear(); 946 DAG.setRoot(Root); 947 return Root; 948} 949 950void SelectionDAGBuilder::visit(const Instruction &I) { 951 // Set up outgoing PHI node register values before emitting the terminator. 952 if (isa<TerminatorInst>(&I)) 953 HandlePHINodesInSuccessorBlocks(I.getParent()); 954 955 ++SDNodeOrder; 956 957 CurInst = &I; 958 959 visit(I.getOpcode(), I); 960 961 if (!isa<TerminatorInst>(&I) && !HasTailCall) 962 CopyToExportRegsIfNeeded(&I); 963 964 CurInst = NULL; 965} 966 967void SelectionDAGBuilder::visitPHI(const PHINode &) { 968 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 969} 970 971void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 972 // Note: this doesn't use InstVisitor, because it has to work with 973 // ConstantExpr's in addition to instructions. 974 switch (Opcode) { 975 default: llvm_unreachable("Unknown instruction type encountered!"); 976 // Build the switch statement using the Instruction.def file. 977#define HANDLE_INST(NUM, OPCODE, CLASS) \ 978 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; 979#include "llvm/IR/Instruction.def" 980 } 981} 982 983// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 984// generate the debug data structures now that we've seen its definition. 985void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 986 SDValue Val) { 987 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 988 if (DDI.getDI()) { 989 const DbgValueInst *DI = DDI.getDI(); 990 DebugLoc dl = DDI.getdl(); 991 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 992 MDNode *Variable = DI->getVariable(); 993 uint64_t Offset = DI->getOffset(); 994 SDDbgValue *SDV; 995 if (Val.getNode()) { 996 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 997 SDV = DAG.getDbgValue(Variable, Val.getNode(), 998 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 999 DAG.AddDbgValue(SDV, Val.getNode(), false); 1000 } 1001 } else 1002 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); 1003 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 1004 } 1005} 1006 1007/// getValue - Return an SDValue for the given Value. 1008SDValue SelectionDAGBuilder::getValue(const Value *V) { 1009 // If we already have an SDValue for this value, use it. It's important 1010 // to do this first, so that we don't create a CopyFromReg if we already 1011 // have a regular SDValue. 1012 SDValue &N = NodeMap[V]; 1013 if (N.getNode()) return N; 1014 1015 // If there's a virtual register allocated and initialized for this 1016 // value, use it. 1017 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 1018 if (It != FuncInfo.ValueMap.end()) { 1019 unsigned InReg = It->second; 1020 RegsForValue RFV(*DAG.getContext(), *TM.getTargetLowering(), 1021 InReg, V->getType()); 1022 SDValue Chain = DAG.getEntryNode(); 1023 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V); 1024 resolveDanglingDebugInfo(V, N); 1025 return N; 1026 } 1027 1028 // Otherwise create a new SDValue and remember it. 1029 SDValue Val = getValueImpl(V); 1030 NodeMap[V] = Val; 1031 resolveDanglingDebugInfo(V, Val); 1032 return Val; 1033} 1034 1035/// getNonRegisterValue - Return an SDValue for the given Value, but 1036/// don't look in FuncInfo.ValueMap for a virtual register. 1037SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1038 // If we already have an SDValue for this value, use it. 1039 SDValue &N = NodeMap[V]; 1040 if (N.getNode()) return N; 1041 1042 // Otherwise create a new SDValue and remember it. 1043 SDValue Val = getValueImpl(V); 1044 NodeMap[V] = Val; 1045 resolveDanglingDebugInfo(V, Val); 1046 return Val; 1047} 1048 1049/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1050/// Create an SDValue for the given value. 1051SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1052 const TargetLowering *TLI = TM.getTargetLowering(); 1053 1054 if (const Constant *C = dyn_cast<Constant>(V)) { 1055 EVT VT = TLI->getValueType(V->getType(), true); 1056 1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1058 return DAG.getConstant(*CI, VT); 1059 1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1061 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT); 1062 1063 if (isa<ConstantPointerNull>(C)) 1064 return DAG.getConstant(0, TLI->getPointerTy()); 1065 1066 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1067 return DAG.getConstantFP(*CFP, VT); 1068 1069 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1070 return DAG.getUNDEF(VT); 1071 1072 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1073 visit(CE->getOpcode(), *CE); 1074 SDValue N1 = NodeMap[V]; 1075 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1076 return N1; 1077 } 1078 1079 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1080 SmallVector<SDValue, 4> Constants; 1081 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1082 OI != OE; ++OI) { 1083 SDNode *Val = getValue(*OI).getNode(); 1084 // If the operand is an empty aggregate, there are no values. 1085 if (!Val) continue; 1086 // Add each leaf value from the operand to the Constants list 1087 // to form a flattened list of all the values. 1088 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1089 Constants.push_back(SDValue(Val, i)); 1090 } 1091 1092 return DAG.getMergeValues(&Constants[0], Constants.size(), 1093 getCurSDLoc()); 1094 } 1095 1096 if (const ConstantDataSequential *CDS = 1097 dyn_cast<ConstantDataSequential>(C)) { 1098 SmallVector<SDValue, 4> Ops; 1099 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1100 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1101 // Add each leaf value from the operand to the Constants list 1102 // to form a flattened list of all the values. 1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1104 Ops.push_back(SDValue(Val, i)); 1105 } 1106 1107 if (isa<ArrayType>(CDS->getType())) 1108 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc()); 1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), 1110 VT, &Ops[0], Ops.size()); 1111 } 1112 1113 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1114 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1115 "Unknown struct or array constant!"); 1116 1117 SmallVector<EVT, 4> ValueVTs; 1118 ComputeValueVTs(*TLI, C->getType(), ValueVTs); 1119 unsigned NumElts = ValueVTs.size(); 1120 if (NumElts == 0) 1121 return SDValue(); // empty struct 1122 SmallVector<SDValue, 4> Constants(NumElts); 1123 for (unsigned i = 0; i != NumElts; ++i) { 1124 EVT EltVT = ValueVTs[i]; 1125 if (isa<UndefValue>(C)) 1126 Constants[i] = DAG.getUNDEF(EltVT); 1127 else if (EltVT.isFloatingPoint()) 1128 Constants[i] = DAG.getConstantFP(0, EltVT); 1129 else 1130 Constants[i] = DAG.getConstant(0, EltVT); 1131 } 1132 1133 return DAG.getMergeValues(&Constants[0], NumElts, 1134 getCurSDLoc()); 1135 } 1136 1137 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1138 return DAG.getBlockAddress(BA, VT); 1139 1140 VectorType *VecTy = cast<VectorType>(V->getType()); 1141 unsigned NumElements = VecTy->getNumElements(); 1142 1143 // Now that we know the number and type of the elements, get that number of 1144 // elements into the Ops array based on what kind of constant it is. 1145 SmallVector<SDValue, 16> Ops; 1146 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1147 for (unsigned i = 0; i != NumElements; ++i) 1148 Ops.push_back(getValue(CV->getOperand(i))); 1149 } else { 1150 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1151 EVT EltVT = TLI->getValueType(VecTy->getElementType()); 1152 1153 SDValue Op; 1154 if (EltVT.isFloatingPoint()) 1155 Op = DAG.getConstantFP(0, EltVT); 1156 else 1157 Op = DAG.getConstant(0, EltVT); 1158 Ops.assign(NumElements, Op); 1159 } 1160 1161 // Create a BUILD_VECTOR node. 1162 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), 1163 VT, &Ops[0], Ops.size()); 1164 } 1165 1166 // If this is a static alloca, generate it as the frameindex instead of 1167 // computation. 1168 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1169 DenseMap<const AllocaInst*, int>::iterator SI = 1170 FuncInfo.StaticAllocaMap.find(AI); 1171 if (SI != FuncInfo.StaticAllocaMap.end()) 1172 return DAG.getFrameIndex(SI->second, TLI->getPointerTy()); 1173 } 1174 1175 // If this is an instruction which fast-isel has deferred, select it now. 1176 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1177 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1178 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType()); 1179 SDValue Chain = DAG.getEntryNode(); 1180 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V); 1181 } 1182 1183 llvm_unreachable("Can't get register for value!"); 1184} 1185 1186void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1187 const TargetLowering *TLI = TM.getTargetLowering(); 1188 SDValue Chain = getControlRoot(); 1189 SmallVector<ISD::OutputArg, 8> Outs; 1190 SmallVector<SDValue, 8> OutVals; 1191 1192 if (!FuncInfo.CanLowerReturn) { 1193 unsigned DemoteReg = FuncInfo.DemoteRegister; 1194 const Function *F = I.getParent()->getParent(); 1195 1196 // Emit a store of the return value through the virtual register. 1197 // Leave Outs empty so that LowerReturn won't try to load return 1198 // registers the usual way. 1199 SmallVector<EVT, 1> PtrValueVTs; 1200 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()), 1201 PtrValueVTs); 1202 1203 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1204 SDValue RetOp = getValue(I.getOperand(0)); 1205 1206 SmallVector<EVT, 4> ValueVTs; 1207 SmallVector<uint64_t, 4> Offsets; 1208 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1209 unsigned NumValues = ValueVTs.size(); 1210 1211 SmallVector<SDValue, 4> Chains(NumValues); 1212 for (unsigned i = 0; i != NumValues; ++i) { 1213 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), 1214 RetPtr.getValueType(), RetPtr, 1215 DAG.getIntPtrConstant(Offsets[i])); 1216 Chains[i] = 1217 DAG.getStore(Chain, getCurSDLoc(), 1218 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1219 // FIXME: better loc info would be nice. 1220 Add, MachinePointerInfo(), false, false, 0); 1221 } 1222 1223 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 1224 MVT::Other, &Chains[0], NumValues); 1225 } else if (I.getNumOperands() != 0) { 1226 SmallVector<EVT, 4> ValueVTs; 1227 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs); 1228 unsigned NumValues = ValueVTs.size(); 1229 if (NumValues) { 1230 SDValue RetOp = getValue(I.getOperand(0)); 1231 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1232 EVT VT = ValueVTs[j]; 1233 1234 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1235 1236 const Function *F = I.getParent()->getParent(); 1237 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1238 Attribute::SExt)) 1239 ExtendKind = ISD::SIGN_EXTEND; 1240 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1241 Attribute::ZExt)) 1242 ExtendKind = ISD::ZERO_EXTEND; 1243 1244 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1245 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind); 1246 1247 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT); 1248 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT); 1249 SmallVector<SDValue, 4> Parts(NumParts); 1250 getCopyToParts(DAG, getCurSDLoc(), 1251 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1252 &Parts[0], NumParts, PartVT, &I, ExtendKind); 1253 1254 // 'inreg' on function refers to return value 1255 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1256 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1257 Attribute::InReg)) 1258 Flags.setInReg(); 1259 1260 // Propagate extension type if any 1261 if (ExtendKind == ISD::SIGN_EXTEND) 1262 Flags.setSExt(); 1263 else if (ExtendKind == ISD::ZERO_EXTEND) 1264 Flags.setZExt(); 1265 1266 for (unsigned i = 0; i < NumParts; ++i) { 1267 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1268 /*isfixed=*/true, 0, 0)); 1269 OutVals.push_back(Parts[i]); 1270 } 1271 } 1272 } 1273 } 1274 1275 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1276 CallingConv::ID CallConv = 1277 DAG.getMachineFunction().getFunction()->getCallingConv(); 1278 Chain = TM.getTargetLowering()->LowerReturn(Chain, CallConv, isVarArg, 1279 Outs, OutVals, getCurSDLoc(), 1280 DAG); 1281 1282 // Verify that the target's LowerReturn behaved as expected. 1283 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1284 "LowerReturn didn't return a valid chain!"); 1285 1286 // Update the DAG with the new chain value resulting from return lowering. 1287 DAG.setRoot(Chain); 1288} 1289 1290/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1291/// created for it, emit nodes to copy the value into the virtual 1292/// registers. 1293void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1294 // Skip empty types 1295 if (V->getType()->isEmptyTy()) 1296 return; 1297 1298 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1299 if (VMI != FuncInfo.ValueMap.end()) { 1300 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1301 CopyValueToVirtualRegister(V, VMI->second); 1302 } 1303} 1304 1305/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1306/// the current basic block, add it to ValueMap now so that we'll get a 1307/// CopyTo/FromReg. 1308void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1309 // No need to export constants. 1310 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1311 1312 // Already exported? 1313 if (FuncInfo.isExportedInst(V)) return; 1314 1315 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1316 CopyValueToVirtualRegister(V, Reg); 1317} 1318 1319bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1320 const BasicBlock *FromBB) { 1321 // The operands of the setcc have to be in this block. We don't know 1322 // how to export them from some other block. 1323 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1324 // Can export from current BB. 1325 if (VI->getParent() == FromBB) 1326 return true; 1327 1328 // Is already exported, noop. 1329 return FuncInfo.isExportedInst(V); 1330 } 1331 1332 // If this is an argument, we can export it if the BB is the entry block or 1333 // if it is already exported. 1334 if (isa<Argument>(V)) { 1335 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1336 return true; 1337 1338 // Otherwise, can only export this if it is already exported. 1339 return FuncInfo.isExportedInst(V); 1340 } 1341 1342 // Otherwise, constants can always be exported. 1343 return true; 1344} 1345 1346/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1347uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1348 const MachineBasicBlock *Dst) const { 1349 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1350 if (!BPI) 1351 return 0; 1352 const BasicBlock *SrcBB = Src->getBasicBlock(); 1353 const BasicBlock *DstBB = Dst->getBasicBlock(); 1354 return BPI->getEdgeWeight(SrcBB, DstBB); 1355} 1356 1357void SelectionDAGBuilder:: 1358addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1359 uint32_t Weight /* = 0 */) { 1360 if (!Weight) 1361 Weight = getEdgeWeight(Src, Dst); 1362 Src->addSuccessor(Dst, Weight); 1363} 1364 1365 1366static bool InBlock(const Value *V, const BasicBlock *BB) { 1367 if (const Instruction *I = dyn_cast<Instruction>(V)) 1368 return I->getParent() == BB; 1369 return true; 1370} 1371 1372/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1373/// This function emits a branch and is used at the leaves of an OR or an 1374/// AND operator tree. 1375/// 1376void 1377SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1378 MachineBasicBlock *TBB, 1379 MachineBasicBlock *FBB, 1380 MachineBasicBlock *CurBB, 1381 MachineBasicBlock *SwitchBB) { 1382 const BasicBlock *BB = CurBB->getBasicBlock(); 1383 1384 // If the leaf of the tree is a comparison, merge the condition into 1385 // the caseblock. 1386 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1387 // The operands of the cmp have to be in this block. We don't know 1388 // how to export them from some other block. If this is the first block 1389 // of the sequence, no exporting is needed. 1390 if (CurBB == SwitchBB || 1391 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1392 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1393 ISD::CondCode Condition; 1394 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1395 Condition = getICmpCondCode(IC->getPredicate()); 1396 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1397 Condition = getFCmpCondCode(FC->getPredicate()); 1398 if (TM.Options.NoNaNsFPMath) 1399 Condition = getFCmpCodeWithoutNaN(Condition); 1400 } else { 1401 Condition = ISD::SETEQ; // silence warning. 1402 llvm_unreachable("Unknown compare instruction"); 1403 } 1404 1405 CaseBlock CB(Condition, BOp->getOperand(0), 1406 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1407 SwitchCases.push_back(CB); 1408 return; 1409 } 1410 } 1411 1412 // Create a CaseBlock record representing this branch. 1413 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1414 NULL, TBB, FBB, CurBB); 1415 SwitchCases.push_back(CB); 1416} 1417 1418/// FindMergedConditions - If Cond is an expression like 1419void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1420 MachineBasicBlock *TBB, 1421 MachineBasicBlock *FBB, 1422 MachineBasicBlock *CurBB, 1423 MachineBasicBlock *SwitchBB, 1424 unsigned Opc) { 1425 // If this node is not part of the or/and tree, emit it as a branch. 1426 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1427 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1428 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1429 BOp->getParent() != CurBB->getBasicBlock() || 1430 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1431 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1432 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1433 return; 1434 } 1435 1436 // Create TmpBB after CurBB. 1437 MachineFunction::iterator BBI = CurBB; 1438 MachineFunction &MF = DAG.getMachineFunction(); 1439 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1440 CurBB->getParent()->insert(++BBI, TmpBB); 1441 1442 if (Opc == Instruction::Or) { 1443 // Codegen X | Y as: 1444 // jmp_if_X TBB 1445 // jmp TmpBB 1446 // TmpBB: 1447 // jmp_if_Y TBB 1448 // jmp FBB 1449 // 1450 1451 // Emit the LHS condition. 1452 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1453 1454 // Emit the RHS condition into TmpBB. 1455 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1456 } else { 1457 assert(Opc == Instruction::And && "Unknown merge op!"); 1458 // Codegen X & Y as: 1459 // jmp_if_X TmpBB 1460 // jmp FBB 1461 // TmpBB: 1462 // jmp_if_Y TBB 1463 // jmp FBB 1464 // 1465 // This requires creation of TmpBB after CurBB. 1466 1467 // Emit the LHS condition. 1468 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1469 1470 // Emit the RHS condition into TmpBB. 1471 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1472 } 1473} 1474 1475/// If the set of cases should be emitted as a series of branches, return true. 1476/// If we should emit this as a bunch of and/or'd together conditions, return 1477/// false. 1478bool 1479SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) { 1480 if (Cases.size() != 2) return true; 1481 1482 // If this is two comparisons of the same values or'd or and'd together, they 1483 // will get folded into a single comparison, so don't emit two blocks. 1484 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1485 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1486 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1487 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1488 return false; 1489 } 1490 1491 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1492 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1493 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1494 Cases[0].CC == Cases[1].CC && 1495 isa<Constant>(Cases[0].CmpRHS) && 1496 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1497 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1498 return false; 1499 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1500 return false; 1501 } 1502 1503 return true; 1504} 1505 1506void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1507 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1508 1509 // Update machine-CFG edges. 1510 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1511 1512 // Figure out which block is immediately after the current one. 1513 MachineBasicBlock *NextBlock = 0; 1514 MachineFunction::iterator BBI = BrMBB; 1515 if (++BBI != FuncInfo.MF->end()) 1516 NextBlock = BBI; 1517 1518 if (I.isUnconditional()) { 1519 // Update machine-CFG edges. 1520 BrMBB->addSuccessor(Succ0MBB); 1521 1522 // If this is not a fall-through branch, emit the branch. 1523 if (Succ0MBB != NextBlock) 1524 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), 1525 MVT::Other, getControlRoot(), 1526 DAG.getBasicBlock(Succ0MBB))); 1527 1528 return; 1529 } 1530 1531 // If this condition is one of the special cases we handle, do special stuff 1532 // now. 1533 const Value *CondVal = I.getCondition(); 1534 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1535 1536 // If this is a series of conditions that are or'd or and'd together, emit 1537 // this as a sequence of branches instead of setcc's with and/or operations. 1538 // As long as jumps are not expensive, this should improve performance. 1539 // For example, instead of something like: 1540 // cmp A, B 1541 // C = seteq 1542 // cmp D, E 1543 // F = setle 1544 // or C, F 1545 // jnz foo 1546 // Emit: 1547 // cmp A, B 1548 // je foo 1549 // cmp D, E 1550 // jle foo 1551 // 1552 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1553 if (!TM.getTargetLowering()->isJumpExpensive() && 1554 BOp->hasOneUse() && 1555 (BOp->getOpcode() == Instruction::And || 1556 BOp->getOpcode() == Instruction::Or)) { 1557 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1558 BOp->getOpcode()); 1559 // If the compares in later blocks need to use values not currently 1560 // exported from this block, export them now. This block should always 1561 // be the first entry. 1562 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1563 1564 // Allow some cases to be rejected. 1565 if (ShouldEmitAsBranches(SwitchCases)) { 1566 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1567 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1568 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1569 } 1570 1571 // Emit the branch for this block. 1572 visitSwitchCase(SwitchCases[0], BrMBB); 1573 SwitchCases.erase(SwitchCases.begin()); 1574 return; 1575 } 1576 1577 // Okay, we decided not to do this, remove any inserted MBB's and clear 1578 // SwitchCases. 1579 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1580 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1581 1582 SwitchCases.clear(); 1583 } 1584 } 1585 1586 // Create a CaseBlock record representing this branch. 1587 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1588 NULL, Succ0MBB, Succ1MBB, BrMBB); 1589 1590 // Use visitSwitchCase to actually insert the fast branch sequence for this 1591 // cond branch. 1592 visitSwitchCase(CB, BrMBB); 1593} 1594 1595/// visitSwitchCase - Emits the necessary code to represent a single node in 1596/// the binary search tree resulting from lowering a switch instruction. 1597void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1598 MachineBasicBlock *SwitchBB) { 1599 SDValue Cond; 1600 SDValue CondLHS = getValue(CB.CmpLHS); 1601 SDLoc dl = getCurSDLoc(); 1602 1603 // Build the setcc now. 1604 if (CB.CmpMHS == NULL) { 1605 // Fold "(X == true)" to X and "(X == false)" to !X to 1606 // handle common cases produced by branch lowering. 1607 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1608 CB.CC == ISD::SETEQ) 1609 Cond = CondLHS; 1610 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1611 CB.CC == ISD::SETEQ) { 1612 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1613 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1614 } else 1615 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1616 } else { 1617 assert(CB.CC == ISD::SETCC_INVALID && 1618 "Condition is undefined for to-the-range belonging check."); 1619 1620 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1621 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1622 1623 SDValue CmpOp = getValue(CB.CmpMHS); 1624 EVT VT = CmpOp.getValueType(); 1625 1626 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) { 1627 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1628 ISD::SETULE); 1629 } else { 1630 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1631 VT, CmpOp, DAG.getConstant(Low, VT)); 1632 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1633 DAG.getConstant(High-Low, VT), ISD::SETULE); 1634 } 1635 } 1636 1637 // Update successor info 1638 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1639 // TrueBB and FalseBB are always different unless the incoming IR is 1640 // degenerate. This only happens when running llc on weird IR. 1641 if (CB.TrueBB != CB.FalseBB) 1642 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1643 1644 // Set NextBlock to be the MBB immediately after the current one, if any. 1645 // This is used to avoid emitting unnecessary branches to the next block. 1646 MachineBasicBlock *NextBlock = 0; 1647 MachineFunction::iterator BBI = SwitchBB; 1648 if (++BBI != FuncInfo.MF->end()) 1649 NextBlock = BBI; 1650 1651 // If the lhs block is the next block, invert the condition so that we can 1652 // fall through to the lhs instead of the rhs block. 1653 if (CB.TrueBB == NextBlock) { 1654 std::swap(CB.TrueBB, CB.FalseBB); 1655 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1656 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1657 } 1658 1659 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1660 MVT::Other, getControlRoot(), Cond, 1661 DAG.getBasicBlock(CB.TrueBB)); 1662 1663 // Insert the false branch. Do this even if it's a fall through branch, 1664 // this makes it easier to do DAG optimizations which require inverting 1665 // the branch condition. 1666 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1667 DAG.getBasicBlock(CB.FalseBB)); 1668 1669 DAG.setRoot(BrCond); 1670} 1671 1672/// visitJumpTable - Emit JumpTable node in the current MBB 1673void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1674 // Emit the code for the jump table 1675 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1676 EVT PTy = TM.getTargetLowering()->getPointerTy(); 1677 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), 1678 JT.Reg, PTy); 1679 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1680 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(), 1681 MVT::Other, Index.getValue(1), 1682 Table, Index); 1683 DAG.setRoot(BrJumpTable); 1684} 1685 1686/// visitJumpTableHeader - This function emits necessary code to produce index 1687/// in the JumpTable from switch case. 1688void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1689 JumpTableHeader &JTH, 1690 MachineBasicBlock *SwitchBB) { 1691 // Subtract the lowest switch case value from the value being switched on and 1692 // conditional branch to default mbb if the result is greater than the 1693 // difference between smallest and largest cases. 1694 SDValue SwitchOp = getValue(JTH.SValue); 1695 EVT VT = SwitchOp.getValueType(); 1696 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp, 1697 DAG.getConstant(JTH.First, VT)); 1698 1699 // The SDNode we just created, which holds the value being switched on minus 1700 // the smallest case value, needs to be copied to a virtual register so it 1701 // can be used as an index into the jump table in a subsequent basic block. 1702 // This value may be smaller or larger than the target's pointer type, and 1703 // therefore require extension or truncating. 1704 const TargetLowering *TLI = TM.getTargetLowering(); 1705 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy()); 1706 1707 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy()); 1708 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(), 1709 JumpTableReg, SwitchOp); 1710 JT.Reg = JumpTableReg; 1711 1712 // Emit the range check for the jump table, and branch to the default block 1713 // for the switch statement if the value being switched on exceeds the largest 1714 // case in the switch. 1715 SDValue CMP = DAG.getSetCC(getCurSDLoc(), 1716 TLI->getSetCCResultType(*DAG.getContext(), 1717 Sub.getValueType()), 1718 Sub, 1719 DAG.getConstant(JTH.Last - JTH.First,VT), 1720 ISD::SETUGT); 1721 1722 // Set NextBlock to be the MBB immediately after the current one, if any. 1723 // This is used to avoid emitting unnecessary branches to the next block. 1724 MachineBasicBlock *NextBlock = 0; 1725 MachineFunction::iterator BBI = SwitchBB; 1726 1727 if (++BBI != FuncInfo.MF->end()) 1728 NextBlock = BBI; 1729 1730 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(), 1731 MVT::Other, CopyTo, CMP, 1732 DAG.getBasicBlock(JT.Default)); 1733 1734 if (JT.MBB != NextBlock) 1735 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond, 1736 DAG.getBasicBlock(JT.MBB)); 1737 1738 DAG.setRoot(BrCond); 1739} 1740 1741/// visitBitTestHeader - This function emits necessary code to produce value 1742/// suitable for "bit tests" 1743void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1744 MachineBasicBlock *SwitchBB) { 1745 // Subtract the minimum value 1746 SDValue SwitchOp = getValue(B.SValue); 1747 EVT VT = SwitchOp.getValueType(); 1748 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp, 1749 DAG.getConstant(B.First, VT)); 1750 1751 // Check range 1752 const TargetLowering *TLI = TM.getTargetLowering(); 1753 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(), 1754 TLI->getSetCCResultType(*DAG.getContext(), 1755 Sub.getValueType()), 1756 Sub, DAG.getConstant(B.Range, VT), 1757 ISD::SETUGT); 1758 1759 // Determine the type of the test operands. 1760 bool UsePtrType = false; 1761 if (!TLI->isTypeLegal(VT)) 1762 UsePtrType = true; 1763 else { 1764 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1765 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1766 // Switch table case range are encoded into series of masks. 1767 // Just use pointer type, it's guaranteed to fit. 1768 UsePtrType = true; 1769 break; 1770 } 1771 } 1772 if (UsePtrType) { 1773 VT = TLI->getPointerTy(); 1774 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT); 1775 } 1776 1777 B.RegVT = VT.getSimpleVT(); 1778 B.Reg = FuncInfo.CreateReg(B.RegVT); 1779 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(), 1780 B.Reg, Sub); 1781 1782 // Set NextBlock to be the MBB immediately after the current one, if any. 1783 // This is used to avoid emitting unnecessary branches to the next block. 1784 MachineBasicBlock *NextBlock = 0; 1785 MachineFunction::iterator BBI = SwitchBB; 1786 if (++BBI != FuncInfo.MF->end()) 1787 NextBlock = BBI; 1788 1789 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1790 1791 addSuccessorWithWeight(SwitchBB, B.Default); 1792 addSuccessorWithWeight(SwitchBB, MBB); 1793 1794 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(), 1795 MVT::Other, CopyTo, RangeCmp, 1796 DAG.getBasicBlock(B.Default)); 1797 1798 if (MBB != NextBlock) 1799 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo, 1800 DAG.getBasicBlock(MBB)); 1801 1802 DAG.setRoot(BrRange); 1803} 1804 1805/// visitBitTestCase - this function produces one "bit test" 1806void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1807 MachineBasicBlock* NextMBB, 1808 uint32_t BranchWeightToNext, 1809 unsigned Reg, 1810 BitTestCase &B, 1811 MachineBasicBlock *SwitchBB) { 1812 MVT VT = BB.RegVT; 1813 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), 1814 Reg, VT); 1815 SDValue Cmp; 1816 unsigned PopCount = CountPopulation_64(B.Mask); 1817 const TargetLowering *TLI = TM.getTargetLowering(); 1818 if (PopCount == 1) { 1819 // Testing for a single bit; just compare the shift count with what it 1820 // would need to be to shift a 1 bit in that position. 1821 Cmp = DAG.getSetCC(getCurSDLoc(), 1822 TLI->getSetCCResultType(*DAG.getContext(), VT), 1823 ShiftOp, 1824 DAG.getConstant(countTrailingZeros(B.Mask), VT), 1825 ISD::SETEQ); 1826 } else if (PopCount == BB.Range) { 1827 // There is only one zero bit in the range, test for it directly. 1828 Cmp = DAG.getSetCC(getCurSDLoc(), 1829 TLI->getSetCCResultType(*DAG.getContext(), VT), 1830 ShiftOp, 1831 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1832 ISD::SETNE); 1833 } else { 1834 // Make desired shift 1835 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT, 1836 DAG.getConstant(1, VT), ShiftOp); 1837 1838 // Emit bit tests and jumps 1839 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(), 1840 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1841 Cmp = DAG.getSetCC(getCurSDLoc(), 1842 TLI->getSetCCResultType(*DAG.getContext(), VT), 1843 AndOp, DAG.getConstant(0, VT), 1844 ISD::SETNE); 1845 } 1846 1847 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight. 1848 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight); 1849 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext. 1850 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext); 1851 1852 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(), 1853 MVT::Other, getControlRoot(), 1854 Cmp, DAG.getBasicBlock(B.TargetBB)); 1855 1856 // Set NextBlock to be the MBB immediately after the current one, if any. 1857 // This is used to avoid emitting unnecessary branches to the next block. 1858 MachineBasicBlock *NextBlock = 0; 1859 MachineFunction::iterator BBI = SwitchBB; 1860 if (++BBI != FuncInfo.MF->end()) 1861 NextBlock = BBI; 1862 1863 if (NextMBB != NextBlock) 1864 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd, 1865 DAG.getBasicBlock(NextMBB)); 1866 1867 DAG.setRoot(BrAnd); 1868} 1869 1870void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1871 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1872 1873 // Retrieve successors. 1874 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1875 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1876 1877 const Value *Callee(I.getCalledValue()); 1878 const Function *Fn = dyn_cast<Function>(Callee); 1879 if (isa<InlineAsm>(Callee)) 1880 visitInlineAsm(&I); 1881 else if (Fn && Fn->isIntrinsic()) { 1882 assert(Fn->getIntrinsicID() == Intrinsic::donothing); 1883 // Ignore invokes to @llvm.donothing: jump directly to the next BB. 1884 } else 1885 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1886 1887 // If the value of the invoke is used outside of its defining block, make it 1888 // available as a virtual register. 1889 CopyToExportRegsIfNeeded(&I); 1890 1891 // Update successor info 1892 addSuccessorWithWeight(InvokeMBB, Return); 1893 addSuccessorWithWeight(InvokeMBB, LandingPad); 1894 1895 // Drop into normal successor. 1896 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), 1897 MVT::Other, getControlRoot(), 1898 DAG.getBasicBlock(Return))); 1899} 1900 1901void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1902 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1903} 1904 1905void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1906 assert(FuncInfo.MBB->isLandingPad() && 1907 "Call to landingpad not in landing pad!"); 1908 1909 MachineBasicBlock *MBB = FuncInfo.MBB; 1910 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1911 AddLandingPadInfo(LP, MMI, MBB); 1912 1913 // If there aren't registers to copy the values into (e.g., during SjLj 1914 // exceptions), then don't bother to create these DAG nodes. 1915 const TargetLowering *TLI = TM.getTargetLowering(); 1916 if (TLI->getExceptionPointerRegister() == 0 && 1917 TLI->getExceptionSelectorRegister() == 0) 1918 return; 1919 1920 SmallVector<EVT, 2> ValueVTs; 1921 ComputeValueVTs(*TLI, LP.getType(), ValueVTs); 1922 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported"); 1923 1924 // Get the two live-in registers as SDValues. The physregs have already been 1925 // copied into virtual registers. 1926 SDValue Ops[2]; 1927 Ops[0] = DAG.getZExtOrTrunc( 1928 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), 1929 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()), 1930 getCurSDLoc(), ValueVTs[0]); 1931 Ops[1] = DAG.getZExtOrTrunc( 1932 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), 1933 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()), 1934 getCurSDLoc(), ValueVTs[1]); 1935 1936 // Merge into one. 1937 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 1938 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1939 &Ops[0], 2); 1940 setValue(&LP, Res); 1941} 1942 1943/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1944/// small case ranges). 1945bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1946 CaseRecVector& WorkList, 1947 const Value* SV, 1948 MachineBasicBlock *Default, 1949 MachineBasicBlock *SwitchBB) { 1950 // Size is the number of Cases represented by this range. 1951 size_t Size = CR.Range.second - CR.Range.first; 1952 if (Size > 3) 1953 return false; 1954 1955 // Get the MachineFunction which holds the current MBB. This is used when 1956 // inserting any additional MBBs necessary to represent the switch. 1957 MachineFunction *CurMF = FuncInfo.MF; 1958 1959 // Figure out which block is immediately after the current one. 1960 MachineBasicBlock *NextBlock = 0; 1961 MachineFunction::iterator BBI = CR.CaseBB; 1962 1963 if (++BBI != FuncInfo.MF->end()) 1964 NextBlock = BBI; 1965 1966 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1967 // If any two of the cases has the same destination, and if one value 1968 // is the same as the other, but has one bit unset that the other has set, 1969 // use bit manipulation to do two compares at once. For example: 1970 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1971 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1972 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1973 if (Size == 2 && CR.CaseBB == SwitchBB) { 1974 Case &Small = *CR.Range.first; 1975 Case &Big = *(CR.Range.second-1); 1976 1977 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1978 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1979 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1980 1981 // Check that there is only one bit different. 1982 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1983 (SmallValue | BigValue) == BigValue) { 1984 // Isolate the common bit. 1985 APInt CommonBit = BigValue & ~SmallValue; 1986 assert((SmallValue | CommonBit) == BigValue && 1987 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1988 1989 SDValue CondLHS = getValue(SV); 1990 EVT VT = CondLHS.getValueType(); 1991 SDLoc DL = getCurSDLoc(); 1992 1993 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1994 DAG.getConstant(CommonBit, VT)); 1995 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1996 Or, DAG.getConstant(BigValue, VT), 1997 ISD::SETEQ); 1998 1999 // Update successor info. 2000 // Both Small and Big will jump to Small.BB, so we sum up the weights. 2001 addSuccessorWithWeight(SwitchBB, Small.BB, 2002 Small.ExtraWeight + Big.ExtraWeight); 2003 addSuccessorWithWeight(SwitchBB, Default, 2004 // The default destination is the first successor in IR. 2005 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0); 2006 2007 // Insert the true branch. 2008 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 2009 getControlRoot(), Cond, 2010 DAG.getBasicBlock(Small.BB)); 2011 2012 // Insert the false branch. 2013 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 2014 DAG.getBasicBlock(Default)); 2015 2016 DAG.setRoot(BrCond); 2017 return true; 2018 } 2019 } 2020 } 2021 2022 // Order cases by weight so the most likely case will be checked first. 2023 uint32_t UnhandledWeights = 0; 2024 if (BPI) { 2025 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) { 2026 uint32_t IWeight = I->ExtraWeight; 2027 UnhandledWeights += IWeight; 2028 for (CaseItr J = CR.Range.first; J < I; ++J) { 2029 uint32_t JWeight = J->ExtraWeight; 2030 if (IWeight > JWeight) 2031 std::swap(*I, *J); 2032 } 2033 } 2034 } 2035 // Rearrange the case blocks so that the last one falls through if possible. 2036 Case &BackCase = *(CR.Range.second-1); 2037 if (Size > 1 && 2038 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 2039 // The last case block won't fall through into 'NextBlock' if we emit the 2040 // branches in this order. See if rearranging a case value would help. 2041 // We start at the bottom as it's the case with the least weight. 2042 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I) 2043 if (I->BB == NextBlock) { 2044 std::swap(*I, BackCase); 2045 break; 2046 } 2047 } 2048 2049 // Create a CaseBlock record representing a conditional branch to 2050 // the Case's target mbb if the value being switched on SV is equal 2051 // to C. 2052 MachineBasicBlock *CurBlock = CR.CaseBB; 2053 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2054 MachineBasicBlock *FallThrough; 2055 if (I != E-1) { 2056 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 2057 CurMF->insert(BBI, FallThrough); 2058 2059 // Put SV in a virtual register to make it available from the new blocks. 2060 ExportFromCurrentBlock(SV); 2061 } else { 2062 // If the last case doesn't match, go to the default block. 2063 FallThrough = Default; 2064 } 2065 2066 const Value *RHS, *LHS, *MHS; 2067 ISD::CondCode CC; 2068 if (I->High == I->Low) { 2069 // This is just small small case range :) containing exactly 1 case 2070 CC = ISD::SETEQ; 2071 LHS = SV; RHS = I->High; MHS = NULL; 2072 } else { 2073 CC = ISD::SETCC_INVALID; 2074 LHS = I->Low; MHS = SV; RHS = I->High; 2075 } 2076 2077 // The false weight should be sum of all un-handled cases. 2078 UnhandledWeights -= I->ExtraWeight; 2079 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2080 /* me */ CurBlock, 2081 /* trueweight */ I->ExtraWeight, 2082 /* falseweight */ UnhandledWeights); 2083 2084 // If emitting the first comparison, just call visitSwitchCase to emit the 2085 // code into the current block. Otherwise, push the CaseBlock onto the 2086 // vector to be later processed by SDISel, and insert the node's MBB 2087 // before the next MBB. 2088 if (CurBlock == SwitchBB) 2089 visitSwitchCase(CB, SwitchBB); 2090 else 2091 SwitchCases.push_back(CB); 2092 2093 CurBlock = FallThrough; 2094 } 2095 2096 return true; 2097} 2098 2099static inline bool areJTsAllowed(const TargetLowering &TLI) { 2100 return TLI.supportJumpTables() && 2101 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2102 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2103} 2104 2105static APInt ComputeRange(const APInt &First, const APInt &Last) { 2106 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2107 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth); 2108 return (LastExt - FirstExt + 1ULL); 2109} 2110 2111/// handleJTSwitchCase - Emit jumptable for current switch case range 2112bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2113 CaseRecVector &WorkList, 2114 const Value *SV, 2115 MachineBasicBlock *Default, 2116 MachineBasicBlock *SwitchBB) { 2117 Case& FrontCase = *CR.Range.first; 2118 Case& BackCase = *(CR.Range.second-1); 2119 2120 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2121 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2122 2123 APInt TSize(First.getBitWidth(), 0); 2124 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2125 TSize += I->size(); 2126 2127 const TargetLowering *TLI = TM.getTargetLowering(); 2128 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries())) 2129 return false; 2130 2131 APInt Range = ComputeRange(First, Last); 2132 // The density is TSize / Range. Require at least 40%. 2133 // It should not be possible for IntTSize to saturate for sane code, but make 2134 // sure we handle Range saturation correctly. 2135 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2136 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2137 if (IntTSize * 10 < IntRange * 4) 2138 return false; 2139 2140 DEBUG(dbgs() << "Lowering jump table\n" 2141 << "First entry: " << First << ". Last entry: " << Last << '\n' 2142 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2143 2144 // Get the MachineFunction which holds the current MBB. This is used when 2145 // inserting any additional MBBs necessary to represent the switch. 2146 MachineFunction *CurMF = FuncInfo.MF; 2147 2148 // Figure out which block is immediately after the current one. 2149 MachineFunction::iterator BBI = CR.CaseBB; 2150 ++BBI; 2151 2152 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2153 2154 // Create a new basic block to hold the code for loading the address 2155 // of the jump table, and jumping to it. Update successor information; 2156 // we will either branch to the default case for the switch, or the jump 2157 // table. 2158 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2159 CurMF->insert(BBI, JumpTableBB); 2160 2161 addSuccessorWithWeight(CR.CaseBB, Default); 2162 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2163 2164 // Build a vector of destination BBs, corresponding to each target 2165 // of the jump table. If the value of the jump table slot corresponds to 2166 // a case statement, push the case's BB onto the vector, otherwise, push 2167 // the default BB. 2168 std::vector<MachineBasicBlock*> DestBBs; 2169 APInt TEI = First; 2170 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2171 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2172 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2173 2174 if (Low.ule(TEI) && TEI.ule(High)) { 2175 DestBBs.push_back(I->BB); 2176 if (TEI==High) 2177 ++I; 2178 } else { 2179 DestBBs.push_back(Default); 2180 } 2181 } 2182 2183 // Calculate weight for each unique destination in CR. 2184 DenseMap<MachineBasicBlock*, uint32_t> DestWeights; 2185 if (FuncInfo.BPI) 2186 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2187 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2188 DestWeights.find(I->BB); 2189 if (Itr != DestWeights.end()) 2190 Itr->second += I->ExtraWeight; 2191 else 2192 DestWeights[I->BB] = I->ExtraWeight; 2193 } 2194 2195 // Update successor info. Add one edge to each unique successor. 2196 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2197 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2198 E = DestBBs.end(); I != E; ++I) { 2199 if (!SuccsHandled[(*I)->getNumber()]) { 2200 SuccsHandled[(*I)->getNumber()] = true; 2201 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2202 DestWeights.find(*I); 2203 addSuccessorWithWeight(JumpTableBB, *I, 2204 Itr != DestWeights.end() ? Itr->second : 0); 2205 } 2206 } 2207 2208 // Create a jump table index for this jump table. 2209 unsigned JTEncoding = TLI->getJumpTableEncoding(); 2210 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2211 ->createJumpTableIndex(DestBBs); 2212 2213 // Set the jump table information so that we can codegen it as a second 2214 // MachineBasicBlock 2215 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2216 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2217 if (CR.CaseBB == SwitchBB) 2218 visitJumpTableHeader(JT, JTH, SwitchBB); 2219 2220 JTCases.push_back(JumpTableBlock(JTH, JT)); 2221 return true; 2222} 2223 2224/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2225/// 2 subtrees. 2226bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2227 CaseRecVector& WorkList, 2228 const Value* SV, 2229 MachineBasicBlock* Default, 2230 MachineBasicBlock* SwitchBB) { 2231 // Get the MachineFunction which holds the current MBB. This is used when 2232 // inserting any additional MBBs necessary to represent the switch. 2233 MachineFunction *CurMF = FuncInfo.MF; 2234 2235 // Figure out which block is immediately after the current one. 2236 MachineFunction::iterator BBI = CR.CaseBB; 2237 ++BBI; 2238 2239 Case& FrontCase = *CR.Range.first; 2240 Case& BackCase = *(CR.Range.second-1); 2241 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2242 2243 // Size is the number of Cases represented by this range. 2244 unsigned Size = CR.Range.second - CR.Range.first; 2245 2246 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2247 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2248 double FMetric = 0; 2249 CaseItr Pivot = CR.Range.first + Size/2; 2250 2251 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2252 // (heuristically) allow us to emit JumpTable's later. 2253 APInt TSize(First.getBitWidth(), 0); 2254 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2255 I!=E; ++I) 2256 TSize += I->size(); 2257 2258 APInt LSize = FrontCase.size(); 2259 APInt RSize = TSize-LSize; 2260 DEBUG(dbgs() << "Selecting best pivot: \n" 2261 << "First: " << First << ", Last: " << Last <<'\n' 2262 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2263 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2264 J!=E; ++I, ++J) { 2265 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2266 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2267 APInt Range = ComputeRange(LEnd, RBegin); 2268 assert((Range - 2ULL).isNonNegative() && 2269 "Invalid case distance"); 2270 // Use volatile double here to avoid excess precision issues on some hosts, 2271 // e.g. that use 80-bit X87 registers. 2272 volatile double LDensity = 2273 (double)LSize.roundToDouble() / 2274 (LEnd - First + 1ULL).roundToDouble(); 2275 volatile double RDensity = 2276 (double)RSize.roundToDouble() / 2277 (Last - RBegin + 1ULL).roundToDouble(); 2278 double Metric = Range.logBase2()*(LDensity+RDensity); 2279 // Should always split in some non-trivial place 2280 DEBUG(dbgs() <<"=>Step\n" 2281 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2282 << "LDensity: " << LDensity 2283 << ", RDensity: " << RDensity << '\n' 2284 << "Metric: " << Metric << '\n'); 2285 if (FMetric < Metric) { 2286 Pivot = J; 2287 FMetric = Metric; 2288 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2289 } 2290 2291 LSize += J->size(); 2292 RSize -= J->size(); 2293 } 2294 2295 const TargetLowering *TLI = TM.getTargetLowering(); 2296 if (areJTsAllowed(*TLI)) { 2297 // If our case is dense we *really* should handle it earlier! 2298 assert((FMetric > 0) && "Should handle dense range earlier!"); 2299 } else { 2300 Pivot = CR.Range.first + Size/2; 2301 } 2302 2303 CaseRange LHSR(CR.Range.first, Pivot); 2304 CaseRange RHSR(Pivot, CR.Range.second); 2305 const Constant *C = Pivot->Low; 2306 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2307 2308 // We know that we branch to the LHS if the Value being switched on is 2309 // less than the Pivot value, C. We use this to optimize our binary 2310 // tree a bit, by recognizing that if SV is greater than or equal to the 2311 // LHS's Case Value, and that Case Value is exactly one less than the 2312 // Pivot's Value, then we can branch directly to the LHS's Target, 2313 // rather than creating a leaf node for it. 2314 if ((LHSR.second - LHSR.first) == 1 && 2315 LHSR.first->High == CR.GE && 2316 cast<ConstantInt>(C)->getValue() == 2317 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2318 TrueBB = LHSR.first->BB; 2319 } else { 2320 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2321 CurMF->insert(BBI, TrueBB); 2322 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2323 2324 // Put SV in a virtual register to make it available from the new blocks. 2325 ExportFromCurrentBlock(SV); 2326 } 2327 2328 // Similar to the optimization above, if the Value being switched on is 2329 // known to be less than the Constant CR.LT, and the current Case Value 2330 // is CR.LT - 1, then we can branch directly to the target block for 2331 // the current Case Value, rather than emitting a RHS leaf node for it. 2332 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2333 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2334 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2335 FalseBB = RHSR.first->BB; 2336 } else { 2337 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2338 CurMF->insert(BBI, FalseBB); 2339 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2340 2341 // Put SV in a virtual register to make it available from the new blocks. 2342 ExportFromCurrentBlock(SV); 2343 } 2344 2345 // Create a CaseBlock record representing a conditional branch to 2346 // the LHS node if the value being switched on SV is less than C. 2347 // Otherwise, branch to LHS. 2348 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2349 2350 if (CR.CaseBB == SwitchBB) 2351 visitSwitchCase(CB, SwitchBB); 2352 else 2353 SwitchCases.push_back(CB); 2354 2355 return true; 2356} 2357 2358/// handleBitTestsSwitchCase - if current case range has few destination and 2359/// range span less, than machine word bitwidth, encode case range into series 2360/// of masks and emit bit tests with these masks. 2361bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2362 CaseRecVector& WorkList, 2363 const Value* SV, 2364 MachineBasicBlock* Default, 2365 MachineBasicBlock* SwitchBB) { 2366 const TargetLowering *TLI = TM.getTargetLowering(); 2367 EVT PTy = TLI->getPointerTy(); 2368 unsigned IntPtrBits = PTy.getSizeInBits(); 2369 2370 Case& FrontCase = *CR.Range.first; 2371 Case& BackCase = *(CR.Range.second-1); 2372 2373 // Get the MachineFunction which holds the current MBB. This is used when 2374 // inserting any additional MBBs necessary to represent the switch. 2375 MachineFunction *CurMF = FuncInfo.MF; 2376 2377 // If target does not have legal shift left, do not emit bit tests at all. 2378 if (!TLI->isOperationLegal(ISD::SHL, TLI->getPointerTy())) 2379 return false; 2380 2381 size_t numCmps = 0; 2382 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2383 I!=E; ++I) { 2384 // Single case counts one, case range - two. 2385 numCmps += (I->Low == I->High ? 1 : 2); 2386 } 2387 2388 // Count unique destinations 2389 SmallSet<MachineBasicBlock*, 4> Dests; 2390 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2391 Dests.insert(I->BB); 2392 if (Dests.size() > 3) 2393 // Don't bother the code below, if there are too much unique destinations 2394 return false; 2395 } 2396 DEBUG(dbgs() << "Total number of unique destinations: " 2397 << Dests.size() << '\n' 2398 << "Total number of comparisons: " << numCmps << '\n'); 2399 2400 // Compute span of values. 2401 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2402 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2403 APInt cmpRange = maxValue - minValue; 2404 2405 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2406 << "Low bound: " << minValue << '\n' 2407 << "High bound: " << maxValue << '\n'); 2408 2409 if (cmpRange.uge(IntPtrBits) || 2410 (!(Dests.size() == 1 && numCmps >= 3) && 2411 !(Dests.size() == 2 && numCmps >= 5) && 2412 !(Dests.size() >= 3 && numCmps >= 6))) 2413 return false; 2414 2415 DEBUG(dbgs() << "Emitting bit tests\n"); 2416 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2417 2418 // Optimize the case where all the case values fit in a 2419 // word without having to subtract minValue. In this case, 2420 // we can optimize away the subtraction. 2421 if (maxValue.ult(IntPtrBits)) { 2422 cmpRange = maxValue; 2423 } else { 2424 lowBound = minValue; 2425 } 2426 2427 CaseBitsVector CasesBits; 2428 unsigned i, count = 0; 2429 2430 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2431 MachineBasicBlock* Dest = I->BB; 2432 for (i = 0; i < count; ++i) 2433 if (Dest == CasesBits[i].BB) 2434 break; 2435 2436 if (i == count) { 2437 assert((count < 3) && "Too much destinations to test!"); 2438 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/)); 2439 count++; 2440 } 2441 2442 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2443 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2444 2445 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2446 uint64_t hi = (highValue - lowBound).getZExtValue(); 2447 CasesBits[i].ExtraWeight += I->ExtraWeight; 2448 2449 for (uint64_t j = lo; j <= hi; j++) { 2450 CasesBits[i].Mask |= 1ULL << j; 2451 CasesBits[i].Bits++; 2452 } 2453 2454 } 2455 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2456 2457 BitTestInfo BTC; 2458 2459 // Figure out which block is immediately after the current one. 2460 MachineFunction::iterator BBI = CR.CaseBB; 2461 ++BBI; 2462 2463 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2464 2465 DEBUG(dbgs() << "Cases:\n"); 2466 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2467 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2468 << ", Bits: " << CasesBits[i].Bits 2469 << ", BB: " << CasesBits[i].BB << '\n'); 2470 2471 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2472 CurMF->insert(BBI, CaseBB); 2473 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2474 CaseBB, 2475 CasesBits[i].BB, CasesBits[i].ExtraWeight)); 2476 2477 // Put SV in a virtual register to make it available from the new blocks. 2478 ExportFromCurrentBlock(SV); 2479 } 2480 2481 BitTestBlock BTB(lowBound, cmpRange, SV, 2482 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2483 CR.CaseBB, Default, BTC); 2484 2485 if (CR.CaseBB == SwitchBB) 2486 visitBitTestHeader(BTB, SwitchBB); 2487 2488 BitTestCases.push_back(BTB); 2489 2490 return true; 2491} 2492 2493/// Clusterify - Transform simple list of Cases into list of CaseRange's 2494size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2495 const SwitchInst& SI) { 2496 2497 /// Use a shorter form of declaration, and also 2498 /// show the we want to use CRSBuilder as Clusterifier. 2499 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier; 2500 2501 Clusterifier TheClusterifier; 2502 2503 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2504 // Start with "simple" cases 2505 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2506 i != e; ++i) { 2507 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2508 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2509 2510 TheClusterifier.add(i.getCaseValueEx(), SMBB, 2511 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0); 2512 } 2513 2514 TheClusterifier.optimize(); 2515 2516 size_t numCmps = 0; 2517 for (Clusterifier::RangeIterator i = TheClusterifier.begin(), 2518 e = TheClusterifier.end(); i != e; ++i, ++numCmps) { 2519 Clusterifier::Cluster &C = *i; 2520 // Update edge weight for the cluster. 2521 unsigned W = C.first.Weight; 2522 2523 // FIXME: Currently work with ConstantInt based numbers. 2524 // Changing it to APInt based is a pretty heavy for this commit. 2525 Cases.push_back(Case(C.first.getLow().toConstantInt(), 2526 C.first.getHigh().toConstantInt(), C.second, W)); 2527 2528 if (C.first.getLow() != C.first.getHigh()) 2529 // A range counts double, since it requires two compares. 2530 ++numCmps; 2531 } 2532 2533 return numCmps; 2534} 2535 2536void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2537 MachineBasicBlock *Last) { 2538 // Update JTCases. 2539 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2540 if (JTCases[i].first.HeaderBB == First) 2541 JTCases[i].first.HeaderBB = Last; 2542 2543 // Update BitTestCases. 2544 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2545 if (BitTestCases[i].Parent == First) 2546 BitTestCases[i].Parent = Last; 2547} 2548 2549void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2550 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2551 2552 // Figure out which block is immediately after the current one. 2553 MachineBasicBlock *NextBlock = 0; 2554 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2555 2556 // If there is only the default destination, branch to it if it is not the 2557 // next basic block. Otherwise, just fall through. 2558 if (!SI.getNumCases()) { 2559 // Update machine-CFG edges. 2560 2561 // If this is not a fall-through branch, emit the branch. 2562 SwitchMBB->addSuccessor(Default); 2563 if (Default != NextBlock) 2564 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), 2565 MVT::Other, getControlRoot(), 2566 DAG.getBasicBlock(Default))); 2567 2568 return; 2569 } 2570 2571 // If there are any non-default case statements, create a vector of Cases 2572 // representing each one, and sort the vector so that we can efficiently 2573 // create a binary search tree from them. 2574 CaseVector Cases; 2575 size_t numCmps = Clusterify(Cases, SI); 2576 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2577 << ". Total compares: " << numCmps << '\n'); 2578 (void)numCmps; 2579 2580 // Get the Value to be switched on and default basic blocks, which will be 2581 // inserted into CaseBlock records, representing basic blocks in the binary 2582 // search tree. 2583 const Value *SV = SI.getCondition(); 2584 2585 // Push the initial CaseRec onto the worklist 2586 CaseRecVector WorkList; 2587 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2588 CaseRange(Cases.begin(),Cases.end()))); 2589 2590 while (!WorkList.empty()) { 2591 // Grab a record representing a case range to process off the worklist 2592 CaseRec CR = WorkList.back(); 2593 WorkList.pop_back(); 2594 2595 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2596 continue; 2597 2598 // If the range has few cases (two or less) emit a series of specific 2599 // tests. 2600 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2601 continue; 2602 2603 // If the switch has more than N blocks, and is at least 40% dense, and the 2604 // target supports indirect branches, then emit a jump table rather than 2605 // lowering the switch to a binary tree of conditional branches. 2606 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries(). 2607 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2608 continue; 2609 2610 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2611 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2612 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2613 } 2614} 2615 2616void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2617 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2618 2619 // Update machine-CFG edges with unique successors. 2620 SmallSet<BasicBlock*, 32> Done; 2621 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) { 2622 BasicBlock *BB = I.getSuccessor(i); 2623 bool Inserted = Done.insert(BB); 2624 if (!Inserted) 2625 continue; 2626 2627 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB]; 2628 addSuccessorWithWeight(IndirectBrMBB, Succ); 2629 } 2630 2631 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(), 2632 MVT::Other, getControlRoot(), 2633 getValue(I.getAddress()))); 2634} 2635 2636void SelectionDAGBuilder::visitFSub(const User &I) { 2637 // -0.0 - X --> fneg 2638 Type *Ty = I.getType(); 2639 if (isa<Constant>(I.getOperand(0)) && 2640 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2641 SDValue Op2 = getValue(I.getOperand(1)); 2642 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(), 2643 Op2.getValueType(), Op2)); 2644 return; 2645 } 2646 2647 visitBinary(I, ISD::FSUB); 2648} 2649 2650void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2651 SDValue Op1 = getValue(I.getOperand(0)); 2652 SDValue Op2 = getValue(I.getOperand(1)); 2653 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(), 2654 Op1.getValueType(), Op1, Op2)); 2655} 2656 2657void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2658 SDValue Op1 = getValue(I.getOperand(0)); 2659 SDValue Op2 = getValue(I.getOperand(1)); 2660 2661 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType()); 2662 2663 // Coerce the shift amount to the right type if we can. 2664 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2665 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2666 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2667 SDLoc DL = getCurSDLoc(); 2668 2669 // If the operand is smaller than the shift count type, promote it. 2670 if (ShiftSize > Op2Size) 2671 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2672 2673 // If the operand is larger than the shift count type but the shift 2674 // count type has enough bits to represent any shift value, truncate 2675 // it now. This is a common case and it exposes the truncate to 2676 // optimization early. 2677 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2678 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2679 // Otherwise we'll need to temporarily settle for some other convenient 2680 // type. Type legalization will make adjustments once the shiftee is split. 2681 else 2682 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2683 } 2684 2685 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), 2686 Op1.getValueType(), Op1, Op2)); 2687} 2688 2689void SelectionDAGBuilder::visitSDiv(const User &I) { 2690 SDValue Op1 = getValue(I.getOperand(0)); 2691 SDValue Op2 = getValue(I.getOperand(1)); 2692 2693 // Turn exact SDivs into multiplications. 2694 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2695 // exact bit. 2696 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2697 !isa<ConstantSDNode>(Op1) && 2698 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2699 setValue(&I, TM.getTargetLowering()->BuildExactSDIV(Op1, Op2, 2700 getCurSDLoc(), DAG)); 2701 else 2702 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), 2703 Op1, Op2)); 2704} 2705 2706void SelectionDAGBuilder::visitICmp(const User &I) { 2707 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2708 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2709 predicate = IC->getPredicate(); 2710 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2711 predicate = ICmpInst::Predicate(IC->getPredicate()); 2712 SDValue Op1 = getValue(I.getOperand(0)); 2713 SDValue Op2 = getValue(I.getOperand(1)); 2714 ISD::CondCode Opcode = getICmpCondCode(predicate); 2715 2716 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2717 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); 2718} 2719 2720void SelectionDAGBuilder::visitFCmp(const User &I) { 2721 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2722 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2723 predicate = FC->getPredicate(); 2724 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2725 predicate = FCmpInst::Predicate(FC->getPredicate()); 2726 SDValue Op1 = getValue(I.getOperand(0)); 2727 SDValue Op2 = getValue(I.getOperand(1)); 2728 ISD::CondCode Condition = getFCmpCondCode(predicate); 2729 if (TM.Options.NoNaNsFPMath) 2730 Condition = getFCmpCodeWithoutNaN(Condition); 2731 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2732 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); 2733} 2734 2735void SelectionDAGBuilder::visitSelect(const User &I) { 2736 SmallVector<EVT, 4> ValueVTs; 2737 ComputeValueVTs(*TM.getTargetLowering(), I.getType(), ValueVTs); 2738 unsigned NumValues = ValueVTs.size(); 2739 if (NumValues == 0) return; 2740 2741 SmallVector<SDValue, 4> Values(NumValues); 2742 SDValue Cond = getValue(I.getOperand(0)); 2743 SDValue TrueVal = getValue(I.getOperand(1)); 2744 SDValue FalseVal = getValue(I.getOperand(2)); 2745 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2746 ISD::VSELECT : ISD::SELECT; 2747 2748 for (unsigned i = 0; i != NumValues; ++i) 2749 Values[i] = DAG.getNode(OpCode, getCurSDLoc(), 2750 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2751 Cond, 2752 SDValue(TrueVal.getNode(), 2753 TrueVal.getResNo() + i), 2754 SDValue(FalseVal.getNode(), 2755 FalseVal.getResNo() + i)); 2756 2757 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 2758 DAG.getVTList(&ValueVTs[0], NumValues), 2759 &Values[0], NumValues)); 2760} 2761 2762void SelectionDAGBuilder::visitTrunc(const User &I) { 2763 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2764 SDValue N = getValue(I.getOperand(0)); 2765 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2766 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); 2767} 2768 2769void SelectionDAGBuilder::visitZExt(const User &I) { 2770 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2771 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2772 SDValue N = getValue(I.getOperand(0)); 2773 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2774 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); 2775} 2776 2777void SelectionDAGBuilder::visitSExt(const User &I) { 2778 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2779 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2780 SDValue N = getValue(I.getOperand(0)); 2781 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2782 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); 2783} 2784 2785void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2786 // FPTrunc is never a no-op cast, no need to check 2787 SDValue N = getValue(I.getOperand(0)); 2788 const TargetLowering *TLI = TM.getTargetLowering(); 2789 EVT DestVT = TLI->getValueType(I.getType()); 2790 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), 2791 DestVT, N, 2792 DAG.getTargetConstant(0, TLI->getPointerTy()))); 2793} 2794 2795void SelectionDAGBuilder::visitFPExt(const User &I) { 2796 // FPExt is never a no-op cast, no need to check 2797 SDValue N = getValue(I.getOperand(0)); 2798 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2799 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N)); 2800} 2801 2802void SelectionDAGBuilder::visitFPToUI(const User &I) { 2803 // FPToUI is never a no-op cast, no need to check 2804 SDValue N = getValue(I.getOperand(0)); 2805 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2806 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N)); 2807} 2808 2809void SelectionDAGBuilder::visitFPToSI(const User &I) { 2810 // FPToSI is never a no-op cast, no need to check 2811 SDValue N = getValue(I.getOperand(0)); 2812 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2813 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N)); 2814} 2815 2816void SelectionDAGBuilder::visitUIToFP(const User &I) { 2817 // UIToFP is never a no-op cast, no need to check 2818 SDValue N = getValue(I.getOperand(0)); 2819 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2820 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N)); 2821} 2822 2823void SelectionDAGBuilder::visitSIToFP(const User &I) { 2824 // SIToFP is never a no-op cast, no need to check 2825 SDValue N = getValue(I.getOperand(0)); 2826 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2827 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N)); 2828} 2829 2830void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2831 // What to do depends on the size of the integer and the size of the pointer. 2832 // We can either truncate, zero extend, or no-op, accordingly. 2833 SDValue N = getValue(I.getOperand(0)); 2834 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2835 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT)); 2836} 2837 2838void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2839 // What to do depends on the size of the integer and the size of the pointer. 2840 // We can either truncate, zero extend, or no-op, accordingly. 2841 SDValue N = getValue(I.getOperand(0)); 2842 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2843 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT)); 2844} 2845 2846void SelectionDAGBuilder::visitBitCast(const User &I) { 2847 SDValue N = getValue(I.getOperand(0)); 2848 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2849 2850 // BitCast assures us that source and destination are the same size so this is 2851 // either a BITCAST or a no-op. 2852 if (DestVT != N.getValueType()) 2853 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(), 2854 DestVT, N)); // convert types. 2855 else 2856 setValue(&I, N); // noop cast. 2857} 2858 2859void SelectionDAGBuilder::visitInsertElement(const User &I) { 2860 SDValue InVec = getValue(I.getOperand(0)); 2861 SDValue InVal = getValue(I.getOperand(1)); 2862 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), 2863 TM.getTargetLowering()->getPointerTy(), 2864 getValue(I.getOperand(2))); 2865 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(), 2866 TM.getTargetLowering()->getValueType(I.getType()), 2867 InVec, InVal, InIdx)); 2868} 2869 2870void SelectionDAGBuilder::visitExtractElement(const User &I) { 2871 SDValue InVec = getValue(I.getOperand(0)); 2872 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), 2873 TM.getTargetLowering()->getPointerTy(), 2874 getValue(I.getOperand(1))); 2875 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(), 2876 TM.getTargetLowering()->getValueType(I.getType()), 2877 InVec, InIdx)); 2878} 2879 2880// Utility for visitShuffleVector - Return true if every element in Mask, 2881// beginning from position Pos and ending in Pos+Size, falls within the 2882// specified sequential range [L, L+Pos). or is undef. 2883static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2884 unsigned Pos, unsigned Size, int Low) { 2885 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2886 if (Mask[i] >= 0 && Mask[i] != Low) 2887 return false; 2888 return true; 2889} 2890 2891void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2892 SDValue Src1 = getValue(I.getOperand(0)); 2893 SDValue Src2 = getValue(I.getOperand(1)); 2894 2895 SmallVector<int, 8> Mask; 2896 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2897 unsigned MaskNumElts = Mask.size(); 2898 2899 const TargetLowering *TLI = TM.getTargetLowering(); 2900 EVT VT = TLI->getValueType(I.getType()); 2901 EVT SrcVT = Src1.getValueType(); 2902 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2903 2904 if (SrcNumElts == MaskNumElts) { 2905 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, 2906 &Mask[0])); 2907 return; 2908 } 2909 2910 // Normalize the shuffle vector since mask and vector length don't match. 2911 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2912 // Mask is longer than the source vectors and is a multiple of the source 2913 // vectors. We can use concatenate vector to make the mask and vectors 2914 // lengths match. 2915 if (SrcNumElts*2 == MaskNumElts) { 2916 // First check for Src1 in low and Src2 in high 2917 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2918 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2919 // The shuffle is concatenating two vectors together. 2920 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(), 2921 VT, Src1, Src2)); 2922 return; 2923 } 2924 // Then check for Src2 in low and Src1 in high 2925 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2926 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2927 // The shuffle is concatenating two vectors together. 2928 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(), 2929 VT, Src2, Src1)); 2930 return; 2931 } 2932 } 2933 2934 // Pad both vectors with undefs to make them the same length as the mask. 2935 unsigned NumConcat = MaskNumElts / SrcNumElts; 2936 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2937 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2938 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2939 2940 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2941 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2942 MOps1[0] = Src1; 2943 MOps2[0] = Src2; 2944 2945 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2946 getCurSDLoc(), VT, 2947 &MOps1[0], NumConcat); 2948 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2949 getCurSDLoc(), VT, 2950 &MOps2[0], NumConcat); 2951 2952 // Readjust mask for new input vector length. 2953 SmallVector<int, 8> MappedOps; 2954 for (unsigned i = 0; i != MaskNumElts; ++i) { 2955 int Idx = Mask[i]; 2956 if (Idx >= (int)SrcNumElts) 2957 Idx -= SrcNumElts - MaskNumElts; 2958 MappedOps.push_back(Idx); 2959 } 2960 2961 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, 2962 &MappedOps[0])); 2963 return; 2964 } 2965 2966 if (SrcNumElts > MaskNumElts) { 2967 // Analyze the access pattern of the vector to see if we can extract 2968 // two subvectors and do the shuffle. The analysis is done by calculating 2969 // the range of elements the mask access on both vectors. 2970 int MinRange[2] = { static_cast<int>(SrcNumElts), 2971 static_cast<int>(SrcNumElts)}; 2972 int MaxRange[2] = {-1, -1}; 2973 2974 for (unsigned i = 0; i != MaskNumElts; ++i) { 2975 int Idx = Mask[i]; 2976 unsigned Input = 0; 2977 if (Idx < 0) 2978 continue; 2979 2980 if (Idx >= (int)SrcNumElts) { 2981 Input = 1; 2982 Idx -= SrcNumElts; 2983 } 2984 if (Idx > MaxRange[Input]) 2985 MaxRange[Input] = Idx; 2986 if (Idx < MinRange[Input]) 2987 MinRange[Input] = Idx; 2988 } 2989 2990 // Check if the access is smaller than the vector size and can we find 2991 // a reasonable extract index. 2992 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 2993 // Extract. 2994 int StartIdx[2]; // StartIdx to extract from 2995 for (unsigned Input = 0; Input < 2; ++Input) { 2996 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 2997 RangeUse[Input] = 0; // Unused 2998 StartIdx[Input] = 0; 2999 continue; 3000 } 3001 3002 // Find a good start index that is a multiple of the mask length. Then 3003 // see if the rest of the elements are in range. 3004 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 3005 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 3006 StartIdx[Input] + MaskNumElts <= SrcNumElts) 3007 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 3008 } 3009 3010 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 3011 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 3012 return; 3013 } 3014 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 3015 // Extract appropriate subvector and generate a vector shuffle 3016 for (unsigned Input = 0; Input < 2; ++Input) { 3017 SDValue &Src = Input == 0 ? Src1 : Src2; 3018 if (RangeUse[Input] == 0) 3019 Src = DAG.getUNDEF(VT); 3020 else 3021 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, 3022 Src, DAG.getIntPtrConstant(StartIdx[Input])); 3023 } 3024 3025 // Calculate new mask. 3026 SmallVector<int, 8> MappedOps; 3027 for (unsigned i = 0; i != MaskNumElts; ++i) { 3028 int Idx = Mask[i]; 3029 if (Idx >= 0) { 3030 if (Idx < (int)SrcNumElts) 3031 Idx -= StartIdx[0]; 3032 else 3033 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 3034 } 3035 MappedOps.push_back(Idx); 3036 } 3037 3038 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, 3039 &MappedOps[0])); 3040 return; 3041 } 3042 } 3043 3044 // We can't use either concat vectors or extract subvectors so fall back to 3045 // replacing the shuffle with extract and build vector. 3046 // to insert and build vector. 3047 EVT EltVT = VT.getVectorElementType(); 3048 EVT PtrVT = TLI->getPointerTy(); 3049 SmallVector<SDValue,8> Ops; 3050 for (unsigned i = 0; i != MaskNumElts; ++i) { 3051 int Idx = Mask[i]; 3052 SDValue Res; 3053 3054 if (Idx < 0) { 3055 Res = DAG.getUNDEF(EltVT); 3056 } else { 3057 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 3058 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 3059 3060 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(), 3061 EltVT, Src, DAG.getConstant(Idx, PtrVT)); 3062 } 3063 3064 Ops.push_back(Res); 3065 } 3066 3067 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), 3068 VT, &Ops[0], Ops.size())); 3069} 3070 3071void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3072 const Value *Op0 = I.getOperand(0); 3073 const Value *Op1 = I.getOperand(1); 3074 Type *AggTy = I.getType(); 3075 Type *ValTy = Op1->getType(); 3076 bool IntoUndef = isa<UndefValue>(Op0); 3077 bool FromUndef = isa<UndefValue>(Op1); 3078 3079 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3080 3081 const TargetLowering *TLI = TM.getTargetLowering(); 3082 SmallVector<EVT, 4> AggValueVTs; 3083 ComputeValueVTs(*TLI, AggTy, AggValueVTs); 3084 SmallVector<EVT, 4> ValValueVTs; 3085 ComputeValueVTs(*TLI, ValTy, ValValueVTs); 3086 3087 unsigned NumAggValues = AggValueVTs.size(); 3088 unsigned NumValValues = ValValueVTs.size(); 3089 SmallVector<SDValue, 4> Values(NumAggValues); 3090 3091 SDValue Agg = getValue(Op0); 3092 unsigned i = 0; 3093 // Copy the beginning value(s) from the original aggregate. 3094 for (; i != LinearIndex; ++i) 3095 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3096 SDValue(Agg.getNode(), Agg.getResNo() + i); 3097 // Copy values from the inserted value(s). 3098 if (NumValValues) { 3099 SDValue Val = getValue(Op1); 3100 for (; i != LinearIndex + NumValValues; ++i) 3101 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3102 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3103 } 3104 // Copy remaining value(s) from the original aggregate. 3105 for (; i != NumAggValues; ++i) 3106 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3107 SDValue(Agg.getNode(), Agg.getResNo() + i); 3108 3109 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3110 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3111 &Values[0], NumAggValues)); 3112} 3113 3114void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3115 const Value *Op0 = I.getOperand(0); 3116 Type *AggTy = Op0->getType(); 3117 Type *ValTy = I.getType(); 3118 bool OutOfUndef = isa<UndefValue>(Op0); 3119 3120 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3121 3122 const TargetLowering *TLI = TM.getTargetLowering(); 3123 SmallVector<EVT, 4> ValValueVTs; 3124 ComputeValueVTs(*TLI, ValTy, ValValueVTs); 3125 3126 unsigned NumValValues = ValValueVTs.size(); 3127 3128 // Ignore a extractvalue that produces an empty object 3129 if (!NumValValues) { 3130 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3131 return; 3132 } 3133 3134 SmallVector<SDValue, 4> Values(NumValValues); 3135 3136 SDValue Agg = getValue(Op0); 3137 // Copy out the selected value(s). 3138 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3139 Values[i - LinearIndex] = 3140 OutOfUndef ? 3141 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3142 SDValue(Agg.getNode(), Agg.getResNo() + i); 3143 3144 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3145 DAG.getVTList(&ValValueVTs[0], NumValValues), 3146 &Values[0], NumValValues)); 3147} 3148 3149void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3150 SDValue N = getValue(I.getOperand(0)); 3151 // Note that the pointer operand may be a vector of pointers. Take the scalar 3152 // element which holds a pointer. 3153 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3154 3155 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3156 OI != E; ++OI) { 3157 const Value *Idx = *OI; 3158 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3159 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue(); 3160 if (Field) { 3161 // N = N + Offset 3162 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3163 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, 3164 DAG.getConstant(Offset, N.getValueType())); 3165 } 3166 3167 Ty = StTy->getElementType(Field); 3168 } else { 3169 Ty = cast<SequentialType>(Ty)->getElementType(); 3170 3171 // If this is a constant subscript, handle it quickly. 3172 const TargetLowering *TLI = TM.getTargetLowering(); 3173 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3174 if (CI->isZero()) continue; 3175 uint64_t Offs = 3176 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3177 SDValue OffsVal; 3178 EVT PTy = TLI->getPointerTy(); 3179 unsigned PtrBits = PTy.getSizeInBits(); 3180 if (PtrBits < 64) 3181 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), 3182 TLI->getPointerTy(), 3183 DAG.getConstant(Offs, MVT::i64)); 3184 else 3185 OffsVal = DAG.getIntPtrConstant(Offs); 3186 3187 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, 3188 OffsVal); 3189 continue; 3190 } 3191 3192 // N = N + Idx * ElementSize; 3193 APInt ElementSize = APInt(TLI->getPointerTy().getSizeInBits(), 3194 TD->getTypeAllocSize(Ty)); 3195 SDValue IdxN = getValue(Idx); 3196 3197 // If the index is smaller or larger than intptr_t, truncate or extend 3198 // it. 3199 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType()); 3200 3201 // If this is a multiply by a power of two, turn it into a shl 3202 // immediately. This is a very common case. 3203 if (ElementSize != 1) { 3204 if (ElementSize.isPowerOf2()) { 3205 unsigned Amt = ElementSize.logBase2(); 3206 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(), 3207 N.getValueType(), IdxN, 3208 DAG.getConstant(Amt, IdxN.getValueType())); 3209 } else { 3210 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType()); 3211 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(), 3212 N.getValueType(), IdxN, Scale); 3213 } 3214 } 3215 3216 N = DAG.getNode(ISD::ADD, getCurSDLoc(), 3217 N.getValueType(), N, IdxN); 3218 } 3219 } 3220 3221 setValue(&I, N); 3222} 3223 3224void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3225 // If this is a fixed sized alloca in the entry block of the function, 3226 // allocate it statically on the stack. 3227 if (FuncInfo.StaticAllocaMap.count(&I)) 3228 return; // getValue will auto-populate this. 3229 3230 Type *Ty = I.getAllocatedType(); 3231 const TargetLowering *TLI = TM.getTargetLowering(); 3232 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty); 3233 unsigned Align = 3234 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty), 3235 I.getAlignment()); 3236 3237 SDValue AllocSize = getValue(I.getArraySize()); 3238 3239 EVT IntPtr = TLI->getPointerTy(); 3240 if (AllocSize.getValueType() != IntPtr) 3241 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr); 3242 3243 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr, 3244 AllocSize, 3245 DAG.getConstant(TySize, IntPtr)); 3246 3247 // Handle alignment. If the requested alignment is less than or equal to 3248 // the stack alignment, ignore it. If the size is greater than or equal to 3249 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3250 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3251 if (Align <= StackAlign) 3252 Align = 0; 3253 3254 // Round the size of the allocation up to the stack alignment size 3255 // by add SA-1 to the size. 3256 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(), 3257 AllocSize.getValueType(), AllocSize, 3258 DAG.getIntPtrConstant(StackAlign-1)); 3259 3260 // Mask out the low bits for alignment purposes. 3261 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(), 3262 AllocSize.getValueType(), AllocSize, 3263 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3264 3265 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3266 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3267 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), 3268 VTs, Ops, 3); 3269 setValue(&I, DSA); 3270 DAG.setRoot(DSA.getValue(1)); 3271 3272 // Inform the Frame Information that we have just allocated a variable-sized 3273 // object. 3274 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3275} 3276 3277void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3278 if (I.isAtomic()) 3279 return visitAtomicLoad(I); 3280 3281 const Value *SV = I.getOperand(0); 3282 SDValue Ptr = getValue(SV); 3283 3284 Type *Ty = I.getType(); 3285 3286 bool isVolatile = I.isVolatile(); 3287 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3288 bool isInvariant = I.getMetadata("invariant.load") != 0; 3289 unsigned Alignment = I.getAlignment(); 3290 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3291 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3292 3293 SmallVector<EVT, 4> ValueVTs; 3294 SmallVector<uint64_t, 4> Offsets; 3295 ComputeValueVTs(*TM.getTargetLowering(), Ty, ValueVTs, &Offsets); 3296 unsigned NumValues = ValueVTs.size(); 3297 if (NumValues == 0) 3298 return; 3299 3300 SDValue Root; 3301 bool ConstantMemory = false; 3302 if (I.isVolatile() || NumValues > MaxParallelChains) 3303 // Serialize volatile loads with other side effects. 3304 Root = getRoot(); 3305 else if (AA->pointsToConstantMemory( 3306 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3307 // Do not serialize (non-volatile) loads of constant memory with anything. 3308 Root = DAG.getEntryNode(); 3309 ConstantMemory = true; 3310 } else { 3311 // Do not serialize non-volatile loads against each other. 3312 Root = DAG.getRoot(); 3313 } 3314 3315 SmallVector<SDValue, 4> Values(NumValues); 3316 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3317 NumValues)); 3318 EVT PtrVT = Ptr.getValueType(); 3319 unsigned ChainI = 0; 3320 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3321 // Serializing loads here may result in excessive register pressure, and 3322 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3323 // could recover a bit by hoisting nodes upward in the chain by recognizing 3324 // they are side-effect free or do not alias. The optimizer should really 3325 // avoid this case by converting large object/array copies to llvm.memcpy 3326 // (MaxParallelChains should always remain as failsafe). 3327 if (ChainI == MaxParallelChains) { 3328 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3329 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3330 MVT::Other, &Chains[0], ChainI); 3331 Root = Chain; 3332 ChainI = 0; 3333 } 3334 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(), 3335 PtrVT, Ptr, 3336 DAG.getConstant(Offsets[i], PtrVT)); 3337 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root, 3338 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3339 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3340 Ranges); 3341 3342 Values[i] = L; 3343 Chains[ChainI] = L.getValue(1); 3344 } 3345 3346 if (!ConstantMemory) { 3347 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3348 MVT::Other, &Chains[0], ChainI); 3349 if (isVolatile) 3350 DAG.setRoot(Chain); 3351 else 3352 PendingLoads.push_back(Chain); 3353 } 3354 3355 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3356 DAG.getVTList(&ValueVTs[0], NumValues), 3357 &Values[0], NumValues)); 3358} 3359 3360void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3361 if (I.isAtomic()) 3362 return visitAtomicStore(I); 3363 3364 const Value *SrcV = I.getOperand(0); 3365 const Value *PtrV = I.getOperand(1); 3366 3367 SmallVector<EVT, 4> ValueVTs; 3368 SmallVector<uint64_t, 4> Offsets; 3369 ComputeValueVTs(*TM.getTargetLowering(), SrcV->getType(), ValueVTs, &Offsets); 3370 unsigned NumValues = ValueVTs.size(); 3371 if (NumValues == 0) 3372 return; 3373 3374 // Get the lowered operands. Note that we do this after 3375 // checking if NumResults is zero, because with zero results 3376 // the operands won't have values in the map. 3377 SDValue Src = getValue(SrcV); 3378 SDValue Ptr = getValue(PtrV); 3379 3380 SDValue Root = getRoot(); 3381 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3382 NumValues)); 3383 EVT PtrVT = Ptr.getValueType(); 3384 bool isVolatile = I.isVolatile(); 3385 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3386 unsigned Alignment = I.getAlignment(); 3387 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3388 3389 unsigned ChainI = 0; 3390 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3391 // See visitLoad comments. 3392 if (ChainI == MaxParallelChains) { 3393 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3394 MVT::Other, &Chains[0], ChainI); 3395 Root = Chain; 3396 ChainI = 0; 3397 } 3398 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr, 3399 DAG.getConstant(Offsets[i], PtrVT)); 3400 SDValue St = DAG.getStore(Root, getCurSDLoc(), 3401 SDValue(Src.getNode(), Src.getResNo() + i), 3402 Add, MachinePointerInfo(PtrV, Offsets[i]), 3403 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3404 Chains[ChainI] = St; 3405 } 3406 3407 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3408 MVT::Other, &Chains[0], ChainI); 3409 DAG.setRoot(StoreNode); 3410} 3411 3412static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3413 SynchronizationScope Scope, 3414 bool Before, SDLoc dl, 3415 SelectionDAG &DAG, 3416 const TargetLowering &TLI) { 3417 // Fence, if necessary 3418 if (Before) { 3419 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3420 Order = Release; 3421 else if (Order == Acquire || Order == Monotonic) 3422 return Chain; 3423 } else { 3424 if (Order == AcquireRelease) 3425 Order = Acquire; 3426 else if (Order == Release || Order == Monotonic) 3427 return Chain; 3428 } 3429 SDValue Ops[3]; 3430 Ops[0] = Chain; 3431 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3432 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3433 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3434} 3435 3436void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3437 SDLoc dl = getCurSDLoc(); 3438 AtomicOrdering Order = I.getOrdering(); 3439 SynchronizationScope Scope = I.getSynchScope(); 3440 3441 SDValue InChain = getRoot(); 3442 3443 const TargetLowering *TLI = TM.getTargetLowering(); 3444 if (TLI->getInsertFencesForAtomic()) 3445 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3446 DAG, *TLI); 3447 3448 SDValue L = 3449 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3450 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3451 InChain, 3452 getValue(I.getPointerOperand()), 3453 getValue(I.getCompareOperand()), 3454 getValue(I.getNewValOperand()), 3455 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3456 TLI->getInsertFencesForAtomic() ? Monotonic : Order, 3457 Scope); 3458 3459 SDValue OutChain = L.getValue(1); 3460 3461 if (TLI->getInsertFencesForAtomic()) 3462 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3463 DAG, *TLI); 3464 3465 setValue(&I, L); 3466 DAG.setRoot(OutChain); 3467} 3468 3469void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3470 SDLoc dl = getCurSDLoc(); 3471 ISD::NodeType NT; 3472 switch (I.getOperation()) { 3473 default: llvm_unreachable("Unknown atomicrmw operation"); 3474 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3475 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3476 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3477 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3478 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3479 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3480 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3481 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3482 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3483 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3484 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3485 } 3486 AtomicOrdering Order = I.getOrdering(); 3487 SynchronizationScope Scope = I.getSynchScope(); 3488 3489 SDValue InChain = getRoot(); 3490 3491 const TargetLowering *TLI = TM.getTargetLowering(); 3492 if (TLI->getInsertFencesForAtomic()) 3493 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3494 DAG, *TLI); 3495 3496 SDValue L = 3497 DAG.getAtomic(NT, dl, 3498 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3499 InChain, 3500 getValue(I.getPointerOperand()), 3501 getValue(I.getValOperand()), 3502 I.getPointerOperand(), 0 /* Alignment */, 3503 TLI->getInsertFencesForAtomic() ? Monotonic : Order, 3504 Scope); 3505 3506 SDValue OutChain = L.getValue(1); 3507 3508 if (TLI->getInsertFencesForAtomic()) 3509 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3510 DAG, *TLI); 3511 3512 setValue(&I, L); 3513 DAG.setRoot(OutChain); 3514} 3515 3516void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3517 SDLoc dl = getCurSDLoc(); 3518 const TargetLowering *TLI = TM.getTargetLowering(); 3519 SDValue Ops[3]; 3520 Ops[0] = getRoot(); 3521 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy()); 3522 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy()); 3523 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3524} 3525 3526void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3527 SDLoc dl = getCurSDLoc(); 3528 AtomicOrdering Order = I.getOrdering(); 3529 SynchronizationScope Scope = I.getSynchScope(); 3530 3531 SDValue InChain = getRoot(); 3532 3533 const TargetLowering *TLI = TM.getTargetLowering(); 3534 EVT VT = TLI->getValueType(I.getType()); 3535 3536 if (I.getAlignment() < VT.getSizeInBits() / 8) 3537 report_fatal_error("Cannot generate unaligned atomic load"); 3538 3539 SDValue L = 3540 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3541 getValue(I.getPointerOperand()), 3542 I.getPointerOperand(), I.getAlignment(), 3543 TLI->getInsertFencesForAtomic() ? Monotonic : Order, 3544 Scope); 3545 3546 SDValue OutChain = L.getValue(1); 3547 3548 if (TLI->getInsertFencesForAtomic()) 3549 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3550 DAG, *TLI); 3551 3552 setValue(&I, L); 3553 DAG.setRoot(OutChain); 3554} 3555 3556void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3557 SDLoc dl = getCurSDLoc(); 3558 3559 AtomicOrdering Order = I.getOrdering(); 3560 SynchronizationScope Scope = I.getSynchScope(); 3561 3562 SDValue InChain = getRoot(); 3563 3564 const TargetLowering *TLI = TM.getTargetLowering(); 3565 EVT VT = TLI->getValueType(I.getValueOperand()->getType()); 3566 3567 if (I.getAlignment() < VT.getSizeInBits() / 8) 3568 report_fatal_error("Cannot generate unaligned atomic store"); 3569 3570 if (TLI->getInsertFencesForAtomic()) 3571 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3572 DAG, *TLI); 3573 3574 SDValue OutChain = 3575 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3576 InChain, 3577 getValue(I.getPointerOperand()), 3578 getValue(I.getValueOperand()), 3579 I.getPointerOperand(), I.getAlignment(), 3580 TLI->getInsertFencesForAtomic() ? Monotonic : Order, 3581 Scope); 3582 3583 if (TLI->getInsertFencesForAtomic()) 3584 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3585 DAG, *TLI); 3586 3587 DAG.setRoot(OutChain); 3588} 3589 3590/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3591/// node. 3592void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3593 unsigned Intrinsic) { 3594 bool HasChain = !I.doesNotAccessMemory(); 3595 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3596 3597 // Build the operand list. 3598 SmallVector<SDValue, 8> Ops; 3599 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3600 if (OnlyLoad) { 3601 // We don't need to serialize loads against other loads. 3602 Ops.push_back(DAG.getRoot()); 3603 } else { 3604 Ops.push_back(getRoot()); 3605 } 3606 } 3607 3608 // Info is set by getTgtMemInstrinsic 3609 TargetLowering::IntrinsicInfo Info; 3610 const TargetLowering *TLI = TM.getTargetLowering(); 3611 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic); 3612 3613 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3614 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3615 Info.opc == ISD::INTRINSIC_W_CHAIN) 3616 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy())); 3617 3618 // Add all operands of the call to the operand list. 3619 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3620 SDValue Op = getValue(I.getArgOperand(i)); 3621 Ops.push_back(Op); 3622 } 3623 3624 SmallVector<EVT, 4> ValueVTs; 3625 ComputeValueVTs(*TLI, I.getType(), ValueVTs); 3626 3627 if (HasChain) 3628 ValueVTs.push_back(MVT::Other); 3629 3630 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3631 3632 // Create the node. 3633 SDValue Result; 3634 if (IsTgtIntrinsic) { 3635 // This is target intrinsic that touches memory 3636 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), 3637 VTs, &Ops[0], Ops.size(), 3638 Info.memVT, 3639 MachinePointerInfo(Info.ptrVal, Info.offset), 3640 Info.align, Info.vol, 3641 Info.readMem, Info.writeMem); 3642 } else if (!HasChain) { 3643 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), 3644 VTs, &Ops[0], Ops.size()); 3645 } else if (!I.getType()->isVoidTy()) { 3646 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), 3647 VTs, &Ops[0], Ops.size()); 3648 } else { 3649 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), 3650 VTs, &Ops[0], Ops.size()); 3651 } 3652 3653 if (HasChain) { 3654 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3655 if (OnlyLoad) 3656 PendingLoads.push_back(Chain); 3657 else 3658 DAG.setRoot(Chain); 3659 } 3660 3661 if (!I.getType()->isVoidTy()) { 3662 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3663 EVT VT = TLI->getValueType(PTy); 3664 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result); 3665 } 3666 3667 setValue(&I, Result); 3668 } 3669} 3670 3671/// GetSignificand - Get the significand and build it into a floating-point 3672/// number with exponent of 1: 3673/// 3674/// Op = (Op & 0x007fffff) | 0x3f800000; 3675/// 3676/// where Op is the hexadecimal representation of floating point value. 3677static SDValue 3678GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) { 3679 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3680 DAG.getConstant(0x007fffff, MVT::i32)); 3681 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3682 DAG.getConstant(0x3f800000, MVT::i32)); 3683 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3684} 3685 3686/// GetExponent - Get the exponent: 3687/// 3688/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3689/// 3690/// where Op is the hexadecimal representation of floating point value. 3691static SDValue 3692GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3693 SDLoc dl) { 3694 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3695 DAG.getConstant(0x7f800000, MVT::i32)); 3696 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3697 DAG.getConstant(23, TLI.getPointerTy())); 3698 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3699 DAG.getConstant(127, MVT::i32)); 3700 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3701} 3702 3703/// getF32Constant - Get 32-bit floating point constant. 3704static SDValue 3705getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3706 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), 3707 MVT::f32); 3708} 3709 3710/// expandExp - Lower an exp intrinsic. Handles the special sequences for 3711/// limited-precision mode. 3712static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG, 3713 const TargetLowering &TLI) { 3714 if (Op.getValueType() == MVT::f32 && 3715 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3716 3717 // Put the exponent in the right bit position for later addition to the 3718 // final result: 3719 // 3720 // #define LOG2OFe 1.4426950f 3721 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3722 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3723 getF32Constant(DAG, 0x3fb8aa3b)); 3724 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3725 3726 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3727 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3728 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3729 3730 // IntegerPartOfX <<= 23; 3731 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3732 DAG.getConstant(23, TLI.getPointerTy())); 3733 3734 SDValue TwoToFracPartOfX; 3735 if (LimitFloatPrecision <= 6) { 3736 // For floating-point precision of 6: 3737 // 3738 // TwoToFractionalPartOfX = 3739 // 0.997535578f + 3740 // (0.735607626f + 0.252464424f * x) * x; 3741 // 3742 // error 0.0144103317, which is 6 bits 3743 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3744 getF32Constant(DAG, 0x3e814304)); 3745 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3746 getF32Constant(DAG, 0x3f3c50c8)); 3747 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3748 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3749 getF32Constant(DAG, 0x3f7f5e7e)); 3750 } else if (LimitFloatPrecision <= 12) { 3751 // For floating-point precision of 12: 3752 // 3753 // TwoToFractionalPartOfX = 3754 // 0.999892986f + 3755 // (0.696457318f + 3756 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3757 // 3758 // 0.000107046256 error, which is 13 to 14 bits 3759 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3760 getF32Constant(DAG, 0x3da235e3)); 3761 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3762 getF32Constant(DAG, 0x3e65b8f3)); 3763 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3764 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3765 getF32Constant(DAG, 0x3f324b07)); 3766 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3767 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3768 getF32Constant(DAG, 0x3f7ff8fd)); 3769 } else { // LimitFloatPrecision <= 18 3770 // For floating-point precision of 18: 3771 // 3772 // TwoToFractionalPartOfX = 3773 // 0.999999982f + 3774 // (0.693148872f + 3775 // (0.240227044f + 3776 // (0.554906021e-1f + 3777 // (0.961591928e-2f + 3778 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3779 // 3780 // error 2.47208000*10^(-7), which is better than 18 bits 3781 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3782 getF32Constant(DAG, 0x3924b03e)); 3783 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3784 getF32Constant(DAG, 0x3ab24b87)); 3785 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3786 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3787 getF32Constant(DAG, 0x3c1d8c17)); 3788 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3789 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3790 getF32Constant(DAG, 0x3d634a1d)); 3791 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3792 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3793 getF32Constant(DAG, 0x3e75fe14)); 3794 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3795 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3796 getF32Constant(DAG, 0x3f317234)); 3797 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3798 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3799 getF32Constant(DAG, 0x3f800000)); 3800 } 3801 3802 // Add the exponent into the result in integer domain. 3803 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX); 3804 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3805 DAG.getNode(ISD::ADD, dl, MVT::i32, 3806 t13, IntegerPartOfX)); 3807 } 3808 3809 // No special expansion. 3810 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op); 3811} 3812 3813/// expandLog - Lower a log intrinsic. Handles the special sequences for 3814/// limited-precision mode. 3815static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG, 3816 const TargetLowering &TLI) { 3817 if (Op.getValueType() == MVT::f32 && 3818 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3819 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3820 3821 // Scale the exponent by log(2) [0.69314718f]. 3822 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3823 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3824 getF32Constant(DAG, 0x3f317218)); 3825 3826 // Get the significand and build it into a floating-point number with 3827 // exponent of 1. 3828 SDValue X = GetSignificand(DAG, Op1, dl); 3829 3830 SDValue LogOfMantissa; 3831 if (LimitFloatPrecision <= 6) { 3832 // For floating-point precision of 6: 3833 // 3834 // LogofMantissa = 3835 // -1.1609546f + 3836 // (1.4034025f - 0.23903021f * x) * x; 3837 // 3838 // error 0.0034276066, which is better than 8 bits 3839 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3840 getF32Constant(DAG, 0xbe74c456)); 3841 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3842 getF32Constant(DAG, 0x3fb3a2b1)); 3843 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3844 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3845 getF32Constant(DAG, 0x3f949a29)); 3846 } else if (LimitFloatPrecision <= 12) { 3847 // For floating-point precision of 12: 3848 // 3849 // LogOfMantissa = 3850 // -1.7417939f + 3851 // (2.8212026f + 3852 // (-1.4699568f + 3853 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3854 // 3855 // error 0.000061011436, which is 14 bits 3856 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3857 getF32Constant(DAG, 0xbd67b6d6)); 3858 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3859 getF32Constant(DAG, 0x3ee4f4b8)); 3860 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3861 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3862 getF32Constant(DAG, 0x3fbc278b)); 3863 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3864 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3865 getF32Constant(DAG, 0x40348e95)); 3866 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3867 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3868 getF32Constant(DAG, 0x3fdef31a)); 3869 } else { // LimitFloatPrecision <= 18 3870 // For floating-point precision of 18: 3871 // 3872 // LogOfMantissa = 3873 // -2.1072184f + 3874 // (4.2372794f + 3875 // (-3.7029485f + 3876 // (2.2781945f + 3877 // (-0.87823314f + 3878 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3879 // 3880 // error 0.0000023660568, which is better than 18 bits 3881 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3882 getF32Constant(DAG, 0xbc91e5ac)); 3883 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3884 getF32Constant(DAG, 0x3e4350aa)); 3885 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3886 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3887 getF32Constant(DAG, 0x3f60d3e3)); 3888 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3889 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3890 getF32Constant(DAG, 0x4011cdf0)); 3891 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3892 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3893 getF32Constant(DAG, 0x406cfd1c)); 3894 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3895 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3896 getF32Constant(DAG, 0x408797cb)); 3897 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3898 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3899 getF32Constant(DAG, 0x4006dcab)); 3900 } 3901 3902 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa); 3903 } 3904 3905 // No special expansion. 3906 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op); 3907} 3908 3909/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for 3910/// limited-precision mode. 3911static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG, 3912 const TargetLowering &TLI) { 3913 if (Op.getValueType() == MVT::f32 && 3914 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3915 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3916 3917 // Get the exponent. 3918 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3919 3920 // Get the significand and build it into a floating-point number with 3921 // exponent of 1. 3922 SDValue X = GetSignificand(DAG, Op1, dl); 3923 3924 // Different possible minimax approximations of significand in 3925 // floating-point for various degrees of accuracy over [1,2]. 3926 SDValue Log2ofMantissa; 3927 if (LimitFloatPrecision <= 6) { 3928 // For floating-point precision of 6: 3929 // 3930 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3931 // 3932 // error 0.0049451742, which is more than 7 bits 3933 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3934 getF32Constant(DAG, 0xbeb08fe0)); 3935 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3936 getF32Constant(DAG, 0x40019463)); 3937 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3938 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3939 getF32Constant(DAG, 0x3fd6633d)); 3940 } else if (LimitFloatPrecision <= 12) { 3941 // For floating-point precision of 12: 3942 // 3943 // Log2ofMantissa = 3944 // -2.51285454f + 3945 // (4.07009056f + 3946 // (-2.12067489f + 3947 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3948 // 3949 // error 0.0000876136000, which is better than 13 bits 3950 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3951 getF32Constant(DAG, 0xbda7262e)); 3952 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3953 getF32Constant(DAG, 0x3f25280b)); 3954 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3955 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3956 getF32Constant(DAG, 0x4007b923)); 3957 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3958 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3959 getF32Constant(DAG, 0x40823e2f)); 3960 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3961 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3962 getF32Constant(DAG, 0x4020d29c)); 3963 } else { // LimitFloatPrecision <= 18 3964 // For floating-point precision of 18: 3965 // 3966 // Log2ofMantissa = 3967 // -3.0400495f + 3968 // (6.1129976f + 3969 // (-5.3420409f + 3970 // (3.2865683f + 3971 // (-1.2669343f + 3972 // (0.27515199f - 3973 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3974 // 3975 // error 0.0000018516, which is better than 18 bits 3976 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3977 getF32Constant(DAG, 0xbcd2769e)); 3978 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3979 getF32Constant(DAG, 0x3e8ce0b9)); 3980 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3981 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3982 getF32Constant(DAG, 0x3fa22ae7)); 3983 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3984 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3985 getF32Constant(DAG, 0x40525723)); 3986 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3987 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3988 getF32Constant(DAG, 0x40aaf200)); 3989 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3990 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3991 getF32Constant(DAG, 0x40c39dad)); 3992 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3993 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3994 getF32Constant(DAG, 0x4042902c)); 3995 } 3996 3997 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa); 3998 } 3999 4000 // No special expansion. 4001 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op); 4002} 4003 4004/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for 4005/// limited-precision mode. 4006static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG, 4007 const TargetLowering &TLI) { 4008 if (Op.getValueType() == MVT::f32 && 4009 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4010 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 4011 4012 // Scale the exponent by log10(2) [0.30102999f]. 4013 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 4014 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 4015 getF32Constant(DAG, 0x3e9a209a)); 4016 4017 // Get the significand and build it into a floating-point number with 4018 // exponent of 1. 4019 SDValue X = GetSignificand(DAG, Op1, dl); 4020 4021 SDValue Log10ofMantissa; 4022 if (LimitFloatPrecision <= 6) { 4023 // For floating-point precision of 6: 4024 // 4025 // Log10ofMantissa = 4026 // -0.50419619f + 4027 // (0.60948995f - 0.10380950f * x) * x; 4028 // 4029 // error 0.0014886165, which is 6 bits 4030 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4031 getF32Constant(DAG, 0xbdd49a13)); 4032 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4033 getF32Constant(DAG, 0x3f1c0789)); 4034 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4035 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4036 getF32Constant(DAG, 0x3f011300)); 4037 } else if (LimitFloatPrecision <= 12) { 4038 // For floating-point precision of 12: 4039 // 4040 // Log10ofMantissa = 4041 // -0.64831180f + 4042 // (0.91751397f + 4043 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4044 // 4045 // error 0.00019228036, which is better than 12 bits 4046 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4047 getF32Constant(DAG, 0x3d431f31)); 4048 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4049 getF32Constant(DAG, 0x3ea21fb2)); 4050 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4051 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4052 getF32Constant(DAG, 0x3f6ae232)); 4053 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4054 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4055 getF32Constant(DAG, 0x3f25f7c3)); 4056 } else { // LimitFloatPrecision <= 18 4057 // For floating-point precision of 18: 4058 // 4059 // Log10ofMantissa = 4060 // -0.84299375f + 4061 // (1.5327582f + 4062 // (-1.0688956f + 4063 // (0.49102474f + 4064 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4065 // 4066 // error 0.0000037995730, which is better than 18 bits 4067 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4068 getF32Constant(DAG, 0x3c5d51ce)); 4069 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4070 getF32Constant(DAG, 0x3e00685a)); 4071 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4072 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4073 getF32Constant(DAG, 0x3efb6798)); 4074 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4075 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4076 getF32Constant(DAG, 0x3f88d192)); 4077 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4078 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4079 getF32Constant(DAG, 0x3fc4316c)); 4080 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4081 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4082 getF32Constant(DAG, 0x3f57ce70)); 4083 } 4084 4085 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa); 4086 } 4087 4088 // No special expansion. 4089 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op); 4090} 4091 4092/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4093/// limited-precision mode. 4094static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG, 4095 const TargetLowering &TLI) { 4096 if (Op.getValueType() == MVT::f32 && 4097 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4098 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4099 4100 // FractionalPartOfX = x - (float)IntegerPartOfX; 4101 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4102 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4103 4104 // IntegerPartOfX <<= 23; 4105 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4106 DAG.getConstant(23, TLI.getPointerTy())); 4107 4108 SDValue TwoToFractionalPartOfX; 4109 if (LimitFloatPrecision <= 6) { 4110 // For floating-point precision of 6: 4111 // 4112 // TwoToFractionalPartOfX = 4113 // 0.997535578f + 4114 // (0.735607626f + 0.252464424f * x) * x; 4115 // 4116 // error 0.0144103317, which is 6 bits 4117 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4118 getF32Constant(DAG, 0x3e814304)); 4119 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4120 getF32Constant(DAG, 0x3f3c50c8)); 4121 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4122 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4123 getF32Constant(DAG, 0x3f7f5e7e)); 4124 } else if (LimitFloatPrecision <= 12) { 4125 // For floating-point precision of 12: 4126 // 4127 // TwoToFractionalPartOfX = 4128 // 0.999892986f + 4129 // (0.696457318f + 4130 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4131 // 4132 // error 0.000107046256, which is 13 to 14 bits 4133 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4134 getF32Constant(DAG, 0x3da235e3)); 4135 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4136 getF32Constant(DAG, 0x3e65b8f3)); 4137 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4138 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4139 getF32Constant(DAG, 0x3f324b07)); 4140 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4141 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4142 getF32Constant(DAG, 0x3f7ff8fd)); 4143 } else { // LimitFloatPrecision <= 18 4144 // For floating-point precision of 18: 4145 // 4146 // TwoToFractionalPartOfX = 4147 // 0.999999982f + 4148 // (0.693148872f + 4149 // (0.240227044f + 4150 // (0.554906021e-1f + 4151 // (0.961591928e-2f + 4152 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4153 // error 2.47208000*10^(-7), which is better than 18 bits 4154 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4155 getF32Constant(DAG, 0x3924b03e)); 4156 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4157 getF32Constant(DAG, 0x3ab24b87)); 4158 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4159 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4160 getF32Constant(DAG, 0x3c1d8c17)); 4161 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4162 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4163 getF32Constant(DAG, 0x3d634a1d)); 4164 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4165 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4166 getF32Constant(DAG, 0x3e75fe14)); 4167 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4168 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4169 getF32Constant(DAG, 0x3f317234)); 4170 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4171 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4172 getF32Constant(DAG, 0x3f800000)); 4173 } 4174 4175 // Add the exponent into the result in integer domain. 4176 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, 4177 TwoToFractionalPartOfX); 4178 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4179 DAG.getNode(ISD::ADD, dl, MVT::i32, 4180 t13, IntegerPartOfX)); 4181 } 4182 4183 // No special expansion. 4184 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op); 4185} 4186 4187/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4188/// limited-precision mode with x == 10.0f. 4189static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS, 4190 SelectionDAG &DAG, const TargetLowering &TLI) { 4191 bool IsExp10 = false; 4192 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 && 4193 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4194 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) { 4195 APFloat Ten(10.0f); 4196 IsExp10 = LHSC->isExactlyValue(Ten); 4197 } 4198 } 4199 4200 if (IsExp10) { 4201 // Put the exponent in the right bit position for later addition to the 4202 // final result: 4203 // 4204 // #define LOG2OF10 3.3219281f 4205 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4206 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS, 4207 getF32Constant(DAG, 0x40549a78)); 4208 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4209 4210 // FractionalPartOfX = x - (float)IntegerPartOfX; 4211 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4212 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4213 4214 // IntegerPartOfX <<= 23; 4215 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4216 DAG.getConstant(23, TLI.getPointerTy())); 4217 4218 SDValue TwoToFractionalPartOfX; 4219 if (LimitFloatPrecision <= 6) { 4220 // For floating-point precision of 6: 4221 // 4222 // twoToFractionalPartOfX = 4223 // 0.997535578f + 4224 // (0.735607626f + 0.252464424f * x) * x; 4225 // 4226 // error 0.0144103317, which is 6 bits 4227 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4228 getF32Constant(DAG, 0x3e814304)); 4229 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4230 getF32Constant(DAG, 0x3f3c50c8)); 4231 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4232 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4233 getF32Constant(DAG, 0x3f7f5e7e)); 4234 } else if (LimitFloatPrecision <= 12) { 4235 // For floating-point precision of 12: 4236 // 4237 // TwoToFractionalPartOfX = 4238 // 0.999892986f + 4239 // (0.696457318f + 4240 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4241 // 4242 // error 0.000107046256, which is 13 to 14 bits 4243 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4244 getF32Constant(DAG, 0x3da235e3)); 4245 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4246 getF32Constant(DAG, 0x3e65b8f3)); 4247 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4248 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4249 getF32Constant(DAG, 0x3f324b07)); 4250 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4251 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4252 getF32Constant(DAG, 0x3f7ff8fd)); 4253 } else { // LimitFloatPrecision <= 18 4254 // For floating-point precision of 18: 4255 // 4256 // TwoToFractionalPartOfX = 4257 // 0.999999982f + 4258 // (0.693148872f + 4259 // (0.240227044f + 4260 // (0.554906021e-1f + 4261 // (0.961591928e-2f + 4262 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4263 // error 2.47208000*10^(-7), which is better than 18 bits 4264 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4265 getF32Constant(DAG, 0x3924b03e)); 4266 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4267 getF32Constant(DAG, 0x3ab24b87)); 4268 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4269 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4270 getF32Constant(DAG, 0x3c1d8c17)); 4271 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4272 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4273 getF32Constant(DAG, 0x3d634a1d)); 4274 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4275 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4276 getF32Constant(DAG, 0x3e75fe14)); 4277 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4278 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4279 getF32Constant(DAG, 0x3f317234)); 4280 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4281 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4282 getF32Constant(DAG, 0x3f800000)); 4283 } 4284 4285 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX); 4286 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4287 DAG.getNode(ISD::ADD, dl, MVT::i32, 4288 t13, IntegerPartOfX)); 4289 } 4290 4291 // No special expansion. 4292 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS); 4293} 4294 4295 4296/// ExpandPowI - Expand a llvm.powi intrinsic. 4297static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS, 4298 SelectionDAG &DAG) { 4299 // If RHS is a constant, we can expand this out to a multiplication tree, 4300 // otherwise we end up lowering to a call to __powidf2 (for example). When 4301 // optimizing for size, we only want to do this if the expansion would produce 4302 // a small number of multiplies, otherwise we do the full expansion. 4303 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4304 // Get the exponent as a positive value. 4305 unsigned Val = RHSC->getSExtValue(); 4306 if ((int)Val < 0) Val = -Val; 4307 4308 // powi(x, 0) -> 1.0 4309 if (Val == 0) 4310 return DAG.getConstantFP(1.0, LHS.getValueType()); 4311 4312 const Function *F = DAG.getMachineFunction().getFunction(); 4313 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 4314 Attribute::OptimizeForSize) || 4315 // If optimizing for size, don't insert too many multiplies. This 4316 // inserts up to 5 multiplies. 4317 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4318 // We use the simple binary decomposition method to generate the multiply 4319 // sequence. There are more optimal ways to do this (for example, 4320 // powi(x,15) generates one more multiply than it should), but this has 4321 // the benefit of being both really simple and much better than a libcall. 4322 SDValue Res; // Logically starts equal to 1.0 4323 SDValue CurSquare = LHS; 4324 while (Val) { 4325 if (Val & 1) { 4326 if (Res.getNode()) 4327 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4328 else 4329 Res = CurSquare; // 1.0*CurSquare. 4330 } 4331 4332 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4333 CurSquare, CurSquare); 4334 Val >>= 1; 4335 } 4336 4337 // If the original was negative, invert the result, producing 1/(x*x*x). 4338 if (RHSC->getSExtValue() < 0) 4339 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4340 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4341 return Res; 4342 } 4343 } 4344 4345 // Otherwise, expand to a libcall. 4346 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4347} 4348 4349// getTruncatedArgReg - Find underlying register used for an truncated 4350// argument. 4351static unsigned getTruncatedArgReg(const SDValue &N) { 4352 if (N.getOpcode() != ISD::TRUNCATE) 4353 return 0; 4354 4355 const SDValue &Ext = N.getOperand(0); 4356 if (Ext.getOpcode() == ISD::AssertZext || 4357 Ext.getOpcode() == ISD::AssertSext) { 4358 const SDValue &CFR = Ext.getOperand(0); 4359 if (CFR.getOpcode() == ISD::CopyFromReg) 4360 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4361 if (CFR.getOpcode() == ISD::TRUNCATE) 4362 return getTruncatedArgReg(CFR); 4363 } 4364 return 0; 4365} 4366 4367/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4368/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4369/// At the end of instruction selection, they will be inserted to the entry BB. 4370bool 4371SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4372 int64_t Offset, 4373 const SDValue &N) { 4374 const Argument *Arg = dyn_cast<Argument>(V); 4375 if (!Arg) 4376 return false; 4377 4378 MachineFunction &MF = DAG.getMachineFunction(); 4379 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4380 4381 // Ignore inlined function arguments here. 4382 DIVariable DV(Variable); 4383 if (DV.isInlinedFnArgument(MF.getFunction())) 4384 return false; 4385 4386 Optional<MachineOperand> Op; 4387 // Some arguments' frame index is recorded during argument lowering. 4388 if (int FI = FuncInfo.getArgumentFrameIndex(Arg)) 4389 Op = MachineOperand::CreateFI(FI); 4390 4391 if (!Op && N.getNode()) { 4392 unsigned Reg; 4393 if (N.getOpcode() == ISD::CopyFromReg) 4394 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4395 else 4396 Reg = getTruncatedArgReg(N); 4397 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4398 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4399 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4400 if (PR) 4401 Reg = PR; 4402 } 4403 if (Reg) 4404 Op = MachineOperand::CreateReg(Reg, false); 4405 } 4406 4407 if (!Op) { 4408 // Check if ValueMap has reg number. 4409 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4410 if (VMI != FuncInfo.ValueMap.end()) 4411 Op = MachineOperand::CreateReg(VMI->second, false); 4412 } 4413 4414 if (!Op && N.getNode()) 4415 // Check if frame index is available. 4416 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4417 if (FrameIndexSDNode *FINode = 4418 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 4419 Op = MachineOperand::CreateFI(FINode->getIndex()); 4420 4421 if (!Op) 4422 return false; 4423 4424 // FIXME: This does not handle register-indirect values at offset 0. 4425 bool IsIndirect = Offset != 0; 4426 if (Op->isReg()) 4427 FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(), 4428 TII->get(TargetOpcode::DBG_VALUE), 4429 IsIndirect, 4430 Op->getReg(), Offset, Variable)); 4431 else 4432 FuncInfo.ArgDbgValues.push_back( 4433 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE)) 4434 .addOperand(*Op).addImm(Offset).addMetadata(Variable)); 4435 4436 return true; 4437} 4438 4439// VisualStudio defines setjmp as _setjmp 4440#if defined(_MSC_VER) && defined(setjmp) && \ 4441 !defined(setjmp_undefined_for_msvc) 4442# pragma push_macro("setjmp") 4443# undef setjmp 4444# define setjmp_undefined_for_msvc 4445#endif 4446 4447/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4448/// we want to emit this as a call to a named external function, return the name 4449/// otherwise lower it and return null. 4450const char * 4451SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4452 const TargetLowering *TLI = TM.getTargetLowering(); 4453 SDLoc sdl = getCurSDLoc(); 4454 DebugLoc dl = getCurDebugLoc(); 4455 SDValue Res; 4456 4457 switch (Intrinsic) { 4458 default: 4459 // By default, turn this into a target intrinsic node. 4460 visitTargetIntrinsic(I, Intrinsic); 4461 return 0; 4462 case Intrinsic::vastart: visitVAStart(I); return 0; 4463 case Intrinsic::vaend: visitVAEnd(I); return 0; 4464 case Intrinsic::vacopy: visitVACopy(I); return 0; 4465 case Intrinsic::returnaddress: 4466 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(), 4467 getValue(I.getArgOperand(0)))); 4468 return 0; 4469 case Intrinsic::frameaddress: 4470 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(), 4471 getValue(I.getArgOperand(0)))); 4472 return 0; 4473 case Intrinsic::setjmp: 4474 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()]; 4475 case Intrinsic::longjmp: 4476 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()]; 4477 case Intrinsic::memcpy: { 4478 // Assert for address < 256 since we support only user defined address 4479 // spaces. 4480 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4481 < 256 && 4482 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4483 < 256 && 4484 "Unknown address space"); 4485 SDValue Op1 = getValue(I.getArgOperand(0)); 4486 SDValue Op2 = getValue(I.getArgOperand(1)); 4487 SDValue Op3 = getValue(I.getArgOperand(2)); 4488 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4489 if (!Align) 4490 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment. 4491 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4492 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false, 4493 MachinePointerInfo(I.getArgOperand(0)), 4494 MachinePointerInfo(I.getArgOperand(1)))); 4495 return 0; 4496 } 4497 case Intrinsic::memset: { 4498 // Assert for address < 256 since we support only user defined address 4499 // spaces. 4500 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4501 < 256 && 4502 "Unknown address space"); 4503 SDValue Op1 = getValue(I.getArgOperand(0)); 4504 SDValue Op2 = getValue(I.getArgOperand(1)); 4505 SDValue Op3 = getValue(I.getArgOperand(2)); 4506 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4507 if (!Align) 4508 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment. 4509 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4510 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, 4511 MachinePointerInfo(I.getArgOperand(0)))); 4512 return 0; 4513 } 4514 case Intrinsic::memmove: { 4515 // Assert for address < 256 since we support only user defined address 4516 // spaces. 4517 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4518 < 256 && 4519 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4520 < 256 && 4521 "Unknown address space"); 4522 SDValue Op1 = getValue(I.getArgOperand(0)); 4523 SDValue Op2 = getValue(I.getArgOperand(1)); 4524 SDValue Op3 = getValue(I.getArgOperand(2)); 4525 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4526 if (!Align) 4527 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment. 4528 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4529 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, 4530 MachinePointerInfo(I.getArgOperand(0)), 4531 MachinePointerInfo(I.getArgOperand(1)))); 4532 return 0; 4533 } 4534 case Intrinsic::dbg_declare: { 4535 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4536 MDNode *Variable = DI.getVariable(); 4537 const Value *Address = DI.getAddress(); 4538 DIVariable DIVar(Variable); 4539 assert((!DIVar || DIVar.isVariable()) && 4540 "Variable in DbgDeclareInst should be either null or a DIVariable."); 4541 if (!Address || !DIVar) { 4542 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4543 return 0; 4544 } 4545 4546 // Check if address has undef value. 4547 if (isa<UndefValue>(Address) || 4548 (Address->use_empty() && !isa<Argument>(Address))) { 4549 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4550 return 0; 4551 } 4552 4553 SDValue &N = NodeMap[Address]; 4554 if (!N.getNode() && isa<Argument>(Address)) 4555 // Check unused arguments map. 4556 N = UnusedArgNodeMap[Address]; 4557 SDDbgValue *SDV; 4558 if (N.getNode()) { 4559 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4560 Address = BCI->getOperand(0); 4561 // Parameters are handled specially. 4562 bool isParameter = 4563 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4564 isa<Argument>(Address)); 4565 4566 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4567 4568 if (isParameter && !AI) { 4569 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4570 if (FINode) 4571 // Byval parameter. We have a frame index at this point. 4572 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4573 0, dl, SDNodeOrder); 4574 else { 4575 // Address is an argument, so try to emit its dbg value using 4576 // virtual register info from the FuncInfo.ValueMap. 4577 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4578 return 0; 4579 } 4580 } else if (AI) 4581 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4582 0, dl, SDNodeOrder); 4583 else { 4584 // Can't do anything with other non-AI cases yet. 4585 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4586 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4587 DEBUG(Address->dump()); 4588 return 0; 4589 } 4590 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4591 } else { 4592 // If Address is an argument then try to emit its dbg value using 4593 // virtual register info from the FuncInfo.ValueMap. 4594 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4595 // If variable is pinned by a alloca in dominating bb then 4596 // use StaticAllocaMap. 4597 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4598 if (AI->getParent() != DI.getParent()) { 4599 DenseMap<const AllocaInst*, int>::iterator SI = 4600 FuncInfo.StaticAllocaMap.find(AI); 4601 if (SI != FuncInfo.StaticAllocaMap.end()) { 4602 SDV = DAG.getDbgValue(Variable, SI->second, 4603 0, dl, SDNodeOrder); 4604 DAG.AddDbgValue(SDV, 0, false); 4605 return 0; 4606 } 4607 } 4608 } 4609 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4610 } 4611 } 4612 return 0; 4613 } 4614 case Intrinsic::dbg_value: { 4615 const DbgValueInst &DI = cast<DbgValueInst>(I); 4616 DIVariable DIVar(DI.getVariable()); 4617 assert((!DIVar || DIVar.isVariable()) && 4618 "Variable in DbgValueInst should be either null or a DIVariable."); 4619 if (!DIVar) 4620 return 0; 4621 4622 MDNode *Variable = DI.getVariable(); 4623 uint64_t Offset = DI.getOffset(); 4624 const Value *V = DI.getValue(); 4625 if (!V) 4626 return 0; 4627 4628 SDDbgValue *SDV; 4629 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4630 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4631 DAG.AddDbgValue(SDV, 0, false); 4632 } else { 4633 // Do not use getValue() in here; we don't want to generate code at 4634 // this point if it hasn't been done yet. 4635 SDValue N = NodeMap[V]; 4636 if (!N.getNode() && isa<Argument>(V)) 4637 // Check unused arguments map. 4638 N = UnusedArgNodeMap[V]; 4639 if (N.getNode()) { 4640 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4641 SDV = DAG.getDbgValue(Variable, N.getNode(), 4642 N.getResNo(), Offset, dl, SDNodeOrder); 4643 DAG.AddDbgValue(SDV, N.getNode(), false); 4644 } 4645 } else if (!V->use_empty() ) { 4646 // Do not call getValue(V) yet, as we don't want to generate code. 4647 // Remember it for later. 4648 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4649 DanglingDebugInfoMap[V] = DDI; 4650 } else { 4651 // We may expand this to cover more cases. One case where we have no 4652 // data available is an unreferenced parameter. 4653 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4654 } 4655 } 4656 4657 // Build a debug info table entry. 4658 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4659 V = BCI->getOperand(0); 4660 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4661 // Don't handle byval struct arguments or VLAs, for example. 4662 if (!AI) { 4663 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4664 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4665 return 0; 4666 } 4667 DenseMap<const AllocaInst*, int>::iterator SI = 4668 FuncInfo.StaticAllocaMap.find(AI); 4669 if (SI == FuncInfo.StaticAllocaMap.end()) 4670 return 0; // VLAs. 4671 int FI = SI->second; 4672 4673 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4674 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4675 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4676 return 0; 4677 } 4678 4679 case Intrinsic::eh_typeid_for: { 4680 // Find the type id for the given typeinfo. 4681 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4682 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4683 Res = DAG.getConstant(TypeID, MVT::i32); 4684 setValue(&I, Res); 4685 return 0; 4686 } 4687 4688 case Intrinsic::eh_return_i32: 4689 case Intrinsic::eh_return_i64: 4690 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4691 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl, 4692 MVT::Other, 4693 getControlRoot(), 4694 getValue(I.getArgOperand(0)), 4695 getValue(I.getArgOperand(1)))); 4696 return 0; 4697 case Intrinsic::eh_unwind_init: 4698 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4699 return 0; 4700 case Intrinsic::eh_dwarf_cfa: { 4701 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl, 4702 TLI->getPointerTy()); 4703 SDValue Offset = DAG.getNode(ISD::ADD, sdl, 4704 TLI->getPointerTy(), 4705 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl, 4706 TLI->getPointerTy()), 4707 CfaArg); 4708 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, 4709 TLI->getPointerTy(), 4710 DAG.getConstant(0, TLI->getPointerTy())); 4711 setValue(&I, DAG.getNode(ISD::ADD, sdl, TLI->getPointerTy(), 4712 FA, Offset)); 4713 return 0; 4714 } 4715 case Intrinsic::eh_sjlj_callsite: { 4716 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4717 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4718 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4719 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4720 4721 MMI.setCurrentCallSite(CI->getZExtValue()); 4722 return 0; 4723 } 4724 case Intrinsic::eh_sjlj_functioncontext: { 4725 // Get and store the index of the function context. 4726 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4727 AllocaInst *FnCtx = 4728 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4729 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4730 MFI->setFunctionContextIndex(FI); 4731 return 0; 4732 } 4733 case Intrinsic::eh_sjlj_setjmp: { 4734 SDValue Ops[2]; 4735 Ops[0] = getRoot(); 4736 Ops[1] = getValue(I.getArgOperand(0)); 4737 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl, 4738 DAG.getVTList(MVT::i32, MVT::Other), 4739 Ops, 2); 4740 setValue(&I, Op.getValue(0)); 4741 DAG.setRoot(Op.getValue(1)); 4742 return 0; 4743 } 4744 case Intrinsic::eh_sjlj_longjmp: { 4745 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other, 4746 getRoot(), getValue(I.getArgOperand(0)))); 4747 return 0; 4748 } 4749 4750 case Intrinsic::x86_mmx_pslli_w: 4751 case Intrinsic::x86_mmx_pslli_d: 4752 case Intrinsic::x86_mmx_pslli_q: 4753 case Intrinsic::x86_mmx_psrli_w: 4754 case Intrinsic::x86_mmx_psrli_d: 4755 case Intrinsic::x86_mmx_psrli_q: 4756 case Intrinsic::x86_mmx_psrai_w: 4757 case Intrinsic::x86_mmx_psrai_d: { 4758 SDValue ShAmt = getValue(I.getArgOperand(1)); 4759 if (isa<ConstantSDNode>(ShAmt)) { 4760 visitTargetIntrinsic(I, Intrinsic); 4761 return 0; 4762 } 4763 unsigned NewIntrinsic = 0; 4764 EVT ShAmtVT = MVT::v2i32; 4765 switch (Intrinsic) { 4766 case Intrinsic::x86_mmx_pslli_w: 4767 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4768 break; 4769 case Intrinsic::x86_mmx_pslli_d: 4770 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4771 break; 4772 case Intrinsic::x86_mmx_pslli_q: 4773 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4774 break; 4775 case Intrinsic::x86_mmx_psrli_w: 4776 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4777 break; 4778 case Intrinsic::x86_mmx_psrli_d: 4779 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4780 break; 4781 case Intrinsic::x86_mmx_psrli_q: 4782 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4783 break; 4784 case Intrinsic::x86_mmx_psrai_w: 4785 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4786 break; 4787 case Intrinsic::x86_mmx_psrai_d: 4788 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4789 break; 4790 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4791 } 4792 4793 // The vector shift intrinsics with scalars uses 32b shift amounts but 4794 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4795 // to be zero. 4796 // We must do this early because v2i32 is not a legal type. 4797 SDValue ShOps[2]; 4798 ShOps[0] = ShAmt; 4799 ShOps[1] = DAG.getConstant(0, MVT::i32); 4800 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2); 4801 EVT DestVT = TLI->getValueType(I.getType()); 4802 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt); 4803 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT, 4804 DAG.getConstant(NewIntrinsic, MVT::i32), 4805 getValue(I.getArgOperand(0)), ShAmt); 4806 setValue(&I, Res); 4807 return 0; 4808 } 4809 case Intrinsic::x86_avx_vinsertf128_pd_256: 4810 case Intrinsic::x86_avx_vinsertf128_ps_256: 4811 case Intrinsic::x86_avx_vinsertf128_si_256: 4812 case Intrinsic::x86_avx2_vinserti128: { 4813 EVT DestVT = TLI->getValueType(I.getType()); 4814 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType()); 4815 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4816 ElVT.getVectorNumElements(); 4817 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT, 4818 getValue(I.getArgOperand(0)), 4819 getValue(I.getArgOperand(1)), 4820 DAG.getIntPtrConstant(Idx)); 4821 setValue(&I, Res); 4822 return 0; 4823 } 4824 case Intrinsic::x86_avx_vextractf128_pd_256: 4825 case Intrinsic::x86_avx_vextractf128_ps_256: 4826 case Intrinsic::x86_avx_vextractf128_si_256: 4827 case Intrinsic::x86_avx2_vextracti128: { 4828 EVT DestVT = TLI->getValueType(I.getType()); 4829 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) * 4830 DestVT.getVectorNumElements(); 4831 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT, 4832 getValue(I.getArgOperand(0)), 4833 DAG.getIntPtrConstant(Idx)); 4834 setValue(&I, Res); 4835 return 0; 4836 } 4837 case Intrinsic::convertff: 4838 case Intrinsic::convertfsi: 4839 case Intrinsic::convertfui: 4840 case Intrinsic::convertsif: 4841 case Intrinsic::convertuif: 4842 case Intrinsic::convertss: 4843 case Intrinsic::convertsu: 4844 case Intrinsic::convertus: 4845 case Intrinsic::convertuu: { 4846 ISD::CvtCode Code = ISD::CVT_INVALID; 4847 switch (Intrinsic) { 4848 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4849 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4850 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4851 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4852 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4853 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4854 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4855 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4856 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4857 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4858 } 4859 EVT DestVT = TLI->getValueType(I.getType()); 4860 const Value *Op1 = I.getArgOperand(0); 4861 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1), 4862 DAG.getValueType(DestVT), 4863 DAG.getValueType(getValue(Op1).getValueType()), 4864 getValue(I.getArgOperand(1)), 4865 getValue(I.getArgOperand(2)), 4866 Code); 4867 setValue(&I, Res); 4868 return 0; 4869 } 4870 case Intrinsic::powi: 4871 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)), 4872 getValue(I.getArgOperand(1)), DAG)); 4873 return 0; 4874 case Intrinsic::log: 4875 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI)); 4876 return 0; 4877 case Intrinsic::log2: 4878 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI)); 4879 return 0; 4880 case Intrinsic::log10: 4881 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI)); 4882 return 0; 4883 case Intrinsic::exp: 4884 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI)); 4885 return 0; 4886 case Intrinsic::exp2: 4887 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI)); 4888 return 0; 4889 case Intrinsic::pow: 4890 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)), 4891 getValue(I.getArgOperand(1)), DAG, *TLI)); 4892 return 0; 4893 case Intrinsic::sqrt: 4894 case Intrinsic::fabs: 4895 case Intrinsic::sin: 4896 case Intrinsic::cos: 4897 case Intrinsic::floor: 4898 case Intrinsic::ceil: 4899 case Intrinsic::trunc: 4900 case Intrinsic::rint: 4901 case Intrinsic::nearbyint: { 4902 unsigned Opcode; 4903 switch (Intrinsic) { 4904 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4905 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 4906 case Intrinsic::fabs: Opcode = ISD::FABS; break; 4907 case Intrinsic::sin: Opcode = ISD::FSIN; break; 4908 case Intrinsic::cos: Opcode = ISD::FCOS; break; 4909 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; 4910 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; 4911 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; 4912 case Intrinsic::rint: Opcode = ISD::FRINT; break; 4913 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; 4914 } 4915 4916 setValue(&I, DAG.getNode(Opcode, sdl, 4917 getValue(I.getArgOperand(0)).getValueType(), 4918 getValue(I.getArgOperand(0)))); 4919 return 0; 4920 } 4921 case Intrinsic::fma: 4922 setValue(&I, DAG.getNode(ISD::FMA, sdl, 4923 getValue(I.getArgOperand(0)).getValueType(), 4924 getValue(I.getArgOperand(0)), 4925 getValue(I.getArgOperand(1)), 4926 getValue(I.getArgOperand(2)))); 4927 return 0; 4928 case Intrinsic::fmuladd: { 4929 EVT VT = TLI->getValueType(I.getType()); 4930 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && 4931 TLI->isFMAFasterThanFMulAndFAdd(VT)) { 4932 setValue(&I, DAG.getNode(ISD::FMA, sdl, 4933 getValue(I.getArgOperand(0)).getValueType(), 4934 getValue(I.getArgOperand(0)), 4935 getValue(I.getArgOperand(1)), 4936 getValue(I.getArgOperand(2)))); 4937 } else { 4938 SDValue Mul = DAG.getNode(ISD::FMUL, sdl, 4939 getValue(I.getArgOperand(0)).getValueType(), 4940 getValue(I.getArgOperand(0)), 4941 getValue(I.getArgOperand(1))); 4942 SDValue Add = DAG.getNode(ISD::FADD, sdl, 4943 getValue(I.getArgOperand(0)).getValueType(), 4944 Mul, 4945 getValue(I.getArgOperand(2))); 4946 setValue(&I, Add); 4947 } 4948 return 0; 4949 } 4950 case Intrinsic::convert_to_fp16: 4951 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl, 4952 MVT::i16, getValue(I.getArgOperand(0)))); 4953 return 0; 4954 case Intrinsic::convert_from_fp16: 4955 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl, 4956 MVT::f32, getValue(I.getArgOperand(0)))); 4957 return 0; 4958 case Intrinsic::pcmarker: { 4959 SDValue Tmp = getValue(I.getArgOperand(0)); 4960 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp)); 4961 return 0; 4962 } 4963 case Intrinsic::readcyclecounter: { 4964 SDValue Op = getRoot(); 4965 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl, 4966 DAG.getVTList(MVT::i64, MVT::Other), 4967 &Op, 1); 4968 setValue(&I, Res); 4969 DAG.setRoot(Res.getValue(1)); 4970 return 0; 4971 } 4972 case Intrinsic::bswap: 4973 setValue(&I, DAG.getNode(ISD::BSWAP, sdl, 4974 getValue(I.getArgOperand(0)).getValueType(), 4975 getValue(I.getArgOperand(0)))); 4976 return 0; 4977 case Intrinsic::cttz: { 4978 SDValue Arg = getValue(I.getArgOperand(0)); 4979 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4980 EVT Ty = Arg.getValueType(); 4981 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4982 sdl, Ty, Arg)); 4983 return 0; 4984 } 4985 case Intrinsic::ctlz: { 4986 SDValue Arg = getValue(I.getArgOperand(0)); 4987 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4988 EVT Ty = Arg.getValueType(); 4989 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4990 sdl, Ty, Arg)); 4991 return 0; 4992 } 4993 case Intrinsic::ctpop: { 4994 SDValue Arg = getValue(I.getArgOperand(0)); 4995 EVT Ty = Arg.getValueType(); 4996 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg)); 4997 return 0; 4998 } 4999 case Intrinsic::stacksave: { 5000 SDValue Op = getRoot(); 5001 Res = DAG.getNode(ISD::STACKSAVE, sdl, 5002 DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1); 5003 setValue(&I, Res); 5004 DAG.setRoot(Res.getValue(1)); 5005 return 0; 5006 } 5007 case Intrinsic::stackrestore: { 5008 Res = getValue(I.getArgOperand(0)); 5009 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res)); 5010 return 0; 5011 } 5012 case Intrinsic::stackprotector: { 5013 // Emit code into the DAG to store the stack guard onto the stack. 5014 MachineFunction &MF = DAG.getMachineFunction(); 5015 MachineFrameInfo *MFI = MF.getFrameInfo(); 5016 EVT PtrTy = TLI->getPointerTy(); 5017 5018 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 5019 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 5020 5021 int FI = FuncInfo.StaticAllocaMap[Slot]; 5022 MFI->setStackProtectorIndex(FI); 5023 5024 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5025 5026 // Store the stack protector onto the stack. 5027 Res = DAG.getStore(getRoot(), sdl, Src, FIN, 5028 MachinePointerInfo::getFixedStack(FI), 5029 true, false, 0); 5030 setValue(&I, Res); 5031 DAG.setRoot(Res); 5032 return 0; 5033 } 5034 case Intrinsic::objectsize: { 5035 // If we don't know by now, we're never going to know. 5036 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5037 5038 assert(CI && "Non-constant type in __builtin_object_size?"); 5039 5040 SDValue Arg = getValue(I.getCalledValue()); 5041 EVT Ty = Arg.getValueType(); 5042 5043 if (CI->isZero()) 5044 Res = DAG.getConstant(-1ULL, Ty); 5045 else 5046 Res = DAG.getConstant(0, Ty); 5047 5048 setValue(&I, Res); 5049 return 0; 5050 } 5051 case Intrinsic::annotation: 5052 case Intrinsic::ptr_annotation: 5053 // Drop the intrinsic, but forward the value 5054 setValue(&I, getValue(I.getOperand(0))); 5055 return 0; 5056 case Intrinsic::var_annotation: 5057 // Discard annotate attributes 5058 return 0; 5059 5060 case Intrinsic::init_trampoline: { 5061 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5062 5063 SDValue Ops[6]; 5064 Ops[0] = getRoot(); 5065 Ops[1] = getValue(I.getArgOperand(0)); 5066 Ops[2] = getValue(I.getArgOperand(1)); 5067 Ops[3] = getValue(I.getArgOperand(2)); 5068 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5069 Ops[5] = DAG.getSrcValue(F); 5070 5071 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6); 5072 5073 DAG.setRoot(Res); 5074 return 0; 5075 } 5076 case Intrinsic::adjust_trampoline: { 5077 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl, 5078 TLI->getPointerTy(), 5079 getValue(I.getArgOperand(0)))); 5080 return 0; 5081 } 5082 case Intrinsic::gcroot: 5083 if (GFI) { 5084 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 5085 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5086 5087 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5088 GFI->addStackRoot(FI->getIndex(), TypeMap); 5089 } 5090 return 0; 5091 case Intrinsic::gcread: 5092 case Intrinsic::gcwrite: 5093 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5094 case Intrinsic::flt_rounds: 5095 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32)); 5096 return 0; 5097 5098 case Intrinsic::expect: { 5099 // Just replace __builtin_expect(exp, c) with EXP. 5100 setValue(&I, getValue(I.getArgOperand(0))); 5101 return 0; 5102 } 5103 5104 case Intrinsic::debugtrap: 5105 case Intrinsic::trap: { 5106 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5107 if (TrapFuncName.empty()) { 5108 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ? 5109 ISD::TRAP : ISD::DEBUGTRAP; 5110 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot())); 5111 return 0; 5112 } 5113 TargetLowering::ArgListTy Args; 5114 TargetLowering:: 5115 CallLoweringInfo CLI(getRoot(), I.getType(), 5116 false, false, false, false, 0, CallingConv::C, 5117 /*isTailCall=*/false, 5118 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5119 DAG.getExternalSymbol(TrapFuncName.data(), 5120 TLI->getPointerTy()), 5121 Args, DAG, sdl); 5122 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI); 5123 DAG.setRoot(Result.second); 5124 return 0; 5125 } 5126 5127 case Intrinsic::uadd_with_overflow: 5128 case Intrinsic::sadd_with_overflow: 5129 case Intrinsic::usub_with_overflow: 5130 case Intrinsic::ssub_with_overflow: 5131 case Intrinsic::umul_with_overflow: 5132 case Intrinsic::smul_with_overflow: { 5133 ISD::NodeType Op; 5134 switch (Intrinsic) { 5135 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5136 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 5137 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 5138 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 5139 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 5140 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 5141 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 5142 } 5143 SDValue Op1 = getValue(I.getArgOperand(0)); 5144 SDValue Op2 = getValue(I.getArgOperand(1)); 5145 5146 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5147 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2)); 5148 return 0; 5149 } 5150 case Intrinsic::prefetch: { 5151 SDValue Ops[5]; 5152 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5153 Ops[0] = getRoot(); 5154 Ops[1] = getValue(I.getArgOperand(0)); 5155 Ops[2] = getValue(I.getArgOperand(1)); 5156 Ops[3] = getValue(I.getArgOperand(2)); 5157 Ops[4] = getValue(I.getArgOperand(3)); 5158 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl, 5159 DAG.getVTList(MVT::Other), 5160 &Ops[0], 5, 5161 EVT::getIntegerVT(*Context, 8), 5162 MachinePointerInfo(I.getArgOperand(0)), 5163 0, /* align */ 5164 false, /* volatile */ 5165 rw==0, /* read */ 5166 rw==1)); /* write */ 5167 return 0; 5168 } 5169 case Intrinsic::lifetime_start: 5170 case Intrinsic::lifetime_end: { 5171 bool IsStart = (Intrinsic == Intrinsic::lifetime_start); 5172 // Stack coloring is not enabled in O0, discard region information. 5173 if (TM.getOptLevel() == CodeGenOpt::None) 5174 return 0; 5175 5176 SmallVector<Value *, 4> Allocas; 5177 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD); 5178 5179 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(), 5180 E = Allocas.end(); Object != E; ++Object) { 5181 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object); 5182 5183 // Could not find an Alloca. 5184 if (!LifetimeObject) 5185 continue; 5186 5187 int FI = FuncInfo.StaticAllocaMap[LifetimeObject]; 5188 5189 SDValue Ops[2]; 5190 Ops[0] = getRoot(); 5191 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true); 5192 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END); 5193 5194 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2); 5195 DAG.setRoot(Res); 5196 } 5197 return 0; 5198 } 5199 case Intrinsic::invariant_start: 5200 // Discard region information. 5201 setValue(&I, DAG.getUNDEF(TLI->getPointerTy())); 5202 return 0; 5203 case Intrinsic::invariant_end: 5204 // Discard region information. 5205 return 0; 5206 case Intrinsic::donothing: 5207 // ignore 5208 return 0; 5209 } 5210} 5211 5212void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5213 bool isTailCall, 5214 MachineBasicBlock *LandingPad) { 5215 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5216 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5217 Type *RetTy = FTy->getReturnType(); 5218 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5219 MCSymbol *BeginLabel = 0; 5220 5221 TargetLowering::ArgListTy Args; 5222 TargetLowering::ArgListEntry Entry; 5223 Args.reserve(CS.arg_size()); 5224 5225 // Check whether the function can return without sret-demotion. 5226 SmallVector<ISD::OutputArg, 4> Outs; 5227 const TargetLowering *TLI = TM.getTargetLowering(); 5228 GetReturnInfo(RetTy, CS.getAttributes(), Outs, *TLI); 5229 5230 bool CanLowerReturn = TLI->CanLowerReturn(CS.getCallingConv(), 5231 DAG.getMachineFunction(), 5232 FTy->isVarArg(), Outs, 5233 FTy->getContext()); 5234 5235 SDValue DemoteStackSlot; 5236 int DemoteStackIdx = -100; 5237 5238 if (!CanLowerReturn) { 5239 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize( 5240 FTy->getReturnType()); 5241 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment( 5242 FTy->getReturnType()); 5243 MachineFunction &MF = DAG.getMachineFunction(); 5244 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5245 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5246 5247 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI->getPointerTy()); 5248 Entry.Node = DemoteStackSlot; 5249 Entry.Ty = StackSlotPtrType; 5250 Entry.isSExt = false; 5251 Entry.isZExt = false; 5252 Entry.isInReg = false; 5253 Entry.isSRet = true; 5254 Entry.isNest = false; 5255 Entry.isByVal = false; 5256 Entry.isReturned = false; 5257 Entry.Alignment = Align; 5258 Args.push_back(Entry); 5259 RetTy = Type::getVoidTy(FTy->getContext()); 5260 } 5261 5262 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5263 i != e; ++i) { 5264 const Value *V = *i; 5265 5266 // Skip empty types 5267 if (V->getType()->isEmptyTy()) 5268 continue; 5269 5270 SDValue ArgNode = getValue(V); 5271 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5272 5273 unsigned attrInd = i - CS.arg_begin() + 1; 5274 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5275 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5276 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5277 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5278 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5279 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5280 Entry.isReturned = CS.paramHasAttr(attrInd, Attribute::Returned); 5281 Entry.Alignment = CS.getParamAlignment(attrInd); 5282 Args.push_back(Entry); 5283 } 5284 5285 if (LandingPad) { 5286 // Insert a label before the invoke call to mark the try range. This can be 5287 // used to detect deletion of the invoke via the MachineModuleInfo. 5288 BeginLabel = MMI.getContext().CreateTempSymbol(); 5289 5290 // For SjLj, keep track of which landing pads go with which invokes 5291 // so as to maintain the ordering of pads in the LSDA. 5292 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5293 if (CallSiteIndex) { 5294 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5295 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5296 5297 // Now that the call site is handled, stop tracking it. 5298 MMI.setCurrentCallSite(0); 5299 } 5300 5301 // Both PendingLoads and PendingExports must be flushed here; 5302 // this call might not return. 5303 (void)getRoot(); 5304 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel)); 5305 } 5306 5307 // Check if target-independent constraints permit a tail call here. 5308 // Target-dependent constraints are checked within TLI->LowerCallTo. 5309 if (isTailCall && !isInTailCallPosition(CS, *TLI)) 5310 isTailCall = false; 5311 5312 TargetLowering:: 5313 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, 5314 getCurSDLoc(), CS); 5315 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI); 5316 assert((isTailCall || Result.second.getNode()) && 5317 "Non-null chain expected with non-tail call!"); 5318 assert((Result.second.getNode() || !Result.first.getNode()) && 5319 "Null value expected with tail call!"); 5320 if (Result.first.getNode()) { 5321 setValue(CS.getInstruction(), Result.first); 5322 } else if (!CanLowerReturn && Result.second.getNode()) { 5323 // The instruction result is the result of loading from the 5324 // hidden sret parameter. 5325 SmallVector<EVT, 1> PVTs; 5326 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5327 5328 ComputeValueVTs(*TLI, PtrRetTy, PVTs); 5329 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5330 EVT PtrVT = PVTs[0]; 5331 5332 SmallVector<EVT, 4> RetTys; 5333 SmallVector<uint64_t, 4> Offsets; 5334 RetTy = FTy->getReturnType(); 5335 ComputeValueVTs(*TLI, RetTy, RetTys, &Offsets); 5336 5337 unsigned NumValues = RetTys.size(); 5338 SmallVector<SDValue, 4> Values(NumValues); 5339 SmallVector<SDValue, 4> Chains(NumValues); 5340 5341 for (unsigned i = 0; i < NumValues; ++i) { 5342 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, 5343 DemoteStackSlot, 5344 DAG.getConstant(Offsets[i], PtrVT)); 5345 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add, 5346 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5347 false, false, false, 1); 5348 Values[i] = L; 5349 Chains[i] = L.getValue(1); 5350 } 5351 5352 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 5353 MVT::Other, &Chains[0], NumValues); 5354 PendingLoads.push_back(Chain); 5355 5356 setValue(CS.getInstruction(), 5357 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 5358 DAG.getVTList(&RetTys[0], RetTys.size()), 5359 &Values[0], Values.size())); 5360 } 5361 5362 if (!Result.second.getNode()) { 5363 // As a special case, a null chain means that a tail call has been emitted and 5364 // the DAG root is already updated. 5365 HasTailCall = true; 5366 5367 // Since there's no actual continuation from this block, nothing can be 5368 // relying on us setting vregs for them. 5369 PendingExports.clear(); 5370 } else { 5371 DAG.setRoot(Result.second); 5372 } 5373 5374 if (LandingPad) { 5375 // Insert a label at the end of the invoke call to mark the try range. This 5376 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5377 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5378 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel)); 5379 5380 // Inform MachineModuleInfo of range. 5381 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5382 } 5383} 5384 5385/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5386/// value is equal or not-equal to zero. 5387static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5388 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5389 UI != E; ++UI) { 5390 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5391 if (IC->isEquality()) 5392 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5393 if (C->isNullValue()) 5394 continue; 5395 // Unknown instruction. 5396 return false; 5397 } 5398 return true; 5399} 5400 5401static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5402 Type *LoadTy, 5403 SelectionDAGBuilder &Builder) { 5404 5405 // Check to see if this load can be trivially constant folded, e.g. if the 5406 // input is from a string literal. 5407 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5408 // Cast pointer to the type we really want to load. 5409 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5410 PointerType::getUnqual(LoadTy)); 5411 5412 if (const Constant *LoadCst = 5413 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5414 Builder.TD)) 5415 return Builder.getValue(LoadCst); 5416 } 5417 5418 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5419 // still constant memory, the input chain can be the entry node. 5420 SDValue Root; 5421 bool ConstantMemory = false; 5422 5423 // Do not serialize (non-volatile) loads of constant memory with anything. 5424 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5425 Root = Builder.DAG.getEntryNode(); 5426 ConstantMemory = true; 5427 } else { 5428 // Do not serialize non-volatile loads against each other. 5429 Root = Builder.DAG.getRoot(); 5430 } 5431 5432 SDValue Ptr = Builder.getValue(PtrVal); 5433 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, 5434 Ptr, MachinePointerInfo(PtrVal), 5435 false /*volatile*/, 5436 false /*nontemporal*/, 5437 false /*isinvariant*/, 1 /* align=1 */); 5438 5439 if (!ConstantMemory) 5440 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5441 return LoadVal; 5442} 5443 5444 5445/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5446/// If so, return true and lower it, otherwise return false and it will be 5447/// lowered like a normal call. 5448bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5449 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5450 if (I.getNumArgOperands() != 3) 5451 return false; 5452 5453 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5454 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5455 !I.getArgOperand(2)->getType()->isIntegerTy() || 5456 !I.getType()->isIntegerTy()) 5457 return false; 5458 5459 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5460 5461 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5462 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5463 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5464 bool ActuallyDoIt = true; 5465 MVT LoadVT; 5466 Type *LoadTy; 5467 switch (Size->getZExtValue()) { 5468 default: 5469 LoadVT = MVT::Other; 5470 LoadTy = 0; 5471 ActuallyDoIt = false; 5472 break; 5473 case 2: 5474 LoadVT = MVT::i16; 5475 LoadTy = Type::getInt16Ty(Size->getContext()); 5476 break; 5477 case 4: 5478 LoadVT = MVT::i32; 5479 LoadTy = Type::getInt32Ty(Size->getContext()); 5480 break; 5481 case 8: 5482 LoadVT = MVT::i64; 5483 LoadTy = Type::getInt64Ty(Size->getContext()); 5484 break; 5485 /* 5486 case 16: 5487 LoadVT = MVT::v4i32; 5488 LoadTy = Type::getInt32Ty(Size->getContext()); 5489 LoadTy = VectorType::get(LoadTy, 4); 5490 break; 5491 */ 5492 } 5493 5494 // This turns into unaligned loads. We only do this if the target natively 5495 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5496 // we'll only produce a small number of byte loads. 5497 5498 // Require that we can find a legal MVT, and only do this if the target 5499 // supports unaligned loads of that type. Expanding into byte loads would 5500 // bloat the code. 5501 const TargetLowering *TLI = TM.getTargetLowering(); 5502 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5503 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5504 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5505 if (!TLI->isTypeLegal(LoadVT) ||!TLI->allowsUnalignedMemoryAccesses(LoadVT)) 5506 ActuallyDoIt = false; 5507 } 5508 5509 if (ActuallyDoIt) { 5510 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5511 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5512 5513 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal, 5514 ISD::SETNE); 5515 EVT CallVT = TLI->getValueType(I.getType(), true); 5516 setValue(&I, DAG.getZExtOrTrunc(Res, getCurSDLoc(), CallVT)); 5517 return true; 5518 } 5519 } 5520 5521 5522 return false; 5523} 5524 5525/// visitUnaryFloatCall - If a call instruction is a unary floating-point 5526/// operation (as expected), translate it to an SDNode with the specified opcode 5527/// and return true. 5528bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I, 5529 unsigned Opcode) { 5530 // Sanity check that it really is a unary floating-point call. 5531 if (I.getNumArgOperands() != 1 || 5532 !I.getArgOperand(0)->getType()->isFloatingPointTy() || 5533 I.getType() != I.getArgOperand(0)->getType() || 5534 !I.onlyReadsMemory()) 5535 return false; 5536 5537 SDValue Tmp = getValue(I.getArgOperand(0)); 5538 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp)); 5539 return true; 5540} 5541 5542void SelectionDAGBuilder::visitCall(const CallInst &I) { 5543 // Handle inline assembly differently. 5544 if (isa<InlineAsm>(I.getCalledValue())) { 5545 visitInlineAsm(&I); 5546 return; 5547 } 5548 5549 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5550 ComputeUsesVAFloatArgument(I, &MMI); 5551 5552 const char *RenameFn = 0; 5553 if (Function *F = I.getCalledFunction()) { 5554 if (F->isDeclaration()) { 5555 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5556 if (unsigned IID = II->getIntrinsicID(F)) { 5557 RenameFn = visitIntrinsicCall(I, IID); 5558 if (!RenameFn) 5559 return; 5560 } 5561 } 5562 if (unsigned IID = F->getIntrinsicID()) { 5563 RenameFn = visitIntrinsicCall(I, IID); 5564 if (!RenameFn) 5565 return; 5566 } 5567 } 5568 5569 // Check for well-known libc/libm calls. If the function is internal, it 5570 // can't be a library call. 5571 LibFunc::Func Func; 5572 if (!F->hasLocalLinkage() && F->hasName() && 5573 LibInfo->getLibFunc(F->getName(), Func) && 5574 LibInfo->hasOptimizedCodeGen(Func)) { 5575 switch (Func) { 5576 default: break; 5577 case LibFunc::copysign: 5578 case LibFunc::copysignf: 5579 case LibFunc::copysignl: 5580 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5581 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5582 I.getType() == I.getArgOperand(0)->getType() && 5583 I.getType() == I.getArgOperand(1)->getType() && 5584 I.onlyReadsMemory()) { 5585 SDValue LHS = getValue(I.getArgOperand(0)); 5586 SDValue RHS = getValue(I.getArgOperand(1)); 5587 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(), 5588 LHS.getValueType(), LHS, RHS)); 5589 return; 5590 } 5591 break; 5592 case LibFunc::fabs: 5593 case LibFunc::fabsf: 5594 case LibFunc::fabsl: 5595 if (visitUnaryFloatCall(I, ISD::FABS)) 5596 return; 5597 break; 5598 case LibFunc::sin: 5599 case LibFunc::sinf: 5600 case LibFunc::sinl: 5601 if (visitUnaryFloatCall(I, ISD::FSIN)) 5602 return; 5603 break; 5604 case LibFunc::cos: 5605 case LibFunc::cosf: 5606 case LibFunc::cosl: 5607 if (visitUnaryFloatCall(I, ISD::FCOS)) 5608 return; 5609 break; 5610 case LibFunc::sqrt: 5611 case LibFunc::sqrtf: 5612 case LibFunc::sqrtl: 5613 case LibFunc::sqrt_finite: 5614 case LibFunc::sqrtf_finite: 5615 case LibFunc::sqrtl_finite: 5616 if (visitUnaryFloatCall(I, ISD::FSQRT)) 5617 return; 5618 break; 5619 case LibFunc::floor: 5620 case LibFunc::floorf: 5621 case LibFunc::floorl: 5622 if (visitUnaryFloatCall(I, ISD::FFLOOR)) 5623 return; 5624 break; 5625 case LibFunc::nearbyint: 5626 case LibFunc::nearbyintf: 5627 case LibFunc::nearbyintl: 5628 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) 5629 return; 5630 break; 5631 case LibFunc::ceil: 5632 case LibFunc::ceilf: 5633 case LibFunc::ceill: 5634 if (visitUnaryFloatCall(I, ISD::FCEIL)) 5635 return; 5636 break; 5637 case LibFunc::rint: 5638 case LibFunc::rintf: 5639 case LibFunc::rintl: 5640 if (visitUnaryFloatCall(I, ISD::FRINT)) 5641 return; 5642 break; 5643 case LibFunc::trunc: 5644 case LibFunc::truncf: 5645 case LibFunc::truncl: 5646 if (visitUnaryFloatCall(I, ISD::FTRUNC)) 5647 return; 5648 break; 5649 case LibFunc::log2: 5650 case LibFunc::log2f: 5651 case LibFunc::log2l: 5652 if (visitUnaryFloatCall(I, ISD::FLOG2)) 5653 return; 5654 break; 5655 case LibFunc::exp2: 5656 case LibFunc::exp2f: 5657 case LibFunc::exp2l: 5658 if (visitUnaryFloatCall(I, ISD::FEXP2)) 5659 return; 5660 break; 5661 case LibFunc::memcmp: 5662 if (visitMemCmpCall(I)) 5663 return; 5664 break; 5665 } 5666 } 5667 } 5668 5669 SDValue Callee; 5670 if (!RenameFn) 5671 Callee = getValue(I.getCalledValue()); 5672 else 5673 Callee = DAG.getExternalSymbol(RenameFn, 5674 TM.getTargetLowering()->getPointerTy()); 5675 5676 // Check if we can potentially perform a tail call. More detailed checking is 5677 // be done within LowerCallTo, after more information about the call is known. 5678 LowerCallTo(&I, Callee, I.isTailCall()); 5679} 5680 5681namespace { 5682 5683/// AsmOperandInfo - This contains information for each constraint that we are 5684/// lowering. 5685class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5686public: 5687 /// CallOperand - If this is the result output operand or a clobber 5688 /// this is null, otherwise it is the incoming operand to the CallInst. 5689 /// This gets modified as the asm is processed. 5690 SDValue CallOperand; 5691 5692 /// AssignedRegs - If this is a register or register class operand, this 5693 /// contains the set of register corresponding to the operand. 5694 RegsForValue AssignedRegs; 5695 5696 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5697 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5698 } 5699 5700 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5701 /// corresponds to. If there is no Value* for this operand, it returns 5702 /// MVT::Other. 5703 EVT getCallOperandValEVT(LLVMContext &Context, 5704 const TargetLowering &TLI, 5705 const DataLayout *TD) const { 5706 if (CallOperandVal == 0) return MVT::Other; 5707 5708 if (isa<BasicBlock>(CallOperandVal)) 5709 return TLI.getPointerTy(); 5710 5711 llvm::Type *OpTy = CallOperandVal->getType(); 5712 5713 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5714 // If this is an indirect operand, the operand is a pointer to the 5715 // accessed type. 5716 if (isIndirect) { 5717 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5718 if (!PtrTy) 5719 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5720 OpTy = PtrTy->getElementType(); 5721 } 5722 5723 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5724 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5725 if (STy->getNumElements() == 1) 5726 OpTy = STy->getElementType(0); 5727 5728 // If OpTy is not a single value, it may be a struct/union that we 5729 // can tile with integers. 5730 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5731 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5732 switch (BitSize) { 5733 default: break; 5734 case 1: 5735 case 8: 5736 case 16: 5737 case 32: 5738 case 64: 5739 case 128: 5740 OpTy = IntegerType::get(Context, BitSize); 5741 break; 5742 } 5743 } 5744 5745 return TLI.getValueType(OpTy, true); 5746 } 5747}; 5748 5749typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5750 5751} // end anonymous namespace 5752 5753/// GetRegistersForValue - Assign registers (virtual or physical) for the 5754/// specified operand. We prefer to assign virtual registers, to allow the 5755/// register allocator to handle the assignment process. However, if the asm 5756/// uses features that we can't model on machineinstrs, we have SDISel do the 5757/// allocation. This produces generally horrible, but correct, code. 5758/// 5759/// OpInfo describes the operand. 5760/// 5761static void GetRegistersForValue(SelectionDAG &DAG, 5762 const TargetLowering &TLI, 5763 SDLoc DL, 5764 SDISelAsmOperandInfo &OpInfo) { 5765 LLVMContext &Context = *DAG.getContext(); 5766 5767 MachineFunction &MF = DAG.getMachineFunction(); 5768 SmallVector<unsigned, 4> Regs; 5769 5770 // If this is a constraint for a single physreg, or a constraint for a 5771 // register class, find it. 5772 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5773 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5774 OpInfo.ConstraintVT); 5775 5776 unsigned NumRegs = 1; 5777 if (OpInfo.ConstraintVT != MVT::Other) { 5778 // If this is a FP input in an integer register (or visa versa) insert a bit 5779 // cast of the input value. More generally, handle any case where the input 5780 // value disagrees with the register class we plan to stick this in. 5781 if (OpInfo.Type == InlineAsm::isInput && 5782 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5783 // Try to convert to the first EVT that the reg class contains. If the 5784 // types are identical size, use a bitcast to convert (e.g. two differing 5785 // vector types). 5786 MVT RegVT = *PhysReg.second->vt_begin(); 5787 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5788 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5789 RegVT, OpInfo.CallOperand); 5790 OpInfo.ConstraintVT = RegVT; 5791 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5792 // If the input is a FP value and we want it in FP registers, do a 5793 // bitcast to the corresponding integer type. This turns an f64 value 5794 // into i64, which can be passed with two i32 values on a 32-bit 5795 // machine. 5796 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); 5797 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5798 RegVT, OpInfo.CallOperand); 5799 OpInfo.ConstraintVT = RegVT; 5800 } 5801 } 5802 5803 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5804 } 5805 5806 MVT RegVT; 5807 EVT ValueVT = OpInfo.ConstraintVT; 5808 5809 // If this is a constraint for a specific physical register, like {r17}, 5810 // assign it now. 5811 if (unsigned AssignedReg = PhysReg.first) { 5812 const TargetRegisterClass *RC = PhysReg.second; 5813 if (OpInfo.ConstraintVT == MVT::Other) 5814 ValueVT = *RC->vt_begin(); 5815 5816 // Get the actual register value type. This is important, because the user 5817 // may have asked for (e.g.) the AX register in i32 type. We need to 5818 // remember that AX is actually i16 to get the right extension. 5819 RegVT = *RC->vt_begin(); 5820 5821 // This is a explicit reference to a physical register. 5822 Regs.push_back(AssignedReg); 5823 5824 // If this is an expanded reference, add the rest of the regs to Regs. 5825 if (NumRegs != 1) { 5826 TargetRegisterClass::iterator I = RC->begin(); 5827 for (; *I != AssignedReg; ++I) 5828 assert(I != RC->end() && "Didn't find reg!"); 5829 5830 // Already added the first reg. 5831 --NumRegs; ++I; 5832 for (; NumRegs; --NumRegs, ++I) { 5833 assert(I != RC->end() && "Ran out of registers to allocate!"); 5834 Regs.push_back(*I); 5835 } 5836 } 5837 5838 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5839 return; 5840 } 5841 5842 // Otherwise, if this was a reference to an LLVM register class, create vregs 5843 // for this reference. 5844 if (const TargetRegisterClass *RC = PhysReg.second) { 5845 RegVT = *RC->vt_begin(); 5846 if (OpInfo.ConstraintVT == MVT::Other) 5847 ValueVT = RegVT; 5848 5849 // Create the appropriate number of virtual registers. 5850 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5851 for (; NumRegs; --NumRegs) 5852 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5853 5854 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5855 return; 5856 } 5857 5858 // Otherwise, we couldn't allocate enough registers for this. 5859} 5860 5861/// visitInlineAsm - Handle a call to an InlineAsm object. 5862/// 5863void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5864 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5865 5866 /// ConstraintOperands - Information about all of the constraints. 5867 SDISelAsmOperandInfoVector ConstraintOperands; 5868 5869 const TargetLowering *TLI = TM.getTargetLowering(); 5870 TargetLowering::AsmOperandInfoVector 5871 TargetConstraints = TLI->ParseConstraints(CS); 5872 5873 bool hasMemory = false; 5874 5875 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5876 unsigned ResNo = 0; // ResNo - The result number of the next output. 5877 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5878 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5879 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5880 5881 MVT OpVT = MVT::Other; 5882 5883 // Compute the value type for each operand. 5884 switch (OpInfo.Type) { 5885 case InlineAsm::isOutput: 5886 // Indirect outputs just consume an argument. 5887 if (OpInfo.isIndirect) { 5888 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5889 break; 5890 } 5891 5892 // The return value of the call is this value. As such, there is no 5893 // corresponding argument. 5894 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5895 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5896 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo)); 5897 } else { 5898 assert(ResNo == 0 && "Asm only has one result!"); 5899 OpVT = TLI->getSimpleValueType(CS.getType()); 5900 } 5901 ++ResNo; 5902 break; 5903 case InlineAsm::isInput: 5904 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5905 break; 5906 case InlineAsm::isClobber: 5907 // Nothing to do. 5908 break; 5909 } 5910 5911 // If this is an input or an indirect output, process the call argument. 5912 // BasicBlocks are labels, currently appearing only in asm's. 5913 if (OpInfo.CallOperandVal) { 5914 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5915 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5916 } else { 5917 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5918 } 5919 5920 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, TD). 5921 getSimpleVT(); 5922 } 5923 5924 OpInfo.ConstraintVT = OpVT; 5925 5926 // Indirect operand accesses access memory. 5927 if (OpInfo.isIndirect) 5928 hasMemory = true; 5929 else { 5930 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5931 TargetLowering::ConstraintType 5932 CType = TLI->getConstraintType(OpInfo.Codes[j]); 5933 if (CType == TargetLowering::C_Memory) { 5934 hasMemory = true; 5935 break; 5936 } 5937 } 5938 } 5939 } 5940 5941 SDValue Chain, Flag; 5942 5943 // We won't need to flush pending loads if this asm doesn't touch 5944 // memory and is nonvolatile. 5945 if (hasMemory || IA->hasSideEffects()) 5946 Chain = getRoot(); 5947 else 5948 Chain = DAG.getRoot(); 5949 5950 // Second pass over the constraints: compute which constraint option to use 5951 // and assign registers to constraints that want a specific physreg. 5952 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5953 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5954 5955 // If this is an output operand with a matching input operand, look up the 5956 // matching input. If their types mismatch, e.g. one is an integer, the 5957 // other is floating point, or their sizes are different, flag it as an 5958 // error. 5959 if (OpInfo.hasMatchingInput()) { 5960 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5961 5962 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5963 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5964 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5965 OpInfo.ConstraintVT); 5966 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5967 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode, 5968 Input.ConstraintVT); 5969 if ((OpInfo.ConstraintVT.isInteger() != 5970 Input.ConstraintVT.isInteger()) || 5971 (MatchRC.second != InputRC.second)) { 5972 report_fatal_error("Unsupported asm: input constraint" 5973 " with a matching output constraint of" 5974 " incompatible type!"); 5975 } 5976 Input.ConstraintVT = OpInfo.ConstraintVT; 5977 } 5978 } 5979 5980 // Compute the constraint code and ConstraintType to use. 5981 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5982 5983 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5984 OpInfo.Type == InlineAsm::isClobber) 5985 continue; 5986 5987 // If this is a memory input, and if the operand is not indirect, do what we 5988 // need to to provide an address for the memory input. 5989 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5990 !OpInfo.isIndirect) { 5991 assert((OpInfo.isMultipleAlternative || 5992 (OpInfo.Type == InlineAsm::isInput)) && 5993 "Can only indirectify direct input operands!"); 5994 5995 // Memory operands really want the address of the value. If we don't have 5996 // an indirect input, put it in the constpool if we can, otherwise spill 5997 // it to a stack slot. 5998 // TODO: This isn't quite right. We need to handle these according to 5999 // the addressing mode that the constraint wants. Also, this may take 6000 // an additional register for the computation and we don't want that 6001 // either. 6002 6003 // If the operand is a float, integer, or vector constant, spill to a 6004 // constant pool entry to get its address. 6005 const Value *OpVal = OpInfo.CallOperandVal; 6006 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 6007 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 6008 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 6009 TLI->getPointerTy()); 6010 } else { 6011 // Otherwise, create a stack slot and emit a store to it before the 6012 // asm. 6013 Type *Ty = OpVal->getType(); 6014 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty); 6015 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty); 6016 MachineFunction &MF = DAG.getMachineFunction(); 6017 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6018 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy()); 6019 Chain = DAG.getStore(Chain, getCurSDLoc(), 6020 OpInfo.CallOperand, StackSlot, 6021 MachinePointerInfo::getFixedStack(SSFI), 6022 false, false, 0); 6023 OpInfo.CallOperand = StackSlot; 6024 } 6025 6026 // There is no longer a Value* corresponding to this operand. 6027 OpInfo.CallOperandVal = 0; 6028 6029 // It is now an indirect operand. 6030 OpInfo.isIndirect = true; 6031 } 6032 6033 // If this constraint is for a specific register, allocate it before 6034 // anything else. 6035 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6036 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo); 6037 } 6038 6039 // Second pass - Loop over all of the operands, assigning virtual or physregs 6040 // to register class operands. 6041 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6042 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6043 6044 // C_Register operands have already been allocated, Other/Memory don't need 6045 // to be. 6046 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6047 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo); 6048 } 6049 6050 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6051 std::vector<SDValue> AsmNodeOperands; 6052 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6053 AsmNodeOperands.push_back( 6054 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6055 TLI->getPointerTy())); 6056 6057 // If we have a !srcloc metadata node associated with it, we want to attach 6058 // this to the ultimately generated inline asm machineinstr. To do this, we 6059 // pass in the third operand as this (potentially null) inline asm MDNode. 6060 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6061 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6062 6063 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore 6064 // bits as operand 3. 6065 unsigned ExtraInfo = 0; 6066 if (IA->hasSideEffects()) 6067 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6068 if (IA->isAlignStack()) 6069 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6070 // Set the asm dialect. 6071 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect; 6072 6073 // Determine if this InlineAsm MayLoad or MayStore based on the constraints. 6074 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 6075 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; 6076 6077 // Compute the constraint code and ConstraintType to use. 6078 TLI->ComputeConstraintToUse(OpInfo, SDValue()); 6079 6080 // Ideally, we would only check against memory constraints. However, the 6081 // meaning of an other constraint can be target-specific and we can't easily 6082 // reason about it. Therefore, be conservative and set MayLoad/MayStore 6083 // for other constriants as well. 6084 if (OpInfo.ConstraintType == TargetLowering::C_Memory || 6085 OpInfo.ConstraintType == TargetLowering::C_Other) { 6086 if (OpInfo.Type == InlineAsm::isInput) 6087 ExtraInfo |= InlineAsm::Extra_MayLoad; 6088 else if (OpInfo.Type == InlineAsm::isOutput) 6089 ExtraInfo |= InlineAsm::Extra_MayStore; 6090 else if (OpInfo.Type == InlineAsm::isClobber) 6091 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore); 6092 } 6093 } 6094 6095 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6096 TLI->getPointerTy())); 6097 6098 // Loop over all of the inputs, copying the operand values into the 6099 // appropriate registers and processing the output regs. 6100 RegsForValue RetValRegs; 6101 6102 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6103 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6104 6105 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6106 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6107 6108 switch (OpInfo.Type) { 6109 case InlineAsm::isOutput: { 6110 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6111 OpInfo.ConstraintType != TargetLowering::C_Register) { 6112 // Memory output, or 'other' output (e.g. 'X' constraint). 6113 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6114 6115 // Add information to the INLINEASM node to know about this output. 6116 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6117 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6118 TLI->getPointerTy())); 6119 AsmNodeOperands.push_back(OpInfo.CallOperand); 6120 break; 6121 } 6122 6123 // Otherwise, this is a register or register class output. 6124 6125 // Copy the output from the appropriate register. Find a register that 6126 // we can use. 6127 if (OpInfo.AssignedRegs.Regs.empty()) { 6128 LLVMContext &Ctx = *DAG.getContext(); 6129 Ctx.emitError(CS.getInstruction(), 6130 "couldn't allocate output register for constraint '" + 6131 Twine(OpInfo.ConstraintCode) + "'"); 6132 return; 6133 } 6134 6135 // If this is an indirect operand, store through the pointer after the 6136 // asm. 6137 if (OpInfo.isIndirect) { 6138 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6139 OpInfo.CallOperandVal)); 6140 } else { 6141 // This is the result value of the call. 6142 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6143 // Concatenate this output onto the outputs list. 6144 RetValRegs.append(OpInfo.AssignedRegs); 6145 } 6146 6147 // Add information to the INLINEASM node to know that this register is 6148 // set. 6149 OpInfo.AssignedRegs 6150 .AddInlineAsmOperands(OpInfo.isEarlyClobber 6151 ? InlineAsm::Kind_RegDefEarlyClobber 6152 : InlineAsm::Kind_RegDef, 6153 false, 0, DAG, AsmNodeOperands); 6154 break; 6155 } 6156 case InlineAsm::isInput: { 6157 SDValue InOperandVal = OpInfo.CallOperand; 6158 6159 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6160 // If this is required to match an output register we have already set, 6161 // just use its register. 6162 unsigned OperandNo = OpInfo.getMatchedOperand(); 6163 6164 // Scan until we find the definition we already emitted of this operand. 6165 // When we find it, create a RegsForValue operand. 6166 unsigned CurOp = InlineAsm::Op_FirstOperand; 6167 for (; OperandNo; --OperandNo) { 6168 // Advance to the next operand. 6169 unsigned OpFlag = 6170 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6171 assert((InlineAsm::isRegDefKind(OpFlag) || 6172 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6173 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6174 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6175 } 6176 6177 unsigned OpFlag = 6178 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6179 if (InlineAsm::isRegDefKind(OpFlag) || 6180 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6181 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6182 if (OpInfo.isIndirect) { 6183 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6184 LLVMContext &Ctx = *DAG.getContext(); 6185 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6186 " don't know how to handle tied " 6187 "indirect register inputs"); 6188 return; 6189 } 6190 6191 RegsForValue MatchedRegs; 6192 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6193 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); 6194 MatchedRegs.RegVTs.push_back(RegVT); 6195 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6196 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6197 i != e; ++i) { 6198 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT)) 6199 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC)); 6200 else { 6201 LLVMContext &Ctx = *DAG.getContext(); 6202 Ctx.emitError(CS.getInstruction(), 6203 "inline asm error: This value" 6204 " type register class is not natively supported!"); 6205 return; 6206 } 6207 } 6208 // Use the produced MatchedRegs object to 6209 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(), 6210 Chain, &Flag, CS.getInstruction()); 6211 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6212 true, OpInfo.getMatchedOperand(), 6213 DAG, AsmNodeOperands); 6214 break; 6215 } 6216 6217 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6218 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6219 "Unexpected number of operands"); 6220 // Add information to the INLINEASM node to know about this input. 6221 // See InlineAsm.h isUseOperandTiedToDef. 6222 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6223 OpInfo.getMatchedOperand()); 6224 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6225 TLI->getPointerTy())); 6226 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6227 break; 6228 } 6229 6230 // Treat indirect 'X' constraint as memory. 6231 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6232 OpInfo.isIndirect) 6233 OpInfo.ConstraintType = TargetLowering::C_Memory; 6234 6235 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6236 std::vector<SDValue> Ops; 6237 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6238 Ops, DAG); 6239 if (Ops.empty()) { 6240 LLVMContext &Ctx = *DAG.getContext(); 6241 Ctx.emitError(CS.getInstruction(), 6242 "invalid operand for inline asm constraint '" + 6243 Twine(OpInfo.ConstraintCode) + "'"); 6244 return; 6245 } 6246 6247 // Add information to the INLINEASM node to know about this input. 6248 unsigned ResOpType = 6249 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6250 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6251 TLI->getPointerTy())); 6252 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6253 break; 6254 } 6255 6256 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6257 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6258 assert(InOperandVal.getValueType() == TLI->getPointerTy() && 6259 "Memory operands expect pointer values"); 6260 6261 // Add information to the INLINEASM node to know about this input. 6262 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6263 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6264 TLI->getPointerTy())); 6265 AsmNodeOperands.push_back(InOperandVal); 6266 break; 6267 } 6268 6269 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6270 OpInfo.ConstraintType == TargetLowering::C_Register) && 6271 "Unknown constraint type!"); 6272 6273 // TODO: Support this. 6274 if (OpInfo.isIndirect) { 6275 LLVMContext &Ctx = *DAG.getContext(); 6276 Ctx.emitError(CS.getInstruction(), 6277 "Don't know how to handle indirect register inputs yet " 6278 "for constraint '" + 6279 Twine(OpInfo.ConstraintCode) + "'"); 6280 return; 6281 } 6282 6283 // Copy the input into the appropriate registers. 6284 if (OpInfo.AssignedRegs.Regs.empty()) { 6285 LLVMContext &Ctx = *DAG.getContext(); 6286 Ctx.emitError(CS.getInstruction(), 6287 "couldn't allocate input reg for constraint '" + 6288 Twine(OpInfo.ConstraintCode) + "'"); 6289 return; 6290 } 6291 6292 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(), 6293 Chain, &Flag, CS.getInstruction()); 6294 6295 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6296 DAG, AsmNodeOperands); 6297 break; 6298 } 6299 case InlineAsm::isClobber: { 6300 // Add the clobbered value to the operand list, so that the register 6301 // allocator is aware that the physreg got clobbered. 6302 if (!OpInfo.AssignedRegs.Regs.empty()) 6303 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6304 false, 0, DAG, 6305 AsmNodeOperands); 6306 break; 6307 } 6308 } 6309 } 6310 6311 // Finish up input operands. Set the input chain and add the flag last. 6312 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6313 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6314 6315 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(), 6316 DAG.getVTList(MVT::Other, MVT::Glue), 6317 &AsmNodeOperands[0], AsmNodeOperands.size()); 6318 Flag = Chain.getValue(1); 6319 6320 // If this asm returns a register value, copy the result from that register 6321 // and set it as the value of the call. 6322 if (!RetValRegs.Regs.empty()) { 6323 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), 6324 Chain, &Flag, CS.getInstruction()); 6325 6326 // FIXME: Why don't we do this for inline asms with MRVs? 6327 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6328 EVT ResultType = TLI->getValueType(CS.getType()); 6329 6330 // If any of the results of the inline asm is a vector, it may have the 6331 // wrong width/num elts. This can happen for register classes that can 6332 // contain multiple different value types. The preg or vreg allocated may 6333 // not have the same VT as was expected. Convert it to the right type 6334 // with bit_convert. 6335 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6336 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(), 6337 ResultType, Val); 6338 6339 } else if (ResultType != Val.getValueType() && 6340 ResultType.isInteger() && Val.getValueType().isInteger()) { 6341 // If a result value was tied to an input value, the computed result may 6342 // have a wider width than the expected result. Extract the relevant 6343 // portion. 6344 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val); 6345 } 6346 6347 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6348 } 6349 6350 setValue(CS.getInstruction(), Val); 6351 // Don't need to use this as a chain in this case. 6352 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6353 return; 6354 } 6355 6356 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6357 6358 // Process indirect outputs, first output all of the flagged copies out of 6359 // physregs. 6360 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6361 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6362 const Value *Ptr = IndirectStoresToEmit[i].second; 6363 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), 6364 Chain, &Flag, IA); 6365 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6366 } 6367 6368 // Emit the non-flagged stores from the physregs. 6369 SmallVector<SDValue, 8> OutChains; 6370 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6371 SDValue Val = DAG.getStore(Chain, getCurSDLoc(), 6372 StoresToEmit[i].first, 6373 getValue(StoresToEmit[i].second), 6374 MachinePointerInfo(StoresToEmit[i].second), 6375 false, false, 0); 6376 OutChains.push_back(Val); 6377 } 6378 6379 if (!OutChains.empty()) 6380 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, 6381 &OutChains[0], OutChains.size()); 6382 6383 DAG.setRoot(Chain); 6384} 6385 6386void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6387 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(), 6388 MVT::Other, getRoot(), 6389 getValue(I.getArgOperand(0)), 6390 DAG.getSrcValue(I.getArgOperand(0)))); 6391} 6392 6393void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6394 const TargetLowering *TLI = TM.getTargetLowering(); 6395 const DataLayout &TD = *TLI->getDataLayout(); 6396 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(), 6397 getRoot(), getValue(I.getOperand(0)), 6398 DAG.getSrcValue(I.getOperand(0)), 6399 TD.getABITypeAlignment(I.getType())); 6400 setValue(&I, V); 6401 DAG.setRoot(V.getValue(1)); 6402} 6403 6404void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6405 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(), 6406 MVT::Other, getRoot(), 6407 getValue(I.getArgOperand(0)), 6408 DAG.getSrcValue(I.getArgOperand(0)))); 6409} 6410 6411void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6412 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(), 6413 MVT::Other, getRoot(), 6414 getValue(I.getArgOperand(0)), 6415 getValue(I.getArgOperand(1)), 6416 DAG.getSrcValue(I.getArgOperand(0)), 6417 DAG.getSrcValue(I.getArgOperand(1)))); 6418} 6419 6420/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6421/// implementation, which just calls LowerCall. 6422/// FIXME: When all targets are 6423/// migrated to using LowerCall, this hook should be integrated into SDISel. 6424std::pair<SDValue, SDValue> 6425TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { 6426 // Handle the incoming return values from the call. 6427 CLI.Ins.clear(); 6428 SmallVector<EVT, 4> RetTys; 6429 ComputeValueVTs(*this, CLI.RetTy, RetTys); 6430 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6431 EVT VT = RetTys[I]; 6432 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6433 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6434 for (unsigned i = 0; i != NumRegs; ++i) { 6435 ISD::InputArg MyFlags; 6436 MyFlags.VT = RegisterVT; 6437 MyFlags.Used = CLI.IsReturnValueUsed; 6438 if (CLI.RetSExt) 6439 MyFlags.Flags.setSExt(); 6440 if (CLI.RetZExt) 6441 MyFlags.Flags.setZExt(); 6442 if (CLI.IsInReg) 6443 MyFlags.Flags.setInReg(); 6444 CLI.Ins.push_back(MyFlags); 6445 } 6446 } 6447 6448 // Handle all of the outgoing arguments. 6449 CLI.Outs.clear(); 6450 CLI.OutVals.clear(); 6451 ArgListTy &Args = CLI.Args; 6452 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6453 SmallVector<EVT, 4> ValueVTs; 6454 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6455 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6456 Value != NumValues; ++Value) { 6457 EVT VT = ValueVTs[Value]; 6458 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); 6459 SDValue Op = SDValue(Args[i].Node.getNode(), 6460 Args[i].Node.getResNo() + Value); 6461 ISD::ArgFlagsTy Flags; 6462 unsigned OriginalAlignment = 6463 getDataLayout()->getABITypeAlignment(ArgTy); 6464 6465 if (Args[i].isZExt) 6466 Flags.setZExt(); 6467 if (Args[i].isSExt) 6468 Flags.setSExt(); 6469 if (Args[i].isInReg) 6470 Flags.setInReg(); 6471 if (Args[i].isSRet) 6472 Flags.setSRet(); 6473 if (Args[i].isByVal) { 6474 Flags.setByVal(); 6475 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6476 Type *ElementTy = Ty->getElementType(); 6477 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy)); 6478 // For ByVal, alignment should come from FE. BE will guess if this 6479 // info is not there but there are cases it cannot get right. 6480 unsigned FrameAlign; 6481 if (Args[i].Alignment) 6482 FrameAlign = Args[i].Alignment; 6483 else 6484 FrameAlign = getByValTypeAlignment(ElementTy); 6485 Flags.setByValAlign(FrameAlign); 6486 } 6487 if (Args[i].isNest) 6488 Flags.setNest(); 6489 Flags.setOrigAlign(OriginalAlignment); 6490 6491 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); 6492 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT); 6493 SmallVector<SDValue, 4> Parts(NumParts); 6494 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6495 6496 if (Args[i].isSExt) 6497 ExtendKind = ISD::SIGN_EXTEND; 6498 else if (Args[i].isZExt) 6499 ExtendKind = ISD::ZERO_EXTEND; 6500 6501 // Conservatively only handle 'returned' on non-vectors for now 6502 if (Args[i].isReturned && !Op.getValueType().isVector()) { 6503 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && 6504 "unexpected use of 'returned'"); 6505 // Before passing 'returned' to the target lowering code, ensure that 6506 // either the register MVT and the actual EVT are the same size or that 6507 // the return value and argument are extended in the same way; in these 6508 // cases it's safe to pass the argument register value unchanged as the 6509 // return register value (although it's at the target's option whether 6510 // to do so) 6511 // TODO: allow code generation to take advantage of partially preserved 6512 // registers rather than clobbering the entire register when the 6513 // parameter extension method is not compatible with the return 6514 // extension method 6515 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) || 6516 (ExtendKind != ISD::ANY_EXTEND && 6517 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt)) 6518 Flags.setReturned(); 6519 } 6520 6521 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, 6522 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind); 6523 6524 for (unsigned j = 0; j != NumParts; ++j) { 6525 // if it isn't first piece, alignment must be 1 6526 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6527 i < CLI.NumFixedArgs, 6528 i, j*Parts[j].getValueType().getStoreSize()); 6529 if (NumParts > 1 && j == 0) 6530 MyFlags.Flags.setSplit(); 6531 else if (j != 0) 6532 MyFlags.Flags.setOrigAlign(1); 6533 6534 CLI.Outs.push_back(MyFlags); 6535 CLI.OutVals.push_back(Parts[j]); 6536 } 6537 } 6538 } 6539 6540 SmallVector<SDValue, 4> InVals; 6541 CLI.Chain = LowerCall(CLI, InVals); 6542 6543 // Verify that the target's LowerCall behaved as expected. 6544 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && 6545 "LowerCall didn't return a valid chain!"); 6546 assert((!CLI.IsTailCall || InVals.empty()) && 6547 "LowerCall emitted a return value for a tail call!"); 6548 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 6549 "LowerCall didn't emit the correct number of values!"); 6550 6551 // For a tail call, the return value is merely live-out and there aren't 6552 // any nodes in the DAG representing it. Return a special value to 6553 // indicate that a tail call has been emitted and no more Instructions 6554 // should be processed in the current block. 6555 if (CLI.IsTailCall) { 6556 CLI.DAG.setRoot(CLI.Chain); 6557 return std::make_pair(SDValue(), SDValue()); 6558 } 6559 6560 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 6561 assert(InVals[i].getNode() && 6562 "LowerCall emitted a null value!"); 6563 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 6564 "LowerCall emitted a value with the wrong type!"); 6565 }); 6566 6567 // Collect the legal value parts into potentially illegal values 6568 // that correspond to the original function's return values. 6569 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6570 if (CLI.RetSExt) 6571 AssertOp = ISD::AssertSext; 6572 else if (CLI.RetZExt) 6573 AssertOp = ISD::AssertZext; 6574 SmallVector<SDValue, 4> ReturnValues; 6575 unsigned CurReg = 0; 6576 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6577 EVT VT = RetTys[I]; 6578 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6579 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6580 6581 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], 6582 NumRegs, RegisterVT, VT, NULL, 6583 AssertOp)); 6584 CurReg += NumRegs; 6585 } 6586 6587 // For a function returning void, there is no return value. We can't create 6588 // such a node, so we just return a null return value in that case. In 6589 // that case, nothing will actually look at the value. 6590 if (ReturnValues.empty()) 6591 return std::make_pair(SDValue(), CLI.Chain); 6592 6593 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, 6594 CLI.DAG.getVTList(&RetTys[0], RetTys.size()), 6595 &ReturnValues[0], ReturnValues.size()); 6596 return std::make_pair(Res, CLI.Chain); 6597} 6598 6599void TargetLowering::LowerOperationWrapper(SDNode *N, 6600 SmallVectorImpl<SDValue> &Results, 6601 SelectionDAG &DAG) const { 6602 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6603 if (Res.getNode()) 6604 Results.push_back(Res); 6605} 6606 6607SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6608 llvm_unreachable("LowerOperation not implemented for this target!"); 6609} 6610 6611void 6612SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6613 SDValue Op = getNonRegisterValue(V); 6614 assert((Op.getOpcode() != ISD::CopyFromReg || 6615 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6616 "Copy from a reg to the same reg!"); 6617 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6618 6619 const TargetLowering *TLI = TM.getTargetLowering(); 6620 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType()); 6621 SDValue Chain = DAG.getEntryNode(); 6622 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, 0, V); 6623 PendingExports.push_back(Chain); 6624} 6625 6626#include "llvm/CodeGen/SelectionDAGISel.h" 6627 6628/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6629/// entry block, return true. This includes arguments used by switches, since 6630/// the switch may expand into multiple basic blocks. 6631static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6632 // With FastISel active, we may be splitting blocks, so force creation 6633 // of virtual registers for all non-dead arguments. 6634 if (FastISel) 6635 return A->use_empty(); 6636 6637 const BasicBlock *Entry = A->getParent()->begin(); 6638 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6639 UI != E; ++UI) { 6640 const User *U = *UI; 6641 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6642 return false; // Use not in entry block. 6643 } 6644 return true; 6645} 6646 6647void SelectionDAGISel::LowerArguments(const Function &F) { 6648 SelectionDAG &DAG = SDB->DAG; 6649 SDLoc dl = SDB->getCurSDLoc(); 6650 const TargetLowering *TLI = getTargetLowering(); 6651 const DataLayout *TD = TLI->getDataLayout(); 6652 SmallVector<ISD::InputArg, 16> Ins; 6653 6654 if (!FuncInfo->CanLowerReturn) { 6655 // Put in an sret pointer parameter before all the other parameters. 6656 SmallVector<EVT, 1> ValueVTs; 6657 ComputeValueVTs(*getTargetLowering(), 6658 PointerType::getUnqual(F.getReturnType()), ValueVTs); 6659 6660 // NOTE: Assuming that a pointer will never break down to more than one VT 6661 // or one register. 6662 ISD::ArgFlagsTy Flags; 6663 Flags.setSRet(); 6664 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]); 6665 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0); 6666 Ins.push_back(RetArg); 6667 } 6668 6669 // Set up the incoming argument description vector. 6670 unsigned Idx = 1; 6671 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6672 I != E; ++I, ++Idx) { 6673 SmallVector<EVT, 4> ValueVTs; 6674 ComputeValueVTs(*TLI, I->getType(), ValueVTs); 6675 bool isArgValueUsed = !I->use_empty(); 6676 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6677 Value != NumValues; ++Value) { 6678 EVT VT = ValueVTs[Value]; 6679 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6680 ISD::ArgFlagsTy Flags; 6681 unsigned OriginalAlignment = 6682 TD->getABITypeAlignment(ArgTy); 6683 6684 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt)) 6685 Flags.setZExt(); 6686 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt)) 6687 Flags.setSExt(); 6688 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg)) 6689 Flags.setInReg(); 6690 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet)) 6691 Flags.setSRet(); 6692 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal)) { 6693 Flags.setByVal(); 6694 PointerType *Ty = cast<PointerType>(I->getType()); 6695 Type *ElementTy = Ty->getElementType(); 6696 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6697 // For ByVal, alignment should be passed from FE. BE will guess if 6698 // this info is not there but there are cases it cannot get right. 6699 unsigned FrameAlign; 6700 if (F.getParamAlignment(Idx)) 6701 FrameAlign = F.getParamAlignment(Idx); 6702 else 6703 FrameAlign = TLI->getByValTypeAlignment(ElementTy); 6704 Flags.setByValAlign(FrameAlign); 6705 } 6706 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest)) 6707 Flags.setNest(); 6708 Flags.setOrigAlign(OriginalAlignment); 6709 6710 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT); 6711 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT); 6712 for (unsigned i = 0; i != NumRegs; ++i) { 6713 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed, 6714 Idx-1, i*RegisterVT.getStoreSize()); 6715 if (NumRegs > 1 && i == 0) 6716 MyFlags.Flags.setSplit(); 6717 // if it isn't first piece, alignment must be 1 6718 else if (i > 0) 6719 MyFlags.Flags.setOrigAlign(1); 6720 Ins.push_back(MyFlags); 6721 } 6722 } 6723 } 6724 6725 // Call the target to set up the argument values. 6726 SmallVector<SDValue, 8> InVals; 6727 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6728 F.isVarArg(), Ins, 6729 dl, DAG, InVals); 6730 6731 // Verify that the target's LowerFormalArguments behaved as expected. 6732 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6733 "LowerFormalArguments didn't return a valid chain!"); 6734 assert(InVals.size() == Ins.size() && 6735 "LowerFormalArguments didn't emit the correct number of values!"); 6736 DEBUG({ 6737 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6738 assert(InVals[i].getNode() && 6739 "LowerFormalArguments emitted a null value!"); 6740 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6741 "LowerFormalArguments emitted a value with the wrong type!"); 6742 } 6743 }); 6744 6745 // Update the DAG with the new chain value resulting from argument lowering. 6746 DAG.setRoot(NewRoot); 6747 6748 // Set up the argument values. 6749 unsigned i = 0; 6750 Idx = 1; 6751 if (!FuncInfo->CanLowerReturn) { 6752 // Create a virtual register for the sret pointer, and put in a copy 6753 // from the sret argument into it. 6754 SmallVector<EVT, 1> ValueVTs; 6755 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6756 MVT VT = ValueVTs[0].getSimpleVT(); 6757 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); 6758 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6759 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6760 RegVT, VT, NULL, AssertOp); 6761 6762 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6763 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6764 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); 6765 FuncInfo->DemoteRegister = SRetReg; 6766 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), 6767 SRetReg, ArgValue); 6768 DAG.setRoot(NewRoot); 6769 6770 // i indexes lowered arguments. Bump it past the hidden sret argument. 6771 // Idx indexes LLVM arguments. Don't touch it. 6772 ++i; 6773 } 6774 6775 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6776 ++I, ++Idx) { 6777 SmallVector<SDValue, 4> ArgValues; 6778 SmallVector<EVT, 4> ValueVTs; 6779 ComputeValueVTs(*TLI, I->getType(), ValueVTs); 6780 unsigned NumValues = ValueVTs.size(); 6781 6782 // If this argument is unused then remember its value. It is used to generate 6783 // debugging information. 6784 if (I->use_empty() && NumValues) { 6785 SDB->setUnusedArgValue(I, InVals[i]); 6786 6787 // Also remember any frame index for use in FastISel. 6788 if (FrameIndexSDNode *FI = 6789 dyn_cast<FrameIndexSDNode>(InVals[i].getNode())) 6790 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6791 } 6792 6793 for (unsigned Val = 0; Val != NumValues; ++Val) { 6794 EVT VT = ValueVTs[Val]; 6795 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT); 6796 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT); 6797 6798 if (!I->use_empty()) { 6799 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6800 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt)) 6801 AssertOp = ISD::AssertSext; 6802 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt)) 6803 AssertOp = ISD::AssertZext; 6804 6805 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6806 NumParts, PartVT, VT, 6807 NULL, AssertOp)); 6808 } 6809 6810 i += NumParts; 6811 } 6812 6813 // We don't need to do anything else for unused arguments. 6814 if (ArgValues.empty()) 6815 continue; 6816 6817 // Note down frame index. 6818 if (FrameIndexSDNode *FI = 6819 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6820 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6821 6822 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6823 SDB->getCurSDLoc()); 6824 6825 SDB->setValue(I, Res); 6826 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6827 if (LoadSDNode *LNode = 6828 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6829 if (FrameIndexSDNode *FI = 6830 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6831 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6832 } 6833 6834 // If this argument is live outside of the entry block, insert a copy from 6835 // wherever we got it to the vreg that other BB's will reference it as. 6836 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6837 // If we can, though, try to skip creating an unnecessary vreg. 6838 // FIXME: This isn't very clean... it would be nice to make this more 6839 // general. It's also subtly incompatible with the hacks FastISel 6840 // uses with vregs. 6841 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6842 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6843 FuncInfo->ValueMap[I] = Reg; 6844 continue; 6845 } 6846 } 6847 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6848 FuncInfo->InitializeRegForValue(I); 6849 SDB->CopyToExportRegsIfNeeded(I); 6850 } 6851 } 6852 6853 assert(i == InVals.size() && "Argument register count mismatch!"); 6854 6855 // Finally, if the target has anything special to do, allow it to do so. 6856 // FIXME: this should insert code into the DAG! 6857 EmitFunctionEntryCode(); 6858} 6859 6860/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6861/// ensure constants are generated when needed. Remember the virtual registers 6862/// that need to be added to the Machine PHI nodes as input. We cannot just 6863/// directly add them, because expansion might result in multiple MBB's for one 6864/// BB. As such, the start of the BB might correspond to a different MBB than 6865/// the end. 6866/// 6867void 6868SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6869 const TerminatorInst *TI = LLVMBB->getTerminator(); 6870 6871 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6872 6873 // Check successor nodes' PHI nodes that expect a constant to be available 6874 // from this block. 6875 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6876 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6877 if (!isa<PHINode>(SuccBB->begin())) continue; 6878 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6879 6880 // If this terminator has multiple identical successors (common for 6881 // switches), only handle each succ once. 6882 if (!SuccsHandled.insert(SuccMBB)) continue; 6883 6884 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6885 6886 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6887 // nodes and Machine PHI nodes, but the incoming operands have not been 6888 // emitted yet. 6889 for (BasicBlock::const_iterator I = SuccBB->begin(); 6890 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6891 // Ignore dead phi's. 6892 if (PN->use_empty()) continue; 6893 6894 // Skip empty types 6895 if (PN->getType()->isEmptyTy()) 6896 continue; 6897 6898 unsigned Reg; 6899 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6900 6901 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6902 unsigned &RegOut = ConstantsOut[C]; 6903 if (RegOut == 0) { 6904 RegOut = FuncInfo.CreateRegs(C->getType()); 6905 CopyValueToVirtualRegister(C, RegOut); 6906 } 6907 Reg = RegOut; 6908 } else { 6909 DenseMap<const Value *, unsigned>::iterator I = 6910 FuncInfo.ValueMap.find(PHIOp); 6911 if (I != FuncInfo.ValueMap.end()) 6912 Reg = I->second; 6913 else { 6914 assert(isa<AllocaInst>(PHIOp) && 6915 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6916 "Didn't codegen value into a register!??"); 6917 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6918 CopyValueToVirtualRegister(PHIOp, Reg); 6919 } 6920 } 6921 6922 // Remember that this register needs to added to the machine PHI node as 6923 // the input for this MBB. 6924 SmallVector<EVT, 4> ValueVTs; 6925 const TargetLowering *TLI = TM.getTargetLowering(); 6926 ComputeValueVTs(*TLI, PN->getType(), ValueVTs); 6927 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6928 EVT VT = ValueVTs[vti]; 6929 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT); 6930 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6931 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6932 Reg += NumRegisters; 6933 } 6934 } 6935 } 6936 6937 ConstantsOut.clear(); 6938} 6939