SelectionDAGBuilder.cpp revision 23de31b13bfde8dfe3d5c21322f5e08608725521
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameLowering.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetIntrinsicInfo.h" 50#include "llvm/Target/TargetLibraryInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getTargetConstant(1, TLI.getPointerTy())); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209} 210 211/// getCopyFromParts - Create a value that contains the specified legal parts 212/// combined into the value they represent. If the parts combine to a type 213/// larger then ValueVT then AssertOp can be used to specify whether the extra 214/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 215/// (ISD::AssertSext). 216static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 217 const SDValue *Parts, unsigned NumParts, 218 EVT PartVT, EVT ValueVT) { 219 assert(ValueVT.isVector() && "Not a vector value"); 220 assert(NumParts > 0 && "No parts to assemble!"); 221 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 222 SDValue Val = Parts[0]; 223 224 // Handle a multi-element vector. 225 if (NumParts > 1) { 226 EVT IntermediateVT, RegisterVT; 227 unsigned NumIntermediates; 228 unsigned NumRegs = 229 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 230 NumIntermediates, RegisterVT); 231 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 232 NumParts = NumRegs; // Silence a compiler warning. 233 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 234 assert(RegisterVT == Parts[0].getValueType() && 235 "Part type doesn't match part!"); 236 237 // Assemble the parts into intermediate operands. 238 SmallVector<SDValue, 8> Ops(NumIntermediates); 239 if (NumIntermediates == NumParts) { 240 // If the register was not expanded, truncate or copy the value, 241 // as appropriate. 242 for (unsigned i = 0; i != NumParts; ++i) 243 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 244 PartVT, IntermediateVT); 245 } else if (NumParts > 0) { 246 // If the intermediate type was expanded, build the intermediate 247 // operands from the parts. 248 assert(NumParts % NumIntermediates == 0 && 249 "Must expand into a divisible number of parts!"); 250 unsigned Factor = NumParts / NumIntermediates; 251 for (unsigned i = 0; i != NumIntermediates; ++i) 252 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 253 PartVT, IntermediateVT); 254 } 255 256 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 257 // intermediate operands. 258 Val = DAG.getNode(IntermediateVT.isVector() ? 259 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 260 ValueVT, &Ops[0], NumIntermediates); 261 } 262 263 // There is now one part, held in Val. Correct it to match ValueVT. 264 PartVT = Val.getValueType(); 265 266 if (PartVT == ValueVT) 267 return Val; 268 269 if (PartVT.isVector()) { 270 // If the element type of the source/dest vectors are the same, but the 271 // parts vector has more elements than the value vector, then we have a 272 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 273 // elements we want. 274 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 275 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 276 "Cannot narrow, it would be a lossy transformation"); 277 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 278 DAG.getIntPtrConstant(0)); 279 } 280 281 // Vector/Vector bitcast. 282 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 283 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 284 285 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 286 "Cannot handle this kind of promotion"); 287 // Promoted vector extract 288 bool Smaller = ValueVT.bitsLE(PartVT); 289 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 290 DL, ValueVT, Val); 291 292 } 293 294 // Trivial bitcast if the types are the same size and the destination 295 // vector type is legal. 296 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 297 TLI.isTypeLegal(ValueVT)) 298 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 299 300 // Handle cases such as i8 -> <1 x i1> 301 assert(ValueVT.getVectorNumElements() == 1 && 302 "Only trivial scalar-to-vector conversions should get here!"); 303 304 if (ValueVT.getVectorNumElements() == 1 && 305 ValueVT.getVectorElementType() != PartVT) { 306 bool Smaller = ValueVT.bitsLE(PartVT); 307 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 308 DL, ValueVT.getScalarType(), Val); 309 } 310 311 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 312} 313 314 315 316 317static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 318 SDValue Val, SDValue *Parts, unsigned NumParts, 319 EVT PartVT); 320 321/// getCopyToParts - Create a series of nodes that contain the specified value 322/// split into legal parts. If the parts contain more bits than Val, then, for 323/// integers, ExtendKind can be used to specify how to generate the extra bits. 324static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 325 SDValue Val, SDValue *Parts, unsigned NumParts, 326 EVT PartVT, 327 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 328 EVT ValueVT = Val.getValueType(); 329 330 // Handle the vector case separately. 331 if (ValueVT.isVector()) 332 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 333 334 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 335 unsigned PartBits = PartVT.getSizeInBits(); 336 unsigned OrigNumParts = NumParts; 337 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 338 339 if (NumParts == 0) 340 return; 341 342 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 343 if (PartVT == ValueVT) { 344 assert(NumParts == 1 && "No-op copy with multiple parts!"); 345 Parts[0] = Val; 346 return; 347 } 348 349 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 350 // If the parts cover more bits than the value has, promote the value. 351 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 352 assert(NumParts == 1 && "Do not know what to promote to!"); 353 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 354 } else { 355 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 356 ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 if (PartVT == MVT::x86mmx) 361 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 362 } 363 } else if (PartBits == ValueVT.getSizeInBits()) { 364 // Different types of the same size. 365 assert(NumParts == 1 && PartVT != ValueVT); 366 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 367 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 368 // If the parts cover less bits than value has, truncate the value. 369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 370 ValueVT.isInteger() && 371 "Unknown mismatch!"); 372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 373 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 374 if (PartVT == MVT::x86mmx) 375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 376 } 377 378 // The value may have changed - recompute ValueVT. 379 ValueVT = Val.getValueType(); 380 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 381 "Failed to tile the value with PartVT!"); 382 383 if (NumParts == 1) { 384 assert(PartVT == ValueVT && "Type conversion failed!"); 385 Parts[0] = Val; 386 return; 387 } 388 389 // Expand the value into multiple parts. 390 if (NumParts & (NumParts - 1)) { 391 // The number of parts is not a power of 2. Split off and copy the tail. 392 assert(PartVT.isInteger() && ValueVT.isInteger() && 393 "Do not know what to expand to!"); 394 unsigned RoundParts = 1 << Log2_32(NumParts); 395 unsigned RoundBits = RoundParts * PartBits; 396 unsigned OddParts = NumParts - RoundParts; 397 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 398 DAG.getIntPtrConstant(RoundBits)); 399 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 400 401 if (TLI.isBigEndian()) 402 // The odd parts were reversed by getCopyToParts - unreverse them. 403 std::reverse(Parts + RoundParts, Parts + NumParts); 404 405 NumParts = RoundParts; 406 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 407 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 408 } 409 410 // The number of parts is a power of 2. Repeatedly bisect the value using 411 // EXTRACT_ELEMENT. 412 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 413 EVT::getIntegerVT(*DAG.getContext(), 414 ValueVT.getSizeInBits()), 415 Val); 416 417 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 418 for (unsigned i = 0; i < NumParts; i += StepSize) { 419 unsigned ThisBits = StepSize * PartBits / 2; 420 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 421 SDValue &Part0 = Parts[i]; 422 SDValue &Part1 = Parts[i+StepSize/2]; 423 424 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 425 ThisVT, Part0, DAG.getIntPtrConstant(1)); 426 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 427 ThisVT, Part0, DAG.getIntPtrConstant(0)); 428 429 if (ThisBits == PartBits && ThisVT != PartVT) { 430 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 431 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 432 } 433 } 434 } 435 436 if (TLI.isBigEndian()) 437 std::reverse(Parts, Parts + OrigNumParts); 438} 439 440 441/// getCopyToPartsVector - Create a series of nodes that contain the specified 442/// value split into legal parts. 443static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 444 SDValue Val, SDValue *Parts, unsigned NumParts, 445 EVT PartVT) { 446 EVT ValueVT = Val.getValueType(); 447 assert(ValueVT.isVector() && "Not a vector"); 448 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 449 450 if (NumParts == 1) { 451 if (PartVT == ValueVT) { 452 // Nothing to do. 453 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 454 // Bitconvert vector->vector case. 455 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 456 } else if (PartVT.isVector() && 457 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 458 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 459 EVT ElementVT = PartVT.getVectorElementType(); 460 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 461 // undef elements. 462 SmallVector<SDValue, 16> Ops; 463 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 465 ElementVT, Val, DAG.getIntPtrConstant(i))); 466 467 for (unsigned i = ValueVT.getVectorNumElements(), 468 e = PartVT.getVectorNumElements(); i != e; ++i) 469 Ops.push_back(DAG.getUNDEF(ElementVT)); 470 471 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 472 473 // FIXME: Use CONCAT for 2x -> 4x. 474 475 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 476 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 477 } else if (PartVT.isVector() && 478 PartVT.getVectorElementType().bitsGE( 479 ValueVT.getVectorElementType()) && 480 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 481 482 // Promoted vector extract 483 bool Smaller = PartVT.bitsLE(ValueVT); 484 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 485 DL, PartVT, Val); 486 } else{ 487 // Vector -> scalar conversion. 488 assert(ValueVT.getVectorNumElements() == 1 && 489 "Only trivial vector-to-scalar conversions should get here!"); 490 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 491 PartVT, Val, DAG.getIntPtrConstant(0)); 492 493 bool Smaller = ValueVT.bitsLE(PartVT); 494 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 495 DL, PartVT, Val); 496 } 497 498 Parts[0] = Val; 499 return; 500 } 501 502 // Handle a multi-element vector. 503 EVT IntermediateVT, RegisterVT; 504 unsigned NumIntermediates; 505 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 506 IntermediateVT, 507 NumIntermediates, RegisterVT); 508 unsigned NumElements = ValueVT.getVectorNumElements(); 509 510 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 511 NumParts = NumRegs; // Silence a compiler warning. 512 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 513 514 // Split the vector into intermediate operands. 515 SmallVector<SDValue, 8> Ops(NumIntermediates); 516 for (unsigned i = 0; i != NumIntermediates; ++i) { 517 if (IntermediateVT.isVector()) 518 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 519 IntermediateVT, Val, 520 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 521 else 522 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 523 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 524 } 525 526 // Split the intermediate operands into legal parts. 527 if (NumParts == NumIntermediates) { 528 // If the register was not expanded, promote or copy the value, 529 // as appropriate. 530 for (unsigned i = 0; i != NumParts; ++i) 531 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 532 } else if (NumParts > 0) { 533 // If the intermediate type was expanded, split each the value into 534 // legal parts. 535 assert(NumParts % NumIntermediates == 0 && 536 "Must expand into a divisible number of parts!"); 537 unsigned Factor = NumParts / NumIntermediates; 538 for (unsigned i = 0; i != NumIntermediates; ++i) 539 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 540 } 541} 542 543 544 545 546namespace { 547 /// RegsForValue - This struct represents the registers (physical or virtual) 548 /// that a particular set of values is assigned, and the type information 549 /// about the value. The most common situation is to represent one value at a 550 /// time, but struct or array values are handled element-wise as multiple 551 /// values. The splitting of aggregates is performed recursively, so that we 552 /// never have aggregate-typed registers. The values at this point do not 553 /// necessarily have legal types, so each value may require one or more 554 /// registers of some legal type. 555 /// 556 struct RegsForValue { 557 /// ValueVTs - The value types of the values, which may not be legal, and 558 /// may need be promoted or synthesized from one or more registers. 559 /// 560 SmallVector<EVT, 4> ValueVTs; 561 562 /// RegVTs - The value types of the registers. This is the same size as 563 /// ValueVTs and it records, for each value, what the type of the assigned 564 /// register or registers are. (Individual values are never synthesized 565 /// from more than one type of register.) 566 /// 567 /// With virtual registers, the contents of RegVTs is redundant with TLI's 568 /// getRegisterType member function, however when with physical registers 569 /// it is necessary to have a separate record of the types. 570 /// 571 SmallVector<EVT, 4> RegVTs; 572 573 /// Regs - This list holds the registers assigned to the values. 574 /// Each legal or promoted value requires one register, and each 575 /// expanded value requires multiple registers. 576 /// 577 SmallVector<unsigned, 4> Regs; 578 579 RegsForValue() {} 580 581 RegsForValue(const SmallVector<unsigned, 4> ®s, 582 EVT regvt, EVT valuevt) 583 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 584 585 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 586 unsigned Reg, Type *Ty) { 587 ComputeValueVTs(tli, Ty, ValueVTs); 588 589 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 590 EVT ValueVT = ValueVTs[Value]; 591 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 592 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 593 for (unsigned i = 0; i != NumRegs; ++i) 594 Regs.push_back(Reg + i); 595 RegVTs.push_back(RegisterVT); 596 Reg += NumRegs; 597 } 598 } 599 600 /// areValueTypesLegal - Return true if types of all the values are legal. 601 bool areValueTypesLegal(const TargetLowering &TLI) { 602 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 603 EVT RegisterVT = RegVTs[Value]; 604 if (!TLI.isTypeLegal(RegisterVT)) 605 return false; 606 } 607 return true; 608 } 609 610 /// append - Add the specified values to this one. 611 void append(const RegsForValue &RHS) { 612 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 613 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 614 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 615 } 616 617 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 618 /// this value and returns the result as a ValueVTs value. This uses 619 /// Chain/Flag as the input and updates them for the output Chain/Flag. 620 /// If the Flag pointer is NULL, no flag is used. 621 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 622 DebugLoc dl, 623 SDValue &Chain, SDValue *Flag) const; 624 625 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 626 /// specified value into the registers specified by this object. This uses 627 /// Chain/Flag as the input and updates them for the output Chain/Flag. 628 /// If the Flag pointer is NULL, no flag is used. 629 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 630 SDValue &Chain, SDValue *Flag) const; 631 632 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 633 /// operand list. This adds the code marker, matching input operand index 634 /// (if applicable), and includes the number of values added into it. 635 void AddInlineAsmOperands(unsigned Kind, 636 bool HasMatching, unsigned MatchingIdx, 637 SelectionDAG &DAG, 638 std::vector<SDValue> &Ops) const; 639 }; 640} 641 642/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 643/// this value and returns the result as a ValueVT value. This uses 644/// Chain/Flag as the input and updates them for the output Chain/Flag. 645/// If the Flag pointer is NULL, no flag is used. 646SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 647 FunctionLoweringInfo &FuncInfo, 648 DebugLoc dl, 649 SDValue &Chain, SDValue *Flag) const { 650 // A Value with type {} or [0 x %t] needs no registers. 651 if (ValueVTs.empty()) 652 return SDValue(); 653 654 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 655 656 // Assemble the legal parts into the final values. 657 SmallVector<SDValue, 4> Values(ValueVTs.size()); 658 SmallVector<SDValue, 8> Parts; 659 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 660 // Copy the legal parts from the registers. 661 EVT ValueVT = ValueVTs[Value]; 662 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 663 EVT RegisterVT = RegVTs[Value]; 664 665 Parts.resize(NumRegs); 666 for (unsigned i = 0; i != NumRegs; ++i) { 667 SDValue P; 668 if (Flag == 0) { 669 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 670 } else { 671 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 672 *Flag = P.getValue(2); 673 } 674 675 Chain = P.getValue(1); 676 Parts[i] = P; 677 678 // If the source register was virtual and if we know something about it, 679 // add an assert node. 680 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 681 !RegisterVT.isInteger() || RegisterVT.isVector()) 682 continue; 683 684 const FunctionLoweringInfo::LiveOutInfo *LOI = 685 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 686 if (!LOI) 687 continue; 688 689 unsigned RegSize = RegisterVT.getSizeInBits(); 690 unsigned NumSignBits = LOI->NumSignBits; 691 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 692 693 // FIXME: We capture more information than the dag can represent. For 694 // now, just use the tightest assertzext/assertsext possible. 695 bool isSExt = true; 696 EVT FromVT(MVT::Other); 697 if (NumSignBits == RegSize) 698 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 699 else if (NumZeroBits >= RegSize-1) 700 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 701 else if (NumSignBits > RegSize-8) 702 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 703 else if (NumZeroBits >= RegSize-8) 704 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 705 else if (NumSignBits > RegSize-16) 706 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 707 else if (NumZeroBits >= RegSize-16) 708 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 709 else if (NumSignBits > RegSize-32) 710 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 711 else if (NumZeroBits >= RegSize-32) 712 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 713 else 714 continue; 715 716 // Add an assertion node. 717 assert(FromVT != MVT::Other); 718 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 719 RegisterVT, P, DAG.getValueType(FromVT)); 720 } 721 722 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 723 NumRegs, RegisterVT, ValueVT); 724 Part += NumRegs; 725 Parts.clear(); 726 } 727 728 return DAG.getNode(ISD::MERGE_VALUES, dl, 729 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 730 &Values[0], ValueVTs.size()); 731} 732 733/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 734/// specified value into the registers specified by this object. This uses 735/// Chain/Flag as the input and updates them for the output Chain/Flag. 736/// If the Flag pointer is NULL, no flag is used. 737void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 738 SDValue &Chain, SDValue *Flag) const { 739 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 740 741 // Get the list of the values's legal parts. 742 unsigned NumRegs = Regs.size(); 743 SmallVector<SDValue, 8> Parts(NumRegs); 744 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 745 EVT ValueVT = ValueVTs[Value]; 746 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 747 EVT RegisterVT = RegVTs[Value]; 748 749 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 750 &Parts[Part], NumParts, RegisterVT); 751 Part += NumParts; 752 } 753 754 // Copy the parts into the registers. 755 SmallVector<SDValue, 8> Chains(NumRegs); 756 for (unsigned i = 0; i != NumRegs; ++i) { 757 SDValue Part; 758 if (Flag == 0) { 759 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 760 } else { 761 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 762 *Flag = Part.getValue(1); 763 } 764 765 Chains[i] = Part.getValue(0); 766 } 767 768 if (NumRegs == 1 || Flag) 769 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 770 // flagged to it. That is the CopyToReg nodes and the user are considered 771 // a single scheduling unit. If we create a TokenFactor and return it as 772 // chain, then the TokenFactor is both a predecessor (operand) of the 773 // user as well as a successor (the TF operands are flagged to the user). 774 // c1, f1 = CopyToReg 775 // c2, f2 = CopyToReg 776 // c3 = TokenFactor c1, c2 777 // ... 778 // = op c3, ..., f2 779 Chain = Chains[NumRegs-1]; 780 else 781 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 782} 783 784/// AddInlineAsmOperands - Add this value to the specified inlineasm node 785/// operand list. This adds the code marker and includes the number of 786/// values added into it. 787void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 788 unsigned MatchingIdx, 789 SelectionDAG &DAG, 790 std::vector<SDValue> &Ops) const { 791 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 792 793 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 794 if (HasMatching) 795 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 796 else if (!Regs.empty() && 797 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 798 // Put the register class of the virtual registers in the flag word. That 799 // way, later passes can recompute register class constraints for inline 800 // assembly as well as normal instructions. 801 // Don't do this for tied operands that can use the regclass information 802 // from the def. 803 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 804 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 805 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 806 } 807 808 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 809 Ops.push_back(Res); 810 811 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 812 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 813 EVT RegisterVT = RegVTs[Value]; 814 for (unsigned i = 0; i != NumRegs; ++i) { 815 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 816 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 817 } 818 } 819} 820 821void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 822 const TargetLibraryInfo *li) { 823 AA = &aa; 824 GFI = gfi; 825 LibInfo = li; 826 TD = DAG.getTarget().getTargetData(); 827 LPadToCallSiteMap.clear(); 828} 829 830/// clear - Clear out the current SelectionDAG and the associated 831/// state and prepare this SelectionDAGBuilder object to be used 832/// for a new block. This doesn't clear out information about 833/// additional blocks that are needed to complete switch lowering 834/// or PHI node updating; that information is cleared out as it is 835/// consumed. 836void SelectionDAGBuilder::clear() { 837 NodeMap.clear(); 838 UnusedArgNodeMap.clear(); 839 PendingLoads.clear(); 840 PendingExports.clear(); 841 CurDebugLoc = DebugLoc(); 842 HasTailCall = false; 843} 844 845/// clearDanglingDebugInfo - Clear the dangling debug information 846/// map. This function is seperated from the clear so that debug 847/// information that is dangling in a basic block can be properly 848/// resolved in a different basic block. This allows the 849/// SelectionDAG to resolve dangling debug information attached 850/// to PHI nodes. 851void SelectionDAGBuilder::clearDanglingDebugInfo() { 852 DanglingDebugInfoMap.clear(); 853} 854 855/// getRoot - Return the current virtual root of the Selection DAG, 856/// flushing any PendingLoad items. This must be done before emitting 857/// a store or any other node that may need to be ordered after any 858/// prior load instructions. 859/// 860SDValue SelectionDAGBuilder::getRoot() { 861 if (PendingLoads.empty()) 862 return DAG.getRoot(); 863 864 if (PendingLoads.size() == 1) { 865 SDValue Root = PendingLoads[0]; 866 DAG.setRoot(Root); 867 PendingLoads.clear(); 868 return Root; 869 } 870 871 // Otherwise, we have to make a token factor node. 872 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 873 &PendingLoads[0], PendingLoads.size()); 874 PendingLoads.clear(); 875 DAG.setRoot(Root); 876 return Root; 877} 878 879/// getControlRoot - Similar to getRoot, but instead of flushing all the 880/// PendingLoad items, flush all the PendingExports items. It is necessary 881/// to do this before emitting a terminator instruction. 882/// 883SDValue SelectionDAGBuilder::getControlRoot() { 884 SDValue Root = DAG.getRoot(); 885 886 if (PendingExports.empty()) 887 return Root; 888 889 // Turn all of the CopyToReg chains into one factored node. 890 if (Root.getOpcode() != ISD::EntryToken) { 891 unsigned i = 0, e = PendingExports.size(); 892 for (; i != e; ++i) { 893 assert(PendingExports[i].getNode()->getNumOperands() > 1); 894 if (PendingExports[i].getNode()->getOperand(0) == Root) 895 break; // Don't add the root if we already indirectly depend on it. 896 } 897 898 if (i == e) 899 PendingExports.push_back(Root); 900 } 901 902 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 903 &PendingExports[0], 904 PendingExports.size()); 905 PendingExports.clear(); 906 DAG.setRoot(Root); 907 return Root; 908} 909 910void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 911 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 912 DAG.AssignOrdering(Node, SDNodeOrder); 913 914 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 915 AssignOrderingToNode(Node->getOperand(I).getNode()); 916} 917 918void SelectionDAGBuilder::visit(const Instruction &I) { 919 // Set up outgoing PHI node register values before emitting the terminator. 920 if (isa<TerminatorInst>(&I)) 921 HandlePHINodesInSuccessorBlocks(I.getParent()); 922 923 CurDebugLoc = I.getDebugLoc(); 924 925 visit(I.getOpcode(), I); 926 927 if (!isa<TerminatorInst>(&I) && !HasTailCall) 928 CopyToExportRegsIfNeeded(&I); 929 930 CurDebugLoc = DebugLoc(); 931} 932 933void SelectionDAGBuilder::visitPHI(const PHINode &) { 934 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 935} 936 937void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 938 // Note: this doesn't use InstVisitor, because it has to work with 939 // ConstantExpr's in addition to instructions. 940 switch (Opcode) { 941 default: llvm_unreachable("Unknown instruction type encountered!"); 942 // Build the switch statement using the Instruction.def file. 943#define HANDLE_INST(NUM, OPCODE, CLASS) \ 944 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 945#include "llvm/Instruction.def" 946 } 947 948 // Assign the ordering to the freshly created DAG nodes. 949 if (NodeMap.count(&I)) { 950 ++SDNodeOrder; 951 AssignOrderingToNode(getValue(&I).getNode()); 952 } 953} 954 955// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 956// generate the debug data structures now that we've seen its definition. 957void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 958 SDValue Val) { 959 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 960 if (DDI.getDI()) { 961 const DbgValueInst *DI = DDI.getDI(); 962 DebugLoc dl = DDI.getdl(); 963 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 964 MDNode *Variable = DI->getVariable(); 965 uint64_t Offset = DI->getOffset(); 966 SDDbgValue *SDV; 967 if (Val.getNode()) { 968 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 969 SDV = DAG.getDbgValue(Variable, Val.getNode(), 970 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 971 DAG.AddDbgValue(SDV, Val.getNode(), false); 972 } 973 } else 974 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 975 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 976 } 977} 978 979/// getValue - Return an SDValue for the given Value. 980SDValue SelectionDAGBuilder::getValue(const Value *V) { 981 // If we already have an SDValue for this value, use it. It's important 982 // to do this first, so that we don't create a CopyFromReg if we already 983 // have a regular SDValue. 984 SDValue &N = NodeMap[V]; 985 if (N.getNode()) return N; 986 987 // If there's a virtual register allocated and initialized for this 988 // value, use it. 989 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 990 if (It != FuncInfo.ValueMap.end()) { 991 unsigned InReg = It->second; 992 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 993 SDValue Chain = DAG.getEntryNode(); 994 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 995 resolveDanglingDebugInfo(V, N); 996 return N; 997 } 998 999 // Otherwise create a new SDValue and remember it. 1000 SDValue Val = getValueImpl(V); 1001 NodeMap[V] = Val; 1002 resolveDanglingDebugInfo(V, Val); 1003 return Val; 1004} 1005 1006/// getNonRegisterValue - Return an SDValue for the given Value, but 1007/// don't look in FuncInfo.ValueMap for a virtual register. 1008SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1009 // If we already have an SDValue for this value, use it. 1010 SDValue &N = NodeMap[V]; 1011 if (N.getNode()) return N; 1012 1013 // Otherwise create a new SDValue and remember it. 1014 SDValue Val = getValueImpl(V); 1015 NodeMap[V] = Val; 1016 resolveDanglingDebugInfo(V, Val); 1017 return Val; 1018} 1019 1020/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1021/// Create an SDValue for the given value. 1022SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1023 if (const Constant *C = dyn_cast<Constant>(V)) { 1024 EVT VT = TLI.getValueType(V->getType(), true); 1025 1026 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1027 return DAG.getConstant(*CI, VT); 1028 1029 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1030 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1031 1032 if (isa<ConstantPointerNull>(C)) 1033 return DAG.getConstant(0, TLI.getPointerTy()); 1034 1035 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1036 return DAG.getConstantFP(*CFP, VT); 1037 1038 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1039 return DAG.getUNDEF(VT); 1040 1041 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1042 visit(CE->getOpcode(), *CE); 1043 SDValue N1 = NodeMap[V]; 1044 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1045 return N1; 1046 } 1047 1048 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1049 SmallVector<SDValue, 4> Constants; 1050 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1051 OI != OE; ++OI) { 1052 SDNode *Val = getValue(*OI).getNode(); 1053 // If the operand is an empty aggregate, there are no values. 1054 if (!Val) continue; 1055 // Add each leaf value from the operand to the Constants list 1056 // to form a flattened list of all the values. 1057 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1058 Constants.push_back(SDValue(Val, i)); 1059 } 1060 1061 return DAG.getMergeValues(&Constants[0], Constants.size(), 1062 getCurDebugLoc()); 1063 } 1064 1065 if (const ConstantDataSequential *CDS = 1066 dyn_cast<ConstantDataSequential>(C)) { 1067 SmallVector<SDValue, 4> Ops; 1068 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1069 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1070 // Add each leaf value from the operand to the Constants list 1071 // to form a flattened list of all the values. 1072 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1073 Ops.push_back(SDValue(Val, i)); 1074 } 1075 1076 if (isa<ArrayType>(CDS->getType())) 1077 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc()); 1078 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1079 VT, &Ops[0], Ops.size()); 1080 } 1081 1082 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1083 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1084 "Unknown struct or array constant!"); 1085 1086 SmallVector<EVT, 4> ValueVTs; 1087 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1088 unsigned NumElts = ValueVTs.size(); 1089 if (NumElts == 0) 1090 return SDValue(); // empty struct 1091 SmallVector<SDValue, 4> Constants(NumElts); 1092 for (unsigned i = 0; i != NumElts; ++i) { 1093 EVT EltVT = ValueVTs[i]; 1094 if (isa<UndefValue>(C)) 1095 Constants[i] = DAG.getUNDEF(EltVT); 1096 else if (EltVT.isFloatingPoint()) 1097 Constants[i] = DAG.getConstantFP(0, EltVT); 1098 else 1099 Constants[i] = DAG.getConstant(0, EltVT); 1100 } 1101 1102 return DAG.getMergeValues(&Constants[0], NumElts, 1103 getCurDebugLoc()); 1104 } 1105 1106 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1107 return DAG.getBlockAddress(BA, VT); 1108 1109 VectorType *VecTy = cast<VectorType>(V->getType()); 1110 unsigned NumElements = VecTy->getNumElements(); 1111 1112 // Now that we know the number and type of the elements, get that number of 1113 // elements into the Ops array based on what kind of constant it is. 1114 SmallVector<SDValue, 16> Ops; 1115 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1116 for (unsigned i = 0; i != NumElements; ++i) 1117 Ops.push_back(getValue(CV->getOperand(i))); 1118 } else { 1119 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1120 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1121 1122 SDValue Op; 1123 if (EltVT.isFloatingPoint()) 1124 Op = DAG.getConstantFP(0, EltVT); 1125 else 1126 Op = DAG.getConstant(0, EltVT); 1127 Ops.assign(NumElements, Op); 1128 } 1129 1130 // Create a BUILD_VECTOR node. 1131 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1132 VT, &Ops[0], Ops.size()); 1133 } 1134 1135 // If this is a static alloca, generate it as the frameindex instead of 1136 // computation. 1137 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1138 DenseMap<const AllocaInst*, int>::iterator SI = 1139 FuncInfo.StaticAllocaMap.find(AI); 1140 if (SI != FuncInfo.StaticAllocaMap.end()) 1141 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1142 } 1143 1144 // If this is an instruction which fast-isel has deferred, select it now. 1145 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1146 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1147 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1148 SDValue Chain = DAG.getEntryNode(); 1149 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1150 } 1151 1152 llvm_unreachable("Can't get register for value!"); 1153} 1154 1155void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1156 SDValue Chain = getControlRoot(); 1157 SmallVector<ISD::OutputArg, 8> Outs; 1158 SmallVector<SDValue, 8> OutVals; 1159 1160 if (!FuncInfo.CanLowerReturn) { 1161 unsigned DemoteReg = FuncInfo.DemoteRegister; 1162 const Function *F = I.getParent()->getParent(); 1163 1164 // Emit a store of the return value through the virtual register. 1165 // Leave Outs empty so that LowerReturn won't try to load return 1166 // registers the usual way. 1167 SmallVector<EVT, 1> PtrValueVTs; 1168 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1169 PtrValueVTs); 1170 1171 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1172 SDValue RetOp = getValue(I.getOperand(0)); 1173 1174 SmallVector<EVT, 4> ValueVTs; 1175 SmallVector<uint64_t, 4> Offsets; 1176 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1177 unsigned NumValues = ValueVTs.size(); 1178 1179 SmallVector<SDValue, 4> Chains(NumValues); 1180 for (unsigned i = 0; i != NumValues; ++i) { 1181 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1182 RetPtr.getValueType(), RetPtr, 1183 DAG.getIntPtrConstant(Offsets[i])); 1184 Chains[i] = 1185 DAG.getStore(Chain, getCurDebugLoc(), 1186 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1187 // FIXME: better loc info would be nice. 1188 Add, MachinePointerInfo(), false, false, 0); 1189 } 1190 1191 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1192 MVT::Other, &Chains[0], NumValues); 1193 } else if (I.getNumOperands() != 0) { 1194 SmallVector<EVT, 4> ValueVTs; 1195 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1196 unsigned NumValues = ValueVTs.size(); 1197 if (NumValues) { 1198 SDValue RetOp = getValue(I.getOperand(0)); 1199 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1200 EVT VT = ValueVTs[j]; 1201 1202 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1203 1204 const Function *F = I.getParent()->getParent(); 1205 if (F->paramHasAttr(0, Attribute::SExt)) 1206 ExtendKind = ISD::SIGN_EXTEND; 1207 else if (F->paramHasAttr(0, Attribute::ZExt)) 1208 ExtendKind = ISD::ZERO_EXTEND; 1209 1210 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1211 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1212 1213 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1214 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1215 SmallVector<SDValue, 4> Parts(NumParts); 1216 getCopyToParts(DAG, getCurDebugLoc(), 1217 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1218 &Parts[0], NumParts, PartVT, ExtendKind); 1219 1220 // 'inreg' on function refers to return value 1221 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1222 if (F->paramHasAttr(0, Attribute::InReg)) 1223 Flags.setInReg(); 1224 1225 // Propagate extension type if any 1226 if (ExtendKind == ISD::SIGN_EXTEND) 1227 Flags.setSExt(); 1228 else if (ExtendKind == ISD::ZERO_EXTEND) 1229 Flags.setZExt(); 1230 1231 for (unsigned i = 0; i < NumParts; ++i) { 1232 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1233 /*isfixed=*/true)); 1234 OutVals.push_back(Parts[i]); 1235 } 1236 } 1237 } 1238 } 1239 1240 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1241 CallingConv::ID CallConv = 1242 DAG.getMachineFunction().getFunction()->getCallingConv(); 1243 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1244 Outs, OutVals, getCurDebugLoc(), DAG); 1245 1246 // Verify that the target's LowerReturn behaved as expected. 1247 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1248 "LowerReturn didn't return a valid chain!"); 1249 1250 // Update the DAG with the new chain value resulting from return lowering. 1251 DAG.setRoot(Chain); 1252} 1253 1254/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1255/// created for it, emit nodes to copy the value into the virtual 1256/// registers. 1257void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1258 // Skip empty types 1259 if (V->getType()->isEmptyTy()) 1260 return; 1261 1262 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1263 if (VMI != FuncInfo.ValueMap.end()) { 1264 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1265 CopyValueToVirtualRegister(V, VMI->second); 1266 } 1267} 1268 1269/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1270/// the current basic block, add it to ValueMap now so that we'll get a 1271/// CopyTo/FromReg. 1272void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1273 // No need to export constants. 1274 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1275 1276 // Already exported? 1277 if (FuncInfo.isExportedInst(V)) return; 1278 1279 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1280 CopyValueToVirtualRegister(V, Reg); 1281} 1282 1283bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1284 const BasicBlock *FromBB) { 1285 // The operands of the setcc have to be in this block. We don't know 1286 // how to export them from some other block. 1287 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1288 // Can export from current BB. 1289 if (VI->getParent() == FromBB) 1290 return true; 1291 1292 // Is already exported, noop. 1293 return FuncInfo.isExportedInst(V); 1294 } 1295 1296 // If this is an argument, we can export it if the BB is the entry block or 1297 // if it is already exported. 1298 if (isa<Argument>(V)) { 1299 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1300 return true; 1301 1302 // Otherwise, can only export this if it is already exported. 1303 return FuncInfo.isExportedInst(V); 1304 } 1305 1306 // Otherwise, constants can always be exported. 1307 return true; 1308} 1309 1310/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1311uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1312 const MachineBasicBlock *Dst) const { 1313 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1314 if (!BPI) 1315 return 0; 1316 const BasicBlock *SrcBB = Src->getBasicBlock(); 1317 const BasicBlock *DstBB = Dst->getBasicBlock(); 1318 return BPI->getEdgeWeight(SrcBB, DstBB); 1319} 1320 1321void SelectionDAGBuilder:: 1322addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1323 uint32_t Weight /* = 0 */) { 1324 if (!Weight) 1325 Weight = getEdgeWeight(Src, Dst); 1326 Src->addSuccessor(Dst, Weight); 1327} 1328 1329 1330static bool InBlock(const Value *V, const BasicBlock *BB) { 1331 if (const Instruction *I = dyn_cast<Instruction>(V)) 1332 return I->getParent() == BB; 1333 return true; 1334} 1335 1336/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1337/// This function emits a branch and is used at the leaves of an OR or an 1338/// AND operator tree. 1339/// 1340void 1341SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1342 MachineBasicBlock *TBB, 1343 MachineBasicBlock *FBB, 1344 MachineBasicBlock *CurBB, 1345 MachineBasicBlock *SwitchBB) { 1346 const BasicBlock *BB = CurBB->getBasicBlock(); 1347 1348 // If the leaf of the tree is a comparison, merge the condition into 1349 // the caseblock. 1350 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1351 // The operands of the cmp have to be in this block. We don't know 1352 // how to export them from some other block. If this is the first block 1353 // of the sequence, no exporting is needed. 1354 if (CurBB == SwitchBB || 1355 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1356 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1357 ISD::CondCode Condition; 1358 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1359 Condition = getICmpCondCode(IC->getPredicate()); 1360 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1361 Condition = getFCmpCondCode(FC->getPredicate()); 1362 if (TM.Options.NoNaNsFPMath) 1363 Condition = getFCmpCodeWithoutNaN(Condition); 1364 } else { 1365 Condition = ISD::SETEQ; // silence warning. 1366 llvm_unreachable("Unknown compare instruction"); 1367 } 1368 1369 CaseBlock CB(Condition, BOp->getOperand(0), 1370 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1371 SwitchCases.push_back(CB); 1372 return; 1373 } 1374 } 1375 1376 // Create a CaseBlock record representing this branch. 1377 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1378 NULL, TBB, FBB, CurBB); 1379 SwitchCases.push_back(CB); 1380} 1381 1382/// FindMergedConditions - If Cond is an expression like 1383void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1384 MachineBasicBlock *TBB, 1385 MachineBasicBlock *FBB, 1386 MachineBasicBlock *CurBB, 1387 MachineBasicBlock *SwitchBB, 1388 unsigned Opc) { 1389 // If this node is not part of the or/and tree, emit it as a branch. 1390 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1391 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1392 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1393 BOp->getParent() != CurBB->getBasicBlock() || 1394 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1395 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1396 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1397 return; 1398 } 1399 1400 // Create TmpBB after CurBB. 1401 MachineFunction::iterator BBI = CurBB; 1402 MachineFunction &MF = DAG.getMachineFunction(); 1403 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1404 CurBB->getParent()->insert(++BBI, TmpBB); 1405 1406 if (Opc == Instruction::Or) { 1407 // Codegen X | Y as: 1408 // jmp_if_X TBB 1409 // jmp TmpBB 1410 // TmpBB: 1411 // jmp_if_Y TBB 1412 // jmp FBB 1413 // 1414 1415 // Emit the LHS condition. 1416 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1417 1418 // Emit the RHS condition into TmpBB. 1419 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1420 } else { 1421 assert(Opc == Instruction::And && "Unknown merge op!"); 1422 // Codegen X & Y as: 1423 // jmp_if_X TmpBB 1424 // jmp FBB 1425 // TmpBB: 1426 // jmp_if_Y TBB 1427 // jmp FBB 1428 // 1429 // This requires creation of TmpBB after CurBB. 1430 1431 // Emit the LHS condition. 1432 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1433 1434 // Emit the RHS condition into TmpBB. 1435 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1436 } 1437} 1438 1439/// If the set of cases should be emitted as a series of branches, return true. 1440/// If we should emit this as a bunch of and/or'd together conditions, return 1441/// false. 1442bool 1443SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1444 if (Cases.size() != 2) return true; 1445 1446 // If this is two comparisons of the same values or'd or and'd together, they 1447 // will get folded into a single comparison, so don't emit two blocks. 1448 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1449 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1450 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1451 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1452 return false; 1453 } 1454 1455 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1456 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1457 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1458 Cases[0].CC == Cases[1].CC && 1459 isa<Constant>(Cases[0].CmpRHS) && 1460 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1461 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1462 return false; 1463 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1464 return false; 1465 } 1466 1467 return true; 1468} 1469 1470void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1471 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1472 1473 // Update machine-CFG edges. 1474 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1475 1476 // Figure out which block is immediately after the current one. 1477 MachineBasicBlock *NextBlock = 0; 1478 MachineFunction::iterator BBI = BrMBB; 1479 if (++BBI != FuncInfo.MF->end()) 1480 NextBlock = BBI; 1481 1482 if (I.isUnconditional()) { 1483 // Update machine-CFG edges. 1484 BrMBB->addSuccessor(Succ0MBB); 1485 1486 // If this is not a fall-through branch, emit the branch. 1487 if (Succ0MBB != NextBlock) 1488 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1489 MVT::Other, getControlRoot(), 1490 DAG.getBasicBlock(Succ0MBB))); 1491 1492 return; 1493 } 1494 1495 // If this condition is one of the special cases we handle, do special stuff 1496 // now. 1497 const Value *CondVal = I.getCondition(); 1498 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1499 1500 // If this is a series of conditions that are or'd or and'd together, emit 1501 // this as a sequence of branches instead of setcc's with and/or operations. 1502 // As long as jumps are not expensive, this should improve performance. 1503 // For example, instead of something like: 1504 // cmp A, B 1505 // C = seteq 1506 // cmp D, E 1507 // F = setle 1508 // or C, F 1509 // jnz foo 1510 // Emit: 1511 // cmp A, B 1512 // je foo 1513 // cmp D, E 1514 // jle foo 1515 // 1516 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1517 if (!TLI.isJumpExpensive() && 1518 BOp->hasOneUse() && 1519 (BOp->getOpcode() == Instruction::And || 1520 BOp->getOpcode() == Instruction::Or)) { 1521 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1522 BOp->getOpcode()); 1523 // If the compares in later blocks need to use values not currently 1524 // exported from this block, export them now. This block should always 1525 // be the first entry. 1526 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1527 1528 // Allow some cases to be rejected. 1529 if (ShouldEmitAsBranches(SwitchCases)) { 1530 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1531 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1532 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1533 } 1534 1535 // Emit the branch for this block. 1536 visitSwitchCase(SwitchCases[0], BrMBB); 1537 SwitchCases.erase(SwitchCases.begin()); 1538 return; 1539 } 1540 1541 // Okay, we decided not to do this, remove any inserted MBB's and clear 1542 // SwitchCases. 1543 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1544 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1545 1546 SwitchCases.clear(); 1547 } 1548 } 1549 1550 // Create a CaseBlock record representing this branch. 1551 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1552 NULL, Succ0MBB, Succ1MBB, BrMBB); 1553 1554 // Use visitSwitchCase to actually insert the fast branch sequence for this 1555 // cond branch. 1556 visitSwitchCase(CB, BrMBB); 1557} 1558 1559/// visitSwitchCase - Emits the necessary code to represent a single node in 1560/// the binary search tree resulting from lowering a switch instruction. 1561void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1562 MachineBasicBlock *SwitchBB) { 1563 SDValue Cond; 1564 SDValue CondLHS = getValue(CB.CmpLHS); 1565 DebugLoc dl = getCurDebugLoc(); 1566 1567 // Build the setcc now. 1568 if (CB.CmpMHS == NULL) { 1569 // Fold "(X == true)" to X and "(X == false)" to !X to 1570 // handle common cases produced by branch lowering. 1571 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1572 CB.CC == ISD::SETEQ) 1573 Cond = CondLHS; 1574 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1575 CB.CC == ISD::SETEQ) { 1576 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1577 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1578 } else 1579 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1580 } else { 1581 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1582 1583 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1584 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1585 1586 SDValue CmpOp = getValue(CB.CmpMHS); 1587 EVT VT = CmpOp.getValueType(); 1588 1589 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1590 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1591 ISD::SETLE); 1592 } else { 1593 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1594 VT, CmpOp, DAG.getConstant(Low, VT)); 1595 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1596 DAG.getConstant(High-Low, VT), ISD::SETULE); 1597 } 1598 } 1599 1600 // Update successor info 1601 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1602 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1603 1604 // Set NextBlock to be the MBB immediately after the current one, if any. 1605 // This is used to avoid emitting unnecessary branches to the next block. 1606 MachineBasicBlock *NextBlock = 0; 1607 MachineFunction::iterator BBI = SwitchBB; 1608 if (++BBI != FuncInfo.MF->end()) 1609 NextBlock = BBI; 1610 1611 // If the lhs block is the next block, invert the condition so that we can 1612 // fall through to the lhs instead of the rhs block. 1613 if (CB.TrueBB == NextBlock) { 1614 std::swap(CB.TrueBB, CB.FalseBB); 1615 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1616 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1617 } 1618 1619 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1620 MVT::Other, getControlRoot(), Cond, 1621 DAG.getBasicBlock(CB.TrueBB)); 1622 1623 // Insert the false branch. Do this even if it's a fall through branch, 1624 // this makes it easier to do DAG optimizations which require inverting 1625 // the branch condition. 1626 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1627 DAG.getBasicBlock(CB.FalseBB)); 1628 1629 DAG.setRoot(BrCond); 1630} 1631 1632/// visitJumpTable - Emit JumpTable node in the current MBB 1633void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1634 // Emit the code for the jump table 1635 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1636 EVT PTy = TLI.getPointerTy(); 1637 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1638 JT.Reg, PTy); 1639 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1640 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1641 MVT::Other, Index.getValue(1), 1642 Table, Index); 1643 DAG.setRoot(BrJumpTable); 1644} 1645 1646/// visitJumpTableHeader - This function emits necessary code to produce index 1647/// in the JumpTable from switch case. 1648void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1649 JumpTableHeader &JTH, 1650 MachineBasicBlock *SwitchBB) { 1651 // Subtract the lowest switch case value from the value being switched on and 1652 // conditional branch to default mbb if the result is greater than the 1653 // difference between smallest and largest cases. 1654 SDValue SwitchOp = getValue(JTH.SValue); 1655 EVT VT = SwitchOp.getValueType(); 1656 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1657 DAG.getConstant(JTH.First, VT)); 1658 1659 // The SDNode we just created, which holds the value being switched on minus 1660 // the smallest case value, needs to be copied to a virtual register so it 1661 // can be used as an index into the jump table in a subsequent basic block. 1662 // This value may be smaller or larger than the target's pointer type, and 1663 // therefore require extension or truncating. 1664 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1665 1666 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1667 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1668 JumpTableReg, SwitchOp); 1669 JT.Reg = JumpTableReg; 1670 1671 // Emit the range check for the jump table, and branch to the default block 1672 // for the switch statement if the value being switched on exceeds the largest 1673 // case in the switch. 1674 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1675 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1676 DAG.getConstant(JTH.Last-JTH.First,VT), 1677 ISD::SETUGT); 1678 1679 // Set NextBlock to be the MBB immediately after the current one, if any. 1680 // This is used to avoid emitting unnecessary branches to the next block. 1681 MachineBasicBlock *NextBlock = 0; 1682 MachineFunction::iterator BBI = SwitchBB; 1683 1684 if (++BBI != FuncInfo.MF->end()) 1685 NextBlock = BBI; 1686 1687 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1688 MVT::Other, CopyTo, CMP, 1689 DAG.getBasicBlock(JT.Default)); 1690 1691 if (JT.MBB != NextBlock) 1692 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1693 DAG.getBasicBlock(JT.MBB)); 1694 1695 DAG.setRoot(BrCond); 1696} 1697 1698/// visitBitTestHeader - This function emits necessary code to produce value 1699/// suitable for "bit tests" 1700void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1701 MachineBasicBlock *SwitchBB) { 1702 // Subtract the minimum value 1703 SDValue SwitchOp = getValue(B.SValue); 1704 EVT VT = SwitchOp.getValueType(); 1705 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1706 DAG.getConstant(B.First, VT)); 1707 1708 // Check range 1709 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1710 TLI.getSetCCResultType(Sub.getValueType()), 1711 Sub, DAG.getConstant(B.Range, VT), 1712 ISD::SETUGT); 1713 1714 // Determine the type of the test operands. 1715 bool UsePtrType = false; 1716 if (!TLI.isTypeLegal(VT)) 1717 UsePtrType = true; 1718 else { 1719 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1720 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1721 // Switch table case range are encoded into series of masks. 1722 // Just use pointer type, it's guaranteed to fit. 1723 UsePtrType = true; 1724 break; 1725 } 1726 } 1727 if (UsePtrType) { 1728 VT = TLI.getPointerTy(); 1729 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1730 } 1731 1732 B.RegVT = VT; 1733 B.Reg = FuncInfo.CreateReg(VT); 1734 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1735 B.Reg, Sub); 1736 1737 // Set NextBlock to be the MBB immediately after the current one, if any. 1738 // This is used to avoid emitting unnecessary branches to the next block. 1739 MachineBasicBlock *NextBlock = 0; 1740 MachineFunction::iterator BBI = SwitchBB; 1741 if (++BBI != FuncInfo.MF->end()) 1742 NextBlock = BBI; 1743 1744 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1745 1746 addSuccessorWithWeight(SwitchBB, B.Default); 1747 addSuccessorWithWeight(SwitchBB, MBB); 1748 1749 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1750 MVT::Other, CopyTo, RangeCmp, 1751 DAG.getBasicBlock(B.Default)); 1752 1753 if (MBB != NextBlock) 1754 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1755 DAG.getBasicBlock(MBB)); 1756 1757 DAG.setRoot(BrRange); 1758} 1759 1760/// visitBitTestCase - this function produces one "bit test" 1761void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1762 MachineBasicBlock* NextMBB, 1763 unsigned Reg, 1764 BitTestCase &B, 1765 MachineBasicBlock *SwitchBB) { 1766 EVT VT = BB.RegVT; 1767 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1768 Reg, VT); 1769 SDValue Cmp; 1770 unsigned PopCount = CountPopulation_64(B.Mask); 1771 if (PopCount == 1) { 1772 // Testing for a single bit; just compare the shift count with what it 1773 // would need to be to shift a 1 bit in that position. 1774 Cmp = DAG.getSetCC(getCurDebugLoc(), 1775 TLI.getSetCCResultType(VT), 1776 ShiftOp, 1777 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1778 ISD::SETEQ); 1779 } else if (PopCount == BB.Range) { 1780 // There is only one zero bit in the range, test for it directly. 1781 Cmp = DAG.getSetCC(getCurDebugLoc(), 1782 TLI.getSetCCResultType(VT), 1783 ShiftOp, 1784 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1785 ISD::SETNE); 1786 } else { 1787 // Make desired shift 1788 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1789 DAG.getConstant(1, VT), ShiftOp); 1790 1791 // Emit bit tests and jumps 1792 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1793 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1794 Cmp = DAG.getSetCC(getCurDebugLoc(), 1795 TLI.getSetCCResultType(VT), 1796 AndOp, DAG.getConstant(0, VT), 1797 ISD::SETNE); 1798 } 1799 1800 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1801 addSuccessorWithWeight(SwitchBB, NextMBB); 1802 1803 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1804 MVT::Other, getControlRoot(), 1805 Cmp, DAG.getBasicBlock(B.TargetBB)); 1806 1807 // Set NextBlock to be the MBB immediately after the current one, if any. 1808 // This is used to avoid emitting unnecessary branches to the next block. 1809 MachineBasicBlock *NextBlock = 0; 1810 MachineFunction::iterator BBI = SwitchBB; 1811 if (++BBI != FuncInfo.MF->end()) 1812 NextBlock = BBI; 1813 1814 if (NextMBB != NextBlock) 1815 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1816 DAG.getBasicBlock(NextMBB)); 1817 1818 DAG.setRoot(BrAnd); 1819} 1820 1821void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1822 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1823 1824 // Retrieve successors. 1825 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1826 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1827 1828 const Value *Callee(I.getCalledValue()); 1829 if (isa<InlineAsm>(Callee)) 1830 visitInlineAsm(&I); 1831 else 1832 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1833 1834 // If the value of the invoke is used outside of its defining block, make it 1835 // available as a virtual register. 1836 CopyToExportRegsIfNeeded(&I); 1837 1838 // Update successor info 1839 addSuccessorWithWeight(InvokeMBB, Return); 1840 addSuccessorWithWeight(InvokeMBB, LandingPad); 1841 1842 // Drop into normal successor. 1843 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1844 MVT::Other, getControlRoot(), 1845 DAG.getBasicBlock(Return))); 1846} 1847 1848void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1849 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1850} 1851 1852void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1853 assert(FuncInfo.MBB->isLandingPad() && 1854 "Call to landingpad not in landing pad!"); 1855 1856 MachineBasicBlock *MBB = FuncInfo.MBB; 1857 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1858 AddLandingPadInfo(LP, MMI, MBB); 1859 1860 // If there aren't registers to copy the values into (e.g., during SjLj 1861 // exceptions), then don't bother to create these DAG nodes. 1862 if (TLI.getExceptionPointerRegister() == 0 && 1863 TLI.getExceptionSelectorRegister() == 0) 1864 return; 1865 1866 SmallVector<EVT, 2> ValueVTs; 1867 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1868 1869 // Insert the EXCEPTIONADDR instruction. 1870 assert(FuncInfo.MBB->isLandingPad() && 1871 "Call to eh.exception not in landing pad!"); 1872 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1873 SDValue Ops[2]; 1874 Ops[0] = DAG.getRoot(); 1875 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1876 SDValue Chain = Op1.getValue(1); 1877 1878 // Insert the EHSELECTION instruction. 1879 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1880 Ops[0] = Op1; 1881 Ops[1] = Chain; 1882 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1883 Chain = Op2.getValue(1); 1884 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1885 1886 Ops[0] = Op1; 1887 Ops[1] = Op2; 1888 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1889 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1890 &Ops[0], 2); 1891 1892 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1893 setValue(&LP, RetPair.first); 1894 DAG.setRoot(RetPair.second); 1895} 1896 1897/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1898/// small case ranges). 1899bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1900 CaseRecVector& WorkList, 1901 const Value* SV, 1902 MachineBasicBlock *Default, 1903 MachineBasicBlock *SwitchBB) { 1904 Case& BackCase = *(CR.Range.second-1); 1905 1906 // Size is the number of Cases represented by this range. 1907 size_t Size = CR.Range.second - CR.Range.first; 1908 if (Size > 3) 1909 return false; 1910 1911 // Get the MachineFunction which holds the current MBB. This is used when 1912 // inserting any additional MBBs necessary to represent the switch. 1913 MachineFunction *CurMF = FuncInfo.MF; 1914 1915 // Figure out which block is immediately after the current one. 1916 MachineBasicBlock *NextBlock = 0; 1917 MachineFunction::iterator BBI = CR.CaseBB; 1918 1919 if (++BBI != FuncInfo.MF->end()) 1920 NextBlock = BBI; 1921 1922 // If any two of the cases has the same destination, and if one value 1923 // is the same as the other, but has one bit unset that the other has set, 1924 // use bit manipulation to do two compares at once. For example: 1925 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1926 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1927 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1928 if (Size == 2 && CR.CaseBB == SwitchBB) { 1929 Case &Small = *CR.Range.first; 1930 Case &Big = *(CR.Range.second-1); 1931 1932 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1933 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1934 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1935 1936 // Check that there is only one bit different. 1937 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1938 (SmallValue | BigValue) == BigValue) { 1939 // Isolate the common bit. 1940 APInt CommonBit = BigValue & ~SmallValue; 1941 assert((SmallValue | CommonBit) == BigValue && 1942 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1943 1944 SDValue CondLHS = getValue(SV); 1945 EVT VT = CondLHS.getValueType(); 1946 DebugLoc DL = getCurDebugLoc(); 1947 1948 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1949 DAG.getConstant(CommonBit, VT)); 1950 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1951 Or, DAG.getConstant(BigValue, VT), 1952 ISD::SETEQ); 1953 1954 // Update successor info. 1955 addSuccessorWithWeight(SwitchBB, Small.BB); 1956 addSuccessorWithWeight(SwitchBB, Default); 1957 1958 // Insert the true branch. 1959 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1960 getControlRoot(), Cond, 1961 DAG.getBasicBlock(Small.BB)); 1962 1963 // Insert the false branch. 1964 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1965 DAG.getBasicBlock(Default)); 1966 1967 DAG.setRoot(BrCond); 1968 return true; 1969 } 1970 } 1971 } 1972 1973 // Rearrange the case blocks so that the last one falls through if possible. 1974 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1975 // The last case block won't fall through into 'NextBlock' if we emit the 1976 // branches in this order. See if rearranging a case value would help. 1977 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1978 if (I->BB == NextBlock) { 1979 std::swap(*I, BackCase); 1980 break; 1981 } 1982 } 1983 } 1984 1985 // Create a CaseBlock record representing a conditional branch to 1986 // the Case's target mbb if the value being switched on SV is equal 1987 // to C. 1988 MachineBasicBlock *CurBlock = CR.CaseBB; 1989 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1990 MachineBasicBlock *FallThrough; 1991 if (I != E-1) { 1992 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1993 CurMF->insert(BBI, FallThrough); 1994 1995 // Put SV in a virtual register to make it available from the new blocks. 1996 ExportFromCurrentBlock(SV); 1997 } else { 1998 // If the last case doesn't match, go to the default block. 1999 FallThrough = Default; 2000 } 2001 2002 const Value *RHS, *LHS, *MHS; 2003 ISD::CondCode CC; 2004 if (I->High == I->Low) { 2005 // This is just small small case range :) containing exactly 1 case 2006 CC = ISD::SETEQ; 2007 LHS = SV; RHS = I->High; MHS = NULL; 2008 } else { 2009 CC = ISD::SETLE; 2010 LHS = I->Low; MHS = SV; RHS = I->High; 2011 } 2012 2013 uint32_t ExtraWeight = I->ExtraWeight; 2014 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2015 /* me */ CurBlock, 2016 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 2017 2018 // If emitting the first comparison, just call visitSwitchCase to emit the 2019 // code into the current block. Otherwise, push the CaseBlock onto the 2020 // vector to be later processed by SDISel, and insert the node's MBB 2021 // before the next MBB. 2022 if (CurBlock == SwitchBB) 2023 visitSwitchCase(CB, SwitchBB); 2024 else 2025 SwitchCases.push_back(CB); 2026 2027 CurBlock = FallThrough; 2028 } 2029 2030 return true; 2031} 2032 2033static inline bool areJTsAllowed(const TargetLowering &TLI) { 2034 return !TLI.getTargetMachine().Options.DisableJumpTables && 2035 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2036 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2037} 2038 2039static APInt ComputeRange(const APInt &First, const APInt &Last) { 2040 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2041 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 2042 return (LastExt - FirstExt + 1ULL); 2043} 2044 2045/// handleJTSwitchCase - Emit jumptable for current switch case range 2046bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2047 CaseRecVector &WorkList, 2048 const Value *SV, 2049 MachineBasicBlock *Default, 2050 MachineBasicBlock *SwitchBB) { 2051 Case& FrontCase = *CR.Range.first; 2052 Case& BackCase = *(CR.Range.second-1); 2053 2054 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2055 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2056 2057 APInt TSize(First.getBitWidth(), 0); 2058 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2059 TSize += I->size(); 2060 2061 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2062 return false; 2063 2064 APInt Range = ComputeRange(First, Last); 2065 // The density is TSize / Range. Require at least 40%. 2066 // It should not be possible for IntTSize to saturate for sane code, but make 2067 // sure we handle Range saturation correctly. 2068 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2069 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2070 if (IntTSize * 10 < IntRange * 4) 2071 return false; 2072 2073 DEBUG(dbgs() << "Lowering jump table\n" 2074 << "First entry: " << First << ". Last entry: " << Last << '\n' 2075 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2076 2077 // Get the MachineFunction which holds the current MBB. This is used when 2078 // inserting any additional MBBs necessary to represent the switch. 2079 MachineFunction *CurMF = FuncInfo.MF; 2080 2081 // Figure out which block is immediately after the current one. 2082 MachineFunction::iterator BBI = CR.CaseBB; 2083 ++BBI; 2084 2085 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2086 2087 // Create a new basic block to hold the code for loading the address 2088 // of the jump table, and jumping to it. Update successor information; 2089 // we will either branch to the default case for the switch, or the jump 2090 // table. 2091 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2092 CurMF->insert(BBI, JumpTableBB); 2093 2094 addSuccessorWithWeight(CR.CaseBB, Default); 2095 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2096 2097 // Build a vector of destination BBs, corresponding to each target 2098 // of the jump table. If the value of the jump table slot corresponds to 2099 // a case statement, push the case's BB onto the vector, otherwise, push 2100 // the default BB. 2101 std::vector<MachineBasicBlock*> DestBBs; 2102 APInt TEI = First; 2103 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2104 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2105 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2106 2107 if (Low.sle(TEI) && TEI.sle(High)) { 2108 DestBBs.push_back(I->BB); 2109 if (TEI==High) 2110 ++I; 2111 } else { 2112 DestBBs.push_back(Default); 2113 } 2114 } 2115 2116 // Update successor info. Add one edge to each unique successor. 2117 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2118 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2119 E = DestBBs.end(); I != E; ++I) { 2120 if (!SuccsHandled[(*I)->getNumber()]) { 2121 SuccsHandled[(*I)->getNumber()] = true; 2122 addSuccessorWithWeight(JumpTableBB, *I); 2123 } 2124 } 2125 2126 // Create a jump table index for this jump table. 2127 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2128 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2129 ->createJumpTableIndex(DestBBs); 2130 2131 // Set the jump table information so that we can codegen it as a second 2132 // MachineBasicBlock 2133 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2134 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2135 if (CR.CaseBB == SwitchBB) 2136 visitJumpTableHeader(JT, JTH, SwitchBB); 2137 2138 JTCases.push_back(JumpTableBlock(JTH, JT)); 2139 return true; 2140} 2141 2142/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2143/// 2 subtrees. 2144bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2145 CaseRecVector& WorkList, 2146 const Value* SV, 2147 MachineBasicBlock *Default, 2148 MachineBasicBlock *SwitchBB) { 2149 // Get the MachineFunction which holds the current MBB. This is used when 2150 // inserting any additional MBBs necessary to represent the switch. 2151 MachineFunction *CurMF = FuncInfo.MF; 2152 2153 // Figure out which block is immediately after the current one. 2154 MachineFunction::iterator BBI = CR.CaseBB; 2155 ++BBI; 2156 2157 Case& FrontCase = *CR.Range.first; 2158 Case& BackCase = *(CR.Range.second-1); 2159 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2160 2161 // Size is the number of Cases represented by this range. 2162 unsigned Size = CR.Range.second - CR.Range.first; 2163 2164 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2165 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2166 double FMetric = 0; 2167 CaseItr Pivot = CR.Range.first + Size/2; 2168 2169 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2170 // (heuristically) allow us to emit JumpTable's later. 2171 APInt TSize(First.getBitWidth(), 0); 2172 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2173 I!=E; ++I) 2174 TSize += I->size(); 2175 2176 APInt LSize = FrontCase.size(); 2177 APInt RSize = TSize-LSize; 2178 DEBUG(dbgs() << "Selecting best pivot: \n" 2179 << "First: " << First << ", Last: " << Last <<'\n' 2180 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2181 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2182 J!=E; ++I, ++J) { 2183 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2184 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2185 APInt Range = ComputeRange(LEnd, RBegin); 2186 assert((Range - 2ULL).isNonNegative() && 2187 "Invalid case distance"); 2188 // Use volatile double here to avoid excess precision issues on some hosts, 2189 // e.g. that use 80-bit X87 registers. 2190 volatile double LDensity = 2191 (double)LSize.roundToDouble() / 2192 (LEnd - First + 1ULL).roundToDouble(); 2193 volatile double RDensity = 2194 (double)RSize.roundToDouble() / 2195 (Last - RBegin + 1ULL).roundToDouble(); 2196 double Metric = Range.logBase2()*(LDensity+RDensity); 2197 // Should always split in some non-trivial place 2198 DEBUG(dbgs() <<"=>Step\n" 2199 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2200 << "LDensity: " << LDensity 2201 << ", RDensity: " << RDensity << '\n' 2202 << "Metric: " << Metric << '\n'); 2203 if (FMetric < Metric) { 2204 Pivot = J; 2205 FMetric = Metric; 2206 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2207 } 2208 2209 LSize += J->size(); 2210 RSize -= J->size(); 2211 } 2212 if (areJTsAllowed(TLI)) { 2213 // If our case is dense we *really* should handle it earlier! 2214 assert((FMetric > 0) && "Should handle dense range earlier!"); 2215 } else { 2216 Pivot = CR.Range.first + Size/2; 2217 } 2218 2219 CaseRange LHSR(CR.Range.first, Pivot); 2220 CaseRange RHSR(Pivot, CR.Range.second); 2221 const Constant *C = Pivot->Low; 2222 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2223 2224 // We know that we branch to the LHS if the Value being switched on is 2225 // less than the Pivot value, C. We use this to optimize our binary 2226 // tree a bit, by recognizing that if SV is greater than or equal to the 2227 // LHS's Case Value, and that Case Value is exactly one less than the 2228 // Pivot's Value, then we can branch directly to the LHS's Target, 2229 // rather than creating a leaf node for it. 2230 if ((LHSR.second - LHSR.first) == 1 && 2231 LHSR.first->High == CR.GE && 2232 cast<ConstantInt>(C)->getValue() == 2233 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2234 TrueBB = LHSR.first->BB; 2235 } else { 2236 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2237 CurMF->insert(BBI, TrueBB); 2238 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2239 2240 // Put SV in a virtual register to make it available from the new blocks. 2241 ExportFromCurrentBlock(SV); 2242 } 2243 2244 // Similar to the optimization above, if the Value being switched on is 2245 // known to be less than the Constant CR.LT, and the current Case Value 2246 // is CR.LT - 1, then we can branch directly to the target block for 2247 // the current Case Value, rather than emitting a RHS leaf node for it. 2248 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2249 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2250 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2251 FalseBB = RHSR.first->BB; 2252 } else { 2253 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2254 CurMF->insert(BBI, FalseBB); 2255 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2256 2257 // Put SV in a virtual register to make it available from the new blocks. 2258 ExportFromCurrentBlock(SV); 2259 } 2260 2261 // Create a CaseBlock record representing a conditional branch to 2262 // the LHS node if the value being switched on SV is less than C. 2263 // Otherwise, branch to LHS. 2264 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2265 2266 if (CR.CaseBB == SwitchBB) 2267 visitSwitchCase(CB, SwitchBB); 2268 else 2269 SwitchCases.push_back(CB); 2270 2271 return true; 2272} 2273 2274/// handleBitTestsSwitchCase - if current case range has few destination and 2275/// range span less, than machine word bitwidth, encode case range into series 2276/// of masks and emit bit tests with these masks. 2277bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2278 CaseRecVector& WorkList, 2279 const Value* SV, 2280 MachineBasicBlock* Default, 2281 MachineBasicBlock *SwitchBB){ 2282 EVT PTy = TLI.getPointerTy(); 2283 unsigned IntPtrBits = PTy.getSizeInBits(); 2284 2285 Case& FrontCase = *CR.Range.first; 2286 Case& BackCase = *(CR.Range.second-1); 2287 2288 // Get the MachineFunction which holds the current MBB. This is used when 2289 // inserting any additional MBBs necessary to represent the switch. 2290 MachineFunction *CurMF = FuncInfo.MF; 2291 2292 // If target does not have legal shift left, do not emit bit tests at all. 2293 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2294 return false; 2295 2296 size_t numCmps = 0; 2297 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2298 I!=E; ++I) { 2299 // Single case counts one, case range - two. 2300 numCmps += (I->Low == I->High ? 1 : 2); 2301 } 2302 2303 // Count unique destinations 2304 SmallSet<MachineBasicBlock*, 4> Dests; 2305 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2306 Dests.insert(I->BB); 2307 if (Dests.size() > 3) 2308 // Don't bother the code below, if there are too much unique destinations 2309 return false; 2310 } 2311 DEBUG(dbgs() << "Total number of unique destinations: " 2312 << Dests.size() << '\n' 2313 << "Total number of comparisons: " << numCmps << '\n'); 2314 2315 // Compute span of values. 2316 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2317 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2318 APInt cmpRange = maxValue - minValue; 2319 2320 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2321 << "Low bound: " << minValue << '\n' 2322 << "High bound: " << maxValue << '\n'); 2323 2324 if (cmpRange.uge(IntPtrBits) || 2325 (!(Dests.size() == 1 && numCmps >= 3) && 2326 !(Dests.size() == 2 && numCmps >= 5) && 2327 !(Dests.size() >= 3 && numCmps >= 6))) 2328 return false; 2329 2330 DEBUG(dbgs() << "Emitting bit tests\n"); 2331 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2332 2333 // Optimize the case where all the case values fit in a 2334 // word without having to subtract minValue. In this case, 2335 // we can optimize away the subtraction. 2336 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2337 cmpRange = maxValue; 2338 } else { 2339 lowBound = minValue; 2340 } 2341 2342 CaseBitsVector CasesBits; 2343 unsigned i, count = 0; 2344 2345 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2346 MachineBasicBlock* Dest = I->BB; 2347 for (i = 0; i < count; ++i) 2348 if (Dest == CasesBits[i].BB) 2349 break; 2350 2351 if (i == count) { 2352 assert((count < 3) && "Too much destinations to test!"); 2353 CasesBits.push_back(CaseBits(0, Dest, 0)); 2354 count++; 2355 } 2356 2357 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2358 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2359 2360 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2361 uint64_t hi = (highValue - lowBound).getZExtValue(); 2362 2363 for (uint64_t j = lo; j <= hi; j++) { 2364 CasesBits[i].Mask |= 1ULL << j; 2365 CasesBits[i].Bits++; 2366 } 2367 2368 } 2369 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2370 2371 BitTestInfo BTC; 2372 2373 // Figure out which block is immediately after the current one. 2374 MachineFunction::iterator BBI = CR.CaseBB; 2375 ++BBI; 2376 2377 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2378 2379 DEBUG(dbgs() << "Cases:\n"); 2380 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2381 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2382 << ", Bits: " << CasesBits[i].Bits 2383 << ", BB: " << CasesBits[i].BB << '\n'); 2384 2385 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2386 CurMF->insert(BBI, CaseBB); 2387 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2388 CaseBB, 2389 CasesBits[i].BB)); 2390 2391 // Put SV in a virtual register to make it available from the new blocks. 2392 ExportFromCurrentBlock(SV); 2393 } 2394 2395 BitTestBlock BTB(lowBound, cmpRange, SV, 2396 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2397 CR.CaseBB, Default, BTC); 2398 2399 if (CR.CaseBB == SwitchBB) 2400 visitBitTestHeader(BTB, SwitchBB); 2401 2402 BitTestCases.push_back(BTB); 2403 2404 return true; 2405} 2406 2407/// Clusterify - Transform simple list of Cases into list of CaseRange's 2408size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2409 const SwitchInst& SI) { 2410 size_t numCmps = 0; 2411 2412 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2413 // Start with "simple" cases 2414 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2415 i != e; ++i) { 2416 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2417 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2418 2419 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0; 2420 2421 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(), 2422 SMBB, ExtraWeight)); 2423 } 2424 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2425 2426 // Merge case into clusters 2427 if (Cases.size() >= 2) 2428 // Must recompute end() each iteration because it may be 2429 // invalidated by erase if we hold on to it 2430 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2431 J != Cases.end(); ) { 2432 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2433 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2434 MachineBasicBlock* nextBB = J->BB; 2435 MachineBasicBlock* currentBB = I->BB; 2436 2437 // If the two neighboring cases go to the same destination, merge them 2438 // into a single case. 2439 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2440 I->High = J->High; 2441 J = Cases.erase(J); 2442 2443 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) { 2444 uint32_t CurWeight = currentBB->getBasicBlock() ? 2445 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16; 2446 uint32_t NextWeight = nextBB->getBasicBlock() ? 2447 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16; 2448 2449 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(), 2450 CurWeight + NextWeight); 2451 } 2452 } else { 2453 I = J++; 2454 } 2455 } 2456 2457 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2458 if (I->Low != I->High) 2459 // A range counts double, since it requires two compares. 2460 ++numCmps; 2461 } 2462 2463 return numCmps; 2464} 2465 2466void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2467 MachineBasicBlock *Last) { 2468 // Update JTCases. 2469 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2470 if (JTCases[i].first.HeaderBB == First) 2471 JTCases[i].first.HeaderBB = Last; 2472 2473 // Update BitTestCases. 2474 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2475 if (BitTestCases[i].Parent == First) 2476 BitTestCases[i].Parent = Last; 2477} 2478 2479void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2480 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2481 2482 // Figure out which block is immediately after the current one. 2483 MachineBasicBlock *NextBlock = 0; 2484 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2485 2486 // If there is only the default destination, branch to it if it is not the 2487 // next basic block. Otherwise, just fall through. 2488 if (!SI.getNumCases()) { 2489 // Update machine-CFG edges. 2490 2491 // If this is not a fall-through branch, emit the branch. 2492 SwitchMBB->addSuccessor(Default); 2493 if (Default != NextBlock) 2494 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2495 MVT::Other, getControlRoot(), 2496 DAG.getBasicBlock(Default))); 2497 2498 return; 2499 } 2500 2501 // If there are any non-default case statements, create a vector of Cases 2502 // representing each one, and sort the vector so that we can efficiently 2503 // create a binary search tree from them. 2504 CaseVector Cases; 2505 size_t numCmps = Clusterify(Cases, SI); 2506 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2507 << ". Total compares: " << numCmps << '\n'); 2508 (void)numCmps; 2509 2510 // Get the Value to be switched on and default basic blocks, which will be 2511 // inserted into CaseBlock records, representing basic blocks in the binary 2512 // search tree. 2513 const Value *SV = SI.getCondition(); 2514 2515 // Push the initial CaseRec onto the worklist 2516 CaseRecVector WorkList; 2517 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2518 CaseRange(Cases.begin(),Cases.end()))); 2519 2520 while (!WorkList.empty()) { 2521 // Grab a record representing a case range to process off the worklist 2522 CaseRec CR = WorkList.back(); 2523 WorkList.pop_back(); 2524 2525 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2526 continue; 2527 2528 // If the range has few cases (two or less) emit a series of specific 2529 // tests. 2530 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2531 continue; 2532 2533 // If the switch has more than 5 blocks, and at least 40% dense, and the 2534 // target supports indirect branches, then emit a jump table rather than 2535 // lowering the switch to a binary tree of conditional branches. 2536 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2537 continue; 2538 2539 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2540 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2541 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2542 } 2543} 2544 2545void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2546 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2547 2548 // Update machine-CFG edges with unique successors. 2549 SmallVector<BasicBlock*, 32> succs; 2550 succs.reserve(I.getNumSuccessors()); 2551 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2552 succs.push_back(I.getSuccessor(i)); 2553 array_pod_sort(succs.begin(), succs.end()); 2554 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2555 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2556 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2557 addSuccessorWithWeight(IndirectBrMBB, Succ); 2558 } 2559 2560 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2561 MVT::Other, getControlRoot(), 2562 getValue(I.getAddress()))); 2563} 2564 2565void SelectionDAGBuilder::visitFSub(const User &I) { 2566 // -0.0 - X --> fneg 2567 Type *Ty = I.getType(); 2568 if (isa<Constant>(I.getOperand(0)) && 2569 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2570 SDValue Op2 = getValue(I.getOperand(1)); 2571 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2572 Op2.getValueType(), Op2)); 2573 return; 2574 } 2575 2576 visitBinary(I, ISD::FSUB); 2577} 2578 2579void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2580 SDValue Op1 = getValue(I.getOperand(0)); 2581 SDValue Op2 = getValue(I.getOperand(1)); 2582 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2583 Op1.getValueType(), Op1, Op2)); 2584} 2585 2586void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2587 SDValue Op1 = getValue(I.getOperand(0)); 2588 SDValue Op2 = getValue(I.getOperand(1)); 2589 2590 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2591 2592 // Coerce the shift amount to the right type if we can. 2593 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2594 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2595 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2596 DebugLoc DL = getCurDebugLoc(); 2597 2598 // If the operand is smaller than the shift count type, promote it. 2599 if (ShiftSize > Op2Size) 2600 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2601 2602 // If the operand is larger than the shift count type but the shift 2603 // count type has enough bits to represent any shift value, truncate 2604 // it now. This is a common case and it exposes the truncate to 2605 // optimization early. 2606 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2607 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2608 // Otherwise we'll need to temporarily settle for some other convenient 2609 // type. Type legalization will make adjustments once the shiftee is split. 2610 else 2611 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2612 } 2613 2614 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2615 Op1.getValueType(), Op1, Op2)); 2616} 2617 2618void SelectionDAGBuilder::visitSDiv(const User &I) { 2619 SDValue Op1 = getValue(I.getOperand(0)); 2620 SDValue Op2 = getValue(I.getOperand(1)); 2621 2622 // Turn exact SDivs into multiplications. 2623 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2624 // exact bit. 2625 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2626 !isa<ConstantSDNode>(Op1) && 2627 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2628 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2629 else 2630 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2631 Op1, Op2)); 2632} 2633 2634void SelectionDAGBuilder::visitICmp(const User &I) { 2635 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2636 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2637 predicate = IC->getPredicate(); 2638 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2639 predicate = ICmpInst::Predicate(IC->getPredicate()); 2640 SDValue Op1 = getValue(I.getOperand(0)); 2641 SDValue Op2 = getValue(I.getOperand(1)); 2642 ISD::CondCode Opcode = getICmpCondCode(predicate); 2643 2644 EVT DestVT = TLI.getValueType(I.getType()); 2645 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2646} 2647 2648void SelectionDAGBuilder::visitFCmp(const User &I) { 2649 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2650 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2651 predicate = FC->getPredicate(); 2652 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2653 predicate = FCmpInst::Predicate(FC->getPredicate()); 2654 SDValue Op1 = getValue(I.getOperand(0)); 2655 SDValue Op2 = getValue(I.getOperand(1)); 2656 ISD::CondCode Condition = getFCmpCondCode(predicate); 2657 if (TM.Options.NoNaNsFPMath) 2658 Condition = getFCmpCodeWithoutNaN(Condition); 2659 EVT DestVT = TLI.getValueType(I.getType()); 2660 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2661} 2662 2663void SelectionDAGBuilder::visitSelect(const User &I) { 2664 SmallVector<EVT, 4> ValueVTs; 2665 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2666 unsigned NumValues = ValueVTs.size(); 2667 if (NumValues == 0) return; 2668 2669 SmallVector<SDValue, 4> Values(NumValues); 2670 SDValue Cond = getValue(I.getOperand(0)); 2671 SDValue TrueVal = getValue(I.getOperand(1)); 2672 SDValue FalseVal = getValue(I.getOperand(2)); 2673 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2674 ISD::VSELECT : ISD::SELECT; 2675 2676 for (unsigned i = 0; i != NumValues; ++i) 2677 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2678 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2679 Cond, 2680 SDValue(TrueVal.getNode(), 2681 TrueVal.getResNo() + i), 2682 SDValue(FalseVal.getNode(), 2683 FalseVal.getResNo() + i)); 2684 2685 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2686 DAG.getVTList(&ValueVTs[0], NumValues), 2687 &Values[0], NumValues)); 2688} 2689 2690void SelectionDAGBuilder::visitTrunc(const User &I) { 2691 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2692 SDValue N = getValue(I.getOperand(0)); 2693 EVT DestVT = TLI.getValueType(I.getType()); 2694 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2695} 2696 2697void SelectionDAGBuilder::visitZExt(const User &I) { 2698 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2699 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2700 SDValue N = getValue(I.getOperand(0)); 2701 EVT DestVT = TLI.getValueType(I.getType()); 2702 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2703} 2704 2705void SelectionDAGBuilder::visitSExt(const User &I) { 2706 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2707 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2708 SDValue N = getValue(I.getOperand(0)); 2709 EVT DestVT = TLI.getValueType(I.getType()); 2710 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2711} 2712 2713void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2714 // FPTrunc is never a no-op cast, no need to check 2715 SDValue N = getValue(I.getOperand(0)); 2716 EVT DestVT = TLI.getValueType(I.getType()); 2717 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2718 DestVT, N, 2719 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2720} 2721 2722void SelectionDAGBuilder::visitFPExt(const User &I){ 2723 // FPExt is never a no-op cast, no need to check 2724 SDValue N = getValue(I.getOperand(0)); 2725 EVT DestVT = TLI.getValueType(I.getType()); 2726 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2727} 2728 2729void SelectionDAGBuilder::visitFPToUI(const User &I) { 2730 // FPToUI is never a no-op cast, no need to check 2731 SDValue N = getValue(I.getOperand(0)); 2732 EVT DestVT = TLI.getValueType(I.getType()); 2733 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2734} 2735 2736void SelectionDAGBuilder::visitFPToSI(const User &I) { 2737 // FPToSI is never a no-op cast, no need to check 2738 SDValue N = getValue(I.getOperand(0)); 2739 EVT DestVT = TLI.getValueType(I.getType()); 2740 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2741} 2742 2743void SelectionDAGBuilder::visitUIToFP(const User &I) { 2744 // UIToFP is never a no-op cast, no need to check 2745 SDValue N = getValue(I.getOperand(0)); 2746 EVT DestVT = TLI.getValueType(I.getType()); 2747 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2748} 2749 2750void SelectionDAGBuilder::visitSIToFP(const User &I){ 2751 // SIToFP is never a no-op cast, no need to check 2752 SDValue N = getValue(I.getOperand(0)); 2753 EVT DestVT = TLI.getValueType(I.getType()); 2754 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2755} 2756 2757void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2758 // What to do depends on the size of the integer and the size of the pointer. 2759 // We can either truncate, zero extend, or no-op, accordingly. 2760 SDValue N = getValue(I.getOperand(0)); 2761 EVT DestVT = TLI.getValueType(I.getType()); 2762 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2763} 2764 2765void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2766 // What to do depends on the size of the integer and the size of the pointer. 2767 // We can either truncate, zero extend, or no-op, accordingly. 2768 SDValue N = getValue(I.getOperand(0)); 2769 EVT DestVT = TLI.getValueType(I.getType()); 2770 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2771} 2772 2773void SelectionDAGBuilder::visitBitCast(const User &I) { 2774 SDValue N = getValue(I.getOperand(0)); 2775 EVT DestVT = TLI.getValueType(I.getType()); 2776 2777 // BitCast assures us that source and destination are the same size so this is 2778 // either a BITCAST or a no-op. 2779 if (DestVT != N.getValueType()) 2780 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2781 DestVT, N)); // convert types. 2782 else 2783 setValue(&I, N); // noop cast. 2784} 2785 2786void SelectionDAGBuilder::visitInsertElement(const User &I) { 2787 SDValue InVec = getValue(I.getOperand(0)); 2788 SDValue InVal = getValue(I.getOperand(1)); 2789 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2790 TLI.getPointerTy(), 2791 getValue(I.getOperand(2))); 2792 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2793 TLI.getValueType(I.getType()), 2794 InVec, InVal, InIdx)); 2795} 2796 2797void SelectionDAGBuilder::visitExtractElement(const User &I) { 2798 SDValue InVec = getValue(I.getOperand(0)); 2799 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2800 TLI.getPointerTy(), 2801 getValue(I.getOperand(1))); 2802 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2803 TLI.getValueType(I.getType()), InVec, InIdx)); 2804} 2805 2806// Utility for visitShuffleVector - Return true if every element in Mask, 2807// begining from position Pos and ending in Pos+Size, falls within the 2808// specified sequential range [L, L+Pos). or is undef. 2809static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2810 unsigned Pos, unsigned Size, int Low) { 2811 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2812 if (Mask[i] >= 0 && Mask[i] != Low) 2813 return false; 2814 return true; 2815} 2816 2817void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2818 SDValue Src1 = getValue(I.getOperand(0)); 2819 SDValue Src2 = getValue(I.getOperand(1)); 2820 2821 SmallVector<int, 8> Mask; 2822 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2823 unsigned MaskNumElts = Mask.size(); 2824 2825 EVT VT = TLI.getValueType(I.getType()); 2826 EVT SrcVT = Src1.getValueType(); 2827 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2828 2829 if (SrcNumElts == MaskNumElts) { 2830 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2831 &Mask[0])); 2832 return; 2833 } 2834 2835 // Normalize the shuffle vector since mask and vector length don't match. 2836 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2837 // Mask is longer than the source vectors and is a multiple of the source 2838 // vectors. We can use concatenate vector to make the mask and vectors 2839 // lengths match. 2840 if (SrcNumElts*2 == MaskNumElts) { 2841 // First check for Src1 in low and Src2 in high 2842 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2843 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2844 // The shuffle is concatenating two vectors together. 2845 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2846 VT, Src1, Src2)); 2847 return; 2848 } 2849 // Then check for Src2 in low and Src1 in high 2850 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2851 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2852 // The shuffle is concatenating two vectors together. 2853 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2854 VT, Src2, Src1)); 2855 return; 2856 } 2857 } 2858 2859 // Pad both vectors with undefs to make them the same length as the mask. 2860 unsigned NumConcat = MaskNumElts / SrcNumElts; 2861 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2862 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2863 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2864 2865 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2866 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2867 MOps1[0] = Src1; 2868 MOps2[0] = Src2; 2869 2870 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2871 getCurDebugLoc(), VT, 2872 &MOps1[0], NumConcat); 2873 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2874 getCurDebugLoc(), VT, 2875 &MOps2[0], NumConcat); 2876 2877 // Readjust mask for new input vector length. 2878 SmallVector<int, 8> MappedOps; 2879 for (unsigned i = 0; i != MaskNumElts; ++i) { 2880 int Idx = Mask[i]; 2881 if (Idx >= (int)SrcNumElts) 2882 Idx -= SrcNumElts - MaskNumElts; 2883 MappedOps.push_back(Idx); 2884 } 2885 2886 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2887 &MappedOps[0])); 2888 return; 2889 } 2890 2891 if (SrcNumElts > MaskNumElts) { 2892 // Analyze the access pattern of the vector to see if we can extract 2893 // two subvectors and do the shuffle. The analysis is done by calculating 2894 // the range of elements the mask access on both vectors. 2895 int MinRange[2] = { static_cast<int>(SrcNumElts), 2896 static_cast<int>(SrcNumElts)}; 2897 int MaxRange[2] = {-1, -1}; 2898 2899 for (unsigned i = 0; i != MaskNumElts; ++i) { 2900 int Idx = Mask[i]; 2901 unsigned Input = 0; 2902 if (Idx < 0) 2903 continue; 2904 2905 if (Idx >= (int)SrcNumElts) { 2906 Input = 1; 2907 Idx -= SrcNumElts; 2908 } 2909 if (Idx > MaxRange[Input]) 2910 MaxRange[Input] = Idx; 2911 if (Idx < MinRange[Input]) 2912 MinRange[Input] = Idx; 2913 } 2914 2915 // Check if the access is smaller than the vector size and can we find 2916 // a reasonable extract index. 2917 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 2918 // Extract. 2919 int StartIdx[2]; // StartIdx to extract from 2920 for (unsigned Input = 0; Input < 2; ++Input) { 2921 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 2922 RangeUse[Input] = 0; // Unused 2923 StartIdx[Input] = 0; 2924 continue; 2925 } 2926 2927 // Find a good start index that is a multiple of the mask length. Then 2928 // see if the rest of the elements are in range. 2929 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2930 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2931 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2932 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2933 } 2934 2935 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2936 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2937 return; 2938 } 2939 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 2940 // Extract appropriate subvector and generate a vector shuffle 2941 for (unsigned Input = 0; Input < 2; ++Input) { 2942 SDValue &Src = Input == 0 ? Src1 : Src2; 2943 if (RangeUse[Input] == 0) 2944 Src = DAG.getUNDEF(VT); 2945 else 2946 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2947 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2948 } 2949 2950 // Calculate new mask. 2951 SmallVector<int, 8> MappedOps; 2952 for (unsigned i = 0; i != MaskNumElts; ++i) { 2953 int Idx = Mask[i]; 2954 if (Idx >= 0) { 2955 if (Idx < (int)SrcNumElts) 2956 Idx -= StartIdx[0]; 2957 else 2958 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 2959 } 2960 MappedOps.push_back(Idx); 2961 } 2962 2963 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2964 &MappedOps[0])); 2965 return; 2966 } 2967 } 2968 2969 // We can't use either concat vectors or extract subvectors so fall back to 2970 // replacing the shuffle with extract and build vector. 2971 // to insert and build vector. 2972 EVT EltVT = VT.getVectorElementType(); 2973 EVT PtrVT = TLI.getPointerTy(); 2974 SmallVector<SDValue,8> Ops; 2975 for (unsigned i = 0; i != MaskNumElts; ++i) { 2976 int Idx = Mask[i]; 2977 SDValue Res; 2978 2979 if (Idx < 0) { 2980 Res = DAG.getUNDEF(EltVT); 2981 } else { 2982 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 2983 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 2984 2985 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2986 EltVT, Src, DAG.getConstant(Idx, PtrVT)); 2987 } 2988 2989 Ops.push_back(Res); 2990 } 2991 2992 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2993 VT, &Ops[0], Ops.size())); 2994} 2995 2996void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2997 const Value *Op0 = I.getOperand(0); 2998 const Value *Op1 = I.getOperand(1); 2999 Type *AggTy = I.getType(); 3000 Type *ValTy = Op1->getType(); 3001 bool IntoUndef = isa<UndefValue>(Op0); 3002 bool FromUndef = isa<UndefValue>(Op1); 3003 3004 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3005 3006 SmallVector<EVT, 4> AggValueVTs; 3007 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3008 SmallVector<EVT, 4> ValValueVTs; 3009 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3010 3011 unsigned NumAggValues = AggValueVTs.size(); 3012 unsigned NumValValues = ValValueVTs.size(); 3013 SmallVector<SDValue, 4> Values(NumAggValues); 3014 3015 SDValue Agg = getValue(Op0); 3016 unsigned i = 0; 3017 // Copy the beginning value(s) from the original aggregate. 3018 for (; i != LinearIndex; ++i) 3019 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3020 SDValue(Agg.getNode(), Agg.getResNo() + i); 3021 // Copy values from the inserted value(s). 3022 if (NumValValues) { 3023 SDValue Val = getValue(Op1); 3024 for (; i != LinearIndex + NumValValues; ++i) 3025 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3026 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3027 } 3028 // Copy remaining value(s) from the original aggregate. 3029 for (; i != NumAggValues; ++i) 3030 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3031 SDValue(Agg.getNode(), Agg.getResNo() + i); 3032 3033 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3034 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3035 &Values[0], NumAggValues)); 3036} 3037 3038void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3039 const Value *Op0 = I.getOperand(0); 3040 Type *AggTy = Op0->getType(); 3041 Type *ValTy = I.getType(); 3042 bool OutOfUndef = isa<UndefValue>(Op0); 3043 3044 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3045 3046 SmallVector<EVT, 4> ValValueVTs; 3047 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3048 3049 unsigned NumValValues = ValValueVTs.size(); 3050 3051 // Ignore a extractvalue that produces an empty object 3052 if (!NumValValues) { 3053 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3054 return; 3055 } 3056 3057 SmallVector<SDValue, 4> Values(NumValValues); 3058 3059 SDValue Agg = getValue(Op0); 3060 // Copy out the selected value(s). 3061 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3062 Values[i - LinearIndex] = 3063 OutOfUndef ? 3064 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3065 SDValue(Agg.getNode(), Agg.getResNo() + i); 3066 3067 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3068 DAG.getVTList(&ValValueVTs[0], NumValValues), 3069 &Values[0], NumValValues)); 3070} 3071 3072void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3073 SDValue N = getValue(I.getOperand(0)); 3074 // Note that the pointer operand may be a vector of pointers. Take the scalar 3075 // element which holds a pointer. 3076 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3077 3078 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3079 OI != E; ++OI) { 3080 const Value *Idx = *OI; 3081 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3082 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3083 if (Field) { 3084 // N = N + Offset 3085 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3086 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3087 DAG.getIntPtrConstant(Offset)); 3088 } 3089 3090 Ty = StTy->getElementType(Field); 3091 } else { 3092 Ty = cast<SequentialType>(Ty)->getElementType(); 3093 3094 // If this is a constant subscript, handle it quickly. 3095 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3096 if (CI->isZero()) continue; 3097 uint64_t Offs = 3098 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3099 SDValue OffsVal; 3100 EVT PTy = TLI.getPointerTy(); 3101 unsigned PtrBits = PTy.getSizeInBits(); 3102 if (PtrBits < 64) 3103 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3104 TLI.getPointerTy(), 3105 DAG.getConstant(Offs, MVT::i64)); 3106 else 3107 OffsVal = DAG.getIntPtrConstant(Offs); 3108 3109 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3110 OffsVal); 3111 continue; 3112 } 3113 3114 // N = N + Idx * ElementSize; 3115 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3116 TD->getTypeAllocSize(Ty)); 3117 SDValue IdxN = getValue(Idx); 3118 3119 // If the index is smaller or larger than intptr_t, truncate or extend 3120 // it. 3121 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3122 3123 // If this is a multiply by a power of two, turn it into a shl 3124 // immediately. This is a very common case. 3125 if (ElementSize != 1) { 3126 if (ElementSize.isPowerOf2()) { 3127 unsigned Amt = ElementSize.logBase2(); 3128 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3129 N.getValueType(), IdxN, 3130 DAG.getConstant(Amt, IdxN.getValueType())); 3131 } else { 3132 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3133 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3134 N.getValueType(), IdxN, Scale); 3135 } 3136 } 3137 3138 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3139 N.getValueType(), N, IdxN); 3140 } 3141 } 3142 3143 setValue(&I, N); 3144} 3145 3146void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3147 // If this is a fixed sized alloca in the entry block of the function, 3148 // allocate it statically on the stack. 3149 if (FuncInfo.StaticAllocaMap.count(&I)) 3150 return; // getValue will auto-populate this. 3151 3152 Type *Ty = I.getAllocatedType(); 3153 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3154 unsigned Align = 3155 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3156 I.getAlignment()); 3157 3158 SDValue AllocSize = getValue(I.getArraySize()); 3159 3160 EVT IntPtr = TLI.getPointerTy(); 3161 if (AllocSize.getValueType() != IntPtr) 3162 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3163 3164 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3165 AllocSize, 3166 DAG.getConstant(TySize, IntPtr)); 3167 3168 // Handle alignment. If the requested alignment is less than or equal to 3169 // the stack alignment, ignore it. If the size is greater than or equal to 3170 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3171 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3172 if (Align <= StackAlign) 3173 Align = 0; 3174 3175 // Round the size of the allocation up to the stack alignment size 3176 // by add SA-1 to the size. 3177 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3178 AllocSize.getValueType(), AllocSize, 3179 DAG.getIntPtrConstant(StackAlign-1)); 3180 3181 // Mask out the low bits for alignment purposes. 3182 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3183 AllocSize.getValueType(), AllocSize, 3184 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3185 3186 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3187 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3188 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3189 VTs, Ops, 3); 3190 setValue(&I, DSA); 3191 DAG.setRoot(DSA.getValue(1)); 3192 3193 // Inform the Frame Information that we have just allocated a variable-sized 3194 // object. 3195 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3196} 3197 3198void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3199 if (I.isAtomic()) 3200 return visitAtomicLoad(I); 3201 3202 const Value *SV = I.getOperand(0); 3203 SDValue Ptr = getValue(SV); 3204 3205 Type *Ty = I.getType(); 3206 3207 bool isVolatile = I.isVolatile(); 3208 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3209 bool isInvariant = I.getMetadata("invariant.load") != 0; 3210 unsigned Alignment = I.getAlignment(); 3211 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3212 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3213 3214 SmallVector<EVT, 4> ValueVTs; 3215 SmallVector<uint64_t, 4> Offsets; 3216 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3217 unsigned NumValues = ValueVTs.size(); 3218 if (NumValues == 0) 3219 return; 3220 3221 SDValue Root; 3222 bool ConstantMemory = false; 3223 if (I.isVolatile() || NumValues > MaxParallelChains) 3224 // Serialize volatile loads with other side effects. 3225 Root = getRoot(); 3226 else if (AA->pointsToConstantMemory( 3227 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3228 // Do not serialize (non-volatile) loads of constant memory with anything. 3229 Root = DAG.getEntryNode(); 3230 ConstantMemory = true; 3231 } else { 3232 // Do not serialize non-volatile loads against each other. 3233 Root = DAG.getRoot(); 3234 } 3235 3236 SmallVector<SDValue, 4> Values(NumValues); 3237 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3238 NumValues)); 3239 EVT PtrVT = Ptr.getValueType(); 3240 unsigned ChainI = 0; 3241 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3242 // Serializing loads here may result in excessive register pressure, and 3243 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3244 // could recover a bit by hoisting nodes upward in the chain by recognizing 3245 // they are side-effect free or do not alias. The optimizer should really 3246 // avoid this case by converting large object/array copies to llvm.memcpy 3247 // (MaxParallelChains should always remain as failsafe). 3248 if (ChainI == MaxParallelChains) { 3249 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3250 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3251 MVT::Other, &Chains[0], ChainI); 3252 Root = Chain; 3253 ChainI = 0; 3254 } 3255 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3256 PtrVT, Ptr, 3257 DAG.getConstant(Offsets[i], PtrVT)); 3258 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3259 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3260 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3261 Ranges); 3262 3263 Values[i] = L; 3264 Chains[ChainI] = L.getValue(1); 3265 } 3266 3267 if (!ConstantMemory) { 3268 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3269 MVT::Other, &Chains[0], ChainI); 3270 if (isVolatile) 3271 DAG.setRoot(Chain); 3272 else 3273 PendingLoads.push_back(Chain); 3274 } 3275 3276 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3277 DAG.getVTList(&ValueVTs[0], NumValues), 3278 &Values[0], NumValues)); 3279} 3280 3281void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3282 if (I.isAtomic()) 3283 return visitAtomicStore(I); 3284 3285 const Value *SrcV = I.getOperand(0); 3286 const Value *PtrV = I.getOperand(1); 3287 3288 SmallVector<EVT, 4> ValueVTs; 3289 SmallVector<uint64_t, 4> Offsets; 3290 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3291 unsigned NumValues = ValueVTs.size(); 3292 if (NumValues == 0) 3293 return; 3294 3295 // Get the lowered operands. Note that we do this after 3296 // checking if NumResults is zero, because with zero results 3297 // the operands won't have values in the map. 3298 SDValue Src = getValue(SrcV); 3299 SDValue Ptr = getValue(PtrV); 3300 3301 SDValue Root = getRoot(); 3302 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3303 NumValues)); 3304 EVT PtrVT = Ptr.getValueType(); 3305 bool isVolatile = I.isVolatile(); 3306 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3307 unsigned Alignment = I.getAlignment(); 3308 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3309 3310 unsigned ChainI = 0; 3311 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3312 // See visitLoad comments. 3313 if (ChainI == MaxParallelChains) { 3314 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3315 MVT::Other, &Chains[0], ChainI); 3316 Root = Chain; 3317 ChainI = 0; 3318 } 3319 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3320 DAG.getConstant(Offsets[i], PtrVT)); 3321 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3322 SDValue(Src.getNode(), Src.getResNo() + i), 3323 Add, MachinePointerInfo(PtrV, Offsets[i]), 3324 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3325 Chains[ChainI] = St; 3326 } 3327 3328 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3329 MVT::Other, &Chains[0], ChainI); 3330 ++SDNodeOrder; 3331 AssignOrderingToNode(StoreNode.getNode()); 3332 DAG.setRoot(StoreNode); 3333} 3334 3335static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3336 SynchronizationScope Scope, 3337 bool Before, DebugLoc dl, 3338 SelectionDAG &DAG, 3339 const TargetLowering &TLI) { 3340 // Fence, if necessary 3341 if (Before) { 3342 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3343 Order = Release; 3344 else if (Order == Acquire || Order == Monotonic) 3345 return Chain; 3346 } else { 3347 if (Order == AcquireRelease) 3348 Order = Acquire; 3349 else if (Order == Release || Order == Monotonic) 3350 return Chain; 3351 } 3352 SDValue Ops[3]; 3353 Ops[0] = Chain; 3354 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3355 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3356 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3357} 3358 3359void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3360 DebugLoc dl = getCurDebugLoc(); 3361 AtomicOrdering Order = I.getOrdering(); 3362 SynchronizationScope Scope = I.getSynchScope(); 3363 3364 SDValue InChain = getRoot(); 3365 3366 if (TLI.getInsertFencesForAtomic()) 3367 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3368 DAG, TLI); 3369 3370 SDValue L = 3371 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3372 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3373 InChain, 3374 getValue(I.getPointerOperand()), 3375 getValue(I.getCompareOperand()), 3376 getValue(I.getNewValOperand()), 3377 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3378 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3379 Scope); 3380 3381 SDValue OutChain = L.getValue(1); 3382 3383 if (TLI.getInsertFencesForAtomic()) 3384 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3385 DAG, TLI); 3386 3387 setValue(&I, L); 3388 DAG.setRoot(OutChain); 3389} 3390 3391void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3392 DebugLoc dl = getCurDebugLoc(); 3393 ISD::NodeType NT; 3394 switch (I.getOperation()) { 3395 default: llvm_unreachable("Unknown atomicrmw operation"); 3396 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3397 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3398 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3399 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3400 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3401 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3402 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3403 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3404 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3405 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3406 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3407 } 3408 AtomicOrdering Order = I.getOrdering(); 3409 SynchronizationScope Scope = I.getSynchScope(); 3410 3411 SDValue InChain = getRoot(); 3412 3413 if (TLI.getInsertFencesForAtomic()) 3414 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3415 DAG, TLI); 3416 3417 SDValue L = 3418 DAG.getAtomic(NT, dl, 3419 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3420 InChain, 3421 getValue(I.getPointerOperand()), 3422 getValue(I.getValOperand()), 3423 I.getPointerOperand(), 0 /* Alignment */, 3424 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3425 Scope); 3426 3427 SDValue OutChain = L.getValue(1); 3428 3429 if (TLI.getInsertFencesForAtomic()) 3430 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3431 DAG, TLI); 3432 3433 setValue(&I, L); 3434 DAG.setRoot(OutChain); 3435} 3436 3437void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3438 DebugLoc dl = getCurDebugLoc(); 3439 SDValue Ops[3]; 3440 Ops[0] = getRoot(); 3441 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3442 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3443 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3444} 3445 3446void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3447 DebugLoc dl = getCurDebugLoc(); 3448 AtomicOrdering Order = I.getOrdering(); 3449 SynchronizationScope Scope = I.getSynchScope(); 3450 3451 SDValue InChain = getRoot(); 3452 3453 EVT VT = EVT::getEVT(I.getType()); 3454 3455 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3456 report_fatal_error("Cannot generate unaligned atomic load"); 3457 3458 SDValue L = 3459 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3460 getValue(I.getPointerOperand()), 3461 I.getPointerOperand(), I.getAlignment(), 3462 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3463 Scope); 3464 3465 SDValue OutChain = L.getValue(1); 3466 3467 if (TLI.getInsertFencesForAtomic()) 3468 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3469 DAG, TLI); 3470 3471 setValue(&I, L); 3472 DAG.setRoot(OutChain); 3473} 3474 3475void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3476 DebugLoc dl = getCurDebugLoc(); 3477 3478 AtomicOrdering Order = I.getOrdering(); 3479 SynchronizationScope Scope = I.getSynchScope(); 3480 3481 SDValue InChain = getRoot(); 3482 3483 EVT VT = EVT::getEVT(I.getValueOperand()->getType()); 3484 3485 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3486 report_fatal_error("Cannot generate unaligned atomic store"); 3487 3488 if (TLI.getInsertFencesForAtomic()) 3489 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3490 DAG, TLI); 3491 3492 SDValue OutChain = 3493 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3494 InChain, 3495 getValue(I.getPointerOperand()), 3496 getValue(I.getValueOperand()), 3497 I.getPointerOperand(), I.getAlignment(), 3498 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3499 Scope); 3500 3501 if (TLI.getInsertFencesForAtomic()) 3502 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3503 DAG, TLI); 3504 3505 DAG.setRoot(OutChain); 3506} 3507 3508/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3509/// node. 3510void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3511 unsigned Intrinsic) { 3512 bool HasChain = !I.doesNotAccessMemory(); 3513 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3514 3515 // Build the operand list. 3516 SmallVector<SDValue, 8> Ops; 3517 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3518 if (OnlyLoad) { 3519 // We don't need to serialize loads against other loads. 3520 Ops.push_back(DAG.getRoot()); 3521 } else { 3522 Ops.push_back(getRoot()); 3523 } 3524 } 3525 3526 // Info is set by getTgtMemInstrinsic 3527 TargetLowering::IntrinsicInfo Info; 3528 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3529 3530 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3531 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3532 Info.opc == ISD::INTRINSIC_W_CHAIN) 3533 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3534 3535 // Add all operands of the call to the operand list. 3536 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3537 SDValue Op = getValue(I.getArgOperand(i)); 3538 Ops.push_back(Op); 3539 } 3540 3541 SmallVector<EVT, 4> ValueVTs; 3542 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3543 3544 if (HasChain) 3545 ValueVTs.push_back(MVT::Other); 3546 3547 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3548 3549 // Create the node. 3550 SDValue Result; 3551 if (IsTgtIntrinsic) { 3552 // This is target intrinsic that touches memory 3553 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3554 VTs, &Ops[0], Ops.size(), 3555 Info.memVT, 3556 MachinePointerInfo(Info.ptrVal, Info.offset), 3557 Info.align, Info.vol, 3558 Info.readMem, Info.writeMem); 3559 } else if (!HasChain) { 3560 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3561 VTs, &Ops[0], Ops.size()); 3562 } else if (!I.getType()->isVoidTy()) { 3563 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3564 VTs, &Ops[0], Ops.size()); 3565 } else { 3566 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3567 VTs, &Ops[0], Ops.size()); 3568 } 3569 3570 if (HasChain) { 3571 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3572 if (OnlyLoad) 3573 PendingLoads.push_back(Chain); 3574 else 3575 DAG.setRoot(Chain); 3576 } 3577 3578 if (!I.getType()->isVoidTy()) { 3579 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3580 EVT VT = TLI.getValueType(PTy); 3581 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3582 } 3583 3584 setValue(&I, Result); 3585 } else { 3586 // Assign order to result here. If the intrinsic does not produce a result, 3587 // it won't be mapped to a SDNode and visit() will not assign it an order 3588 // number. 3589 ++SDNodeOrder; 3590 AssignOrderingToNode(Result.getNode()); 3591 } 3592} 3593 3594/// GetSignificand - Get the significand and build it into a floating-point 3595/// number with exponent of 1: 3596/// 3597/// Op = (Op & 0x007fffff) | 0x3f800000; 3598/// 3599/// where Op is the hexidecimal representation of floating point value. 3600static SDValue 3601GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3602 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3603 DAG.getConstant(0x007fffff, MVT::i32)); 3604 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3605 DAG.getConstant(0x3f800000, MVT::i32)); 3606 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3607} 3608 3609/// GetExponent - Get the exponent: 3610/// 3611/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3612/// 3613/// where Op is the hexidecimal representation of floating point value. 3614static SDValue 3615GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3616 DebugLoc dl) { 3617 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3618 DAG.getConstant(0x7f800000, MVT::i32)); 3619 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3620 DAG.getConstant(23, TLI.getPointerTy())); 3621 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3622 DAG.getConstant(127, MVT::i32)); 3623 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3624} 3625 3626/// getF32Constant - Get 32-bit floating point constant. 3627static SDValue 3628getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3629 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3630} 3631 3632// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3633const char * 3634SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3635 SDValue Op1 = getValue(I.getArgOperand(0)); 3636 SDValue Op2 = getValue(I.getArgOperand(1)); 3637 3638 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3639 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3640 return 0; 3641} 3642 3643/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3644/// limited-precision mode. 3645void 3646SelectionDAGBuilder::visitExp(const CallInst &I) { 3647 SDValue result; 3648 DebugLoc dl = getCurDebugLoc(); 3649 3650 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3651 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3652 SDValue Op = getValue(I.getArgOperand(0)); 3653 3654 // Put the exponent in the right bit position for later addition to the 3655 // final result: 3656 // 3657 // #define LOG2OFe 1.4426950f 3658 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3659 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3660 getF32Constant(DAG, 0x3fb8aa3b)); 3661 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3662 3663 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3664 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3665 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3666 3667 // IntegerPartOfX <<= 23; 3668 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3669 DAG.getConstant(23, TLI.getPointerTy())); 3670 3671 if (LimitFloatPrecision <= 6) { 3672 // For floating-point precision of 6: 3673 // 3674 // TwoToFractionalPartOfX = 3675 // 0.997535578f + 3676 // (0.735607626f + 0.252464424f * x) * x; 3677 // 3678 // error 0.0144103317, which is 6 bits 3679 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3680 getF32Constant(DAG, 0x3e814304)); 3681 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3682 getF32Constant(DAG, 0x3f3c50c8)); 3683 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3684 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3685 getF32Constant(DAG, 0x3f7f5e7e)); 3686 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3687 3688 // Add the exponent into the result in integer domain. 3689 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3690 TwoToFracPartOfX, IntegerPartOfX); 3691 3692 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3693 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3694 // For floating-point precision of 12: 3695 // 3696 // TwoToFractionalPartOfX = 3697 // 0.999892986f + 3698 // (0.696457318f + 3699 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3700 // 3701 // 0.000107046256 error, which is 13 to 14 bits 3702 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3703 getF32Constant(DAG, 0x3da235e3)); 3704 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3705 getF32Constant(DAG, 0x3e65b8f3)); 3706 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3707 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3708 getF32Constant(DAG, 0x3f324b07)); 3709 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3710 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3711 getF32Constant(DAG, 0x3f7ff8fd)); 3712 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3713 3714 // Add the exponent into the result in integer domain. 3715 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3716 TwoToFracPartOfX, IntegerPartOfX); 3717 3718 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3719 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3720 // For floating-point precision of 18: 3721 // 3722 // TwoToFractionalPartOfX = 3723 // 0.999999982f + 3724 // (0.693148872f + 3725 // (0.240227044f + 3726 // (0.554906021e-1f + 3727 // (0.961591928e-2f + 3728 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3729 // 3730 // error 2.47208000*10^(-7), which is better than 18 bits 3731 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3732 getF32Constant(DAG, 0x3924b03e)); 3733 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3734 getF32Constant(DAG, 0x3ab24b87)); 3735 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3736 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3737 getF32Constant(DAG, 0x3c1d8c17)); 3738 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3739 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3740 getF32Constant(DAG, 0x3d634a1d)); 3741 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3742 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3743 getF32Constant(DAG, 0x3e75fe14)); 3744 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3745 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3746 getF32Constant(DAG, 0x3f317234)); 3747 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3748 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3749 getF32Constant(DAG, 0x3f800000)); 3750 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3751 MVT::i32, t13); 3752 3753 // Add the exponent into the result in integer domain. 3754 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3755 TwoToFracPartOfX, IntegerPartOfX); 3756 3757 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3758 } 3759 } else { 3760 // No special expansion. 3761 result = DAG.getNode(ISD::FEXP, dl, 3762 getValue(I.getArgOperand(0)).getValueType(), 3763 getValue(I.getArgOperand(0))); 3764 } 3765 3766 setValue(&I, result); 3767} 3768 3769/// visitLog - Lower a log intrinsic. Handles the special sequences for 3770/// limited-precision mode. 3771void 3772SelectionDAGBuilder::visitLog(const CallInst &I) { 3773 SDValue result; 3774 DebugLoc dl = getCurDebugLoc(); 3775 3776 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3777 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3778 SDValue Op = getValue(I.getArgOperand(0)); 3779 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3780 3781 // Scale the exponent by log(2) [0.69314718f]. 3782 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3783 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3784 getF32Constant(DAG, 0x3f317218)); 3785 3786 // Get the significand and build it into a floating-point number with 3787 // exponent of 1. 3788 SDValue X = GetSignificand(DAG, Op1, dl); 3789 3790 if (LimitFloatPrecision <= 6) { 3791 // For floating-point precision of 6: 3792 // 3793 // LogofMantissa = 3794 // -1.1609546f + 3795 // (1.4034025f - 0.23903021f * x) * x; 3796 // 3797 // error 0.0034276066, which is better than 8 bits 3798 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3799 getF32Constant(DAG, 0xbe74c456)); 3800 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3801 getF32Constant(DAG, 0x3fb3a2b1)); 3802 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3803 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3804 getF32Constant(DAG, 0x3f949a29)); 3805 3806 result = DAG.getNode(ISD::FADD, dl, 3807 MVT::f32, LogOfExponent, LogOfMantissa); 3808 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3809 // For floating-point precision of 12: 3810 // 3811 // LogOfMantissa = 3812 // -1.7417939f + 3813 // (2.8212026f + 3814 // (-1.4699568f + 3815 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3816 // 3817 // error 0.000061011436, which is 14 bits 3818 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3819 getF32Constant(DAG, 0xbd67b6d6)); 3820 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3821 getF32Constant(DAG, 0x3ee4f4b8)); 3822 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3823 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3824 getF32Constant(DAG, 0x3fbc278b)); 3825 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3826 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3827 getF32Constant(DAG, 0x40348e95)); 3828 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3829 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3830 getF32Constant(DAG, 0x3fdef31a)); 3831 3832 result = DAG.getNode(ISD::FADD, dl, 3833 MVT::f32, LogOfExponent, LogOfMantissa); 3834 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3835 // For floating-point precision of 18: 3836 // 3837 // LogOfMantissa = 3838 // -2.1072184f + 3839 // (4.2372794f + 3840 // (-3.7029485f + 3841 // (2.2781945f + 3842 // (-0.87823314f + 3843 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3844 // 3845 // error 0.0000023660568, which is better than 18 bits 3846 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3847 getF32Constant(DAG, 0xbc91e5ac)); 3848 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3849 getF32Constant(DAG, 0x3e4350aa)); 3850 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3851 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3852 getF32Constant(DAG, 0x3f60d3e3)); 3853 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3854 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3855 getF32Constant(DAG, 0x4011cdf0)); 3856 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3857 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3858 getF32Constant(DAG, 0x406cfd1c)); 3859 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3860 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3861 getF32Constant(DAG, 0x408797cb)); 3862 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3863 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3864 getF32Constant(DAG, 0x4006dcab)); 3865 3866 result = DAG.getNode(ISD::FADD, dl, 3867 MVT::f32, LogOfExponent, LogOfMantissa); 3868 } 3869 } else { 3870 // No special expansion. 3871 result = DAG.getNode(ISD::FLOG, dl, 3872 getValue(I.getArgOperand(0)).getValueType(), 3873 getValue(I.getArgOperand(0))); 3874 } 3875 3876 setValue(&I, result); 3877} 3878 3879/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3880/// limited-precision mode. 3881void 3882SelectionDAGBuilder::visitLog2(const CallInst &I) { 3883 SDValue result; 3884 DebugLoc dl = getCurDebugLoc(); 3885 3886 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3887 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3888 SDValue Op = getValue(I.getArgOperand(0)); 3889 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3890 3891 // Get the exponent. 3892 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3893 3894 // Get the significand and build it into a floating-point number with 3895 // exponent of 1. 3896 SDValue X = GetSignificand(DAG, Op1, dl); 3897 3898 // Different possible minimax approximations of significand in 3899 // floating-point for various degrees of accuracy over [1,2]. 3900 if (LimitFloatPrecision <= 6) { 3901 // For floating-point precision of 6: 3902 // 3903 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3904 // 3905 // error 0.0049451742, which is more than 7 bits 3906 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3907 getF32Constant(DAG, 0xbeb08fe0)); 3908 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3909 getF32Constant(DAG, 0x40019463)); 3910 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3911 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3912 getF32Constant(DAG, 0x3fd6633d)); 3913 3914 result = DAG.getNode(ISD::FADD, dl, 3915 MVT::f32, LogOfExponent, Log2ofMantissa); 3916 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3917 // For floating-point precision of 12: 3918 // 3919 // Log2ofMantissa = 3920 // -2.51285454f + 3921 // (4.07009056f + 3922 // (-2.12067489f + 3923 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3924 // 3925 // error 0.0000876136000, which is better than 13 bits 3926 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3927 getF32Constant(DAG, 0xbda7262e)); 3928 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3929 getF32Constant(DAG, 0x3f25280b)); 3930 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3931 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3932 getF32Constant(DAG, 0x4007b923)); 3933 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3934 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3935 getF32Constant(DAG, 0x40823e2f)); 3936 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3937 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3938 getF32Constant(DAG, 0x4020d29c)); 3939 3940 result = DAG.getNode(ISD::FADD, dl, 3941 MVT::f32, LogOfExponent, Log2ofMantissa); 3942 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3943 // For floating-point precision of 18: 3944 // 3945 // Log2ofMantissa = 3946 // -3.0400495f + 3947 // (6.1129976f + 3948 // (-5.3420409f + 3949 // (3.2865683f + 3950 // (-1.2669343f + 3951 // (0.27515199f - 3952 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3953 // 3954 // error 0.0000018516, which is better than 18 bits 3955 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3956 getF32Constant(DAG, 0xbcd2769e)); 3957 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3958 getF32Constant(DAG, 0x3e8ce0b9)); 3959 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3960 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3961 getF32Constant(DAG, 0x3fa22ae7)); 3962 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3963 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3964 getF32Constant(DAG, 0x40525723)); 3965 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3966 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3967 getF32Constant(DAG, 0x40aaf200)); 3968 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3969 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3970 getF32Constant(DAG, 0x40c39dad)); 3971 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3972 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3973 getF32Constant(DAG, 0x4042902c)); 3974 3975 result = DAG.getNode(ISD::FADD, dl, 3976 MVT::f32, LogOfExponent, Log2ofMantissa); 3977 } 3978 } else { 3979 // No special expansion. 3980 result = DAG.getNode(ISD::FLOG2, dl, 3981 getValue(I.getArgOperand(0)).getValueType(), 3982 getValue(I.getArgOperand(0))); 3983 } 3984 3985 setValue(&I, result); 3986} 3987 3988/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3989/// limited-precision mode. 3990void 3991SelectionDAGBuilder::visitLog10(const CallInst &I) { 3992 SDValue result; 3993 DebugLoc dl = getCurDebugLoc(); 3994 3995 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3996 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3997 SDValue Op = getValue(I.getArgOperand(0)); 3998 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3999 4000 // Scale the exponent by log10(2) [0.30102999f]. 4001 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 4002 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 4003 getF32Constant(DAG, 0x3e9a209a)); 4004 4005 // Get the significand and build it into a floating-point number with 4006 // exponent of 1. 4007 SDValue X = GetSignificand(DAG, Op1, dl); 4008 4009 if (LimitFloatPrecision <= 6) { 4010 // For floating-point precision of 6: 4011 // 4012 // Log10ofMantissa = 4013 // -0.50419619f + 4014 // (0.60948995f - 0.10380950f * x) * x; 4015 // 4016 // error 0.0014886165, which is 6 bits 4017 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4018 getF32Constant(DAG, 0xbdd49a13)); 4019 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4020 getF32Constant(DAG, 0x3f1c0789)); 4021 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4022 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4023 getF32Constant(DAG, 0x3f011300)); 4024 4025 result = DAG.getNode(ISD::FADD, dl, 4026 MVT::f32, LogOfExponent, Log10ofMantissa); 4027 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4028 // For floating-point precision of 12: 4029 // 4030 // Log10ofMantissa = 4031 // -0.64831180f + 4032 // (0.91751397f + 4033 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4034 // 4035 // error 0.00019228036, which is better than 12 bits 4036 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4037 getF32Constant(DAG, 0x3d431f31)); 4038 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4039 getF32Constant(DAG, 0x3ea21fb2)); 4040 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4041 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4042 getF32Constant(DAG, 0x3f6ae232)); 4043 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4044 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4045 getF32Constant(DAG, 0x3f25f7c3)); 4046 4047 result = DAG.getNode(ISD::FADD, dl, 4048 MVT::f32, LogOfExponent, Log10ofMantissa); 4049 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4050 // For floating-point precision of 18: 4051 // 4052 // Log10ofMantissa = 4053 // -0.84299375f + 4054 // (1.5327582f + 4055 // (-1.0688956f + 4056 // (0.49102474f + 4057 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4058 // 4059 // error 0.0000037995730, which is better than 18 bits 4060 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4061 getF32Constant(DAG, 0x3c5d51ce)); 4062 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4063 getF32Constant(DAG, 0x3e00685a)); 4064 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4065 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4066 getF32Constant(DAG, 0x3efb6798)); 4067 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4068 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4069 getF32Constant(DAG, 0x3f88d192)); 4070 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4071 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4072 getF32Constant(DAG, 0x3fc4316c)); 4073 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4074 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4075 getF32Constant(DAG, 0x3f57ce70)); 4076 4077 result = DAG.getNode(ISD::FADD, dl, 4078 MVT::f32, LogOfExponent, Log10ofMantissa); 4079 } 4080 } else { 4081 // No special expansion. 4082 result = DAG.getNode(ISD::FLOG10, dl, 4083 getValue(I.getArgOperand(0)).getValueType(), 4084 getValue(I.getArgOperand(0))); 4085 } 4086 4087 setValue(&I, result); 4088} 4089 4090/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4091/// limited-precision mode. 4092void 4093SelectionDAGBuilder::visitExp2(const CallInst &I) { 4094 SDValue result; 4095 DebugLoc dl = getCurDebugLoc(); 4096 4097 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4098 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4099 SDValue Op = getValue(I.getArgOperand(0)); 4100 4101 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4102 4103 // FractionalPartOfX = x - (float)IntegerPartOfX; 4104 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4105 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4106 4107 // IntegerPartOfX <<= 23; 4108 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4109 DAG.getConstant(23, TLI.getPointerTy())); 4110 4111 if (LimitFloatPrecision <= 6) { 4112 // For floating-point precision of 6: 4113 // 4114 // TwoToFractionalPartOfX = 4115 // 0.997535578f + 4116 // (0.735607626f + 0.252464424f * x) * x; 4117 // 4118 // error 0.0144103317, which is 6 bits 4119 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4120 getF32Constant(DAG, 0x3e814304)); 4121 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4122 getF32Constant(DAG, 0x3f3c50c8)); 4123 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4124 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4125 getF32Constant(DAG, 0x3f7f5e7e)); 4126 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4127 SDValue TwoToFractionalPartOfX = 4128 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4129 4130 result = DAG.getNode(ISD::BITCAST, dl, 4131 MVT::f32, TwoToFractionalPartOfX); 4132 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4133 // For floating-point precision of 12: 4134 // 4135 // TwoToFractionalPartOfX = 4136 // 0.999892986f + 4137 // (0.696457318f + 4138 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4139 // 4140 // error 0.000107046256, which is 13 to 14 bits 4141 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4142 getF32Constant(DAG, 0x3da235e3)); 4143 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4144 getF32Constant(DAG, 0x3e65b8f3)); 4145 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4146 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4147 getF32Constant(DAG, 0x3f324b07)); 4148 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4149 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4150 getF32Constant(DAG, 0x3f7ff8fd)); 4151 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4152 SDValue TwoToFractionalPartOfX = 4153 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4154 4155 result = DAG.getNode(ISD::BITCAST, dl, 4156 MVT::f32, TwoToFractionalPartOfX); 4157 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4158 // For floating-point precision of 18: 4159 // 4160 // TwoToFractionalPartOfX = 4161 // 0.999999982f + 4162 // (0.693148872f + 4163 // (0.240227044f + 4164 // (0.554906021e-1f + 4165 // (0.961591928e-2f + 4166 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4167 // error 2.47208000*10^(-7), which is better than 18 bits 4168 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4169 getF32Constant(DAG, 0x3924b03e)); 4170 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4171 getF32Constant(DAG, 0x3ab24b87)); 4172 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4173 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4174 getF32Constant(DAG, 0x3c1d8c17)); 4175 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4176 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4177 getF32Constant(DAG, 0x3d634a1d)); 4178 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4179 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4180 getF32Constant(DAG, 0x3e75fe14)); 4181 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4182 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4183 getF32Constant(DAG, 0x3f317234)); 4184 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4185 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4186 getF32Constant(DAG, 0x3f800000)); 4187 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4188 SDValue TwoToFractionalPartOfX = 4189 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4190 4191 result = DAG.getNode(ISD::BITCAST, dl, 4192 MVT::f32, TwoToFractionalPartOfX); 4193 } 4194 } else { 4195 // No special expansion. 4196 result = DAG.getNode(ISD::FEXP2, dl, 4197 getValue(I.getArgOperand(0)).getValueType(), 4198 getValue(I.getArgOperand(0))); 4199 } 4200 4201 setValue(&I, result); 4202} 4203 4204/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4205/// limited-precision mode with x == 10.0f. 4206void 4207SelectionDAGBuilder::visitPow(const CallInst &I) { 4208 SDValue result; 4209 const Value *Val = I.getArgOperand(0); 4210 DebugLoc dl = getCurDebugLoc(); 4211 bool IsExp10 = false; 4212 4213 if (getValue(Val).getValueType() == MVT::f32 && 4214 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4215 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4216 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4217 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4218 APFloat Ten(10.0f); 4219 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4220 } 4221 } 4222 } 4223 4224 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4225 SDValue Op = getValue(I.getArgOperand(1)); 4226 4227 // Put the exponent in the right bit position for later addition to the 4228 // final result: 4229 // 4230 // #define LOG2OF10 3.3219281f 4231 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4232 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4233 getF32Constant(DAG, 0x40549a78)); 4234 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4235 4236 // FractionalPartOfX = x - (float)IntegerPartOfX; 4237 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4238 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4239 4240 // IntegerPartOfX <<= 23; 4241 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4242 DAG.getConstant(23, TLI.getPointerTy())); 4243 4244 if (LimitFloatPrecision <= 6) { 4245 // For floating-point precision of 6: 4246 // 4247 // twoToFractionalPartOfX = 4248 // 0.997535578f + 4249 // (0.735607626f + 0.252464424f * x) * x; 4250 // 4251 // error 0.0144103317, which is 6 bits 4252 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4253 getF32Constant(DAG, 0x3e814304)); 4254 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4255 getF32Constant(DAG, 0x3f3c50c8)); 4256 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4257 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4258 getF32Constant(DAG, 0x3f7f5e7e)); 4259 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4260 SDValue TwoToFractionalPartOfX = 4261 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4262 4263 result = DAG.getNode(ISD::BITCAST, dl, 4264 MVT::f32, TwoToFractionalPartOfX); 4265 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4266 // For floating-point precision of 12: 4267 // 4268 // TwoToFractionalPartOfX = 4269 // 0.999892986f + 4270 // (0.696457318f + 4271 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4272 // 4273 // error 0.000107046256, which is 13 to 14 bits 4274 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4275 getF32Constant(DAG, 0x3da235e3)); 4276 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4277 getF32Constant(DAG, 0x3e65b8f3)); 4278 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4279 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4280 getF32Constant(DAG, 0x3f324b07)); 4281 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4282 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4283 getF32Constant(DAG, 0x3f7ff8fd)); 4284 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4285 SDValue TwoToFractionalPartOfX = 4286 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4287 4288 result = DAG.getNode(ISD::BITCAST, dl, 4289 MVT::f32, TwoToFractionalPartOfX); 4290 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4291 // For floating-point precision of 18: 4292 // 4293 // TwoToFractionalPartOfX = 4294 // 0.999999982f + 4295 // (0.693148872f + 4296 // (0.240227044f + 4297 // (0.554906021e-1f + 4298 // (0.961591928e-2f + 4299 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4300 // error 2.47208000*10^(-7), which is better than 18 bits 4301 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4302 getF32Constant(DAG, 0x3924b03e)); 4303 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4304 getF32Constant(DAG, 0x3ab24b87)); 4305 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4306 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4307 getF32Constant(DAG, 0x3c1d8c17)); 4308 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4309 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4310 getF32Constant(DAG, 0x3d634a1d)); 4311 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4312 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4313 getF32Constant(DAG, 0x3e75fe14)); 4314 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4315 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4316 getF32Constant(DAG, 0x3f317234)); 4317 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4318 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4319 getF32Constant(DAG, 0x3f800000)); 4320 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4321 SDValue TwoToFractionalPartOfX = 4322 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4323 4324 result = DAG.getNode(ISD::BITCAST, dl, 4325 MVT::f32, TwoToFractionalPartOfX); 4326 } 4327 } else { 4328 // No special expansion. 4329 result = DAG.getNode(ISD::FPOW, dl, 4330 getValue(I.getArgOperand(0)).getValueType(), 4331 getValue(I.getArgOperand(0)), 4332 getValue(I.getArgOperand(1))); 4333 } 4334 4335 setValue(&I, result); 4336} 4337 4338 4339/// ExpandPowI - Expand a llvm.powi intrinsic. 4340static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4341 SelectionDAG &DAG) { 4342 // If RHS is a constant, we can expand this out to a multiplication tree, 4343 // otherwise we end up lowering to a call to __powidf2 (for example). When 4344 // optimizing for size, we only want to do this if the expansion would produce 4345 // a small number of multiplies, otherwise we do the full expansion. 4346 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4347 // Get the exponent as a positive value. 4348 unsigned Val = RHSC->getSExtValue(); 4349 if ((int)Val < 0) Val = -Val; 4350 4351 // powi(x, 0) -> 1.0 4352 if (Val == 0) 4353 return DAG.getConstantFP(1.0, LHS.getValueType()); 4354 4355 const Function *F = DAG.getMachineFunction().getFunction(); 4356 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4357 // If optimizing for size, don't insert too many multiplies. This 4358 // inserts up to 5 multiplies. 4359 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4360 // We use the simple binary decomposition method to generate the multiply 4361 // sequence. There are more optimal ways to do this (for example, 4362 // powi(x,15) generates one more multiply than it should), but this has 4363 // the benefit of being both really simple and much better than a libcall. 4364 SDValue Res; // Logically starts equal to 1.0 4365 SDValue CurSquare = LHS; 4366 while (Val) { 4367 if (Val & 1) { 4368 if (Res.getNode()) 4369 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4370 else 4371 Res = CurSquare; // 1.0*CurSquare. 4372 } 4373 4374 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4375 CurSquare, CurSquare); 4376 Val >>= 1; 4377 } 4378 4379 // If the original was negative, invert the result, producing 1/(x*x*x). 4380 if (RHSC->getSExtValue() < 0) 4381 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4382 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4383 return Res; 4384 } 4385 } 4386 4387 // Otherwise, expand to a libcall. 4388 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4389} 4390 4391// getTruncatedArgReg - Find underlying register used for an truncated 4392// argument. 4393static unsigned getTruncatedArgReg(const SDValue &N) { 4394 if (N.getOpcode() != ISD::TRUNCATE) 4395 return 0; 4396 4397 const SDValue &Ext = N.getOperand(0); 4398 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4399 const SDValue &CFR = Ext.getOperand(0); 4400 if (CFR.getOpcode() == ISD::CopyFromReg) 4401 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4402 else 4403 if (CFR.getOpcode() == ISD::TRUNCATE) 4404 return getTruncatedArgReg(CFR); 4405 } 4406 return 0; 4407} 4408 4409/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4410/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4411/// At the end of instruction selection, they will be inserted to the entry BB. 4412bool 4413SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4414 int64_t Offset, 4415 const SDValue &N) { 4416 const Argument *Arg = dyn_cast<Argument>(V); 4417 if (!Arg) 4418 return false; 4419 4420 MachineFunction &MF = DAG.getMachineFunction(); 4421 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4422 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4423 4424 // Ignore inlined function arguments here. 4425 DIVariable DV(Variable); 4426 if (DV.isInlinedFnArgument(MF.getFunction())) 4427 return false; 4428 4429 unsigned Reg = 0; 4430 // Some arguments' frame index is recorded during argument lowering. 4431 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4432 if (Offset) 4433 Reg = TRI->getFrameRegister(MF); 4434 4435 if (!Reg && N.getNode()) { 4436 if (N.getOpcode() == ISD::CopyFromReg) 4437 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4438 else 4439 Reg = getTruncatedArgReg(N); 4440 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4441 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4442 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4443 if (PR) 4444 Reg = PR; 4445 } 4446 } 4447 4448 if (!Reg) { 4449 // Check if ValueMap has reg number. 4450 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4451 if (VMI != FuncInfo.ValueMap.end()) 4452 Reg = VMI->second; 4453 } 4454 4455 if (!Reg && N.getNode()) { 4456 // Check if frame index is available. 4457 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4458 if (FrameIndexSDNode *FINode = 4459 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4460 Reg = TRI->getFrameRegister(MF); 4461 Offset = FINode->getIndex(); 4462 } 4463 } 4464 4465 if (!Reg) 4466 return false; 4467 4468 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4469 TII->get(TargetOpcode::DBG_VALUE)) 4470 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4471 FuncInfo.ArgDbgValues.push_back(&*MIB); 4472 return true; 4473} 4474 4475// VisualStudio defines setjmp as _setjmp 4476#if defined(_MSC_VER) && defined(setjmp) && \ 4477 !defined(setjmp_undefined_for_msvc) 4478# pragma push_macro("setjmp") 4479# undef setjmp 4480# define setjmp_undefined_for_msvc 4481#endif 4482 4483/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4484/// we want to emit this as a call to a named external function, return the name 4485/// otherwise lower it and return null. 4486const char * 4487SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4488 DebugLoc dl = getCurDebugLoc(); 4489 SDValue Res; 4490 4491 switch (Intrinsic) { 4492 default: 4493 // By default, turn this into a target intrinsic node. 4494 visitTargetIntrinsic(I, Intrinsic); 4495 return 0; 4496 case Intrinsic::vastart: visitVAStart(I); return 0; 4497 case Intrinsic::vaend: visitVAEnd(I); return 0; 4498 case Intrinsic::vacopy: visitVACopy(I); return 0; 4499 case Intrinsic::returnaddress: 4500 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4501 getValue(I.getArgOperand(0)))); 4502 return 0; 4503 case Intrinsic::frameaddress: 4504 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4505 getValue(I.getArgOperand(0)))); 4506 return 0; 4507 case Intrinsic::setjmp: 4508 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; 4509 case Intrinsic::longjmp: 4510 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; 4511 case Intrinsic::memcpy: { 4512 // Assert for address < 256 since we support only user defined address 4513 // spaces. 4514 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4515 < 256 && 4516 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4517 < 256 && 4518 "Unknown address space"); 4519 SDValue Op1 = getValue(I.getArgOperand(0)); 4520 SDValue Op2 = getValue(I.getArgOperand(1)); 4521 SDValue Op3 = getValue(I.getArgOperand(2)); 4522 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4523 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4524 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4525 MachinePointerInfo(I.getArgOperand(0)), 4526 MachinePointerInfo(I.getArgOperand(1)))); 4527 return 0; 4528 } 4529 case Intrinsic::memset: { 4530 // Assert for address < 256 since we support only user defined address 4531 // spaces. 4532 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4533 < 256 && 4534 "Unknown address space"); 4535 SDValue Op1 = getValue(I.getArgOperand(0)); 4536 SDValue Op2 = getValue(I.getArgOperand(1)); 4537 SDValue Op3 = getValue(I.getArgOperand(2)); 4538 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4539 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4540 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4541 MachinePointerInfo(I.getArgOperand(0)))); 4542 return 0; 4543 } 4544 case Intrinsic::memmove: { 4545 // Assert for address < 256 since we support only user defined address 4546 // spaces. 4547 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4548 < 256 && 4549 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4550 < 256 && 4551 "Unknown address space"); 4552 SDValue Op1 = getValue(I.getArgOperand(0)); 4553 SDValue Op2 = getValue(I.getArgOperand(1)); 4554 SDValue Op3 = getValue(I.getArgOperand(2)); 4555 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4556 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4557 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4558 MachinePointerInfo(I.getArgOperand(0)), 4559 MachinePointerInfo(I.getArgOperand(1)))); 4560 return 0; 4561 } 4562 case Intrinsic::dbg_declare: { 4563 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4564 MDNode *Variable = DI.getVariable(); 4565 const Value *Address = DI.getAddress(); 4566 if (!Address || !DIVariable(Variable).Verify()) { 4567 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4568 return 0; 4569 } 4570 4571 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4572 // but do not always have a corresponding SDNode built. The SDNodeOrder 4573 // absolute, but not relative, values are different depending on whether 4574 // debug info exists. 4575 ++SDNodeOrder; 4576 4577 // Check if address has undef value. 4578 if (isa<UndefValue>(Address) || 4579 (Address->use_empty() && !isa<Argument>(Address))) { 4580 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4581 return 0; 4582 } 4583 4584 SDValue &N = NodeMap[Address]; 4585 if (!N.getNode() && isa<Argument>(Address)) 4586 // Check unused arguments map. 4587 N = UnusedArgNodeMap[Address]; 4588 SDDbgValue *SDV; 4589 if (N.getNode()) { 4590 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4591 Address = BCI->getOperand(0); 4592 // Parameters are handled specially. 4593 bool isParameter = 4594 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4595 isa<Argument>(Address)); 4596 4597 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4598 4599 if (isParameter && !AI) { 4600 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4601 if (FINode) 4602 // Byval parameter. We have a frame index at this point. 4603 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4604 0, dl, SDNodeOrder); 4605 else { 4606 // Address is an argument, so try to emit its dbg value using 4607 // virtual register info from the FuncInfo.ValueMap. 4608 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4609 return 0; 4610 } 4611 } else if (AI) 4612 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4613 0, dl, SDNodeOrder); 4614 else { 4615 // Can't do anything with other non-AI cases yet. 4616 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4617 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4618 DEBUG(Address->dump()); 4619 return 0; 4620 } 4621 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4622 } else { 4623 // If Address is an argument then try to emit its dbg value using 4624 // virtual register info from the FuncInfo.ValueMap. 4625 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4626 // If variable is pinned by a alloca in dominating bb then 4627 // use StaticAllocaMap. 4628 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4629 if (AI->getParent() != DI.getParent()) { 4630 DenseMap<const AllocaInst*, int>::iterator SI = 4631 FuncInfo.StaticAllocaMap.find(AI); 4632 if (SI != FuncInfo.StaticAllocaMap.end()) { 4633 SDV = DAG.getDbgValue(Variable, SI->second, 4634 0, dl, SDNodeOrder); 4635 DAG.AddDbgValue(SDV, 0, false); 4636 return 0; 4637 } 4638 } 4639 } 4640 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4641 } 4642 } 4643 return 0; 4644 } 4645 case Intrinsic::dbg_value: { 4646 const DbgValueInst &DI = cast<DbgValueInst>(I); 4647 if (!DIVariable(DI.getVariable()).Verify()) 4648 return 0; 4649 4650 MDNode *Variable = DI.getVariable(); 4651 uint64_t Offset = DI.getOffset(); 4652 const Value *V = DI.getValue(); 4653 if (!V) 4654 return 0; 4655 4656 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4657 // but do not always have a corresponding SDNode built. The SDNodeOrder 4658 // absolute, but not relative, values are different depending on whether 4659 // debug info exists. 4660 ++SDNodeOrder; 4661 SDDbgValue *SDV; 4662 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4663 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4664 DAG.AddDbgValue(SDV, 0, false); 4665 } else { 4666 // Do not use getValue() in here; we don't want to generate code at 4667 // this point if it hasn't been done yet. 4668 SDValue N = NodeMap[V]; 4669 if (!N.getNode() && isa<Argument>(V)) 4670 // Check unused arguments map. 4671 N = UnusedArgNodeMap[V]; 4672 if (N.getNode()) { 4673 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4674 SDV = DAG.getDbgValue(Variable, N.getNode(), 4675 N.getResNo(), Offset, dl, SDNodeOrder); 4676 DAG.AddDbgValue(SDV, N.getNode(), false); 4677 } 4678 } else if (!V->use_empty() ) { 4679 // Do not call getValue(V) yet, as we don't want to generate code. 4680 // Remember it for later. 4681 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4682 DanglingDebugInfoMap[V] = DDI; 4683 } else { 4684 // We may expand this to cover more cases. One case where we have no 4685 // data available is an unreferenced parameter. 4686 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4687 } 4688 } 4689 4690 // Build a debug info table entry. 4691 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4692 V = BCI->getOperand(0); 4693 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4694 // Don't handle byval struct arguments or VLAs, for example. 4695 if (!AI) { 4696 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4697 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4698 return 0; 4699 } 4700 DenseMap<const AllocaInst*, int>::iterator SI = 4701 FuncInfo.StaticAllocaMap.find(AI); 4702 if (SI == FuncInfo.StaticAllocaMap.end()) 4703 return 0; // VLAs. 4704 int FI = SI->second; 4705 4706 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4707 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4708 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4709 return 0; 4710 } 4711 4712 case Intrinsic::eh_typeid_for: { 4713 // Find the type id for the given typeinfo. 4714 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4715 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4716 Res = DAG.getConstant(TypeID, MVT::i32); 4717 setValue(&I, Res); 4718 return 0; 4719 } 4720 4721 case Intrinsic::eh_return_i32: 4722 case Intrinsic::eh_return_i64: 4723 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4724 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4725 MVT::Other, 4726 getControlRoot(), 4727 getValue(I.getArgOperand(0)), 4728 getValue(I.getArgOperand(1)))); 4729 return 0; 4730 case Intrinsic::eh_unwind_init: 4731 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4732 return 0; 4733 case Intrinsic::eh_dwarf_cfa: { 4734 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4735 TLI.getPointerTy()); 4736 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4737 TLI.getPointerTy(), 4738 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4739 TLI.getPointerTy()), 4740 CfaArg); 4741 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4742 TLI.getPointerTy(), 4743 DAG.getConstant(0, TLI.getPointerTy())); 4744 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4745 FA, Offset)); 4746 return 0; 4747 } 4748 case Intrinsic::eh_sjlj_callsite: { 4749 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4750 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4751 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4752 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4753 4754 MMI.setCurrentCallSite(CI->getZExtValue()); 4755 return 0; 4756 } 4757 case Intrinsic::eh_sjlj_functioncontext: { 4758 // Get and store the index of the function context. 4759 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4760 AllocaInst *FnCtx = 4761 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4762 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4763 MFI->setFunctionContextIndex(FI); 4764 return 0; 4765 } 4766 case Intrinsic::eh_sjlj_setjmp: { 4767 SDValue Ops[2]; 4768 Ops[0] = getRoot(); 4769 Ops[1] = getValue(I.getArgOperand(0)); 4770 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4771 DAG.getVTList(MVT::i32, MVT::Other), 4772 Ops, 2); 4773 setValue(&I, Op.getValue(0)); 4774 DAG.setRoot(Op.getValue(1)); 4775 return 0; 4776 } 4777 case Intrinsic::eh_sjlj_longjmp: { 4778 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4779 getRoot(), getValue(I.getArgOperand(0)))); 4780 return 0; 4781 } 4782 4783 case Intrinsic::x86_mmx_pslli_w: 4784 case Intrinsic::x86_mmx_pslli_d: 4785 case Intrinsic::x86_mmx_pslli_q: 4786 case Intrinsic::x86_mmx_psrli_w: 4787 case Intrinsic::x86_mmx_psrli_d: 4788 case Intrinsic::x86_mmx_psrli_q: 4789 case Intrinsic::x86_mmx_psrai_w: 4790 case Intrinsic::x86_mmx_psrai_d: { 4791 SDValue ShAmt = getValue(I.getArgOperand(1)); 4792 if (isa<ConstantSDNode>(ShAmt)) { 4793 visitTargetIntrinsic(I, Intrinsic); 4794 return 0; 4795 } 4796 unsigned NewIntrinsic = 0; 4797 EVT ShAmtVT = MVT::v2i32; 4798 switch (Intrinsic) { 4799 case Intrinsic::x86_mmx_pslli_w: 4800 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4801 break; 4802 case Intrinsic::x86_mmx_pslli_d: 4803 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4804 break; 4805 case Intrinsic::x86_mmx_pslli_q: 4806 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4807 break; 4808 case Intrinsic::x86_mmx_psrli_w: 4809 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4810 break; 4811 case Intrinsic::x86_mmx_psrli_d: 4812 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4813 break; 4814 case Intrinsic::x86_mmx_psrli_q: 4815 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4816 break; 4817 case Intrinsic::x86_mmx_psrai_w: 4818 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4819 break; 4820 case Intrinsic::x86_mmx_psrai_d: 4821 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4822 break; 4823 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4824 } 4825 4826 // The vector shift intrinsics with scalars uses 32b shift amounts but 4827 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4828 // to be zero. 4829 // We must do this early because v2i32 is not a legal type. 4830 DebugLoc dl = getCurDebugLoc(); 4831 SDValue ShOps[2]; 4832 ShOps[0] = ShAmt; 4833 ShOps[1] = DAG.getConstant(0, MVT::i32); 4834 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4835 EVT DestVT = TLI.getValueType(I.getType()); 4836 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4837 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4838 DAG.getConstant(NewIntrinsic, MVT::i32), 4839 getValue(I.getArgOperand(0)), ShAmt); 4840 setValue(&I, Res); 4841 return 0; 4842 } 4843 case Intrinsic::x86_avx_vinsertf128_pd_256: 4844 case Intrinsic::x86_avx_vinsertf128_ps_256: 4845 case Intrinsic::x86_avx_vinsertf128_si_256: 4846 case Intrinsic::x86_avx2_vinserti128: { 4847 DebugLoc dl = getCurDebugLoc(); 4848 EVT DestVT = TLI.getValueType(I.getType()); 4849 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType()); 4850 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4851 ElVT.getVectorNumElements(); 4852 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT, 4853 getValue(I.getArgOperand(0)), 4854 getValue(I.getArgOperand(1)), 4855 DAG.getConstant(Idx, MVT::i32)); 4856 setValue(&I, Res); 4857 return 0; 4858 } 4859 case Intrinsic::convertff: 4860 case Intrinsic::convertfsi: 4861 case Intrinsic::convertfui: 4862 case Intrinsic::convertsif: 4863 case Intrinsic::convertuif: 4864 case Intrinsic::convertss: 4865 case Intrinsic::convertsu: 4866 case Intrinsic::convertus: 4867 case Intrinsic::convertuu: { 4868 ISD::CvtCode Code = ISD::CVT_INVALID; 4869 switch (Intrinsic) { 4870 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4871 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4872 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4873 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4874 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4875 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4876 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4877 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4878 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4879 } 4880 EVT DestVT = TLI.getValueType(I.getType()); 4881 const Value *Op1 = I.getArgOperand(0); 4882 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4883 DAG.getValueType(DestVT), 4884 DAG.getValueType(getValue(Op1).getValueType()), 4885 getValue(I.getArgOperand(1)), 4886 getValue(I.getArgOperand(2)), 4887 Code); 4888 setValue(&I, Res); 4889 return 0; 4890 } 4891 case Intrinsic::sqrt: 4892 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4893 getValue(I.getArgOperand(0)).getValueType(), 4894 getValue(I.getArgOperand(0)))); 4895 return 0; 4896 case Intrinsic::powi: 4897 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4898 getValue(I.getArgOperand(1)), DAG)); 4899 return 0; 4900 case Intrinsic::sin: 4901 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4902 getValue(I.getArgOperand(0)).getValueType(), 4903 getValue(I.getArgOperand(0)))); 4904 return 0; 4905 case Intrinsic::cos: 4906 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4907 getValue(I.getArgOperand(0)).getValueType(), 4908 getValue(I.getArgOperand(0)))); 4909 return 0; 4910 case Intrinsic::log: 4911 visitLog(I); 4912 return 0; 4913 case Intrinsic::log2: 4914 visitLog2(I); 4915 return 0; 4916 case Intrinsic::log10: 4917 visitLog10(I); 4918 return 0; 4919 case Intrinsic::exp: 4920 visitExp(I); 4921 return 0; 4922 case Intrinsic::exp2: 4923 visitExp2(I); 4924 return 0; 4925 case Intrinsic::pow: 4926 visitPow(I); 4927 return 0; 4928 case Intrinsic::fma: 4929 setValue(&I, DAG.getNode(ISD::FMA, dl, 4930 getValue(I.getArgOperand(0)).getValueType(), 4931 getValue(I.getArgOperand(0)), 4932 getValue(I.getArgOperand(1)), 4933 getValue(I.getArgOperand(2)))); 4934 return 0; 4935 case Intrinsic::convert_to_fp16: 4936 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4937 MVT::i16, getValue(I.getArgOperand(0)))); 4938 return 0; 4939 case Intrinsic::convert_from_fp16: 4940 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4941 MVT::f32, getValue(I.getArgOperand(0)))); 4942 return 0; 4943 case Intrinsic::pcmarker: { 4944 SDValue Tmp = getValue(I.getArgOperand(0)); 4945 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4946 return 0; 4947 } 4948 case Intrinsic::readcyclecounter: { 4949 SDValue Op = getRoot(); 4950 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4951 DAG.getVTList(MVT::i64, MVT::Other), 4952 &Op, 1); 4953 setValue(&I, Res); 4954 DAG.setRoot(Res.getValue(1)); 4955 return 0; 4956 } 4957 case Intrinsic::bswap: 4958 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4959 getValue(I.getArgOperand(0)).getValueType(), 4960 getValue(I.getArgOperand(0)))); 4961 return 0; 4962 case Intrinsic::cttz: { 4963 SDValue Arg = getValue(I.getArgOperand(0)); 4964 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4965 EVT Ty = Arg.getValueType(); 4966 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4967 dl, Ty, Arg)); 4968 return 0; 4969 } 4970 case Intrinsic::ctlz: { 4971 SDValue Arg = getValue(I.getArgOperand(0)); 4972 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4973 EVT Ty = Arg.getValueType(); 4974 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4975 dl, Ty, Arg)); 4976 return 0; 4977 } 4978 case Intrinsic::ctpop: { 4979 SDValue Arg = getValue(I.getArgOperand(0)); 4980 EVT Ty = Arg.getValueType(); 4981 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4982 return 0; 4983 } 4984 case Intrinsic::stacksave: { 4985 SDValue Op = getRoot(); 4986 Res = DAG.getNode(ISD::STACKSAVE, dl, 4987 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4988 setValue(&I, Res); 4989 DAG.setRoot(Res.getValue(1)); 4990 return 0; 4991 } 4992 case Intrinsic::stackrestore: { 4993 Res = getValue(I.getArgOperand(0)); 4994 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4995 return 0; 4996 } 4997 case Intrinsic::stackprotector: { 4998 // Emit code into the DAG to store the stack guard onto the stack. 4999 MachineFunction &MF = DAG.getMachineFunction(); 5000 MachineFrameInfo *MFI = MF.getFrameInfo(); 5001 EVT PtrTy = TLI.getPointerTy(); 5002 5003 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 5004 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 5005 5006 int FI = FuncInfo.StaticAllocaMap[Slot]; 5007 MFI->setStackProtectorIndex(FI); 5008 5009 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5010 5011 // Store the stack protector onto the stack. 5012 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 5013 MachinePointerInfo::getFixedStack(FI), 5014 true, false, 0); 5015 setValue(&I, Res); 5016 DAG.setRoot(Res); 5017 return 0; 5018 } 5019 case Intrinsic::objectsize: { 5020 // If we don't know by now, we're never going to know. 5021 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5022 5023 assert(CI && "Non-constant type in __builtin_object_size?"); 5024 5025 SDValue Arg = getValue(I.getCalledValue()); 5026 EVT Ty = Arg.getValueType(); 5027 5028 if (CI->isZero()) 5029 Res = DAG.getConstant(-1ULL, Ty); 5030 else 5031 Res = DAG.getConstant(0, Ty); 5032 5033 setValue(&I, Res); 5034 return 0; 5035 } 5036 case Intrinsic::var_annotation: 5037 // Discard annotate attributes 5038 return 0; 5039 5040 case Intrinsic::init_trampoline: { 5041 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5042 5043 SDValue Ops[6]; 5044 Ops[0] = getRoot(); 5045 Ops[1] = getValue(I.getArgOperand(0)); 5046 Ops[2] = getValue(I.getArgOperand(1)); 5047 Ops[3] = getValue(I.getArgOperand(2)); 5048 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5049 Ops[5] = DAG.getSrcValue(F); 5050 5051 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5052 5053 DAG.setRoot(Res); 5054 return 0; 5055 } 5056 case Intrinsic::adjust_trampoline: { 5057 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5058 TLI.getPointerTy(), 5059 getValue(I.getArgOperand(0)))); 5060 return 0; 5061 } 5062 case Intrinsic::gcroot: 5063 if (GFI) { 5064 const Value *Alloca = I.getArgOperand(0); 5065 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5066 5067 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5068 GFI->addStackRoot(FI->getIndex(), TypeMap); 5069 } 5070 return 0; 5071 case Intrinsic::gcread: 5072 case Intrinsic::gcwrite: 5073 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5074 case Intrinsic::flt_rounds: 5075 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5076 return 0; 5077 5078 case Intrinsic::expect: { 5079 // Just replace __builtin_expect(exp, c) with EXP. 5080 setValue(&I, getValue(I.getArgOperand(0))); 5081 return 0; 5082 } 5083 5084 case Intrinsic::trap: { 5085 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5086 if (TrapFuncName.empty()) { 5087 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5088 return 0; 5089 } 5090 TargetLowering::ArgListTy Args; 5091 std::pair<SDValue, SDValue> Result = 5092 TLI.LowerCallTo(getRoot(), I.getType(), 5093 false, false, false, false, 0, CallingConv::C, 5094 /*isTailCall=*/false, 5095 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5096 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5097 Args, DAG, getCurDebugLoc()); 5098 DAG.setRoot(Result.second); 5099 return 0; 5100 } 5101 case Intrinsic::uadd_with_overflow: 5102 return implVisitAluOverflow(I, ISD::UADDO); 5103 case Intrinsic::sadd_with_overflow: 5104 return implVisitAluOverflow(I, ISD::SADDO); 5105 case Intrinsic::usub_with_overflow: 5106 return implVisitAluOverflow(I, ISD::USUBO); 5107 case Intrinsic::ssub_with_overflow: 5108 return implVisitAluOverflow(I, ISD::SSUBO); 5109 case Intrinsic::umul_with_overflow: 5110 return implVisitAluOverflow(I, ISD::UMULO); 5111 case Intrinsic::smul_with_overflow: 5112 return implVisitAluOverflow(I, ISD::SMULO); 5113 5114 case Intrinsic::prefetch: { 5115 SDValue Ops[5]; 5116 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5117 Ops[0] = getRoot(); 5118 Ops[1] = getValue(I.getArgOperand(0)); 5119 Ops[2] = getValue(I.getArgOperand(1)); 5120 Ops[3] = getValue(I.getArgOperand(2)); 5121 Ops[4] = getValue(I.getArgOperand(3)); 5122 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5123 DAG.getVTList(MVT::Other), 5124 &Ops[0], 5, 5125 EVT::getIntegerVT(*Context, 8), 5126 MachinePointerInfo(I.getArgOperand(0)), 5127 0, /* align */ 5128 false, /* volatile */ 5129 rw==0, /* read */ 5130 rw==1)); /* write */ 5131 return 0; 5132 } 5133 5134 case Intrinsic::invariant_start: 5135 case Intrinsic::lifetime_start: 5136 // Discard region information. 5137 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5138 return 0; 5139 case Intrinsic::invariant_end: 5140 case Intrinsic::lifetime_end: 5141 // Discard region information. 5142 return 0; 5143 } 5144} 5145 5146void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5147 bool isTailCall, 5148 MachineBasicBlock *LandingPad) { 5149 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5150 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5151 Type *RetTy = FTy->getReturnType(); 5152 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5153 MCSymbol *BeginLabel = 0; 5154 5155 TargetLowering::ArgListTy Args; 5156 TargetLowering::ArgListEntry Entry; 5157 Args.reserve(CS.arg_size()); 5158 5159 // Check whether the function can return without sret-demotion. 5160 SmallVector<ISD::OutputArg, 4> Outs; 5161 SmallVector<uint64_t, 4> Offsets; 5162 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5163 Outs, TLI, &Offsets); 5164 5165 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5166 DAG.getMachineFunction(), 5167 FTy->isVarArg(), Outs, 5168 FTy->getContext()); 5169 5170 SDValue DemoteStackSlot; 5171 int DemoteStackIdx = -100; 5172 5173 if (!CanLowerReturn) { 5174 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5175 FTy->getReturnType()); 5176 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5177 FTy->getReturnType()); 5178 MachineFunction &MF = DAG.getMachineFunction(); 5179 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5180 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5181 5182 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5183 Entry.Node = DemoteStackSlot; 5184 Entry.Ty = StackSlotPtrType; 5185 Entry.isSExt = false; 5186 Entry.isZExt = false; 5187 Entry.isInReg = false; 5188 Entry.isSRet = true; 5189 Entry.isNest = false; 5190 Entry.isByVal = false; 5191 Entry.Alignment = Align; 5192 Args.push_back(Entry); 5193 RetTy = Type::getVoidTy(FTy->getContext()); 5194 } 5195 5196 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5197 i != e; ++i) { 5198 const Value *V = *i; 5199 5200 // Skip empty types 5201 if (V->getType()->isEmptyTy()) 5202 continue; 5203 5204 SDValue ArgNode = getValue(V); 5205 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5206 5207 unsigned attrInd = i - CS.arg_begin() + 1; 5208 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5209 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5210 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5211 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5212 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5213 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5214 Entry.Alignment = CS.getParamAlignment(attrInd); 5215 Args.push_back(Entry); 5216 } 5217 5218 if (LandingPad) { 5219 // Insert a label before the invoke call to mark the try range. This can be 5220 // used to detect deletion of the invoke via the MachineModuleInfo. 5221 BeginLabel = MMI.getContext().CreateTempSymbol(); 5222 5223 // For SjLj, keep track of which landing pads go with which invokes 5224 // so as to maintain the ordering of pads in the LSDA. 5225 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5226 if (CallSiteIndex) { 5227 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5228 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5229 5230 // Now that the call site is handled, stop tracking it. 5231 MMI.setCurrentCallSite(0); 5232 } 5233 5234 // Both PendingLoads and PendingExports must be flushed here; 5235 // this call might not return. 5236 (void)getRoot(); 5237 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5238 } 5239 5240 // Check if target-independent constraints permit a tail call here. 5241 // Target-dependent constraints are checked within TLI.LowerCallTo. 5242 if (isTailCall && 5243 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5244 isTailCall = false; 5245 5246 // If there's a possibility that fast-isel has already selected some amount 5247 // of the current basic block, don't emit a tail call. 5248 if (isTailCall && TM.Options.EnableFastISel) 5249 isTailCall = false; 5250 5251 std::pair<SDValue,SDValue> Result = 5252 TLI.LowerCallTo(getRoot(), RetTy, 5253 CS.paramHasAttr(0, Attribute::SExt), 5254 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5255 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5256 CS.getCallingConv(), 5257 isTailCall, 5258 CS.doesNotReturn(), 5259 !CS.getInstruction()->use_empty(), 5260 Callee, Args, DAG, getCurDebugLoc()); 5261 assert((isTailCall || Result.second.getNode()) && 5262 "Non-null chain expected with non-tail call!"); 5263 assert((Result.second.getNode() || !Result.first.getNode()) && 5264 "Null value expected with tail call!"); 5265 if (Result.first.getNode()) { 5266 setValue(CS.getInstruction(), Result.first); 5267 } else if (!CanLowerReturn && Result.second.getNode()) { 5268 // The instruction result is the result of loading from the 5269 // hidden sret parameter. 5270 SmallVector<EVT, 1> PVTs; 5271 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5272 5273 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5274 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5275 EVT PtrVT = PVTs[0]; 5276 unsigned NumValues = Outs.size(); 5277 SmallVector<SDValue, 4> Values(NumValues); 5278 SmallVector<SDValue, 4> Chains(NumValues); 5279 5280 for (unsigned i = 0; i < NumValues; ++i) { 5281 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5282 DemoteStackSlot, 5283 DAG.getConstant(Offsets[i], PtrVT)); 5284 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5285 Add, 5286 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5287 false, false, false, 1); 5288 Values[i] = L; 5289 Chains[i] = L.getValue(1); 5290 } 5291 5292 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5293 MVT::Other, &Chains[0], NumValues); 5294 PendingLoads.push_back(Chain); 5295 5296 // Collect the legal value parts into potentially illegal values 5297 // that correspond to the original function's return values. 5298 SmallVector<EVT, 4> RetTys; 5299 RetTy = FTy->getReturnType(); 5300 ComputeValueVTs(TLI, RetTy, RetTys); 5301 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5302 SmallVector<SDValue, 4> ReturnValues; 5303 unsigned CurReg = 0; 5304 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5305 EVT VT = RetTys[I]; 5306 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5307 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5308 5309 SDValue ReturnValue = 5310 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5311 RegisterVT, VT, AssertOp); 5312 ReturnValues.push_back(ReturnValue); 5313 CurReg += NumRegs; 5314 } 5315 5316 setValue(CS.getInstruction(), 5317 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5318 DAG.getVTList(&RetTys[0], RetTys.size()), 5319 &ReturnValues[0], ReturnValues.size())); 5320 } 5321 5322 // Assign order to nodes here. If the call does not produce a result, it won't 5323 // be mapped to a SDNode and visit() will not assign it an order number. 5324 if (!Result.second.getNode()) { 5325 // As a special case, a null chain means that a tail call has been emitted and 5326 // the DAG root is already updated. 5327 HasTailCall = true; 5328 ++SDNodeOrder; 5329 AssignOrderingToNode(DAG.getRoot().getNode()); 5330 } else { 5331 DAG.setRoot(Result.second); 5332 ++SDNodeOrder; 5333 AssignOrderingToNode(Result.second.getNode()); 5334 } 5335 5336 if (LandingPad) { 5337 // Insert a label at the end of the invoke call to mark the try range. This 5338 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5339 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5340 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5341 5342 // Inform MachineModuleInfo of range. 5343 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5344 } 5345} 5346 5347/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5348/// value is equal or not-equal to zero. 5349static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5350 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5351 UI != E; ++UI) { 5352 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5353 if (IC->isEquality()) 5354 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5355 if (C->isNullValue()) 5356 continue; 5357 // Unknown instruction. 5358 return false; 5359 } 5360 return true; 5361} 5362 5363static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5364 Type *LoadTy, 5365 SelectionDAGBuilder &Builder) { 5366 5367 // Check to see if this load can be trivially constant folded, e.g. if the 5368 // input is from a string literal. 5369 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5370 // Cast pointer to the type we really want to load. 5371 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5372 PointerType::getUnqual(LoadTy)); 5373 5374 if (const Constant *LoadCst = 5375 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5376 Builder.TD)) 5377 return Builder.getValue(LoadCst); 5378 } 5379 5380 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5381 // still constant memory, the input chain can be the entry node. 5382 SDValue Root; 5383 bool ConstantMemory = false; 5384 5385 // Do not serialize (non-volatile) loads of constant memory with anything. 5386 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5387 Root = Builder.DAG.getEntryNode(); 5388 ConstantMemory = true; 5389 } else { 5390 // Do not serialize non-volatile loads against each other. 5391 Root = Builder.DAG.getRoot(); 5392 } 5393 5394 SDValue Ptr = Builder.getValue(PtrVal); 5395 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5396 Ptr, MachinePointerInfo(PtrVal), 5397 false /*volatile*/, 5398 false /*nontemporal*/, 5399 false /*isinvariant*/, 1 /* align=1 */); 5400 5401 if (!ConstantMemory) 5402 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5403 return LoadVal; 5404} 5405 5406 5407/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5408/// If so, return true and lower it, otherwise return false and it will be 5409/// lowered like a normal call. 5410bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5411 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5412 if (I.getNumArgOperands() != 3) 5413 return false; 5414 5415 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5416 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5417 !I.getArgOperand(2)->getType()->isIntegerTy() || 5418 !I.getType()->isIntegerTy()) 5419 return false; 5420 5421 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5422 5423 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5424 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5425 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5426 bool ActuallyDoIt = true; 5427 MVT LoadVT; 5428 Type *LoadTy; 5429 switch (Size->getZExtValue()) { 5430 default: 5431 LoadVT = MVT::Other; 5432 LoadTy = 0; 5433 ActuallyDoIt = false; 5434 break; 5435 case 2: 5436 LoadVT = MVT::i16; 5437 LoadTy = Type::getInt16Ty(Size->getContext()); 5438 break; 5439 case 4: 5440 LoadVT = MVT::i32; 5441 LoadTy = Type::getInt32Ty(Size->getContext()); 5442 break; 5443 case 8: 5444 LoadVT = MVT::i64; 5445 LoadTy = Type::getInt64Ty(Size->getContext()); 5446 break; 5447 /* 5448 case 16: 5449 LoadVT = MVT::v4i32; 5450 LoadTy = Type::getInt32Ty(Size->getContext()); 5451 LoadTy = VectorType::get(LoadTy, 4); 5452 break; 5453 */ 5454 } 5455 5456 // This turns into unaligned loads. We only do this if the target natively 5457 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5458 // we'll only produce a small number of byte loads. 5459 5460 // Require that we can find a legal MVT, and only do this if the target 5461 // supports unaligned loads of that type. Expanding into byte loads would 5462 // bloat the code. 5463 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5464 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5465 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5466 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5467 ActuallyDoIt = false; 5468 } 5469 5470 if (ActuallyDoIt) { 5471 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5472 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5473 5474 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5475 ISD::SETNE); 5476 EVT CallVT = TLI.getValueType(I.getType(), true); 5477 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5478 return true; 5479 } 5480 } 5481 5482 5483 return false; 5484} 5485 5486 5487void SelectionDAGBuilder::visitCall(const CallInst &I) { 5488 // Handle inline assembly differently. 5489 if (isa<InlineAsm>(I.getCalledValue())) { 5490 visitInlineAsm(&I); 5491 return; 5492 } 5493 5494 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5495 ComputeUsesVAFloatArgument(I, &MMI); 5496 5497 const char *RenameFn = 0; 5498 if (Function *F = I.getCalledFunction()) { 5499 if (F->isDeclaration()) { 5500 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5501 if (unsigned IID = II->getIntrinsicID(F)) { 5502 RenameFn = visitIntrinsicCall(I, IID); 5503 if (!RenameFn) 5504 return; 5505 } 5506 } 5507 if (unsigned IID = F->getIntrinsicID()) { 5508 RenameFn = visitIntrinsicCall(I, IID); 5509 if (!RenameFn) 5510 return; 5511 } 5512 } 5513 5514 // Check for well-known libc/libm calls. If the function is internal, it 5515 // can't be a library call. 5516 if (!F->hasLocalLinkage() && F->hasName()) { 5517 StringRef Name = F->getName(); 5518 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") || 5519 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") || 5520 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) { 5521 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5522 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5523 I.getType() == I.getArgOperand(0)->getType() && 5524 I.getType() == I.getArgOperand(1)->getType()) { 5525 SDValue LHS = getValue(I.getArgOperand(0)); 5526 SDValue RHS = getValue(I.getArgOperand(1)); 5527 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5528 LHS.getValueType(), LHS, RHS)); 5529 return; 5530 } 5531 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") || 5532 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") || 5533 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) { 5534 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5535 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5536 I.getType() == I.getArgOperand(0)->getType()) { 5537 SDValue Tmp = getValue(I.getArgOperand(0)); 5538 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5539 Tmp.getValueType(), Tmp)); 5540 return; 5541 } 5542 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") || 5543 (LibInfo->has(LibFunc::sinf) && Name == "sinf") || 5544 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) { 5545 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5546 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5547 I.getType() == I.getArgOperand(0)->getType() && 5548 I.onlyReadsMemory()) { 5549 SDValue Tmp = getValue(I.getArgOperand(0)); 5550 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5551 Tmp.getValueType(), Tmp)); 5552 return; 5553 } 5554 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") || 5555 (LibInfo->has(LibFunc::cosf) && Name == "cosf") || 5556 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) { 5557 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5558 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5559 I.getType() == I.getArgOperand(0)->getType() && 5560 I.onlyReadsMemory()) { 5561 SDValue Tmp = getValue(I.getArgOperand(0)); 5562 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5563 Tmp.getValueType(), Tmp)); 5564 return; 5565 } 5566 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") || 5567 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") || 5568 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) { 5569 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5570 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5571 I.getType() == I.getArgOperand(0)->getType() && 5572 I.onlyReadsMemory()) { 5573 SDValue Tmp = getValue(I.getArgOperand(0)); 5574 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5575 Tmp.getValueType(), Tmp)); 5576 return; 5577 } 5578 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") || 5579 (LibInfo->has(LibFunc::floorf) && Name == "floorf") || 5580 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) { 5581 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5582 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5583 I.getType() == I.getArgOperand(0)->getType()) { 5584 SDValue Tmp = getValue(I.getArgOperand(0)); 5585 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(), 5586 Tmp.getValueType(), Tmp)); 5587 return; 5588 } 5589 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") || 5590 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") || 5591 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) { 5592 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5593 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5594 I.getType() == I.getArgOperand(0)->getType()) { 5595 SDValue Tmp = getValue(I.getArgOperand(0)); 5596 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(), 5597 Tmp.getValueType(), Tmp)); 5598 return; 5599 } 5600 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") || 5601 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") || 5602 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) { 5603 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5604 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5605 I.getType() == I.getArgOperand(0)->getType()) { 5606 SDValue Tmp = getValue(I.getArgOperand(0)); 5607 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(), 5608 Tmp.getValueType(), Tmp)); 5609 return; 5610 } 5611 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") || 5612 (LibInfo->has(LibFunc::rintf) && Name == "rintf") || 5613 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) { 5614 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5615 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5616 I.getType() == I.getArgOperand(0)->getType()) { 5617 SDValue Tmp = getValue(I.getArgOperand(0)); 5618 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(), 5619 Tmp.getValueType(), Tmp)); 5620 return; 5621 } 5622 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") || 5623 (LibInfo->has(LibFunc::truncf) && Name == "truncf") || 5624 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) { 5625 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5626 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5627 I.getType() == I.getArgOperand(0)->getType()) { 5628 SDValue Tmp = getValue(I.getArgOperand(0)); 5629 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(), 5630 Tmp.getValueType(), Tmp)); 5631 return; 5632 } 5633 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") || 5634 (LibInfo->has(LibFunc::log2f) && Name == "log2f") || 5635 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) { 5636 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5637 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5638 I.getType() == I.getArgOperand(0)->getType() && 5639 I.onlyReadsMemory()) { 5640 SDValue Tmp = getValue(I.getArgOperand(0)); 5641 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(), 5642 Tmp.getValueType(), Tmp)); 5643 return; 5644 } 5645 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") || 5646 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") || 5647 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) { 5648 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5649 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5650 I.getType() == I.getArgOperand(0)->getType() && 5651 I.onlyReadsMemory()) { 5652 SDValue Tmp = getValue(I.getArgOperand(0)); 5653 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(), 5654 Tmp.getValueType(), Tmp)); 5655 return; 5656 } 5657 } else if (Name == "memcmp") { 5658 if (visitMemCmpCall(I)) 5659 return; 5660 } 5661 } 5662 } 5663 5664 SDValue Callee; 5665 if (!RenameFn) 5666 Callee = getValue(I.getCalledValue()); 5667 else 5668 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5669 5670 // Check if we can potentially perform a tail call. More detailed checking is 5671 // be done within LowerCallTo, after more information about the call is known. 5672 LowerCallTo(&I, Callee, I.isTailCall()); 5673} 5674 5675namespace { 5676 5677/// AsmOperandInfo - This contains information for each constraint that we are 5678/// lowering. 5679class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5680public: 5681 /// CallOperand - If this is the result output operand or a clobber 5682 /// this is null, otherwise it is the incoming operand to the CallInst. 5683 /// This gets modified as the asm is processed. 5684 SDValue CallOperand; 5685 5686 /// AssignedRegs - If this is a register or register class operand, this 5687 /// contains the set of register corresponding to the operand. 5688 RegsForValue AssignedRegs; 5689 5690 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5691 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5692 } 5693 5694 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5695 /// corresponds to. If there is no Value* for this operand, it returns 5696 /// MVT::Other. 5697 EVT getCallOperandValEVT(LLVMContext &Context, 5698 const TargetLowering &TLI, 5699 const TargetData *TD) const { 5700 if (CallOperandVal == 0) return MVT::Other; 5701 5702 if (isa<BasicBlock>(CallOperandVal)) 5703 return TLI.getPointerTy(); 5704 5705 llvm::Type *OpTy = CallOperandVal->getType(); 5706 5707 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5708 // If this is an indirect operand, the operand is a pointer to the 5709 // accessed type. 5710 if (isIndirect) { 5711 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5712 if (!PtrTy) 5713 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5714 OpTy = PtrTy->getElementType(); 5715 } 5716 5717 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5718 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5719 if (STy->getNumElements() == 1) 5720 OpTy = STy->getElementType(0); 5721 5722 // If OpTy is not a single value, it may be a struct/union that we 5723 // can tile with integers. 5724 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5725 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5726 switch (BitSize) { 5727 default: break; 5728 case 1: 5729 case 8: 5730 case 16: 5731 case 32: 5732 case 64: 5733 case 128: 5734 OpTy = IntegerType::get(Context, BitSize); 5735 break; 5736 } 5737 } 5738 5739 return TLI.getValueType(OpTy, true); 5740 } 5741}; 5742 5743typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5744 5745} // end anonymous namespace 5746 5747/// GetRegistersForValue - Assign registers (virtual or physical) for the 5748/// specified operand. We prefer to assign virtual registers, to allow the 5749/// register allocator to handle the assignment process. However, if the asm 5750/// uses features that we can't model on machineinstrs, we have SDISel do the 5751/// allocation. This produces generally horrible, but correct, code. 5752/// 5753/// OpInfo describes the operand. 5754/// 5755static void GetRegistersForValue(SelectionDAG &DAG, 5756 const TargetLowering &TLI, 5757 DebugLoc DL, 5758 SDISelAsmOperandInfo &OpInfo) { 5759 LLVMContext &Context = *DAG.getContext(); 5760 5761 MachineFunction &MF = DAG.getMachineFunction(); 5762 SmallVector<unsigned, 4> Regs; 5763 5764 // If this is a constraint for a single physreg, or a constraint for a 5765 // register class, find it. 5766 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5767 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5768 OpInfo.ConstraintVT); 5769 5770 unsigned NumRegs = 1; 5771 if (OpInfo.ConstraintVT != MVT::Other) { 5772 // If this is a FP input in an integer register (or visa versa) insert a bit 5773 // cast of the input value. More generally, handle any case where the input 5774 // value disagrees with the register class we plan to stick this in. 5775 if (OpInfo.Type == InlineAsm::isInput && 5776 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5777 // Try to convert to the first EVT that the reg class contains. If the 5778 // types are identical size, use a bitcast to convert (e.g. two differing 5779 // vector types). 5780 EVT RegVT = *PhysReg.second->vt_begin(); 5781 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5782 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5783 RegVT, OpInfo.CallOperand); 5784 OpInfo.ConstraintVT = RegVT; 5785 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5786 // If the input is a FP value and we want it in FP registers, do a 5787 // bitcast to the corresponding integer type. This turns an f64 value 5788 // into i64, which can be passed with two i32 values on a 32-bit 5789 // machine. 5790 RegVT = EVT::getIntegerVT(Context, 5791 OpInfo.ConstraintVT.getSizeInBits()); 5792 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5793 RegVT, OpInfo.CallOperand); 5794 OpInfo.ConstraintVT = RegVT; 5795 } 5796 } 5797 5798 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5799 } 5800 5801 EVT RegVT; 5802 EVT ValueVT = OpInfo.ConstraintVT; 5803 5804 // If this is a constraint for a specific physical register, like {r17}, 5805 // assign it now. 5806 if (unsigned AssignedReg = PhysReg.first) { 5807 const TargetRegisterClass *RC = PhysReg.second; 5808 if (OpInfo.ConstraintVT == MVT::Other) 5809 ValueVT = *RC->vt_begin(); 5810 5811 // Get the actual register value type. This is important, because the user 5812 // may have asked for (e.g.) the AX register in i32 type. We need to 5813 // remember that AX is actually i16 to get the right extension. 5814 RegVT = *RC->vt_begin(); 5815 5816 // This is a explicit reference to a physical register. 5817 Regs.push_back(AssignedReg); 5818 5819 // If this is an expanded reference, add the rest of the regs to Regs. 5820 if (NumRegs != 1) { 5821 TargetRegisterClass::iterator I = RC->begin(); 5822 for (; *I != AssignedReg; ++I) 5823 assert(I != RC->end() && "Didn't find reg!"); 5824 5825 // Already added the first reg. 5826 --NumRegs; ++I; 5827 for (; NumRegs; --NumRegs, ++I) { 5828 assert(I != RC->end() && "Ran out of registers to allocate!"); 5829 Regs.push_back(*I); 5830 } 5831 } 5832 5833 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5834 return; 5835 } 5836 5837 // Otherwise, if this was a reference to an LLVM register class, create vregs 5838 // for this reference. 5839 if (const TargetRegisterClass *RC = PhysReg.second) { 5840 RegVT = *RC->vt_begin(); 5841 if (OpInfo.ConstraintVT == MVT::Other) 5842 ValueVT = RegVT; 5843 5844 // Create the appropriate number of virtual registers. 5845 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5846 for (; NumRegs; --NumRegs) 5847 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5848 5849 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5850 return; 5851 } 5852 5853 // Otherwise, we couldn't allocate enough registers for this. 5854} 5855 5856/// visitInlineAsm - Handle a call to an InlineAsm object. 5857/// 5858void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5859 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5860 5861 /// ConstraintOperands - Information about all of the constraints. 5862 SDISelAsmOperandInfoVector ConstraintOperands; 5863 5864 TargetLowering::AsmOperandInfoVector 5865 TargetConstraints = TLI.ParseConstraints(CS); 5866 5867 bool hasMemory = false; 5868 5869 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5870 unsigned ResNo = 0; // ResNo - The result number of the next output. 5871 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5872 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5873 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5874 5875 EVT OpVT = MVT::Other; 5876 5877 // Compute the value type for each operand. 5878 switch (OpInfo.Type) { 5879 case InlineAsm::isOutput: 5880 // Indirect outputs just consume an argument. 5881 if (OpInfo.isIndirect) { 5882 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5883 break; 5884 } 5885 5886 // The return value of the call is this value. As such, there is no 5887 // corresponding argument. 5888 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5889 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5890 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5891 } else { 5892 assert(ResNo == 0 && "Asm only has one result!"); 5893 OpVT = TLI.getValueType(CS.getType()); 5894 } 5895 ++ResNo; 5896 break; 5897 case InlineAsm::isInput: 5898 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5899 break; 5900 case InlineAsm::isClobber: 5901 // Nothing to do. 5902 break; 5903 } 5904 5905 // If this is an input or an indirect output, process the call argument. 5906 // BasicBlocks are labels, currently appearing only in asm's. 5907 if (OpInfo.CallOperandVal) { 5908 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5909 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5910 } else { 5911 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5912 } 5913 5914 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5915 } 5916 5917 OpInfo.ConstraintVT = OpVT; 5918 5919 // Indirect operand accesses access memory. 5920 if (OpInfo.isIndirect) 5921 hasMemory = true; 5922 else { 5923 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5924 TargetLowering::ConstraintType 5925 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5926 if (CType == TargetLowering::C_Memory) { 5927 hasMemory = true; 5928 break; 5929 } 5930 } 5931 } 5932 } 5933 5934 SDValue Chain, Flag; 5935 5936 // We won't need to flush pending loads if this asm doesn't touch 5937 // memory and is nonvolatile. 5938 if (hasMemory || IA->hasSideEffects()) 5939 Chain = getRoot(); 5940 else 5941 Chain = DAG.getRoot(); 5942 5943 // Second pass over the constraints: compute which constraint option to use 5944 // and assign registers to constraints that want a specific physreg. 5945 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5946 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5947 5948 // If this is an output operand with a matching input operand, look up the 5949 // matching input. If their types mismatch, e.g. one is an integer, the 5950 // other is floating point, or their sizes are different, flag it as an 5951 // error. 5952 if (OpInfo.hasMatchingInput()) { 5953 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5954 5955 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5956 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5957 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5958 OpInfo.ConstraintVT); 5959 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5960 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5961 Input.ConstraintVT); 5962 if ((OpInfo.ConstraintVT.isInteger() != 5963 Input.ConstraintVT.isInteger()) || 5964 (MatchRC.second != InputRC.second)) { 5965 report_fatal_error("Unsupported asm: input constraint" 5966 " with a matching output constraint of" 5967 " incompatible type!"); 5968 } 5969 Input.ConstraintVT = OpInfo.ConstraintVT; 5970 } 5971 } 5972 5973 // Compute the constraint code and ConstraintType to use. 5974 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5975 5976 // If this is a memory input, and if the operand is not indirect, do what we 5977 // need to to provide an address for the memory input. 5978 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5979 !OpInfo.isIndirect) { 5980 assert((OpInfo.isMultipleAlternative || 5981 (OpInfo.Type == InlineAsm::isInput)) && 5982 "Can only indirectify direct input operands!"); 5983 5984 // Memory operands really want the address of the value. If we don't have 5985 // an indirect input, put it in the constpool if we can, otherwise spill 5986 // it to a stack slot. 5987 // TODO: This isn't quite right. We need to handle these according to 5988 // the addressing mode that the constraint wants. Also, this may take 5989 // an additional register for the computation and we don't want that 5990 // either. 5991 5992 // If the operand is a float, integer, or vector constant, spill to a 5993 // constant pool entry to get its address. 5994 const Value *OpVal = OpInfo.CallOperandVal; 5995 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5996 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 5997 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5998 TLI.getPointerTy()); 5999 } else { 6000 // Otherwise, create a stack slot and emit a store to it before the 6001 // asm. 6002 Type *Ty = OpVal->getType(); 6003 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 6004 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 6005 MachineFunction &MF = DAG.getMachineFunction(); 6006 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6007 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 6008 Chain = DAG.getStore(Chain, getCurDebugLoc(), 6009 OpInfo.CallOperand, StackSlot, 6010 MachinePointerInfo::getFixedStack(SSFI), 6011 false, false, 0); 6012 OpInfo.CallOperand = StackSlot; 6013 } 6014 6015 // There is no longer a Value* corresponding to this operand. 6016 OpInfo.CallOperandVal = 0; 6017 6018 // It is now an indirect operand. 6019 OpInfo.isIndirect = true; 6020 } 6021 6022 // If this constraint is for a specific register, allocate it before 6023 // anything else. 6024 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6025 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6026 } 6027 6028 // Second pass - Loop over all of the operands, assigning virtual or physregs 6029 // to register class operands. 6030 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6031 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6032 6033 // C_Register operands have already been allocated, Other/Memory don't need 6034 // to be. 6035 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6036 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6037 } 6038 6039 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6040 std::vector<SDValue> AsmNodeOperands; 6041 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6042 AsmNodeOperands.push_back( 6043 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6044 TLI.getPointerTy())); 6045 6046 // If we have a !srcloc metadata node associated with it, we want to attach 6047 // this to the ultimately generated inline asm machineinstr. To do this, we 6048 // pass in the third operand as this (potentially null) inline asm MDNode. 6049 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6050 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6051 6052 // Remember the HasSideEffect and AlignStack bits as operand 3. 6053 unsigned ExtraInfo = 0; 6054 if (IA->hasSideEffects()) 6055 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6056 if (IA->isAlignStack()) 6057 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6058 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6059 TLI.getPointerTy())); 6060 6061 // Loop over all of the inputs, copying the operand values into the 6062 // appropriate registers and processing the output regs. 6063 RegsForValue RetValRegs; 6064 6065 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6066 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6067 6068 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6069 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6070 6071 switch (OpInfo.Type) { 6072 case InlineAsm::isOutput: { 6073 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6074 OpInfo.ConstraintType != TargetLowering::C_Register) { 6075 // Memory output, or 'other' output (e.g. 'X' constraint). 6076 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6077 6078 // Add information to the INLINEASM node to know about this output. 6079 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6080 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6081 TLI.getPointerTy())); 6082 AsmNodeOperands.push_back(OpInfo.CallOperand); 6083 break; 6084 } 6085 6086 // Otherwise, this is a register or register class output. 6087 6088 // Copy the output from the appropriate register. Find a register that 6089 // we can use. 6090 if (OpInfo.AssignedRegs.Regs.empty()) { 6091 LLVMContext &Ctx = *DAG.getContext(); 6092 Ctx.emitError(CS.getInstruction(), 6093 "couldn't allocate output register for constraint '" + 6094 Twine(OpInfo.ConstraintCode) + "'"); 6095 break; 6096 } 6097 6098 // If this is an indirect operand, store through the pointer after the 6099 // asm. 6100 if (OpInfo.isIndirect) { 6101 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6102 OpInfo.CallOperandVal)); 6103 } else { 6104 // This is the result value of the call. 6105 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6106 // Concatenate this output onto the outputs list. 6107 RetValRegs.append(OpInfo.AssignedRegs); 6108 } 6109 6110 // Add information to the INLINEASM node to know that this register is 6111 // set. 6112 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6113 InlineAsm::Kind_RegDefEarlyClobber : 6114 InlineAsm::Kind_RegDef, 6115 false, 6116 0, 6117 DAG, 6118 AsmNodeOperands); 6119 break; 6120 } 6121 case InlineAsm::isInput: { 6122 SDValue InOperandVal = OpInfo.CallOperand; 6123 6124 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6125 // If this is required to match an output register we have already set, 6126 // just use its register. 6127 unsigned OperandNo = OpInfo.getMatchedOperand(); 6128 6129 // Scan until we find the definition we already emitted of this operand. 6130 // When we find it, create a RegsForValue operand. 6131 unsigned CurOp = InlineAsm::Op_FirstOperand; 6132 for (; OperandNo; --OperandNo) { 6133 // Advance to the next operand. 6134 unsigned OpFlag = 6135 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6136 assert((InlineAsm::isRegDefKind(OpFlag) || 6137 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6138 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6139 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6140 } 6141 6142 unsigned OpFlag = 6143 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6144 if (InlineAsm::isRegDefKind(OpFlag) || 6145 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6146 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6147 if (OpInfo.isIndirect) { 6148 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6149 LLVMContext &Ctx = *DAG.getContext(); 6150 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6151 " don't know how to handle tied " 6152 "indirect register inputs"); 6153 } 6154 6155 RegsForValue MatchedRegs; 6156 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6157 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6158 MatchedRegs.RegVTs.push_back(RegVT); 6159 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6160 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6161 i != e; ++i) 6162 MatchedRegs.Regs.push_back 6163 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6164 6165 // Use the produced MatchedRegs object to 6166 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6167 Chain, &Flag); 6168 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6169 true, OpInfo.getMatchedOperand(), 6170 DAG, AsmNodeOperands); 6171 break; 6172 } 6173 6174 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6175 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6176 "Unexpected number of operands"); 6177 // Add information to the INLINEASM node to know about this input. 6178 // See InlineAsm.h isUseOperandTiedToDef. 6179 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6180 OpInfo.getMatchedOperand()); 6181 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6182 TLI.getPointerTy())); 6183 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6184 break; 6185 } 6186 6187 // Treat indirect 'X' constraint as memory. 6188 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6189 OpInfo.isIndirect) 6190 OpInfo.ConstraintType = TargetLowering::C_Memory; 6191 6192 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6193 std::vector<SDValue> Ops; 6194 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6195 Ops, DAG); 6196 if (Ops.empty()) { 6197 LLVMContext &Ctx = *DAG.getContext(); 6198 Ctx.emitError(CS.getInstruction(), 6199 "invalid operand for inline asm constraint '" + 6200 Twine(OpInfo.ConstraintCode) + "'"); 6201 break; 6202 } 6203 6204 // Add information to the INLINEASM node to know about this input. 6205 unsigned ResOpType = 6206 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6207 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6208 TLI.getPointerTy())); 6209 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6210 break; 6211 } 6212 6213 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6214 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6215 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6216 "Memory operands expect pointer values"); 6217 6218 // Add information to the INLINEASM node to know about this input. 6219 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6220 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6221 TLI.getPointerTy())); 6222 AsmNodeOperands.push_back(InOperandVal); 6223 break; 6224 } 6225 6226 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6227 OpInfo.ConstraintType == TargetLowering::C_Register) && 6228 "Unknown constraint type!"); 6229 assert(!OpInfo.isIndirect && 6230 "Don't know how to handle indirect register inputs yet!"); 6231 6232 // Copy the input into the appropriate registers. 6233 if (OpInfo.AssignedRegs.Regs.empty()) { 6234 LLVMContext &Ctx = *DAG.getContext(); 6235 Ctx.emitError(CS.getInstruction(), 6236 "couldn't allocate input reg for constraint '" + 6237 Twine(OpInfo.ConstraintCode) + "'"); 6238 break; 6239 } 6240 6241 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6242 Chain, &Flag); 6243 6244 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6245 DAG, AsmNodeOperands); 6246 break; 6247 } 6248 case InlineAsm::isClobber: { 6249 // Add the clobbered value to the operand list, so that the register 6250 // allocator is aware that the physreg got clobbered. 6251 if (!OpInfo.AssignedRegs.Regs.empty()) 6252 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6253 false, 0, DAG, 6254 AsmNodeOperands); 6255 break; 6256 } 6257 } 6258 } 6259 6260 // Finish up input operands. Set the input chain and add the flag last. 6261 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6262 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6263 6264 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6265 DAG.getVTList(MVT::Other, MVT::Glue), 6266 &AsmNodeOperands[0], AsmNodeOperands.size()); 6267 Flag = Chain.getValue(1); 6268 6269 // If this asm returns a register value, copy the result from that register 6270 // and set it as the value of the call. 6271 if (!RetValRegs.Regs.empty()) { 6272 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6273 Chain, &Flag); 6274 6275 // FIXME: Why don't we do this for inline asms with MRVs? 6276 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6277 EVT ResultType = TLI.getValueType(CS.getType()); 6278 6279 // If any of the results of the inline asm is a vector, it may have the 6280 // wrong width/num elts. This can happen for register classes that can 6281 // contain multiple different value types. The preg or vreg allocated may 6282 // not have the same VT as was expected. Convert it to the right type 6283 // with bit_convert. 6284 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6285 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6286 ResultType, Val); 6287 6288 } else if (ResultType != Val.getValueType() && 6289 ResultType.isInteger() && Val.getValueType().isInteger()) { 6290 // If a result value was tied to an input value, the computed result may 6291 // have a wider width than the expected result. Extract the relevant 6292 // portion. 6293 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6294 } 6295 6296 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6297 } 6298 6299 setValue(CS.getInstruction(), Val); 6300 // Don't need to use this as a chain in this case. 6301 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6302 return; 6303 } 6304 6305 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6306 6307 // Process indirect outputs, first output all of the flagged copies out of 6308 // physregs. 6309 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6310 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6311 const Value *Ptr = IndirectStoresToEmit[i].second; 6312 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6313 Chain, &Flag); 6314 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6315 } 6316 6317 // Emit the non-flagged stores from the physregs. 6318 SmallVector<SDValue, 8> OutChains; 6319 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6320 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6321 StoresToEmit[i].first, 6322 getValue(StoresToEmit[i].second), 6323 MachinePointerInfo(StoresToEmit[i].second), 6324 false, false, 0); 6325 OutChains.push_back(Val); 6326 } 6327 6328 if (!OutChains.empty()) 6329 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6330 &OutChains[0], OutChains.size()); 6331 6332 DAG.setRoot(Chain); 6333} 6334 6335void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6336 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6337 MVT::Other, getRoot(), 6338 getValue(I.getArgOperand(0)), 6339 DAG.getSrcValue(I.getArgOperand(0)))); 6340} 6341 6342void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6343 const TargetData &TD = *TLI.getTargetData(); 6344 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6345 getRoot(), getValue(I.getOperand(0)), 6346 DAG.getSrcValue(I.getOperand(0)), 6347 TD.getABITypeAlignment(I.getType())); 6348 setValue(&I, V); 6349 DAG.setRoot(V.getValue(1)); 6350} 6351 6352void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6353 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6354 MVT::Other, getRoot(), 6355 getValue(I.getArgOperand(0)), 6356 DAG.getSrcValue(I.getArgOperand(0)))); 6357} 6358 6359void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6360 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6361 MVT::Other, getRoot(), 6362 getValue(I.getArgOperand(0)), 6363 getValue(I.getArgOperand(1)), 6364 DAG.getSrcValue(I.getArgOperand(0)), 6365 DAG.getSrcValue(I.getArgOperand(1)))); 6366} 6367 6368/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6369/// implementation, which just calls LowerCall. 6370/// FIXME: When all targets are 6371/// migrated to using LowerCall, this hook should be integrated into SDISel. 6372std::pair<SDValue, SDValue> 6373TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6374 bool RetSExt, bool RetZExt, bool isVarArg, 6375 bool isInreg, unsigned NumFixedArgs, 6376 CallingConv::ID CallConv, bool isTailCall, 6377 bool doesNotRet, bool isReturnValueUsed, 6378 SDValue Callee, 6379 ArgListTy &Args, SelectionDAG &DAG, 6380 DebugLoc dl) const { 6381 // Handle all of the outgoing arguments. 6382 SmallVector<ISD::OutputArg, 32> Outs; 6383 SmallVector<SDValue, 32> OutVals; 6384 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6385 SmallVector<EVT, 4> ValueVTs; 6386 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6387 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6388 Value != NumValues; ++Value) { 6389 EVT VT = ValueVTs[Value]; 6390 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6391 SDValue Op = SDValue(Args[i].Node.getNode(), 6392 Args[i].Node.getResNo() + Value); 6393 ISD::ArgFlagsTy Flags; 6394 unsigned OriginalAlignment = 6395 getTargetData()->getABITypeAlignment(ArgTy); 6396 6397 if (Args[i].isZExt) 6398 Flags.setZExt(); 6399 if (Args[i].isSExt) 6400 Flags.setSExt(); 6401 if (Args[i].isInReg) 6402 Flags.setInReg(); 6403 if (Args[i].isSRet) 6404 Flags.setSRet(); 6405 if (Args[i].isByVal) { 6406 Flags.setByVal(); 6407 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6408 Type *ElementTy = Ty->getElementType(); 6409 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6410 // For ByVal, alignment should come from FE. BE will guess if this 6411 // info is not there but there are cases it cannot get right. 6412 unsigned FrameAlign; 6413 if (Args[i].Alignment) 6414 FrameAlign = Args[i].Alignment; 6415 else 6416 FrameAlign = getByValTypeAlignment(ElementTy); 6417 Flags.setByValAlign(FrameAlign); 6418 } 6419 if (Args[i].isNest) 6420 Flags.setNest(); 6421 Flags.setOrigAlign(OriginalAlignment); 6422 6423 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6424 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6425 SmallVector<SDValue, 4> Parts(NumParts); 6426 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6427 6428 if (Args[i].isSExt) 6429 ExtendKind = ISD::SIGN_EXTEND; 6430 else if (Args[i].isZExt) 6431 ExtendKind = ISD::ZERO_EXTEND; 6432 6433 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6434 PartVT, ExtendKind); 6435 6436 for (unsigned j = 0; j != NumParts; ++j) { 6437 // if it isn't first piece, alignment must be 1 6438 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6439 i < NumFixedArgs); 6440 if (NumParts > 1 && j == 0) 6441 MyFlags.Flags.setSplit(); 6442 else if (j != 0) 6443 MyFlags.Flags.setOrigAlign(1); 6444 6445 Outs.push_back(MyFlags); 6446 OutVals.push_back(Parts[j]); 6447 } 6448 } 6449 } 6450 6451 // Handle the incoming return values from the call. 6452 SmallVector<ISD::InputArg, 32> Ins; 6453 SmallVector<EVT, 4> RetTys; 6454 ComputeValueVTs(*this, RetTy, RetTys); 6455 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6456 EVT VT = RetTys[I]; 6457 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6458 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6459 for (unsigned i = 0; i != NumRegs; ++i) { 6460 ISD::InputArg MyFlags; 6461 MyFlags.VT = RegisterVT.getSimpleVT(); 6462 MyFlags.Used = isReturnValueUsed; 6463 if (RetSExt) 6464 MyFlags.Flags.setSExt(); 6465 if (RetZExt) 6466 MyFlags.Flags.setZExt(); 6467 if (isInreg) 6468 MyFlags.Flags.setInReg(); 6469 Ins.push_back(MyFlags); 6470 } 6471 } 6472 6473 SmallVector<SDValue, 4> InVals; 6474 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, doesNotRet, isTailCall, 6475 Outs, OutVals, Ins, dl, DAG, InVals); 6476 6477 // Verify that the target's LowerCall behaved as expected. 6478 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6479 "LowerCall didn't return a valid chain!"); 6480 assert((!isTailCall || InVals.empty()) && 6481 "LowerCall emitted a return value for a tail call!"); 6482 assert((isTailCall || InVals.size() == Ins.size()) && 6483 "LowerCall didn't emit the correct number of values!"); 6484 6485 // For a tail call, the return value is merely live-out and there aren't 6486 // any nodes in the DAG representing it. Return a special value to 6487 // indicate that a tail call has been emitted and no more Instructions 6488 // should be processed in the current block. 6489 if (isTailCall) { 6490 DAG.setRoot(Chain); 6491 return std::make_pair(SDValue(), SDValue()); 6492 } 6493 6494 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6495 assert(InVals[i].getNode() && 6496 "LowerCall emitted a null value!"); 6497 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6498 "LowerCall emitted a value with the wrong type!"); 6499 }); 6500 6501 // Collect the legal value parts into potentially illegal values 6502 // that correspond to the original function's return values. 6503 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6504 if (RetSExt) 6505 AssertOp = ISD::AssertSext; 6506 else if (RetZExt) 6507 AssertOp = ISD::AssertZext; 6508 SmallVector<SDValue, 4> ReturnValues; 6509 unsigned CurReg = 0; 6510 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6511 EVT VT = RetTys[I]; 6512 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6513 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6514 6515 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6516 NumRegs, RegisterVT, VT, 6517 AssertOp)); 6518 CurReg += NumRegs; 6519 } 6520 6521 // For a function returning void, there is no return value. We can't create 6522 // such a node, so we just return a null return value in that case. In 6523 // that case, nothing will actually look at the value. 6524 if (ReturnValues.empty()) 6525 return std::make_pair(SDValue(), Chain); 6526 6527 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6528 DAG.getVTList(&RetTys[0], RetTys.size()), 6529 &ReturnValues[0], ReturnValues.size()); 6530 return std::make_pair(Res, Chain); 6531} 6532 6533void TargetLowering::LowerOperationWrapper(SDNode *N, 6534 SmallVectorImpl<SDValue> &Results, 6535 SelectionDAG &DAG) const { 6536 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6537 if (Res.getNode()) 6538 Results.push_back(Res); 6539} 6540 6541SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6542 llvm_unreachable("LowerOperation not implemented for this target!"); 6543} 6544 6545void 6546SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6547 SDValue Op = getNonRegisterValue(V); 6548 assert((Op.getOpcode() != ISD::CopyFromReg || 6549 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6550 "Copy from a reg to the same reg!"); 6551 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6552 6553 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6554 SDValue Chain = DAG.getEntryNode(); 6555 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6556 PendingExports.push_back(Chain); 6557} 6558 6559#include "llvm/CodeGen/SelectionDAGISel.h" 6560 6561/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6562/// entry block, return true. This includes arguments used by switches, since 6563/// the switch may expand into multiple basic blocks. 6564static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6565 // With FastISel active, we may be splitting blocks, so force creation 6566 // of virtual registers for all non-dead arguments. 6567 if (FastISel) 6568 return A->use_empty(); 6569 6570 const BasicBlock *Entry = A->getParent()->begin(); 6571 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6572 UI != E; ++UI) { 6573 const User *U = *UI; 6574 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6575 return false; // Use not in entry block. 6576 } 6577 return true; 6578} 6579 6580void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6581 // If this is the entry block, emit arguments. 6582 const Function &F = *LLVMBB->getParent(); 6583 SelectionDAG &DAG = SDB->DAG; 6584 DebugLoc dl = SDB->getCurDebugLoc(); 6585 const TargetData *TD = TLI.getTargetData(); 6586 SmallVector<ISD::InputArg, 16> Ins; 6587 6588 // Check whether the function can return without sret-demotion. 6589 SmallVector<ISD::OutputArg, 4> Outs; 6590 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6591 Outs, TLI); 6592 6593 if (!FuncInfo->CanLowerReturn) { 6594 // Put in an sret pointer parameter before all the other parameters. 6595 SmallVector<EVT, 1> ValueVTs; 6596 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6597 6598 // NOTE: Assuming that a pointer will never break down to more than one VT 6599 // or one register. 6600 ISD::ArgFlagsTy Flags; 6601 Flags.setSRet(); 6602 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6603 ISD::InputArg RetArg(Flags, RegisterVT, true); 6604 Ins.push_back(RetArg); 6605 } 6606 6607 // Set up the incoming argument description vector. 6608 unsigned Idx = 1; 6609 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6610 I != E; ++I, ++Idx) { 6611 SmallVector<EVT, 4> ValueVTs; 6612 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6613 bool isArgValueUsed = !I->use_empty(); 6614 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6615 Value != NumValues; ++Value) { 6616 EVT VT = ValueVTs[Value]; 6617 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6618 ISD::ArgFlagsTy Flags; 6619 unsigned OriginalAlignment = 6620 TD->getABITypeAlignment(ArgTy); 6621 6622 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6623 Flags.setZExt(); 6624 if (F.paramHasAttr(Idx, Attribute::SExt)) 6625 Flags.setSExt(); 6626 if (F.paramHasAttr(Idx, Attribute::InReg)) 6627 Flags.setInReg(); 6628 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6629 Flags.setSRet(); 6630 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6631 Flags.setByVal(); 6632 PointerType *Ty = cast<PointerType>(I->getType()); 6633 Type *ElementTy = Ty->getElementType(); 6634 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6635 // For ByVal, alignment should be passed from FE. BE will guess if 6636 // this info is not there but there are cases it cannot get right. 6637 unsigned FrameAlign; 6638 if (F.getParamAlignment(Idx)) 6639 FrameAlign = F.getParamAlignment(Idx); 6640 else 6641 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6642 Flags.setByValAlign(FrameAlign); 6643 } 6644 if (F.paramHasAttr(Idx, Attribute::Nest)) 6645 Flags.setNest(); 6646 Flags.setOrigAlign(OriginalAlignment); 6647 6648 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6649 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6650 for (unsigned i = 0; i != NumRegs; ++i) { 6651 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6652 if (NumRegs > 1 && i == 0) 6653 MyFlags.Flags.setSplit(); 6654 // if it isn't first piece, alignment must be 1 6655 else if (i > 0) 6656 MyFlags.Flags.setOrigAlign(1); 6657 Ins.push_back(MyFlags); 6658 } 6659 } 6660 } 6661 6662 // Call the target to set up the argument values. 6663 SmallVector<SDValue, 8> InVals; 6664 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6665 F.isVarArg(), Ins, 6666 dl, DAG, InVals); 6667 6668 // Verify that the target's LowerFormalArguments behaved as expected. 6669 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6670 "LowerFormalArguments didn't return a valid chain!"); 6671 assert(InVals.size() == Ins.size() && 6672 "LowerFormalArguments didn't emit the correct number of values!"); 6673 DEBUG({ 6674 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6675 assert(InVals[i].getNode() && 6676 "LowerFormalArguments emitted a null value!"); 6677 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6678 "LowerFormalArguments emitted a value with the wrong type!"); 6679 } 6680 }); 6681 6682 // Update the DAG with the new chain value resulting from argument lowering. 6683 DAG.setRoot(NewRoot); 6684 6685 // Set up the argument values. 6686 unsigned i = 0; 6687 Idx = 1; 6688 if (!FuncInfo->CanLowerReturn) { 6689 // Create a virtual register for the sret pointer, and put in a copy 6690 // from the sret argument into it. 6691 SmallVector<EVT, 1> ValueVTs; 6692 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6693 EVT VT = ValueVTs[0]; 6694 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6695 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6696 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6697 RegVT, VT, AssertOp); 6698 6699 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6700 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6701 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6702 FuncInfo->DemoteRegister = SRetReg; 6703 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6704 SRetReg, ArgValue); 6705 DAG.setRoot(NewRoot); 6706 6707 // i indexes lowered arguments. Bump it past the hidden sret argument. 6708 // Idx indexes LLVM arguments. Don't touch it. 6709 ++i; 6710 } 6711 6712 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6713 ++I, ++Idx) { 6714 SmallVector<SDValue, 4> ArgValues; 6715 SmallVector<EVT, 4> ValueVTs; 6716 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6717 unsigned NumValues = ValueVTs.size(); 6718 6719 // If this argument is unused then remember its value. It is used to generate 6720 // debugging information. 6721 if (I->use_empty() && NumValues) 6722 SDB->setUnusedArgValue(I, InVals[i]); 6723 6724 for (unsigned Val = 0; Val != NumValues; ++Val) { 6725 EVT VT = ValueVTs[Val]; 6726 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6727 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6728 6729 if (!I->use_empty()) { 6730 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6731 if (F.paramHasAttr(Idx, Attribute::SExt)) 6732 AssertOp = ISD::AssertSext; 6733 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6734 AssertOp = ISD::AssertZext; 6735 6736 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6737 NumParts, PartVT, VT, 6738 AssertOp)); 6739 } 6740 6741 i += NumParts; 6742 } 6743 6744 // We don't need to do anything else for unused arguments. 6745 if (ArgValues.empty()) 6746 continue; 6747 6748 // Note down frame index. 6749 if (FrameIndexSDNode *FI = 6750 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6751 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6752 6753 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6754 SDB->getCurDebugLoc()); 6755 6756 SDB->setValue(I, Res); 6757 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6758 if (LoadSDNode *LNode = 6759 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6760 if (FrameIndexSDNode *FI = 6761 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6762 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6763 } 6764 6765 // If this argument is live outside of the entry block, insert a copy from 6766 // wherever we got it to the vreg that other BB's will reference it as. 6767 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6768 // If we can, though, try to skip creating an unnecessary vreg. 6769 // FIXME: This isn't very clean... it would be nice to make this more 6770 // general. It's also subtly incompatible with the hacks FastISel 6771 // uses with vregs. 6772 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6773 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6774 FuncInfo->ValueMap[I] = Reg; 6775 continue; 6776 } 6777 } 6778 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6779 FuncInfo->InitializeRegForValue(I); 6780 SDB->CopyToExportRegsIfNeeded(I); 6781 } 6782 } 6783 6784 assert(i == InVals.size() && "Argument register count mismatch!"); 6785 6786 // Finally, if the target has anything special to do, allow it to do so. 6787 // FIXME: this should insert code into the DAG! 6788 EmitFunctionEntryCode(); 6789} 6790 6791/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6792/// ensure constants are generated when needed. Remember the virtual registers 6793/// that need to be added to the Machine PHI nodes as input. We cannot just 6794/// directly add them, because expansion might result in multiple MBB's for one 6795/// BB. As such, the start of the BB might correspond to a different MBB than 6796/// the end. 6797/// 6798void 6799SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6800 const TerminatorInst *TI = LLVMBB->getTerminator(); 6801 6802 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6803 6804 // Check successor nodes' PHI nodes that expect a constant to be available 6805 // from this block. 6806 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6807 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6808 if (!isa<PHINode>(SuccBB->begin())) continue; 6809 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6810 6811 // If this terminator has multiple identical successors (common for 6812 // switches), only handle each succ once. 6813 if (!SuccsHandled.insert(SuccMBB)) continue; 6814 6815 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6816 6817 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6818 // nodes and Machine PHI nodes, but the incoming operands have not been 6819 // emitted yet. 6820 for (BasicBlock::const_iterator I = SuccBB->begin(); 6821 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6822 // Ignore dead phi's. 6823 if (PN->use_empty()) continue; 6824 6825 // Skip empty types 6826 if (PN->getType()->isEmptyTy()) 6827 continue; 6828 6829 unsigned Reg; 6830 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6831 6832 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6833 unsigned &RegOut = ConstantsOut[C]; 6834 if (RegOut == 0) { 6835 RegOut = FuncInfo.CreateRegs(C->getType()); 6836 CopyValueToVirtualRegister(C, RegOut); 6837 } 6838 Reg = RegOut; 6839 } else { 6840 DenseMap<const Value *, unsigned>::iterator I = 6841 FuncInfo.ValueMap.find(PHIOp); 6842 if (I != FuncInfo.ValueMap.end()) 6843 Reg = I->second; 6844 else { 6845 assert(isa<AllocaInst>(PHIOp) && 6846 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6847 "Didn't codegen value into a register!??"); 6848 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6849 CopyValueToVirtualRegister(PHIOp, Reg); 6850 } 6851 } 6852 6853 // Remember that this register needs to added to the machine PHI node as 6854 // the input for this MBB. 6855 SmallVector<EVT, 4> ValueVTs; 6856 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6857 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6858 EVT VT = ValueVTs[vti]; 6859 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6860 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6861 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6862 Reg += NumRegisters; 6863 } 6864 } 6865 } 6866 ConstantsOut.clear(); 6867} 6868