SelectionDAGBuilder.cpp revision 47fd10f2fc45d280308b77ed4eda16f3c9c88248
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SelectionDAGBuilder.h" 16#include "SDNodeDbgValue.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Analysis/ValueTracking.h" 23#include "llvm/CallingConv.h" 24#include "llvm/CodeGen/Analysis.h" 25#include "llvm/CodeGen/FastISel.h" 26#include "llvm/CodeGen/FunctionLoweringInfo.h" 27#include "llvm/CodeGen/GCMetadata.h" 28#include "llvm/CodeGen/GCStrategy.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/Constants.h" 37#include "llvm/DataLayout.h" 38#include "llvm/DebugInfo.h" 39#include "llvm/DerivedTypes.h" 40#include "llvm/Function.h" 41#include "llvm/GlobalVariable.h" 42#include "llvm/InlineAsm.h" 43#include "llvm/Instructions.h" 44#include "llvm/IntrinsicInst.h" 45#include "llvm/Intrinsics.h" 46#include "llvm/LLVMContext.h" 47#include "llvm/Module.h" 48#include "llvm/Support/CommandLine.h" 49#include "llvm/Support/Debug.h" 50#include "llvm/Support/ErrorHandling.h" 51#include "llvm/Support/IntegersSubsetMapping.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include "llvm/Target/TargetFrameLowering.h" 55#include "llvm/Target/TargetInstrInfo.h" 56#include "llvm/Target/TargetIntrinsicInfo.h" 57#include "llvm/Target/TargetLibraryInfo.h" 58#include "llvm/Target/TargetLowering.h" 59#include "llvm/Target/TargetOptions.h" 60#include <algorithm> 61using namespace llvm; 62 63/// LimitFloatPrecision - Generate low-precision inline sequences for 64/// some float libcalls (6, 8 or 12 bits). 65static unsigned LimitFloatPrecision; 66 67static cl::opt<unsigned, true> 68LimitFPPrecision("limit-float-precision", 69 cl::desc("Generate low-precision inline sequences " 70 "for some float libcalls"), 71 cl::location(LimitFloatPrecision), 72 cl::init(0)); 73 74// Limit the width of DAG chains. This is important in general to prevent 75// prevent DAG-based analysis from blowing up. For example, alias analysis and 76// load clustering may not complete in reasonable time. It is difficult to 77// recognize and avoid this situation within each individual analysis, and 78// future analyses are likely to have the same behavior. Limiting DAG width is 79// the safe approach, and will be especially important with global DAGs. 80// 81// MaxParallelChains default is arbitrarily high to avoid affecting 82// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 83// sequence over this should have been converted to llvm.memcpy by the 84// frontend. It easy to induce this behavior with .ll code such as: 85// %buffer = alloca [4096 x i8] 86// %data = load [4096 x i8]* %argPtr 87// store [4096 x i8] %data, [4096 x i8]* %buffer 88static const unsigned MaxParallelChains = 64; 89 90static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 91 const SDValue *Parts, unsigned NumParts, 92 EVT PartVT, EVT ValueVT, const Value *V); 93 94/// getCopyFromParts - Create a value that contains the specified legal parts 95/// combined into the value they represent. If the parts combine to a type 96/// larger then ValueVT then AssertOp can be used to specify whether the extra 97/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 98/// (ISD::AssertSext). 99static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 100 const SDValue *Parts, 101 unsigned NumParts, EVT PartVT, EVT ValueVT, 102 const Value *V, 103 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 104 if (ValueVT.isVector()) 105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, 106 PartVT, ValueVT, V); 107 108 assert(NumParts > 0 && "No parts to assemble!"); 109 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 110 SDValue Val = Parts[0]; 111 112 if (NumParts > 1) { 113 // Assemble the value from multiple parts. 114 if (ValueVT.isInteger()) { 115 unsigned PartBits = PartVT.getSizeInBits(); 116 unsigned ValueBits = ValueVT.getSizeInBits(); 117 118 // Assemble the power of 2 part. 119 unsigned RoundParts = NumParts & (NumParts - 1) ? 120 1 << Log2_32(NumParts) : NumParts; 121 unsigned RoundBits = PartBits * RoundParts; 122 EVT RoundVT = RoundBits == ValueBits ? 123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 124 SDValue Lo, Hi; 125 126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 127 128 if (RoundParts > 2) { 129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 130 PartVT, HalfVT, V); 131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 132 RoundParts / 2, PartVT, HalfVT, V); 133 } else { 134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 136 } 137 138 if (TLI.isBigEndian()) 139 std::swap(Lo, Hi); 140 141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 142 143 if (RoundParts < NumParts) { 144 // Assemble the trailing non-power-of-2 part. 145 unsigned OddParts = NumParts - RoundParts; 146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 147 Hi = getCopyFromParts(DAG, DL, 148 Parts + RoundParts, OddParts, PartVT, OddVT, V); 149 150 // Combine the round and odd parts. 151 Lo = Val; 152 if (TLI.isBigEndian()) 153 std::swap(Lo, Hi); 154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 157 DAG.getConstant(Lo.getValueType().getSizeInBits(), 158 TLI.getPointerTy())); 159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 161 } 162 } else if (PartVT.isFloatingPoint()) { 163 // FP split into multiple FP parts (for ppcf128) 164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 165 "Unexpected split"); 166 SDValue Lo, Hi; 167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 169 if (TLI.isBigEndian()) 170 std::swap(Lo, Hi); 171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 172 } else { 173 // FP split into integer parts (soft fp) 174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 175 !PartVT.isVector() && "Unexpected split"); 176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V); 178 } 179 } 180 181 // There is now one part, held in Val. Correct it to match ValueVT. 182 PartVT = Val.getValueType(); 183 184 if (PartVT == ValueVT) 185 return Val; 186 187 if (PartVT.isInteger() && ValueVT.isInteger()) { 188 if (ValueVT.bitsLT(PartVT)) { 189 // For a truncate, see if we have any information to 190 // indicate whether the truncated bits will always be 191 // zero or sign-extension. 192 if (AssertOp != ISD::DELETED_NODE) 193 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 194 DAG.getValueType(ValueVT)); 195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 196 } 197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 198 } 199 200 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 201 // FP_ROUND's are always exact here. 202 if (ValueVT.bitsLT(Val.getValueType())) 203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 204 DAG.getTargetConstant(1, TLI.getPointerTy())); 205 206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 207 } 208 209 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 211 212 llvm_unreachable("Unknown mismatch!"); 213} 214 215/// getCopyFromPartsVector - Create a value that contains the specified legal 216/// parts combined into the value they represent. If the parts combine to a 217/// type larger then ValueVT then AssertOp can be used to specify whether the 218/// extra bits are known to be zero (ISD::AssertZext) or sign extended from 219/// ValueVT (ISD::AssertSext). 220static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 221 const SDValue *Parts, unsigned NumParts, 222 EVT PartVT, EVT ValueVT, const Value *V) { 223 assert(ValueVT.isVector() && "Not a vector value"); 224 assert(NumParts > 0 && "No parts to assemble!"); 225 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 226 SDValue Val = Parts[0]; 227 228 // Handle a multi-element vector. 229 if (NumParts > 1) { 230 EVT IntermediateVT; 231 MVT RegisterVT; 232 unsigned NumIntermediates; 233 unsigned NumRegs = 234 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 235 NumIntermediates, RegisterVT); 236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 237 NumParts = NumRegs; // Silence a compiler warning. 238 assert(RegisterVT == PartVT.getSimpleVT() && 239 "Part type doesn't match vector breakdown!"); 240 assert(RegisterVT == Parts[0].getSimpleValueType() && 241 "Part type doesn't match part!"); 242 243 // Assemble the parts into intermediate operands. 244 SmallVector<SDValue, 8> Ops(NumIntermediates); 245 if (NumIntermediates == NumParts) { 246 // If the register was not expanded, truncate or copy the value, 247 // as appropriate. 248 for (unsigned i = 0; i != NumParts; ++i) 249 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 250 PartVT, IntermediateVT, V); 251 } else if (NumParts > 0) { 252 // If the intermediate type was expanded, build the intermediate 253 // operands from the parts. 254 assert(NumParts % NumIntermediates == 0 && 255 "Must expand into a divisible number of parts!"); 256 unsigned Factor = NumParts / NumIntermediates; 257 for (unsigned i = 0; i != NumIntermediates; ++i) 258 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 259 PartVT, IntermediateVT, V); 260 } 261 262 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 263 // intermediate operands. 264 Val = DAG.getNode(IntermediateVT.isVector() ? 265 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 266 ValueVT, &Ops[0], NumIntermediates); 267 } 268 269 // There is now one part, held in Val. Correct it to match ValueVT. 270 PartVT = Val.getValueType(); 271 272 if (PartVT == ValueVT) 273 return Val; 274 275 if (PartVT.isVector()) { 276 // If the element type of the source/dest vectors are the same, but the 277 // parts vector has more elements than the value vector, then we have a 278 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 279 // elements we want. 280 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 281 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 282 "Cannot narrow, it would be a lossy transformation"); 283 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 284 DAG.getIntPtrConstant(0)); 285 } 286 287 // Vector/Vector bitcast. 288 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 289 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 290 291 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 292 "Cannot handle this kind of promotion"); 293 // Promoted vector extract 294 bool Smaller = ValueVT.bitsLE(PartVT); 295 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 296 DL, ValueVT, Val); 297 298 } 299 300 // Trivial bitcast if the types are the same size and the destination 301 // vector type is legal. 302 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 303 TLI.isTypeLegal(ValueVT)) 304 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 305 306 // Handle cases such as i8 -> <1 x i1> 307 if (ValueVT.getVectorNumElements() != 1) { 308 LLVMContext &Ctx = *DAG.getContext(); 309 Twine ErrMsg("non-trivial scalar-to-vector conversion"); 310 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 311 if (const CallInst *CI = dyn_cast<CallInst>(I)) 312 if (isa<InlineAsm>(CI->getCalledValue())) 313 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 314 Ctx.emitError(I, ErrMsg); 315 } else { 316 Ctx.emitError(ErrMsg); 317 } 318 report_fatal_error("Cannot handle scalar-to-vector conversion!"); 319 } 320 321 if (ValueVT.getVectorNumElements() == 1 && 322 ValueVT.getVectorElementType() != PartVT) { 323 bool Smaller = ValueVT.bitsLE(PartVT); 324 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 325 DL, ValueVT.getScalarType(), Val); 326 } 327 328 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 329} 330 331static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 332 SDValue Val, SDValue *Parts, unsigned NumParts, 333 EVT PartVT, const Value *V); 334 335/// getCopyToParts - Create a series of nodes that contain the specified value 336/// split into legal parts. If the parts contain more bits than Val, then, for 337/// integers, ExtendKind can be used to specify how to generate the extra bits. 338static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 339 SDValue Val, SDValue *Parts, unsigned NumParts, 340 EVT PartVT, const Value *V, 341 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 342 EVT ValueVT = Val.getValueType(); 343 344 // Handle the vector case separately. 345 if (ValueVT.isVector()) 346 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V); 347 348 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 349 unsigned PartBits = PartVT.getSizeInBits(); 350 unsigned OrigNumParts = NumParts; 351 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 352 353 if (NumParts == 0) 354 return; 355 356 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 357 if (PartVT == ValueVT) { 358 assert(NumParts == 1 && "No-op copy with multiple parts!"); 359 Parts[0] = Val; 360 return; 361 } 362 363 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 364 // If the parts cover more bits than the value has, promote the value. 365 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 366 assert(NumParts == 1 && "Do not know what to promote to!"); 367 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 368 } else { 369 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 370 ValueVT.isInteger() && 371 "Unknown mismatch!"); 372 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 373 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 374 if (PartVT == MVT::x86mmx) 375 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 376 } 377 } else if (PartBits == ValueVT.getSizeInBits()) { 378 // Different types of the same size. 379 assert(NumParts == 1 && PartVT != ValueVT); 380 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 381 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 382 // If the parts cover less bits than value has, truncate the value. 383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 384 ValueVT.isInteger() && 385 "Unknown mismatch!"); 386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 387 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 388 if (PartVT == MVT::x86mmx) 389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 390 } 391 392 // The value may have changed - recompute ValueVT. 393 ValueVT = Val.getValueType(); 394 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 395 "Failed to tile the value with PartVT!"); 396 397 if (NumParts == 1) { 398 if (PartVT != ValueVT) { 399 LLVMContext &Ctx = *DAG.getContext(); 400 Twine ErrMsg("scalar-to-vector conversion failed"); 401 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 402 if (const CallInst *CI = dyn_cast<CallInst>(I)) 403 if (isa<InlineAsm>(CI->getCalledValue())) 404 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 405 Ctx.emitError(I, ErrMsg); 406 } else { 407 Ctx.emitError(ErrMsg); 408 } 409 } 410 411 Parts[0] = Val; 412 return; 413 } 414 415 // Expand the value into multiple parts. 416 if (NumParts & (NumParts - 1)) { 417 // The number of parts is not a power of 2. Split off and copy the tail. 418 assert(PartVT.isInteger() && ValueVT.isInteger() && 419 "Do not know what to expand to!"); 420 unsigned RoundParts = 1 << Log2_32(NumParts); 421 unsigned RoundBits = RoundParts * PartBits; 422 unsigned OddParts = NumParts - RoundParts; 423 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 424 DAG.getIntPtrConstant(RoundBits)); 425 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V); 426 427 if (TLI.isBigEndian()) 428 // The odd parts were reversed by getCopyToParts - unreverse them. 429 std::reverse(Parts + RoundParts, Parts + NumParts); 430 431 NumParts = RoundParts; 432 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 433 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 434 } 435 436 // The number of parts is a power of 2. Repeatedly bisect the value using 437 // EXTRACT_ELEMENT. 438 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 439 EVT::getIntegerVT(*DAG.getContext(), 440 ValueVT.getSizeInBits()), 441 Val); 442 443 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 444 for (unsigned i = 0; i < NumParts; i += StepSize) { 445 unsigned ThisBits = StepSize * PartBits / 2; 446 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 447 SDValue &Part0 = Parts[i]; 448 SDValue &Part1 = Parts[i+StepSize/2]; 449 450 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 451 ThisVT, Part0, DAG.getIntPtrConstant(1)); 452 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 453 ThisVT, Part0, DAG.getIntPtrConstant(0)); 454 455 if (ThisBits == PartBits && ThisVT != PartVT) { 456 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 457 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 458 } 459 } 460 } 461 462 if (TLI.isBigEndian()) 463 std::reverse(Parts, Parts + OrigNumParts); 464} 465 466 467/// getCopyToPartsVector - Create a series of nodes that contain the specified 468/// value split into legal parts. 469static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 470 SDValue Val, SDValue *Parts, unsigned NumParts, 471 EVT PartVT, const Value *V) { 472 EVT ValueVT = Val.getValueType(); 473 assert(ValueVT.isVector() && "Not a vector"); 474 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 475 476 if (NumParts == 1) { 477 if (PartVT == ValueVT) { 478 // Nothing to do. 479 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 480 // Bitconvert vector->vector case. 481 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 482 } else if (PartVT.isVector() && 483 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 484 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 485 EVT ElementVT = PartVT.getVectorElementType(); 486 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 487 // undef elements. 488 SmallVector<SDValue, 16> Ops; 489 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 490 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 491 ElementVT, Val, DAG.getIntPtrConstant(i))); 492 493 for (unsigned i = ValueVT.getVectorNumElements(), 494 e = PartVT.getVectorNumElements(); i != e; ++i) 495 Ops.push_back(DAG.getUNDEF(ElementVT)); 496 497 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 498 499 // FIXME: Use CONCAT for 2x -> 4x. 500 501 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 502 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 503 } else if (PartVT.isVector() && 504 PartVT.getVectorElementType().bitsGE( 505 ValueVT.getVectorElementType()) && 506 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 507 508 // Promoted vector extract 509 bool Smaller = PartVT.bitsLE(ValueVT); 510 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 511 DL, PartVT, Val); 512 } else{ 513 // Vector -> scalar conversion. 514 assert(ValueVT.getVectorNumElements() == 1 && 515 "Only trivial vector-to-scalar conversions should get here!"); 516 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 517 PartVT, Val, DAG.getIntPtrConstant(0)); 518 519 bool Smaller = ValueVT.bitsLE(PartVT); 520 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 521 DL, PartVT, Val); 522 } 523 524 Parts[0] = Val; 525 return; 526 } 527 528 // Handle a multi-element vector. 529 EVT IntermediateVT; 530 MVT RegisterVT; 531 unsigned NumIntermediates; 532 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 533 IntermediateVT, 534 NumIntermediates, RegisterVT); 535 unsigned NumElements = ValueVT.getVectorNumElements(); 536 537 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 538 NumParts = NumRegs; // Silence a compiler warning. 539 assert(RegisterVT == PartVT.getSimpleVT() && 540 "Part type doesn't match vector breakdown!"); 541 542 // Split the vector into intermediate operands. 543 SmallVector<SDValue, 8> Ops(NumIntermediates); 544 for (unsigned i = 0; i != NumIntermediates; ++i) { 545 if (IntermediateVT.isVector()) 546 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 547 IntermediateVT, Val, 548 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 549 else 550 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 551 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 552 } 553 554 // Split the intermediate operands into legal parts. 555 if (NumParts == NumIntermediates) { 556 // If the register was not expanded, promote or copy the value, 557 // as appropriate. 558 for (unsigned i = 0; i != NumParts; ++i) 559 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V); 560 } else if (NumParts > 0) { 561 // If the intermediate type was expanded, split each the value into 562 // legal parts. 563 assert(NumParts % NumIntermediates == 0 && 564 "Must expand into a divisible number of parts!"); 565 unsigned Factor = NumParts / NumIntermediates; 566 for (unsigned i = 0; i != NumIntermediates; ++i) 567 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V); 568 } 569} 570 571namespace { 572 /// RegsForValue - This struct represents the registers (physical or virtual) 573 /// that a particular set of values is assigned, and the type information 574 /// about the value. The most common situation is to represent one value at a 575 /// time, but struct or array values are handled element-wise as multiple 576 /// values. The splitting of aggregates is performed recursively, so that we 577 /// never have aggregate-typed registers. The values at this point do not 578 /// necessarily have legal types, so each value may require one or more 579 /// registers of some legal type. 580 /// 581 struct RegsForValue { 582 /// ValueVTs - The value types of the values, which may not be legal, and 583 /// may need be promoted or synthesized from one or more registers. 584 /// 585 SmallVector<EVT, 4> ValueVTs; 586 587 /// RegVTs - The value types of the registers. This is the same size as 588 /// ValueVTs and it records, for each value, what the type of the assigned 589 /// register or registers are. (Individual values are never synthesized 590 /// from more than one type of register.) 591 /// 592 /// With virtual registers, the contents of RegVTs is redundant with TLI's 593 /// getRegisterType member function, however when with physical registers 594 /// it is necessary to have a separate record of the types. 595 /// 596 SmallVector<EVT, 4> RegVTs; 597 598 /// Regs - This list holds the registers assigned to the values. 599 /// Each legal or promoted value requires one register, and each 600 /// expanded value requires multiple registers. 601 /// 602 SmallVector<unsigned, 4> Regs; 603 604 RegsForValue() {} 605 606 RegsForValue(const SmallVector<unsigned, 4> ®s, 607 EVT regvt, EVT valuevt) 608 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 609 610 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 611 unsigned Reg, Type *Ty) { 612 ComputeValueVTs(tli, Ty, ValueVTs); 613 614 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 615 EVT ValueVT = ValueVTs[Value]; 616 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 617 MVT RegisterVT = tli.getRegisterType(Context, ValueVT); 618 for (unsigned i = 0; i != NumRegs; ++i) 619 Regs.push_back(Reg + i); 620 RegVTs.push_back(RegisterVT); 621 Reg += NumRegs; 622 } 623 } 624 625 /// areValueTypesLegal - Return true if types of all the values are legal. 626 bool areValueTypesLegal(const TargetLowering &TLI) { 627 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 628 EVT RegisterVT = RegVTs[Value]; 629 if (!TLI.isTypeLegal(RegisterVT)) 630 return false; 631 } 632 return true; 633 } 634 635 /// append - Add the specified values to this one. 636 void append(const RegsForValue &RHS) { 637 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 638 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 639 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 640 } 641 642 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 643 /// this value and returns the result as a ValueVTs value. This uses 644 /// Chain/Flag as the input and updates them for the output Chain/Flag. 645 /// If the Flag pointer is NULL, no flag is used. 646 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 647 DebugLoc dl, 648 SDValue &Chain, SDValue *Flag, 649 const Value *V = 0) const; 650 651 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 652 /// specified value into the registers specified by this object. This uses 653 /// Chain/Flag as the input and updates them for the output Chain/Flag. 654 /// If the Flag pointer is NULL, no flag is used. 655 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 656 SDValue &Chain, SDValue *Flag, const Value *V) const; 657 658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 659 /// operand list. This adds the code marker, matching input operand index 660 /// (if applicable), and includes the number of values added into it. 661 void AddInlineAsmOperands(unsigned Kind, 662 bool HasMatching, unsigned MatchingIdx, 663 SelectionDAG &DAG, 664 std::vector<SDValue> &Ops) const; 665 }; 666} 667 668/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 669/// this value and returns the result as a ValueVT value. This uses 670/// Chain/Flag as the input and updates them for the output Chain/Flag. 671/// If the Flag pointer is NULL, no flag is used. 672SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 673 FunctionLoweringInfo &FuncInfo, 674 DebugLoc dl, 675 SDValue &Chain, SDValue *Flag, 676 const Value *V) const { 677 // A Value with type {} or [0 x %t] needs no registers. 678 if (ValueVTs.empty()) 679 return SDValue(); 680 681 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 682 683 // Assemble the legal parts into the final values. 684 SmallVector<SDValue, 4> Values(ValueVTs.size()); 685 SmallVector<SDValue, 8> Parts; 686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 687 // Copy the legal parts from the registers. 688 EVT ValueVT = ValueVTs[Value]; 689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 690 EVT RegisterVT = RegVTs[Value]; 691 692 Parts.resize(NumRegs); 693 for (unsigned i = 0; i != NumRegs; ++i) { 694 SDValue P; 695 if (Flag == 0) { 696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 697 } else { 698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 699 *Flag = P.getValue(2); 700 } 701 702 Chain = P.getValue(1); 703 Parts[i] = P; 704 705 // If the source register was virtual and if we know something about it, 706 // add an assert node. 707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 708 !RegisterVT.isInteger() || RegisterVT.isVector()) 709 continue; 710 711 const FunctionLoweringInfo::LiveOutInfo *LOI = 712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 713 if (!LOI) 714 continue; 715 716 unsigned RegSize = RegisterVT.getSizeInBits(); 717 unsigned NumSignBits = LOI->NumSignBits; 718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 719 720 // FIXME: We capture more information than the dag can represent. For 721 // now, just use the tightest assertzext/assertsext possible. 722 bool isSExt = true; 723 EVT FromVT(MVT::Other); 724 if (NumSignBits == RegSize) 725 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 726 else if (NumZeroBits >= RegSize-1) 727 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 728 else if (NumSignBits > RegSize-8) 729 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 730 else if (NumZeroBits >= RegSize-8) 731 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 732 else if (NumSignBits > RegSize-16) 733 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 734 else if (NumZeroBits >= RegSize-16) 735 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 736 else if (NumSignBits > RegSize-32) 737 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 738 else if (NumZeroBits >= RegSize-32) 739 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 740 else 741 continue; 742 743 // Add an assertion node. 744 assert(FromVT != MVT::Other); 745 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 746 RegisterVT, P, DAG.getValueType(FromVT)); 747 } 748 749 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 750 NumRegs, RegisterVT, ValueVT, V); 751 Part += NumRegs; 752 Parts.clear(); 753 } 754 755 return DAG.getNode(ISD::MERGE_VALUES, dl, 756 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 757 &Values[0], ValueVTs.size()); 758} 759 760/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 761/// specified value into the registers specified by this object. This uses 762/// Chain/Flag as the input and updates them for the output Chain/Flag. 763/// If the Flag pointer is NULL, no flag is used. 764void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 765 SDValue &Chain, SDValue *Flag, 766 const Value *V) const { 767 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 768 769 // Get the list of the values's legal parts. 770 unsigned NumRegs = Regs.size(); 771 SmallVector<SDValue, 8> Parts(NumRegs); 772 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 773 EVT ValueVT = ValueVTs[Value]; 774 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 775 EVT RegisterVT = RegVTs[Value]; 776 ISD::NodeType ExtendKind = 777 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND; 778 779 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 780 &Parts[Part], NumParts, RegisterVT, V, ExtendKind); 781 Part += NumParts; 782 } 783 784 // Copy the parts into the registers. 785 SmallVector<SDValue, 8> Chains(NumRegs); 786 for (unsigned i = 0; i != NumRegs; ++i) { 787 SDValue Part; 788 if (Flag == 0) { 789 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 790 } else { 791 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 792 *Flag = Part.getValue(1); 793 } 794 795 Chains[i] = Part.getValue(0); 796 } 797 798 if (NumRegs == 1 || Flag) 799 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 800 // flagged to it. That is the CopyToReg nodes and the user are considered 801 // a single scheduling unit. If we create a TokenFactor and return it as 802 // chain, then the TokenFactor is both a predecessor (operand) of the 803 // user as well as a successor (the TF operands are flagged to the user). 804 // c1, f1 = CopyToReg 805 // c2, f2 = CopyToReg 806 // c3 = TokenFactor c1, c2 807 // ... 808 // = op c3, ..., f2 809 Chain = Chains[NumRegs-1]; 810 else 811 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 812} 813 814/// AddInlineAsmOperands - Add this value to the specified inlineasm node 815/// operand list. This adds the code marker and includes the number of 816/// values added into it. 817void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 818 unsigned MatchingIdx, 819 SelectionDAG &DAG, 820 std::vector<SDValue> &Ops) const { 821 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 822 823 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 824 if (HasMatching) 825 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 826 else if (!Regs.empty() && 827 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 828 // Put the register class of the virtual registers in the flag word. That 829 // way, later passes can recompute register class constraints for inline 830 // assembly as well as normal instructions. 831 // Don't do this for tied operands that can use the regclass information 832 // from the def. 833 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 834 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 835 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 836 } 837 838 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 839 Ops.push_back(Res); 840 841 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 842 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 843 EVT RegisterVT = RegVTs[Value]; 844 for (unsigned i = 0; i != NumRegs; ++i) { 845 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 846 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 847 } 848 } 849} 850 851void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 852 const TargetLibraryInfo *li) { 853 AA = &aa; 854 GFI = gfi; 855 LibInfo = li; 856 TD = DAG.getTarget().getDataLayout(); 857 Context = DAG.getContext(); 858 LPadToCallSiteMap.clear(); 859} 860 861/// clear - Clear out the current SelectionDAG and the associated 862/// state and prepare this SelectionDAGBuilder object to be used 863/// for a new block. This doesn't clear out information about 864/// additional blocks that are needed to complete switch lowering 865/// or PHI node updating; that information is cleared out as it is 866/// consumed. 867void SelectionDAGBuilder::clear() { 868 NodeMap.clear(); 869 UnusedArgNodeMap.clear(); 870 PendingLoads.clear(); 871 PendingExports.clear(); 872 CurDebugLoc = DebugLoc(); 873 HasTailCall = false; 874} 875 876/// clearDanglingDebugInfo - Clear the dangling debug information 877/// map. This function is separated from the clear so that debug 878/// information that is dangling in a basic block can be properly 879/// resolved in a different basic block. This allows the 880/// SelectionDAG to resolve dangling debug information attached 881/// to PHI nodes. 882void SelectionDAGBuilder::clearDanglingDebugInfo() { 883 DanglingDebugInfoMap.clear(); 884} 885 886/// getRoot - Return the current virtual root of the Selection DAG, 887/// flushing any PendingLoad items. This must be done before emitting 888/// a store or any other node that may need to be ordered after any 889/// prior load instructions. 890/// 891SDValue SelectionDAGBuilder::getRoot() { 892 if (PendingLoads.empty()) 893 return DAG.getRoot(); 894 895 if (PendingLoads.size() == 1) { 896 SDValue Root = PendingLoads[0]; 897 DAG.setRoot(Root); 898 PendingLoads.clear(); 899 return Root; 900 } 901 902 // Otherwise, we have to make a token factor node. 903 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 904 &PendingLoads[0], PendingLoads.size()); 905 PendingLoads.clear(); 906 DAG.setRoot(Root); 907 return Root; 908} 909 910/// getControlRoot - Similar to getRoot, but instead of flushing all the 911/// PendingLoad items, flush all the PendingExports items. It is necessary 912/// to do this before emitting a terminator instruction. 913/// 914SDValue SelectionDAGBuilder::getControlRoot() { 915 SDValue Root = DAG.getRoot(); 916 917 if (PendingExports.empty()) 918 return Root; 919 920 // Turn all of the CopyToReg chains into one factored node. 921 if (Root.getOpcode() != ISD::EntryToken) { 922 unsigned i = 0, e = PendingExports.size(); 923 for (; i != e; ++i) { 924 assert(PendingExports[i].getNode()->getNumOperands() > 1); 925 if (PendingExports[i].getNode()->getOperand(0) == Root) 926 break; // Don't add the root if we already indirectly depend on it. 927 } 928 929 if (i == e) 930 PendingExports.push_back(Root); 931 } 932 933 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 934 &PendingExports[0], 935 PendingExports.size()); 936 PendingExports.clear(); 937 DAG.setRoot(Root); 938 return Root; 939} 940 941void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 942 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 943 DAG.AssignOrdering(Node, SDNodeOrder); 944 945 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 946 AssignOrderingToNode(Node->getOperand(I).getNode()); 947} 948 949void SelectionDAGBuilder::visit(const Instruction &I) { 950 // Set up outgoing PHI node register values before emitting the terminator. 951 if (isa<TerminatorInst>(&I)) 952 HandlePHINodesInSuccessorBlocks(I.getParent()); 953 954 CurDebugLoc = I.getDebugLoc(); 955 956 visit(I.getOpcode(), I); 957 958 if (!isa<TerminatorInst>(&I) && !HasTailCall) 959 CopyToExportRegsIfNeeded(&I); 960 961 CurDebugLoc = DebugLoc(); 962} 963 964void SelectionDAGBuilder::visitPHI(const PHINode &) { 965 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 966} 967 968void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 969 // Note: this doesn't use InstVisitor, because it has to work with 970 // ConstantExpr's in addition to instructions. 971 switch (Opcode) { 972 default: llvm_unreachable("Unknown instruction type encountered!"); 973 // Build the switch statement using the Instruction.def file. 974#define HANDLE_INST(NUM, OPCODE, CLASS) \ 975 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; 976#include "llvm/Instruction.def" 977 } 978 979 // Assign the ordering to the freshly created DAG nodes. 980 if (NodeMap.count(&I)) { 981 ++SDNodeOrder; 982 AssignOrderingToNode(getValue(&I).getNode()); 983 } 984} 985 986// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 987// generate the debug data structures now that we've seen its definition. 988void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 989 SDValue Val) { 990 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 991 if (DDI.getDI()) { 992 const DbgValueInst *DI = DDI.getDI(); 993 DebugLoc dl = DDI.getdl(); 994 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 995 MDNode *Variable = DI->getVariable(); 996 uint64_t Offset = DI->getOffset(); 997 SDDbgValue *SDV; 998 if (Val.getNode()) { 999 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 1000 SDV = DAG.getDbgValue(Variable, Val.getNode(), 1001 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 1002 DAG.AddDbgValue(SDV, Val.getNode(), false); 1003 } 1004 } else 1005 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 1006 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 1007 } 1008} 1009 1010/// getValue - Return an SDValue for the given Value. 1011SDValue SelectionDAGBuilder::getValue(const Value *V) { 1012 // If we already have an SDValue for this value, use it. It's important 1013 // to do this first, so that we don't create a CopyFromReg if we already 1014 // have a regular SDValue. 1015 SDValue &N = NodeMap[V]; 1016 if (N.getNode()) return N; 1017 1018 // If there's a virtual register allocated and initialized for this 1019 // value, use it. 1020 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 1021 if (It != FuncInfo.ValueMap.end()) { 1022 unsigned InReg = It->second; 1023 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 1024 SDValue Chain = DAG.getEntryNode(); 1025 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V); 1026 resolveDanglingDebugInfo(V, N); 1027 return N; 1028 } 1029 1030 // Otherwise create a new SDValue and remember it. 1031 SDValue Val = getValueImpl(V); 1032 NodeMap[V] = Val; 1033 resolveDanglingDebugInfo(V, Val); 1034 return Val; 1035} 1036 1037/// getNonRegisterValue - Return an SDValue for the given Value, but 1038/// don't look in FuncInfo.ValueMap for a virtual register. 1039SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1040 // If we already have an SDValue for this value, use it. 1041 SDValue &N = NodeMap[V]; 1042 if (N.getNode()) return N; 1043 1044 // Otherwise create a new SDValue and remember it. 1045 SDValue Val = getValueImpl(V); 1046 NodeMap[V] = Val; 1047 resolveDanglingDebugInfo(V, Val); 1048 return Val; 1049} 1050 1051/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1052/// Create an SDValue for the given value. 1053SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1054 if (const Constant *C = dyn_cast<Constant>(V)) { 1055 EVT VT = TLI.getValueType(V->getType(), true); 1056 1057 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1058 return DAG.getConstant(*CI, VT); 1059 1060 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1061 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1062 1063 if (isa<ConstantPointerNull>(C)) 1064 return DAG.getConstant(0, TLI.getPointerTy()); 1065 1066 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1067 return DAG.getConstantFP(*CFP, VT); 1068 1069 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1070 return DAG.getUNDEF(VT); 1071 1072 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1073 visit(CE->getOpcode(), *CE); 1074 SDValue N1 = NodeMap[V]; 1075 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1076 return N1; 1077 } 1078 1079 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1080 SmallVector<SDValue, 4> Constants; 1081 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1082 OI != OE; ++OI) { 1083 SDNode *Val = getValue(*OI).getNode(); 1084 // If the operand is an empty aggregate, there are no values. 1085 if (!Val) continue; 1086 // Add each leaf value from the operand to the Constants list 1087 // to form a flattened list of all the values. 1088 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1089 Constants.push_back(SDValue(Val, i)); 1090 } 1091 1092 return DAG.getMergeValues(&Constants[0], Constants.size(), 1093 getCurDebugLoc()); 1094 } 1095 1096 if (const ConstantDataSequential *CDS = 1097 dyn_cast<ConstantDataSequential>(C)) { 1098 SmallVector<SDValue, 4> Ops; 1099 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1100 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1101 // Add each leaf value from the operand to the Constants list 1102 // to form a flattened list of all the values. 1103 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1104 Ops.push_back(SDValue(Val, i)); 1105 } 1106 1107 if (isa<ArrayType>(CDS->getType())) 1108 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc()); 1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1110 VT, &Ops[0], Ops.size()); 1111 } 1112 1113 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1114 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1115 "Unknown struct or array constant!"); 1116 1117 SmallVector<EVT, 4> ValueVTs; 1118 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1119 unsigned NumElts = ValueVTs.size(); 1120 if (NumElts == 0) 1121 return SDValue(); // empty struct 1122 SmallVector<SDValue, 4> Constants(NumElts); 1123 for (unsigned i = 0; i != NumElts; ++i) { 1124 EVT EltVT = ValueVTs[i]; 1125 if (isa<UndefValue>(C)) 1126 Constants[i] = DAG.getUNDEF(EltVT); 1127 else if (EltVT.isFloatingPoint()) 1128 Constants[i] = DAG.getConstantFP(0, EltVT); 1129 else 1130 Constants[i] = DAG.getConstant(0, EltVT); 1131 } 1132 1133 return DAG.getMergeValues(&Constants[0], NumElts, 1134 getCurDebugLoc()); 1135 } 1136 1137 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1138 return DAG.getBlockAddress(BA, VT); 1139 1140 VectorType *VecTy = cast<VectorType>(V->getType()); 1141 unsigned NumElements = VecTy->getNumElements(); 1142 1143 // Now that we know the number and type of the elements, get that number of 1144 // elements into the Ops array based on what kind of constant it is. 1145 SmallVector<SDValue, 16> Ops; 1146 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1147 for (unsigned i = 0; i != NumElements; ++i) 1148 Ops.push_back(getValue(CV->getOperand(i))); 1149 } else { 1150 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1151 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1152 1153 SDValue Op; 1154 if (EltVT.isFloatingPoint()) 1155 Op = DAG.getConstantFP(0, EltVT); 1156 else 1157 Op = DAG.getConstant(0, EltVT); 1158 Ops.assign(NumElements, Op); 1159 } 1160 1161 // Create a BUILD_VECTOR node. 1162 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1163 VT, &Ops[0], Ops.size()); 1164 } 1165 1166 // If this is a static alloca, generate it as the frameindex instead of 1167 // computation. 1168 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1169 DenseMap<const AllocaInst*, int>::iterator SI = 1170 FuncInfo.StaticAllocaMap.find(AI); 1171 if (SI != FuncInfo.StaticAllocaMap.end()) 1172 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1173 } 1174 1175 // If this is an instruction which fast-isel has deferred, select it now. 1176 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1177 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1178 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1179 SDValue Chain = DAG.getEntryNode(); 1180 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL, V); 1181 } 1182 1183 llvm_unreachable("Can't get register for value!"); 1184} 1185 1186void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1187 SDValue Chain = getControlRoot(); 1188 SmallVector<ISD::OutputArg, 8> Outs; 1189 SmallVector<SDValue, 8> OutVals; 1190 1191 if (!FuncInfo.CanLowerReturn) { 1192 unsigned DemoteReg = FuncInfo.DemoteRegister; 1193 const Function *F = I.getParent()->getParent(); 1194 1195 // Emit a store of the return value through the virtual register. 1196 // Leave Outs empty so that LowerReturn won't try to load return 1197 // registers the usual way. 1198 SmallVector<EVT, 1> PtrValueVTs; 1199 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1200 PtrValueVTs); 1201 1202 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1203 SDValue RetOp = getValue(I.getOperand(0)); 1204 1205 SmallVector<EVT, 4> ValueVTs; 1206 SmallVector<uint64_t, 4> Offsets; 1207 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1208 unsigned NumValues = ValueVTs.size(); 1209 1210 SmallVector<SDValue, 4> Chains(NumValues); 1211 for (unsigned i = 0; i != NumValues; ++i) { 1212 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1213 RetPtr.getValueType(), RetPtr, 1214 DAG.getIntPtrConstant(Offsets[i])); 1215 Chains[i] = 1216 DAG.getStore(Chain, getCurDebugLoc(), 1217 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1218 // FIXME: better loc info would be nice. 1219 Add, MachinePointerInfo(), false, false, 0); 1220 } 1221 1222 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1223 MVT::Other, &Chains[0], NumValues); 1224 } else if (I.getNumOperands() != 0) { 1225 SmallVector<EVT, 4> ValueVTs; 1226 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1227 unsigned NumValues = ValueVTs.size(); 1228 if (NumValues) { 1229 SDValue RetOp = getValue(I.getOperand(0)); 1230 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1231 EVT VT = ValueVTs[j]; 1232 1233 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1234 1235 const Function *F = I.getParent()->getParent(); 1236 if (F->getRetAttributes().hasAttribute(Attributes::SExt)) 1237 ExtendKind = ISD::SIGN_EXTEND; 1238 else if (F->getRetAttributes().hasAttribute(Attributes::ZExt)) 1239 ExtendKind = ISD::ZERO_EXTEND; 1240 1241 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1242 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), 1243 VT.getSimpleVT(), ExtendKind); 1244 1245 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1246 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1247 SmallVector<SDValue, 4> Parts(NumParts); 1248 getCopyToParts(DAG, getCurDebugLoc(), 1249 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1250 &Parts[0], NumParts, PartVT, &I, ExtendKind); 1251 1252 // 'inreg' on function refers to return value 1253 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1254 if (F->getRetAttributes().hasAttribute(Attributes::InReg)) 1255 Flags.setInReg(); 1256 1257 // Propagate extension type if any 1258 if (ExtendKind == ISD::SIGN_EXTEND) 1259 Flags.setSExt(); 1260 else if (ExtendKind == ISD::ZERO_EXTEND) 1261 Flags.setZExt(); 1262 1263 for (unsigned i = 0; i < NumParts; ++i) { 1264 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1265 /*isfixed=*/true, 0, 0)); 1266 OutVals.push_back(Parts[i]); 1267 } 1268 } 1269 } 1270 } 1271 1272 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1273 CallingConv::ID CallConv = 1274 DAG.getMachineFunction().getFunction()->getCallingConv(); 1275 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1276 Outs, OutVals, getCurDebugLoc(), DAG); 1277 1278 // Verify that the target's LowerReturn behaved as expected. 1279 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1280 "LowerReturn didn't return a valid chain!"); 1281 1282 // Update the DAG with the new chain value resulting from return lowering. 1283 DAG.setRoot(Chain); 1284} 1285 1286/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1287/// created for it, emit nodes to copy the value into the virtual 1288/// registers. 1289void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1290 // Skip empty types 1291 if (V->getType()->isEmptyTy()) 1292 return; 1293 1294 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1295 if (VMI != FuncInfo.ValueMap.end()) { 1296 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1297 CopyValueToVirtualRegister(V, VMI->second); 1298 } 1299} 1300 1301/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1302/// the current basic block, add it to ValueMap now so that we'll get a 1303/// CopyTo/FromReg. 1304void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1305 // No need to export constants. 1306 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1307 1308 // Already exported? 1309 if (FuncInfo.isExportedInst(V)) return; 1310 1311 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1312 CopyValueToVirtualRegister(V, Reg); 1313} 1314 1315bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1316 const BasicBlock *FromBB) { 1317 // The operands of the setcc have to be in this block. We don't know 1318 // how to export them from some other block. 1319 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1320 // Can export from current BB. 1321 if (VI->getParent() == FromBB) 1322 return true; 1323 1324 // Is already exported, noop. 1325 return FuncInfo.isExportedInst(V); 1326 } 1327 1328 // If this is an argument, we can export it if the BB is the entry block or 1329 // if it is already exported. 1330 if (isa<Argument>(V)) { 1331 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1332 return true; 1333 1334 // Otherwise, can only export this if it is already exported. 1335 return FuncInfo.isExportedInst(V); 1336 } 1337 1338 // Otherwise, constants can always be exported. 1339 return true; 1340} 1341 1342/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1343uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1344 const MachineBasicBlock *Dst) const { 1345 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1346 if (!BPI) 1347 return 0; 1348 const BasicBlock *SrcBB = Src->getBasicBlock(); 1349 const BasicBlock *DstBB = Dst->getBasicBlock(); 1350 return BPI->getEdgeWeight(SrcBB, DstBB); 1351} 1352 1353void SelectionDAGBuilder:: 1354addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1355 uint32_t Weight /* = 0 */) { 1356 if (!Weight) 1357 Weight = getEdgeWeight(Src, Dst); 1358 Src->addSuccessor(Dst, Weight); 1359} 1360 1361 1362static bool InBlock(const Value *V, const BasicBlock *BB) { 1363 if (const Instruction *I = dyn_cast<Instruction>(V)) 1364 return I->getParent() == BB; 1365 return true; 1366} 1367 1368/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1369/// This function emits a branch and is used at the leaves of an OR or an 1370/// AND operator tree. 1371/// 1372void 1373SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1374 MachineBasicBlock *TBB, 1375 MachineBasicBlock *FBB, 1376 MachineBasicBlock *CurBB, 1377 MachineBasicBlock *SwitchBB) { 1378 const BasicBlock *BB = CurBB->getBasicBlock(); 1379 1380 // If the leaf of the tree is a comparison, merge the condition into 1381 // the caseblock. 1382 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1383 // The operands of the cmp have to be in this block. We don't know 1384 // how to export them from some other block. If this is the first block 1385 // of the sequence, no exporting is needed. 1386 if (CurBB == SwitchBB || 1387 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1388 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1389 ISD::CondCode Condition; 1390 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1391 Condition = getICmpCondCode(IC->getPredicate()); 1392 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1393 Condition = getFCmpCondCode(FC->getPredicate()); 1394 if (TM.Options.NoNaNsFPMath) 1395 Condition = getFCmpCodeWithoutNaN(Condition); 1396 } else { 1397 Condition = ISD::SETEQ; // silence warning. 1398 llvm_unreachable("Unknown compare instruction"); 1399 } 1400 1401 CaseBlock CB(Condition, BOp->getOperand(0), 1402 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1403 SwitchCases.push_back(CB); 1404 return; 1405 } 1406 } 1407 1408 // Create a CaseBlock record representing this branch. 1409 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1410 NULL, TBB, FBB, CurBB); 1411 SwitchCases.push_back(CB); 1412} 1413 1414/// FindMergedConditions - If Cond is an expression like 1415void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1416 MachineBasicBlock *TBB, 1417 MachineBasicBlock *FBB, 1418 MachineBasicBlock *CurBB, 1419 MachineBasicBlock *SwitchBB, 1420 unsigned Opc) { 1421 // If this node is not part of the or/and tree, emit it as a branch. 1422 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1423 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1424 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1425 BOp->getParent() != CurBB->getBasicBlock() || 1426 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1427 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1428 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1429 return; 1430 } 1431 1432 // Create TmpBB after CurBB. 1433 MachineFunction::iterator BBI = CurBB; 1434 MachineFunction &MF = DAG.getMachineFunction(); 1435 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1436 CurBB->getParent()->insert(++BBI, TmpBB); 1437 1438 if (Opc == Instruction::Or) { 1439 // Codegen X | Y as: 1440 // jmp_if_X TBB 1441 // jmp TmpBB 1442 // TmpBB: 1443 // jmp_if_Y TBB 1444 // jmp FBB 1445 // 1446 1447 // Emit the LHS condition. 1448 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1449 1450 // Emit the RHS condition into TmpBB. 1451 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1452 } else { 1453 assert(Opc == Instruction::And && "Unknown merge op!"); 1454 // Codegen X & Y as: 1455 // jmp_if_X TmpBB 1456 // jmp FBB 1457 // TmpBB: 1458 // jmp_if_Y TBB 1459 // jmp FBB 1460 // 1461 // This requires creation of TmpBB after CurBB. 1462 1463 // Emit the LHS condition. 1464 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1465 1466 // Emit the RHS condition into TmpBB. 1467 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1468 } 1469} 1470 1471/// If the set of cases should be emitted as a series of branches, return true. 1472/// If we should emit this as a bunch of and/or'd together conditions, return 1473/// false. 1474bool 1475SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1476 if (Cases.size() != 2) return true; 1477 1478 // If this is two comparisons of the same values or'd or and'd together, they 1479 // will get folded into a single comparison, so don't emit two blocks. 1480 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1481 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1482 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1483 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1484 return false; 1485 } 1486 1487 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1488 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1489 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1490 Cases[0].CC == Cases[1].CC && 1491 isa<Constant>(Cases[0].CmpRHS) && 1492 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1493 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1494 return false; 1495 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1496 return false; 1497 } 1498 1499 return true; 1500} 1501 1502void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1503 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1504 1505 // Update machine-CFG edges. 1506 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1507 1508 // Figure out which block is immediately after the current one. 1509 MachineBasicBlock *NextBlock = 0; 1510 MachineFunction::iterator BBI = BrMBB; 1511 if (++BBI != FuncInfo.MF->end()) 1512 NextBlock = BBI; 1513 1514 if (I.isUnconditional()) { 1515 // Update machine-CFG edges. 1516 BrMBB->addSuccessor(Succ0MBB); 1517 1518 // If this is not a fall-through branch, emit the branch. 1519 if (Succ0MBB != NextBlock) 1520 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1521 MVT::Other, getControlRoot(), 1522 DAG.getBasicBlock(Succ0MBB))); 1523 1524 return; 1525 } 1526 1527 // If this condition is one of the special cases we handle, do special stuff 1528 // now. 1529 const Value *CondVal = I.getCondition(); 1530 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1531 1532 // If this is a series of conditions that are or'd or and'd together, emit 1533 // this as a sequence of branches instead of setcc's with and/or operations. 1534 // As long as jumps are not expensive, this should improve performance. 1535 // For example, instead of something like: 1536 // cmp A, B 1537 // C = seteq 1538 // cmp D, E 1539 // F = setle 1540 // or C, F 1541 // jnz foo 1542 // Emit: 1543 // cmp A, B 1544 // je foo 1545 // cmp D, E 1546 // jle foo 1547 // 1548 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1549 if (!TLI.isJumpExpensive() && 1550 BOp->hasOneUse() && 1551 (BOp->getOpcode() == Instruction::And || 1552 BOp->getOpcode() == Instruction::Or)) { 1553 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1554 BOp->getOpcode()); 1555 // If the compares in later blocks need to use values not currently 1556 // exported from this block, export them now. This block should always 1557 // be the first entry. 1558 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1559 1560 // Allow some cases to be rejected. 1561 if (ShouldEmitAsBranches(SwitchCases)) { 1562 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1563 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1564 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1565 } 1566 1567 // Emit the branch for this block. 1568 visitSwitchCase(SwitchCases[0], BrMBB); 1569 SwitchCases.erase(SwitchCases.begin()); 1570 return; 1571 } 1572 1573 // Okay, we decided not to do this, remove any inserted MBB's and clear 1574 // SwitchCases. 1575 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1576 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1577 1578 SwitchCases.clear(); 1579 } 1580 } 1581 1582 // Create a CaseBlock record representing this branch. 1583 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1584 NULL, Succ0MBB, Succ1MBB, BrMBB); 1585 1586 // Use visitSwitchCase to actually insert the fast branch sequence for this 1587 // cond branch. 1588 visitSwitchCase(CB, BrMBB); 1589} 1590 1591/// visitSwitchCase - Emits the necessary code to represent a single node in 1592/// the binary search tree resulting from lowering a switch instruction. 1593void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1594 MachineBasicBlock *SwitchBB) { 1595 SDValue Cond; 1596 SDValue CondLHS = getValue(CB.CmpLHS); 1597 DebugLoc dl = getCurDebugLoc(); 1598 1599 // Build the setcc now. 1600 if (CB.CmpMHS == NULL) { 1601 // Fold "(X == true)" to X and "(X == false)" to !X to 1602 // handle common cases produced by branch lowering. 1603 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1604 CB.CC == ISD::SETEQ) 1605 Cond = CondLHS; 1606 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1607 CB.CC == ISD::SETEQ) { 1608 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1609 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1610 } else 1611 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1612 } else { 1613 assert(CB.CC == ISD::SETCC_INVALID && 1614 "Condition is undefined for to-the-range belonging check."); 1615 1616 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1617 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1618 1619 SDValue CmpOp = getValue(CB.CmpMHS); 1620 EVT VT = CmpOp.getValueType(); 1621 1622 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) { 1623 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1624 ISD::SETULE); 1625 } else { 1626 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1627 VT, CmpOp, DAG.getConstant(Low, VT)); 1628 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1629 DAG.getConstant(High-Low, VT), ISD::SETULE); 1630 } 1631 } 1632 1633 // Update successor info 1634 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1635 // TrueBB and FalseBB are always different unless the incoming IR is 1636 // degenerate. This only happens when running llc on weird IR. 1637 if (CB.TrueBB != CB.FalseBB) 1638 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1639 1640 // Set NextBlock to be the MBB immediately after the current one, if any. 1641 // This is used to avoid emitting unnecessary branches to the next block. 1642 MachineBasicBlock *NextBlock = 0; 1643 MachineFunction::iterator BBI = SwitchBB; 1644 if (++BBI != FuncInfo.MF->end()) 1645 NextBlock = BBI; 1646 1647 // If the lhs block is the next block, invert the condition so that we can 1648 // fall through to the lhs instead of the rhs block. 1649 if (CB.TrueBB == NextBlock) { 1650 std::swap(CB.TrueBB, CB.FalseBB); 1651 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1652 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1653 } 1654 1655 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1656 MVT::Other, getControlRoot(), Cond, 1657 DAG.getBasicBlock(CB.TrueBB)); 1658 1659 // Insert the false branch. Do this even if it's a fall through branch, 1660 // this makes it easier to do DAG optimizations which require inverting 1661 // the branch condition. 1662 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1663 DAG.getBasicBlock(CB.FalseBB)); 1664 1665 DAG.setRoot(BrCond); 1666} 1667 1668/// visitJumpTable - Emit JumpTable node in the current MBB 1669void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1670 // Emit the code for the jump table 1671 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1672 EVT PTy = TLI.getPointerTy(); 1673 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1674 JT.Reg, PTy); 1675 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1676 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1677 MVT::Other, Index.getValue(1), 1678 Table, Index); 1679 DAG.setRoot(BrJumpTable); 1680} 1681 1682/// visitJumpTableHeader - This function emits necessary code to produce index 1683/// in the JumpTable from switch case. 1684void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1685 JumpTableHeader &JTH, 1686 MachineBasicBlock *SwitchBB) { 1687 // Subtract the lowest switch case value from the value being switched on and 1688 // conditional branch to default mbb if the result is greater than the 1689 // difference between smallest and largest cases. 1690 SDValue SwitchOp = getValue(JTH.SValue); 1691 EVT VT = SwitchOp.getValueType(); 1692 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1693 DAG.getConstant(JTH.First, VT)); 1694 1695 // The SDNode we just created, which holds the value being switched on minus 1696 // the smallest case value, needs to be copied to a virtual register so it 1697 // can be used as an index into the jump table in a subsequent basic block. 1698 // This value may be smaller or larger than the target's pointer type, and 1699 // therefore require extension or truncating. 1700 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1701 1702 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1703 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1704 JumpTableReg, SwitchOp); 1705 JT.Reg = JumpTableReg; 1706 1707 // Emit the range check for the jump table, and branch to the default block 1708 // for the switch statement if the value being switched on exceeds the largest 1709 // case in the switch. 1710 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1711 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1712 DAG.getConstant(JTH.Last-JTH.First,VT), 1713 ISD::SETUGT); 1714 1715 // Set NextBlock to be the MBB immediately after the current one, if any. 1716 // This is used to avoid emitting unnecessary branches to the next block. 1717 MachineBasicBlock *NextBlock = 0; 1718 MachineFunction::iterator BBI = SwitchBB; 1719 1720 if (++BBI != FuncInfo.MF->end()) 1721 NextBlock = BBI; 1722 1723 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1724 MVT::Other, CopyTo, CMP, 1725 DAG.getBasicBlock(JT.Default)); 1726 1727 if (JT.MBB != NextBlock) 1728 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1729 DAG.getBasicBlock(JT.MBB)); 1730 1731 DAG.setRoot(BrCond); 1732} 1733 1734/// visitBitTestHeader - This function emits necessary code to produce value 1735/// suitable for "bit tests" 1736void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1737 MachineBasicBlock *SwitchBB) { 1738 // Subtract the minimum value 1739 SDValue SwitchOp = getValue(B.SValue); 1740 MVT VT = SwitchOp.getSimpleValueType(); 1741 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1742 DAG.getConstant(B.First, VT)); 1743 1744 // Check range 1745 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1746 TLI.getSetCCResultType(Sub.getValueType()), 1747 Sub, DAG.getConstant(B.Range, VT), 1748 ISD::SETUGT); 1749 1750 // Determine the type of the test operands. 1751 bool UsePtrType = false; 1752 if (!TLI.isTypeLegal(VT)) 1753 UsePtrType = true; 1754 else { 1755 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1756 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1757 // Switch table case range are encoded into series of masks. 1758 // Just use pointer type, it's guaranteed to fit. 1759 UsePtrType = true; 1760 break; 1761 } 1762 } 1763 if (UsePtrType) { 1764 VT = TLI.getPointerTy(); 1765 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1766 } 1767 1768 B.RegVT = VT; 1769 B.Reg = FuncInfo.CreateReg(VT); 1770 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1771 B.Reg, Sub); 1772 1773 // Set NextBlock to be the MBB immediately after the current one, if any. 1774 // This is used to avoid emitting unnecessary branches to the next block. 1775 MachineBasicBlock *NextBlock = 0; 1776 MachineFunction::iterator BBI = SwitchBB; 1777 if (++BBI != FuncInfo.MF->end()) 1778 NextBlock = BBI; 1779 1780 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1781 1782 addSuccessorWithWeight(SwitchBB, B.Default); 1783 addSuccessorWithWeight(SwitchBB, MBB); 1784 1785 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1786 MVT::Other, CopyTo, RangeCmp, 1787 DAG.getBasicBlock(B.Default)); 1788 1789 if (MBB != NextBlock) 1790 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1791 DAG.getBasicBlock(MBB)); 1792 1793 DAG.setRoot(BrRange); 1794} 1795 1796/// visitBitTestCase - this function produces one "bit test" 1797void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1798 MachineBasicBlock* NextMBB, 1799 uint32_t BranchWeightToNext, 1800 unsigned Reg, 1801 BitTestCase &B, 1802 MachineBasicBlock *SwitchBB) { 1803 EVT VT = BB.RegVT; 1804 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1805 Reg, VT); 1806 SDValue Cmp; 1807 unsigned PopCount = CountPopulation_64(B.Mask); 1808 if (PopCount == 1) { 1809 // Testing for a single bit; just compare the shift count with what it 1810 // would need to be to shift a 1 bit in that position. 1811 Cmp = DAG.getSetCC(getCurDebugLoc(), 1812 TLI.getSetCCResultType(VT), 1813 ShiftOp, 1814 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1815 ISD::SETEQ); 1816 } else if (PopCount == BB.Range) { 1817 // There is only one zero bit in the range, test for it directly. 1818 Cmp = DAG.getSetCC(getCurDebugLoc(), 1819 TLI.getSetCCResultType(VT), 1820 ShiftOp, 1821 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1822 ISD::SETNE); 1823 } else { 1824 // Make desired shift 1825 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1826 DAG.getConstant(1, VT), ShiftOp); 1827 1828 // Emit bit tests and jumps 1829 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1830 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1831 Cmp = DAG.getSetCC(getCurDebugLoc(), 1832 TLI.getSetCCResultType(VT), 1833 AndOp, DAG.getConstant(0, VT), 1834 ISD::SETNE); 1835 } 1836 1837 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight. 1838 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight); 1839 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext. 1840 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext); 1841 1842 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1843 MVT::Other, getControlRoot(), 1844 Cmp, DAG.getBasicBlock(B.TargetBB)); 1845 1846 // Set NextBlock to be the MBB immediately after the current one, if any. 1847 // This is used to avoid emitting unnecessary branches to the next block. 1848 MachineBasicBlock *NextBlock = 0; 1849 MachineFunction::iterator BBI = SwitchBB; 1850 if (++BBI != FuncInfo.MF->end()) 1851 NextBlock = BBI; 1852 1853 if (NextMBB != NextBlock) 1854 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1855 DAG.getBasicBlock(NextMBB)); 1856 1857 DAG.setRoot(BrAnd); 1858} 1859 1860void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1861 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1862 1863 // Retrieve successors. 1864 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1865 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1866 1867 const Value *Callee(I.getCalledValue()); 1868 const Function *Fn = dyn_cast<Function>(Callee); 1869 if (isa<InlineAsm>(Callee)) 1870 visitInlineAsm(&I); 1871 else if (Fn && Fn->isIntrinsic()) { 1872 assert(Fn->getIntrinsicID() == Intrinsic::donothing); 1873 // Ignore invokes to @llvm.donothing: jump directly to the next BB. 1874 } else 1875 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1876 1877 // If the value of the invoke is used outside of its defining block, make it 1878 // available as a virtual register. 1879 CopyToExportRegsIfNeeded(&I); 1880 1881 // Update successor info 1882 addSuccessorWithWeight(InvokeMBB, Return); 1883 addSuccessorWithWeight(InvokeMBB, LandingPad); 1884 1885 // Drop into normal successor. 1886 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1887 MVT::Other, getControlRoot(), 1888 DAG.getBasicBlock(Return))); 1889} 1890 1891void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1892 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1893} 1894 1895void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1896 assert(FuncInfo.MBB->isLandingPad() && 1897 "Call to landingpad not in landing pad!"); 1898 1899 MachineBasicBlock *MBB = FuncInfo.MBB; 1900 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1901 AddLandingPadInfo(LP, MMI, MBB); 1902 1903 // If there aren't registers to copy the values into (e.g., during SjLj 1904 // exceptions), then don't bother to create these DAG nodes. 1905 if (TLI.getExceptionPointerRegister() == 0 && 1906 TLI.getExceptionSelectorRegister() == 0) 1907 return; 1908 1909 SmallVector<EVT, 2> ValueVTs; 1910 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1911 1912 // Insert the EXCEPTIONADDR instruction. 1913 assert(FuncInfo.MBB->isLandingPad() && 1914 "Call to eh.exception not in landing pad!"); 1915 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1916 SDValue Ops[2]; 1917 Ops[0] = DAG.getRoot(); 1918 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1919 SDValue Chain = Op1.getValue(1); 1920 1921 // Insert the EHSELECTION instruction. 1922 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1923 Ops[0] = Op1; 1924 Ops[1] = Chain; 1925 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1926 Chain = Op2.getValue(1); 1927 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1928 1929 Ops[0] = Op1; 1930 Ops[1] = Op2; 1931 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1932 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1933 &Ops[0], 2); 1934 1935 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1936 setValue(&LP, RetPair.first); 1937 DAG.setRoot(RetPair.second); 1938} 1939 1940/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1941/// small case ranges). 1942bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1943 CaseRecVector& WorkList, 1944 const Value* SV, 1945 MachineBasicBlock *Default, 1946 MachineBasicBlock *SwitchBB) { 1947 // Size is the number of Cases represented by this range. 1948 size_t Size = CR.Range.second - CR.Range.first; 1949 if (Size > 3) 1950 return false; 1951 1952 // Get the MachineFunction which holds the current MBB. This is used when 1953 // inserting any additional MBBs necessary to represent the switch. 1954 MachineFunction *CurMF = FuncInfo.MF; 1955 1956 // Figure out which block is immediately after the current one. 1957 MachineBasicBlock *NextBlock = 0; 1958 MachineFunction::iterator BBI = CR.CaseBB; 1959 1960 if (++BBI != FuncInfo.MF->end()) 1961 NextBlock = BBI; 1962 1963 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1964 // If any two of the cases has the same destination, and if one value 1965 // is the same as the other, but has one bit unset that the other has set, 1966 // use bit manipulation to do two compares at once. For example: 1967 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1968 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1969 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1970 if (Size == 2 && CR.CaseBB == SwitchBB) { 1971 Case &Small = *CR.Range.first; 1972 Case &Big = *(CR.Range.second-1); 1973 1974 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1975 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1976 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1977 1978 // Check that there is only one bit different. 1979 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1980 (SmallValue | BigValue) == BigValue) { 1981 // Isolate the common bit. 1982 APInt CommonBit = BigValue & ~SmallValue; 1983 assert((SmallValue | CommonBit) == BigValue && 1984 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1985 1986 SDValue CondLHS = getValue(SV); 1987 EVT VT = CondLHS.getValueType(); 1988 DebugLoc DL = getCurDebugLoc(); 1989 1990 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1991 DAG.getConstant(CommonBit, VT)); 1992 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1993 Or, DAG.getConstant(BigValue, VT), 1994 ISD::SETEQ); 1995 1996 // Update successor info. 1997 // Both Small and Big will jump to Small.BB, so we sum up the weights. 1998 addSuccessorWithWeight(SwitchBB, Small.BB, 1999 Small.ExtraWeight + Big.ExtraWeight); 2000 addSuccessorWithWeight(SwitchBB, Default, 2001 // The default destination is the first successor in IR. 2002 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0); 2003 2004 // Insert the true branch. 2005 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 2006 getControlRoot(), Cond, 2007 DAG.getBasicBlock(Small.BB)); 2008 2009 // Insert the false branch. 2010 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 2011 DAG.getBasicBlock(Default)); 2012 2013 DAG.setRoot(BrCond); 2014 return true; 2015 } 2016 } 2017 } 2018 2019 // Order cases by weight so the most likely case will be checked first. 2020 uint32_t UnhandledWeights = 0; 2021 if (BPI) { 2022 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) { 2023 uint32_t IWeight = I->ExtraWeight; 2024 UnhandledWeights += IWeight; 2025 for (CaseItr J = CR.Range.first; J < I; ++J) { 2026 uint32_t JWeight = J->ExtraWeight; 2027 if (IWeight > JWeight) 2028 std::swap(*I, *J); 2029 } 2030 } 2031 } 2032 // Rearrange the case blocks so that the last one falls through if possible. 2033 Case &BackCase = *(CR.Range.second-1); 2034 if (Size > 1 && 2035 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 2036 // The last case block won't fall through into 'NextBlock' if we emit the 2037 // branches in this order. See if rearranging a case value would help. 2038 // We start at the bottom as it's the case with the least weight. 2039 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){ 2040 if (I->BB == NextBlock) { 2041 std::swap(*I, BackCase); 2042 break; 2043 } 2044 } 2045 } 2046 2047 // Create a CaseBlock record representing a conditional branch to 2048 // the Case's target mbb if the value being switched on SV is equal 2049 // to C. 2050 MachineBasicBlock *CurBlock = CR.CaseBB; 2051 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2052 MachineBasicBlock *FallThrough; 2053 if (I != E-1) { 2054 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 2055 CurMF->insert(BBI, FallThrough); 2056 2057 // Put SV in a virtual register to make it available from the new blocks. 2058 ExportFromCurrentBlock(SV); 2059 } else { 2060 // If the last case doesn't match, go to the default block. 2061 FallThrough = Default; 2062 } 2063 2064 const Value *RHS, *LHS, *MHS; 2065 ISD::CondCode CC; 2066 if (I->High == I->Low) { 2067 // This is just small small case range :) containing exactly 1 case 2068 CC = ISD::SETEQ; 2069 LHS = SV; RHS = I->High; MHS = NULL; 2070 } else { 2071 CC = ISD::SETCC_INVALID; 2072 LHS = I->Low; MHS = SV; RHS = I->High; 2073 } 2074 2075 // The false weight should be sum of all un-handled cases. 2076 UnhandledWeights -= I->ExtraWeight; 2077 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2078 /* me */ CurBlock, 2079 /* trueweight */ I->ExtraWeight, 2080 /* falseweight */ UnhandledWeights); 2081 2082 // If emitting the first comparison, just call visitSwitchCase to emit the 2083 // code into the current block. Otherwise, push the CaseBlock onto the 2084 // vector to be later processed by SDISel, and insert the node's MBB 2085 // before the next MBB. 2086 if (CurBlock == SwitchBB) 2087 visitSwitchCase(CB, SwitchBB); 2088 else 2089 SwitchCases.push_back(CB); 2090 2091 CurBlock = FallThrough; 2092 } 2093 2094 return true; 2095} 2096 2097static inline bool areJTsAllowed(const TargetLowering &TLI) { 2098 return TLI.supportJumpTables() && 2099 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2100 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2101} 2102 2103static APInt ComputeRange(const APInt &First, const APInt &Last) { 2104 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2105 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth); 2106 return (LastExt - FirstExt + 1ULL); 2107} 2108 2109/// handleJTSwitchCase - Emit jumptable for current switch case range 2110bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2111 CaseRecVector &WorkList, 2112 const Value *SV, 2113 MachineBasicBlock *Default, 2114 MachineBasicBlock *SwitchBB) { 2115 Case& FrontCase = *CR.Range.first; 2116 Case& BackCase = *(CR.Range.second-1); 2117 2118 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2119 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2120 2121 APInt TSize(First.getBitWidth(), 0); 2122 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2123 TSize += I->size(); 2124 2125 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries())) 2126 return false; 2127 2128 APInt Range = ComputeRange(First, Last); 2129 // The density is TSize / Range. Require at least 40%. 2130 // It should not be possible for IntTSize to saturate for sane code, but make 2131 // sure we handle Range saturation correctly. 2132 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2133 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2134 if (IntTSize * 10 < IntRange * 4) 2135 return false; 2136 2137 DEBUG(dbgs() << "Lowering jump table\n" 2138 << "First entry: " << First << ". Last entry: " << Last << '\n' 2139 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2140 2141 // Get the MachineFunction which holds the current MBB. This is used when 2142 // inserting any additional MBBs necessary to represent the switch. 2143 MachineFunction *CurMF = FuncInfo.MF; 2144 2145 // Figure out which block is immediately after the current one. 2146 MachineFunction::iterator BBI = CR.CaseBB; 2147 ++BBI; 2148 2149 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2150 2151 // Create a new basic block to hold the code for loading the address 2152 // of the jump table, and jumping to it. Update successor information; 2153 // we will either branch to the default case for the switch, or the jump 2154 // table. 2155 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2156 CurMF->insert(BBI, JumpTableBB); 2157 2158 addSuccessorWithWeight(CR.CaseBB, Default); 2159 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2160 2161 // Build a vector of destination BBs, corresponding to each target 2162 // of the jump table. If the value of the jump table slot corresponds to 2163 // a case statement, push the case's BB onto the vector, otherwise, push 2164 // the default BB. 2165 std::vector<MachineBasicBlock*> DestBBs; 2166 APInt TEI = First; 2167 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2168 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2169 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2170 2171 if (Low.ule(TEI) && TEI.ule(High)) { 2172 DestBBs.push_back(I->BB); 2173 if (TEI==High) 2174 ++I; 2175 } else { 2176 DestBBs.push_back(Default); 2177 } 2178 } 2179 2180 // Calculate weight for each unique destination in CR. 2181 DenseMap<MachineBasicBlock*, uint32_t> DestWeights; 2182 if (FuncInfo.BPI) 2183 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2184 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2185 DestWeights.find(I->BB); 2186 if (Itr != DestWeights.end()) 2187 Itr->second += I->ExtraWeight; 2188 else 2189 DestWeights[I->BB] = I->ExtraWeight; 2190 } 2191 2192 // Update successor info. Add one edge to each unique successor. 2193 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2194 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2195 E = DestBBs.end(); I != E; ++I) { 2196 if (!SuccsHandled[(*I)->getNumber()]) { 2197 SuccsHandled[(*I)->getNumber()] = true; 2198 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2199 DestWeights.find(*I); 2200 addSuccessorWithWeight(JumpTableBB, *I, 2201 Itr != DestWeights.end() ? Itr->second : 0); 2202 } 2203 } 2204 2205 // Create a jump table index for this jump table. 2206 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2207 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2208 ->createJumpTableIndex(DestBBs); 2209 2210 // Set the jump table information so that we can codegen it as a second 2211 // MachineBasicBlock 2212 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2213 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2214 if (CR.CaseBB == SwitchBB) 2215 visitJumpTableHeader(JT, JTH, SwitchBB); 2216 2217 JTCases.push_back(JumpTableBlock(JTH, JT)); 2218 return true; 2219} 2220 2221/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2222/// 2 subtrees. 2223bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2224 CaseRecVector& WorkList, 2225 const Value* SV, 2226 MachineBasicBlock *Default, 2227 MachineBasicBlock *SwitchBB) { 2228 // Get the MachineFunction which holds the current MBB. This is used when 2229 // inserting any additional MBBs necessary to represent the switch. 2230 MachineFunction *CurMF = FuncInfo.MF; 2231 2232 // Figure out which block is immediately after the current one. 2233 MachineFunction::iterator BBI = CR.CaseBB; 2234 ++BBI; 2235 2236 Case& FrontCase = *CR.Range.first; 2237 Case& BackCase = *(CR.Range.second-1); 2238 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2239 2240 // Size is the number of Cases represented by this range. 2241 unsigned Size = CR.Range.second - CR.Range.first; 2242 2243 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2244 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2245 double FMetric = 0; 2246 CaseItr Pivot = CR.Range.first + Size/2; 2247 2248 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2249 // (heuristically) allow us to emit JumpTable's later. 2250 APInt TSize(First.getBitWidth(), 0); 2251 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2252 I!=E; ++I) 2253 TSize += I->size(); 2254 2255 APInt LSize = FrontCase.size(); 2256 APInt RSize = TSize-LSize; 2257 DEBUG(dbgs() << "Selecting best pivot: \n" 2258 << "First: " << First << ", Last: " << Last <<'\n' 2259 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2260 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2261 J!=E; ++I, ++J) { 2262 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2263 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2264 APInt Range = ComputeRange(LEnd, RBegin); 2265 assert((Range - 2ULL).isNonNegative() && 2266 "Invalid case distance"); 2267 // Use volatile double here to avoid excess precision issues on some hosts, 2268 // e.g. that use 80-bit X87 registers. 2269 volatile double LDensity = 2270 (double)LSize.roundToDouble() / 2271 (LEnd - First + 1ULL).roundToDouble(); 2272 volatile double RDensity = 2273 (double)RSize.roundToDouble() / 2274 (Last - RBegin + 1ULL).roundToDouble(); 2275 double Metric = Range.logBase2()*(LDensity+RDensity); 2276 // Should always split in some non-trivial place 2277 DEBUG(dbgs() <<"=>Step\n" 2278 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2279 << "LDensity: " << LDensity 2280 << ", RDensity: " << RDensity << '\n' 2281 << "Metric: " << Metric << '\n'); 2282 if (FMetric < Metric) { 2283 Pivot = J; 2284 FMetric = Metric; 2285 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2286 } 2287 2288 LSize += J->size(); 2289 RSize -= J->size(); 2290 } 2291 if (areJTsAllowed(TLI)) { 2292 // If our case is dense we *really* should handle it earlier! 2293 assert((FMetric > 0) && "Should handle dense range earlier!"); 2294 } else { 2295 Pivot = CR.Range.first + Size/2; 2296 } 2297 2298 CaseRange LHSR(CR.Range.first, Pivot); 2299 CaseRange RHSR(Pivot, CR.Range.second); 2300 const Constant *C = Pivot->Low; 2301 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2302 2303 // We know that we branch to the LHS if the Value being switched on is 2304 // less than the Pivot value, C. We use this to optimize our binary 2305 // tree a bit, by recognizing that if SV is greater than or equal to the 2306 // LHS's Case Value, and that Case Value is exactly one less than the 2307 // Pivot's Value, then we can branch directly to the LHS's Target, 2308 // rather than creating a leaf node for it. 2309 if ((LHSR.second - LHSR.first) == 1 && 2310 LHSR.first->High == CR.GE && 2311 cast<ConstantInt>(C)->getValue() == 2312 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2313 TrueBB = LHSR.first->BB; 2314 } else { 2315 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2316 CurMF->insert(BBI, TrueBB); 2317 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2318 2319 // Put SV in a virtual register to make it available from the new blocks. 2320 ExportFromCurrentBlock(SV); 2321 } 2322 2323 // Similar to the optimization above, if the Value being switched on is 2324 // known to be less than the Constant CR.LT, and the current Case Value 2325 // is CR.LT - 1, then we can branch directly to the target block for 2326 // the current Case Value, rather than emitting a RHS leaf node for it. 2327 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2328 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2329 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2330 FalseBB = RHSR.first->BB; 2331 } else { 2332 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2333 CurMF->insert(BBI, FalseBB); 2334 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2335 2336 // Put SV in a virtual register to make it available from the new blocks. 2337 ExportFromCurrentBlock(SV); 2338 } 2339 2340 // Create a CaseBlock record representing a conditional branch to 2341 // the LHS node if the value being switched on SV is less than C. 2342 // Otherwise, branch to LHS. 2343 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2344 2345 if (CR.CaseBB == SwitchBB) 2346 visitSwitchCase(CB, SwitchBB); 2347 else 2348 SwitchCases.push_back(CB); 2349 2350 return true; 2351} 2352 2353/// handleBitTestsSwitchCase - if current case range has few destination and 2354/// range span less, than machine word bitwidth, encode case range into series 2355/// of masks and emit bit tests with these masks. 2356bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2357 CaseRecVector& WorkList, 2358 const Value* SV, 2359 MachineBasicBlock* Default, 2360 MachineBasicBlock *SwitchBB){ 2361 EVT PTy = TLI.getPointerTy(); 2362 unsigned IntPtrBits = PTy.getSizeInBits(); 2363 2364 Case& FrontCase = *CR.Range.first; 2365 Case& BackCase = *(CR.Range.second-1); 2366 2367 // Get the MachineFunction which holds the current MBB. This is used when 2368 // inserting any additional MBBs necessary to represent the switch. 2369 MachineFunction *CurMF = FuncInfo.MF; 2370 2371 // If target does not have legal shift left, do not emit bit tests at all. 2372 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2373 return false; 2374 2375 size_t numCmps = 0; 2376 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2377 I!=E; ++I) { 2378 // Single case counts one, case range - two. 2379 numCmps += (I->Low == I->High ? 1 : 2); 2380 } 2381 2382 // Count unique destinations 2383 SmallSet<MachineBasicBlock*, 4> Dests; 2384 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2385 Dests.insert(I->BB); 2386 if (Dests.size() > 3) 2387 // Don't bother the code below, if there are too much unique destinations 2388 return false; 2389 } 2390 DEBUG(dbgs() << "Total number of unique destinations: " 2391 << Dests.size() << '\n' 2392 << "Total number of comparisons: " << numCmps << '\n'); 2393 2394 // Compute span of values. 2395 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2396 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2397 APInt cmpRange = maxValue - minValue; 2398 2399 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2400 << "Low bound: " << minValue << '\n' 2401 << "High bound: " << maxValue << '\n'); 2402 2403 if (cmpRange.uge(IntPtrBits) || 2404 (!(Dests.size() == 1 && numCmps >= 3) && 2405 !(Dests.size() == 2 && numCmps >= 5) && 2406 !(Dests.size() >= 3 && numCmps >= 6))) 2407 return false; 2408 2409 DEBUG(dbgs() << "Emitting bit tests\n"); 2410 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2411 2412 // Optimize the case where all the case values fit in a 2413 // word without having to subtract minValue. In this case, 2414 // we can optimize away the subtraction. 2415 if (maxValue.ult(IntPtrBits)) { 2416 cmpRange = maxValue; 2417 } else { 2418 lowBound = minValue; 2419 } 2420 2421 CaseBitsVector CasesBits; 2422 unsigned i, count = 0; 2423 2424 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2425 MachineBasicBlock* Dest = I->BB; 2426 for (i = 0; i < count; ++i) 2427 if (Dest == CasesBits[i].BB) 2428 break; 2429 2430 if (i == count) { 2431 assert((count < 3) && "Too much destinations to test!"); 2432 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/)); 2433 count++; 2434 } 2435 2436 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2437 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2438 2439 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2440 uint64_t hi = (highValue - lowBound).getZExtValue(); 2441 CasesBits[i].ExtraWeight += I->ExtraWeight; 2442 2443 for (uint64_t j = lo; j <= hi; j++) { 2444 CasesBits[i].Mask |= 1ULL << j; 2445 CasesBits[i].Bits++; 2446 } 2447 2448 } 2449 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2450 2451 BitTestInfo BTC; 2452 2453 // Figure out which block is immediately after the current one. 2454 MachineFunction::iterator BBI = CR.CaseBB; 2455 ++BBI; 2456 2457 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2458 2459 DEBUG(dbgs() << "Cases:\n"); 2460 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2461 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2462 << ", Bits: " << CasesBits[i].Bits 2463 << ", BB: " << CasesBits[i].BB << '\n'); 2464 2465 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2466 CurMF->insert(BBI, CaseBB); 2467 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2468 CaseBB, 2469 CasesBits[i].BB, CasesBits[i].ExtraWeight)); 2470 2471 // Put SV in a virtual register to make it available from the new blocks. 2472 ExportFromCurrentBlock(SV); 2473 } 2474 2475 BitTestBlock BTB(lowBound, cmpRange, SV, 2476 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2477 CR.CaseBB, Default, BTC); 2478 2479 if (CR.CaseBB == SwitchBB) 2480 visitBitTestHeader(BTB, SwitchBB); 2481 2482 BitTestCases.push_back(BTB); 2483 2484 return true; 2485} 2486 2487/// Clusterify - Transform simple list of Cases into list of CaseRange's 2488size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2489 const SwitchInst& SI) { 2490 2491 /// Use a shorter form of declaration, and also 2492 /// show the we want to use CRSBuilder as Clusterifier. 2493 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier; 2494 2495 Clusterifier TheClusterifier; 2496 2497 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2498 // Start with "simple" cases 2499 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2500 i != e; ++i) { 2501 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2502 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2503 2504 TheClusterifier.add(i.getCaseValueEx(), SMBB, 2505 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0); 2506 } 2507 2508 TheClusterifier.optimize(); 2509 2510 size_t numCmps = 0; 2511 for (Clusterifier::RangeIterator i = TheClusterifier.begin(), 2512 e = TheClusterifier.end(); i != e; ++i, ++numCmps) { 2513 Clusterifier::Cluster &C = *i; 2514 // Update edge weight for the cluster. 2515 unsigned W = C.first.Weight; 2516 2517 // FIXME: Currently work with ConstantInt based numbers. 2518 // Changing it to APInt based is a pretty heavy for this commit. 2519 Cases.push_back(Case(C.first.getLow().toConstantInt(), 2520 C.first.getHigh().toConstantInt(), C.second, W)); 2521 2522 if (C.first.getLow() != C.first.getHigh()) 2523 // A range counts double, since it requires two compares. 2524 ++numCmps; 2525 } 2526 2527 return numCmps; 2528} 2529 2530void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2531 MachineBasicBlock *Last) { 2532 // Update JTCases. 2533 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2534 if (JTCases[i].first.HeaderBB == First) 2535 JTCases[i].first.HeaderBB = Last; 2536 2537 // Update BitTestCases. 2538 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2539 if (BitTestCases[i].Parent == First) 2540 BitTestCases[i].Parent = Last; 2541} 2542 2543void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2544 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2545 2546 // Figure out which block is immediately after the current one. 2547 MachineBasicBlock *NextBlock = 0; 2548 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2549 2550 // If there is only the default destination, branch to it if it is not the 2551 // next basic block. Otherwise, just fall through. 2552 if (!SI.getNumCases()) { 2553 // Update machine-CFG edges. 2554 2555 // If this is not a fall-through branch, emit the branch. 2556 SwitchMBB->addSuccessor(Default); 2557 if (Default != NextBlock) 2558 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2559 MVT::Other, getControlRoot(), 2560 DAG.getBasicBlock(Default))); 2561 2562 return; 2563 } 2564 2565 // If there are any non-default case statements, create a vector of Cases 2566 // representing each one, and sort the vector so that we can efficiently 2567 // create a binary search tree from them. 2568 CaseVector Cases; 2569 size_t numCmps = Clusterify(Cases, SI); 2570 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2571 << ". Total compares: " << numCmps << '\n'); 2572 (void)numCmps; 2573 2574 // Get the Value to be switched on and default basic blocks, which will be 2575 // inserted into CaseBlock records, representing basic blocks in the binary 2576 // search tree. 2577 const Value *SV = SI.getCondition(); 2578 2579 // Push the initial CaseRec onto the worklist 2580 CaseRecVector WorkList; 2581 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2582 CaseRange(Cases.begin(),Cases.end()))); 2583 2584 while (!WorkList.empty()) { 2585 // Grab a record representing a case range to process off the worklist 2586 CaseRec CR = WorkList.back(); 2587 WorkList.pop_back(); 2588 2589 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2590 continue; 2591 2592 // If the range has few cases (two or less) emit a series of specific 2593 // tests. 2594 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2595 continue; 2596 2597 // If the switch has more than N blocks, and is at least 40% dense, and the 2598 // target supports indirect branches, then emit a jump table rather than 2599 // lowering the switch to a binary tree of conditional branches. 2600 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries(). 2601 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2602 continue; 2603 2604 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2605 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2606 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2607 } 2608} 2609 2610void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2611 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2612 2613 // Update machine-CFG edges with unique successors. 2614 SmallSet<BasicBlock*, 32> Done; 2615 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) { 2616 BasicBlock *BB = I.getSuccessor(i); 2617 bool Inserted = Done.insert(BB); 2618 if (!Inserted) 2619 continue; 2620 2621 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB]; 2622 addSuccessorWithWeight(IndirectBrMBB, Succ); 2623 } 2624 2625 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2626 MVT::Other, getControlRoot(), 2627 getValue(I.getAddress()))); 2628} 2629 2630void SelectionDAGBuilder::visitFSub(const User &I) { 2631 // -0.0 - X --> fneg 2632 Type *Ty = I.getType(); 2633 if (isa<Constant>(I.getOperand(0)) && 2634 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2635 SDValue Op2 = getValue(I.getOperand(1)); 2636 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2637 Op2.getValueType(), Op2)); 2638 return; 2639 } 2640 2641 visitBinary(I, ISD::FSUB); 2642} 2643 2644void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2645 SDValue Op1 = getValue(I.getOperand(0)); 2646 SDValue Op2 = getValue(I.getOperand(1)); 2647 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2648 Op1.getValueType(), Op1, Op2)); 2649} 2650 2651void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2652 SDValue Op1 = getValue(I.getOperand(0)); 2653 SDValue Op2 = getValue(I.getOperand(1)); 2654 2655 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2656 2657 // Coerce the shift amount to the right type if we can. 2658 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2659 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2660 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2661 DebugLoc DL = getCurDebugLoc(); 2662 2663 // If the operand is smaller than the shift count type, promote it. 2664 if (ShiftSize > Op2Size) 2665 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2666 2667 // If the operand is larger than the shift count type but the shift 2668 // count type has enough bits to represent any shift value, truncate 2669 // it now. This is a common case and it exposes the truncate to 2670 // optimization early. 2671 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2672 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2673 // Otherwise we'll need to temporarily settle for some other convenient 2674 // type. Type legalization will make adjustments once the shiftee is split. 2675 else 2676 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2677 } 2678 2679 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2680 Op1.getValueType(), Op1, Op2)); 2681} 2682 2683void SelectionDAGBuilder::visitSDiv(const User &I) { 2684 SDValue Op1 = getValue(I.getOperand(0)); 2685 SDValue Op2 = getValue(I.getOperand(1)); 2686 2687 // Turn exact SDivs into multiplications. 2688 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2689 // exact bit. 2690 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2691 !isa<ConstantSDNode>(Op1) && 2692 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2693 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2694 else 2695 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2696 Op1, Op2)); 2697} 2698 2699void SelectionDAGBuilder::visitICmp(const User &I) { 2700 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2701 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2702 predicate = IC->getPredicate(); 2703 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2704 predicate = ICmpInst::Predicate(IC->getPredicate()); 2705 SDValue Op1 = getValue(I.getOperand(0)); 2706 SDValue Op2 = getValue(I.getOperand(1)); 2707 ISD::CondCode Opcode = getICmpCondCode(predicate); 2708 2709 EVT DestVT = TLI.getValueType(I.getType()); 2710 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2711} 2712 2713void SelectionDAGBuilder::visitFCmp(const User &I) { 2714 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2715 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2716 predicate = FC->getPredicate(); 2717 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2718 predicate = FCmpInst::Predicate(FC->getPredicate()); 2719 SDValue Op1 = getValue(I.getOperand(0)); 2720 SDValue Op2 = getValue(I.getOperand(1)); 2721 ISD::CondCode Condition = getFCmpCondCode(predicate); 2722 if (TM.Options.NoNaNsFPMath) 2723 Condition = getFCmpCodeWithoutNaN(Condition); 2724 EVT DestVT = TLI.getValueType(I.getType()); 2725 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2726} 2727 2728void SelectionDAGBuilder::visitSelect(const User &I) { 2729 SmallVector<EVT, 4> ValueVTs; 2730 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2731 unsigned NumValues = ValueVTs.size(); 2732 if (NumValues == 0) return; 2733 2734 SmallVector<SDValue, 4> Values(NumValues); 2735 SDValue Cond = getValue(I.getOperand(0)); 2736 SDValue TrueVal = getValue(I.getOperand(1)); 2737 SDValue FalseVal = getValue(I.getOperand(2)); 2738 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2739 ISD::VSELECT : ISD::SELECT; 2740 2741 for (unsigned i = 0; i != NumValues; ++i) 2742 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2743 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2744 Cond, 2745 SDValue(TrueVal.getNode(), 2746 TrueVal.getResNo() + i), 2747 SDValue(FalseVal.getNode(), 2748 FalseVal.getResNo() + i)); 2749 2750 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2751 DAG.getVTList(&ValueVTs[0], NumValues), 2752 &Values[0], NumValues)); 2753} 2754 2755void SelectionDAGBuilder::visitTrunc(const User &I) { 2756 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2757 SDValue N = getValue(I.getOperand(0)); 2758 EVT DestVT = TLI.getValueType(I.getType()); 2759 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2760} 2761 2762void SelectionDAGBuilder::visitZExt(const User &I) { 2763 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2764 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2765 SDValue N = getValue(I.getOperand(0)); 2766 EVT DestVT = TLI.getValueType(I.getType()); 2767 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2768} 2769 2770void SelectionDAGBuilder::visitSExt(const User &I) { 2771 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2772 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2773 SDValue N = getValue(I.getOperand(0)); 2774 EVT DestVT = TLI.getValueType(I.getType()); 2775 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2776} 2777 2778void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2779 // FPTrunc is never a no-op cast, no need to check 2780 SDValue N = getValue(I.getOperand(0)); 2781 EVT DestVT = TLI.getValueType(I.getType()); 2782 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2783 DestVT, N, 2784 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2785} 2786 2787void SelectionDAGBuilder::visitFPExt(const User &I){ 2788 // FPExt is never a no-op cast, no need to check 2789 SDValue N = getValue(I.getOperand(0)); 2790 EVT DestVT = TLI.getValueType(I.getType()); 2791 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2792} 2793 2794void SelectionDAGBuilder::visitFPToUI(const User &I) { 2795 // FPToUI is never a no-op cast, no need to check 2796 SDValue N = getValue(I.getOperand(0)); 2797 EVT DestVT = TLI.getValueType(I.getType()); 2798 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2799} 2800 2801void SelectionDAGBuilder::visitFPToSI(const User &I) { 2802 // FPToSI is never a no-op cast, no need to check 2803 SDValue N = getValue(I.getOperand(0)); 2804 EVT DestVT = TLI.getValueType(I.getType()); 2805 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2806} 2807 2808void SelectionDAGBuilder::visitUIToFP(const User &I) { 2809 // UIToFP is never a no-op cast, no need to check 2810 SDValue N = getValue(I.getOperand(0)); 2811 EVT DestVT = TLI.getValueType(I.getType()); 2812 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2813} 2814 2815void SelectionDAGBuilder::visitSIToFP(const User &I){ 2816 // SIToFP is never a no-op cast, no need to check 2817 SDValue N = getValue(I.getOperand(0)); 2818 EVT DestVT = TLI.getValueType(I.getType()); 2819 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2820} 2821 2822void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2823 // What to do depends on the size of the integer and the size of the pointer. 2824 // We can either truncate, zero extend, or no-op, accordingly. 2825 SDValue N = getValue(I.getOperand(0)); 2826 EVT DestVT = TLI.getValueType(I.getType()); 2827 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2828} 2829 2830void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2831 // What to do depends on the size of the integer and the size of the pointer. 2832 // We can either truncate, zero extend, or no-op, accordingly. 2833 SDValue N = getValue(I.getOperand(0)); 2834 EVT DestVT = TLI.getValueType(I.getType()); 2835 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2836} 2837 2838void SelectionDAGBuilder::visitBitCast(const User &I) { 2839 SDValue N = getValue(I.getOperand(0)); 2840 EVT DestVT = TLI.getValueType(I.getType()); 2841 2842 // BitCast assures us that source and destination are the same size so this is 2843 // either a BITCAST or a no-op. 2844 if (DestVT != N.getValueType()) 2845 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2846 DestVT, N)); // convert types. 2847 else 2848 setValue(&I, N); // noop cast. 2849} 2850 2851void SelectionDAGBuilder::visitInsertElement(const User &I) { 2852 SDValue InVec = getValue(I.getOperand(0)); 2853 SDValue InVal = getValue(I.getOperand(1)); 2854 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2855 TLI.getPointerTy(), 2856 getValue(I.getOperand(2))); 2857 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2858 TLI.getValueType(I.getType()), 2859 InVec, InVal, InIdx)); 2860} 2861 2862void SelectionDAGBuilder::visitExtractElement(const User &I) { 2863 SDValue InVec = getValue(I.getOperand(0)); 2864 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2865 TLI.getPointerTy(), 2866 getValue(I.getOperand(1))); 2867 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2868 TLI.getValueType(I.getType()), InVec, InIdx)); 2869} 2870 2871// Utility for visitShuffleVector - Return true if every element in Mask, 2872// beginning from position Pos and ending in Pos+Size, falls within the 2873// specified sequential range [L, L+Pos). or is undef. 2874static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2875 unsigned Pos, unsigned Size, int Low) { 2876 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2877 if (Mask[i] >= 0 && Mask[i] != Low) 2878 return false; 2879 return true; 2880} 2881 2882void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2883 SDValue Src1 = getValue(I.getOperand(0)); 2884 SDValue Src2 = getValue(I.getOperand(1)); 2885 2886 SmallVector<int, 8> Mask; 2887 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2888 unsigned MaskNumElts = Mask.size(); 2889 2890 EVT VT = TLI.getValueType(I.getType()); 2891 EVT SrcVT = Src1.getValueType(); 2892 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2893 2894 if (SrcNumElts == MaskNumElts) { 2895 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2896 &Mask[0])); 2897 return; 2898 } 2899 2900 // Normalize the shuffle vector since mask and vector length don't match. 2901 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2902 // Mask is longer than the source vectors and is a multiple of the source 2903 // vectors. We can use concatenate vector to make the mask and vectors 2904 // lengths match. 2905 if (SrcNumElts*2 == MaskNumElts) { 2906 // First check for Src1 in low and Src2 in high 2907 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2908 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2909 // The shuffle is concatenating two vectors together. 2910 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2911 VT, Src1, Src2)); 2912 return; 2913 } 2914 // Then check for Src2 in low and Src1 in high 2915 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2916 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2917 // The shuffle is concatenating two vectors together. 2918 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2919 VT, Src2, Src1)); 2920 return; 2921 } 2922 } 2923 2924 // Pad both vectors with undefs to make them the same length as the mask. 2925 unsigned NumConcat = MaskNumElts / SrcNumElts; 2926 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2927 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2928 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2929 2930 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2931 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2932 MOps1[0] = Src1; 2933 MOps2[0] = Src2; 2934 2935 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2936 getCurDebugLoc(), VT, 2937 &MOps1[0], NumConcat); 2938 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2939 getCurDebugLoc(), VT, 2940 &MOps2[0], NumConcat); 2941 2942 // Readjust mask for new input vector length. 2943 SmallVector<int, 8> MappedOps; 2944 for (unsigned i = 0; i != MaskNumElts; ++i) { 2945 int Idx = Mask[i]; 2946 if (Idx >= (int)SrcNumElts) 2947 Idx -= SrcNumElts - MaskNumElts; 2948 MappedOps.push_back(Idx); 2949 } 2950 2951 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2952 &MappedOps[0])); 2953 return; 2954 } 2955 2956 if (SrcNumElts > MaskNumElts) { 2957 // Analyze the access pattern of the vector to see if we can extract 2958 // two subvectors and do the shuffle. The analysis is done by calculating 2959 // the range of elements the mask access on both vectors. 2960 int MinRange[2] = { static_cast<int>(SrcNumElts), 2961 static_cast<int>(SrcNumElts)}; 2962 int MaxRange[2] = {-1, -1}; 2963 2964 for (unsigned i = 0; i != MaskNumElts; ++i) { 2965 int Idx = Mask[i]; 2966 unsigned Input = 0; 2967 if (Idx < 0) 2968 continue; 2969 2970 if (Idx >= (int)SrcNumElts) { 2971 Input = 1; 2972 Idx -= SrcNumElts; 2973 } 2974 if (Idx > MaxRange[Input]) 2975 MaxRange[Input] = Idx; 2976 if (Idx < MinRange[Input]) 2977 MinRange[Input] = Idx; 2978 } 2979 2980 // Check if the access is smaller than the vector size and can we find 2981 // a reasonable extract index. 2982 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 2983 // Extract. 2984 int StartIdx[2]; // StartIdx to extract from 2985 for (unsigned Input = 0; Input < 2; ++Input) { 2986 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 2987 RangeUse[Input] = 0; // Unused 2988 StartIdx[Input] = 0; 2989 continue; 2990 } 2991 2992 // Find a good start index that is a multiple of the mask length. Then 2993 // see if the rest of the elements are in range. 2994 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2995 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2996 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2997 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2998 } 2999 3000 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 3001 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 3002 return; 3003 } 3004 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 3005 // Extract appropriate subvector and generate a vector shuffle 3006 for (unsigned Input = 0; Input < 2; ++Input) { 3007 SDValue &Src = Input == 0 ? Src1 : Src2; 3008 if (RangeUse[Input] == 0) 3009 Src = DAG.getUNDEF(VT); 3010 else 3011 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 3012 Src, DAG.getIntPtrConstant(StartIdx[Input])); 3013 } 3014 3015 // Calculate new mask. 3016 SmallVector<int, 8> MappedOps; 3017 for (unsigned i = 0; i != MaskNumElts; ++i) { 3018 int Idx = Mask[i]; 3019 if (Idx >= 0) { 3020 if (Idx < (int)SrcNumElts) 3021 Idx -= StartIdx[0]; 3022 else 3023 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 3024 } 3025 MappedOps.push_back(Idx); 3026 } 3027 3028 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 3029 &MappedOps[0])); 3030 return; 3031 } 3032 } 3033 3034 // We can't use either concat vectors or extract subvectors so fall back to 3035 // replacing the shuffle with extract and build vector. 3036 // to insert and build vector. 3037 EVT EltVT = VT.getVectorElementType(); 3038 EVT PtrVT = TLI.getPointerTy(); 3039 SmallVector<SDValue,8> Ops; 3040 for (unsigned i = 0; i != MaskNumElts; ++i) { 3041 int Idx = Mask[i]; 3042 SDValue Res; 3043 3044 if (Idx < 0) { 3045 Res = DAG.getUNDEF(EltVT); 3046 } else { 3047 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 3048 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 3049 3050 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 3051 EltVT, Src, DAG.getConstant(Idx, PtrVT)); 3052 } 3053 3054 Ops.push_back(Res); 3055 } 3056 3057 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 3058 VT, &Ops[0], Ops.size())); 3059} 3060 3061void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3062 const Value *Op0 = I.getOperand(0); 3063 const Value *Op1 = I.getOperand(1); 3064 Type *AggTy = I.getType(); 3065 Type *ValTy = Op1->getType(); 3066 bool IntoUndef = isa<UndefValue>(Op0); 3067 bool FromUndef = isa<UndefValue>(Op1); 3068 3069 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3070 3071 SmallVector<EVT, 4> AggValueVTs; 3072 ComputeValueVTs(TLI, AggTy, AggValueVTs); 3073 SmallVector<EVT, 4> ValValueVTs; 3074 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3075 3076 unsigned NumAggValues = AggValueVTs.size(); 3077 unsigned NumValValues = ValValueVTs.size(); 3078 SmallVector<SDValue, 4> Values(NumAggValues); 3079 3080 SDValue Agg = getValue(Op0); 3081 unsigned i = 0; 3082 // Copy the beginning value(s) from the original aggregate. 3083 for (; i != LinearIndex; ++i) 3084 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3085 SDValue(Agg.getNode(), Agg.getResNo() + i); 3086 // Copy values from the inserted value(s). 3087 if (NumValValues) { 3088 SDValue Val = getValue(Op1); 3089 for (; i != LinearIndex + NumValValues; ++i) 3090 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3091 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3092 } 3093 // Copy remaining value(s) from the original aggregate. 3094 for (; i != NumAggValues; ++i) 3095 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3096 SDValue(Agg.getNode(), Agg.getResNo() + i); 3097 3098 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3099 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3100 &Values[0], NumAggValues)); 3101} 3102 3103void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3104 const Value *Op0 = I.getOperand(0); 3105 Type *AggTy = Op0->getType(); 3106 Type *ValTy = I.getType(); 3107 bool OutOfUndef = isa<UndefValue>(Op0); 3108 3109 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3110 3111 SmallVector<EVT, 4> ValValueVTs; 3112 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3113 3114 unsigned NumValValues = ValValueVTs.size(); 3115 3116 // Ignore a extractvalue that produces an empty object 3117 if (!NumValValues) { 3118 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3119 return; 3120 } 3121 3122 SmallVector<SDValue, 4> Values(NumValValues); 3123 3124 SDValue Agg = getValue(Op0); 3125 // Copy out the selected value(s). 3126 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3127 Values[i - LinearIndex] = 3128 OutOfUndef ? 3129 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3130 SDValue(Agg.getNode(), Agg.getResNo() + i); 3131 3132 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3133 DAG.getVTList(&ValValueVTs[0], NumValValues), 3134 &Values[0], NumValValues)); 3135} 3136 3137void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3138 SDValue N = getValue(I.getOperand(0)); 3139 // Note that the pointer operand may be a vector of pointers. Take the scalar 3140 // element which holds a pointer. 3141 Type *Ty = I.getOperand(0)->getType()->getScalarType(); 3142 3143 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3144 OI != E; ++OI) { 3145 const Value *Idx = *OI; 3146 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3147 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue(); 3148 if (Field) { 3149 // N = N + Offset 3150 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3151 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3152 DAG.getConstant(Offset, N.getValueType())); 3153 } 3154 3155 Ty = StTy->getElementType(Field); 3156 } else { 3157 Ty = cast<SequentialType>(Ty)->getElementType(); 3158 3159 // If this is a constant subscript, handle it quickly. 3160 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3161 if (CI->isZero()) continue; 3162 uint64_t Offs = 3163 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3164 SDValue OffsVal; 3165 EVT PTy = TLI.getPointerTy(); 3166 unsigned PtrBits = PTy.getSizeInBits(); 3167 if (PtrBits < 64) 3168 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3169 TLI.getPointerTy(), 3170 DAG.getConstant(Offs, MVT::i64)); 3171 else 3172 OffsVal = DAG.getIntPtrConstant(Offs); 3173 3174 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3175 OffsVal); 3176 continue; 3177 } 3178 3179 // N = N + Idx * ElementSize; 3180 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3181 TD->getTypeAllocSize(Ty)); 3182 SDValue IdxN = getValue(Idx); 3183 3184 // If the index is smaller or larger than intptr_t, truncate or extend 3185 // it. 3186 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3187 3188 // If this is a multiply by a power of two, turn it into a shl 3189 // immediately. This is a very common case. 3190 if (ElementSize != 1) { 3191 if (ElementSize.isPowerOf2()) { 3192 unsigned Amt = ElementSize.logBase2(); 3193 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3194 N.getValueType(), IdxN, 3195 DAG.getConstant(Amt, IdxN.getValueType())); 3196 } else { 3197 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType()); 3198 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3199 N.getValueType(), IdxN, Scale); 3200 } 3201 } 3202 3203 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3204 N.getValueType(), N, IdxN); 3205 } 3206 } 3207 3208 setValue(&I, N); 3209} 3210 3211void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3212 // If this is a fixed sized alloca in the entry block of the function, 3213 // allocate it statically on the stack. 3214 if (FuncInfo.StaticAllocaMap.count(&I)) 3215 return; // getValue will auto-populate this. 3216 3217 Type *Ty = I.getAllocatedType(); 3218 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty); 3219 unsigned Align = 3220 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty), 3221 I.getAlignment()); 3222 3223 SDValue AllocSize = getValue(I.getArraySize()); 3224 3225 EVT IntPtr = TLI.getPointerTy(); 3226 if (AllocSize.getValueType() != IntPtr) 3227 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3228 3229 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3230 AllocSize, 3231 DAG.getConstant(TySize, IntPtr)); 3232 3233 // Handle alignment. If the requested alignment is less than or equal to 3234 // the stack alignment, ignore it. If the size is greater than or equal to 3235 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3236 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3237 if (Align <= StackAlign) 3238 Align = 0; 3239 3240 // Round the size of the allocation up to the stack alignment size 3241 // by add SA-1 to the size. 3242 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3243 AllocSize.getValueType(), AllocSize, 3244 DAG.getIntPtrConstant(StackAlign-1)); 3245 3246 // Mask out the low bits for alignment purposes. 3247 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3248 AllocSize.getValueType(), AllocSize, 3249 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3250 3251 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3252 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3253 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3254 VTs, Ops, 3); 3255 setValue(&I, DSA); 3256 DAG.setRoot(DSA.getValue(1)); 3257 3258 // Inform the Frame Information that we have just allocated a variable-sized 3259 // object. 3260 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3261} 3262 3263void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3264 if (I.isAtomic()) 3265 return visitAtomicLoad(I); 3266 3267 const Value *SV = I.getOperand(0); 3268 SDValue Ptr = getValue(SV); 3269 3270 Type *Ty = I.getType(); 3271 3272 bool isVolatile = I.isVolatile(); 3273 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3274 bool isInvariant = I.getMetadata("invariant.load") != 0; 3275 unsigned Alignment = I.getAlignment(); 3276 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3277 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3278 3279 SmallVector<EVT, 4> ValueVTs; 3280 SmallVector<uint64_t, 4> Offsets; 3281 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3282 unsigned NumValues = ValueVTs.size(); 3283 if (NumValues == 0) 3284 return; 3285 3286 SDValue Root; 3287 bool ConstantMemory = false; 3288 if (I.isVolatile() || NumValues > MaxParallelChains) 3289 // Serialize volatile loads with other side effects. 3290 Root = getRoot(); 3291 else if (AA->pointsToConstantMemory( 3292 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3293 // Do not serialize (non-volatile) loads of constant memory with anything. 3294 Root = DAG.getEntryNode(); 3295 ConstantMemory = true; 3296 } else { 3297 // Do not serialize non-volatile loads against each other. 3298 Root = DAG.getRoot(); 3299 } 3300 3301 SmallVector<SDValue, 4> Values(NumValues); 3302 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3303 NumValues)); 3304 EVT PtrVT = Ptr.getValueType(); 3305 unsigned ChainI = 0; 3306 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3307 // Serializing loads here may result in excessive register pressure, and 3308 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3309 // could recover a bit by hoisting nodes upward in the chain by recognizing 3310 // they are side-effect free or do not alias. The optimizer should really 3311 // avoid this case by converting large object/array copies to llvm.memcpy 3312 // (MaxParallelChains should always remain as failsafe). 3313 if (ChainI == MaxParallelChains) { 3314 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3315 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3316 MVT::Other, &Chains[0], ChainI); 3317 Root = Chain; 3318 ChainI = 0; 3319 } 3320 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3321 PtrVT, Ptr, 3322 DAG.getConstant(Offsets[i], PtrVT)); 3323 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3324 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3325 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3326 Ranges); 3327 3328 Values[i] = L; 3329 Chains[ChainI] = L.getValue(1); 3330 } 3331 3332 if (!ConstantMemory) { 3333 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3334 MVT::Other, &Chains[0], ChainI); 3335 if (isVolatile) 3336 DAG.setRoot(Chain); 3337 else 3338 PendingLoads.push_back(Chain); 3339 } 3340 3341 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3342 DAG.getVTList(&ValueVTs[0], NumValues), 3343 &Values[0], NumValues)); 3344} 3345 3346void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3347 if (I.isAtomic()) 3348 return visitAtomicStore(I); 3349 3350 const Value *SrcV = I.getOperand(0); 3351 const Value *PtrV = I.getOperand(1); 3352 3353 SmallVector<EVT, 4> ValueVTs; 3354 SmallVector<uint64_t, 4> Offsets; 3355 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3356 unsigned NumValues = ValueVTs.size(); 3357 if (NumValues == 0) 3358 return; 3359 3360 // Get the lowered operands. Note that we do this after 3361 // checking if NumResults is zero, because with zero results 3362 // the operands won't have values in the map. 3363 SDValue Src = getValue(SrcV); 3364 SDValue Ptr = getValue(PtrV); 3365 3366 SDValue Root = getRoot(); 3367 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3368 NumValues)); 3369 EVT PtrVT = Ptr.getValueType(); 3370 bool isVolatile = I.isVolatile(); 3371 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3372 unsigned Alignment = I.getAlignment(); 3373 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3374 3375 unsigned ChainI = 0; 3376 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3377 // See visitLoad comments. 3378 if (ChainI == MaxParallelChains) { 3379 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3380 MVT::Other, &Chains[0], ChainI); 3381 Root = Chain; 3382 ChainI = 0; 3383 } 3384 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3385 DAG.getConstant(Offsets[i], PtrVT)); 3386 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3387 SDValue(Src.getNode(), Src.getResNo() + i), 3388 Add, MachinePointerInfo(PtrV, Offsets[i]), 3389 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3390 Chains[ChainI] = St; 3391 } 3392 3393 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3394 MVT::Other, &Chains[0], ChainI); 3395 ++SDNodeOrder; 3396 AssignOrderingToNode(StoreNode.getNode()); 3397 DAG.setRoot(StoreNode); 3398} 3399 3400static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3401 SynchronizationScope Scope, 3402 bool Before, DebugLoc dl, 3403 SelectionDAG &DAG, 3404 const TargetLowering &TLI) { 3405 // Fence, if necessary 3406 if (Before) { 3407 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3408 Order = Release; 3409 else if (Order == Acquire || Order == Monotonic) 3410 return Chain; 3411 } else { 3412 if (Order == AcquireRelease) 3413 Order = Acquire; 3414 else if (Order == Release || Order == Monotonic) 3415 return Chain; 3416 } 3417 SDValue Ops[3]; 3418 Ops[0] = Chain; 3419 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3420 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3421 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3422} 3423 3424void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3425 DebugLoc dl = getCurDebugLoc(); 3426 AtomicOrdering Order = I.getOrdering(); 3427 SynchronizationScope Scope = I.getSynchScope(); 3428 3429 SDValue InChain = getRoot(); 3430 3431 if (TLI.getInsertFencesForAtomic()) 3432 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3433 DAG, TLI); 3434 3435 SDValue L = 3436 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3437 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3438 InChain, 3439 getValue(I.getPointerOperand()), 3440 getValue(I.getCompareOperand()), 3441 getValue(I.getNewValOperand()), 3442 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3443 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3444 Scope); 3445 3446 SDValue OutChain = L.getValue(1); 3447 3448 if (TLI.getInsertFencesForAtomic()) 3449 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3450 DAG, TLI); 3451 3452 setValue(&I, L); 3453 DAG.setRoot(OutChain); 3454} 3455 3456void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3457 DebugLoc dl = getCurDebugLoc(); 3458 ISD::NodeType NT; 3459 switch (I.getOperation()) { 3460 default: llvm_unreachable("Unknown atomicrmw operation"); 3461 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3462 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3463 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3464 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3465 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3466 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3467 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3468 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3469 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3470 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3471 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3472 } 3473 AtomicOrdering Order = I.getOrdering(); 3474 SynchronizationScope Scope = I.getSynchScope(); 3475 3476 SDValue InChain = getRoot(); 3477 3478 if (TLI.getInsertFencesForAtomic()) 3479 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3480 DAG, TLI); 3481 3482 SDValue L = 3483 DAG.getAtomic(NT, dl, 3484 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3485 InChain, 3486 getValue(I.getPointerOperand()), 3487 getValue(I.getValOperand()), 3488 I.getPointerOperand(), 0 /* Alignment */, 3489 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3490 Scope); 3491 3492 SDValue OutChain = L.getValue(1); 3493 3494 if (TLI.getInsertFencesForAtomic()) 3495 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3496 DAG, TLI); 3497 3498 setValue(&I, L); 3499 DAG.setRoot(OutChain); 3500} 3501 3502void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3503 DebugLoc dl = getCurDebugLoc(); 3504 SDValue Ops[3]; 3505 Ops[0] = getRoot(); 3506 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3507 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3508 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3509} 3510 3511void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3512 DebugLoc dl = getCurDebugLoc(); 3513 AtomicOrdering Order = I.getOrdering(); 3514 SynchronizationScope Scope = I.getSynchScope(); 3515 3516 SDValue InChain = getRoot(); 3517 3518 EVT VT = TLI.getValueType(I.getType()); 3519 3520 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3521 report_fatal_error("Cannot generate unaligned atomic load"); 3522 3523 SDValue L = 3524 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3525 getValue(I.getPointerOperand()), 3526 I.getPointerOperand(), I.getAlignment(), 3527 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3528 Scope); 3529 3530 SDValue OutChain = L.getValue(1); 3531 3532 if (TLI.getInsertFencesForAtomic()) 3533 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3534 DAG, TLI); 3535 3536 setValue(&I, L); 3537 DAG.setRoot(OutChain); 3538} 3539 3540void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3541 DebugLoc dl = getCurDebugLoc(); 3542 3543 AtomicOrdering Order = I.getOrdering(); 3544 SynchronizationScope Scope = I.getSynchScope(); 3545 3546 SDValue InChain = getRoot(); 3547 3548 EVT VT = TLI.getValueType(I.getValueOperand()->getType()); 3549 3550 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3551 report_fatal_error("Cannot generate unaligned atomic store"); 3552 3553 if (TLI.getInsertFencesForAtomic()) 3554 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3555 DAG, TLI); 3556 3557 SDValue OutChain = 3558 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3559 InChain, 3560 getValue(I.getPointerOperand()), 3561 getValue(I.getValueOperand()), 3562 I.getPointerOperand(), I.getAlignment(), 3563 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3564 Scope); 3565 3566 if (TLI.getInsertFencesForAtomic()) 3567 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3568 DAG, TLI); 3569 3570 DAG.setRoot(OutChain); 3571} 3572 3573/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3574/// node. 3575void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3576 unsigned Intrinsic) { 3577 bool HasChain = !I.doesNotAccessMemory(); 3578 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3579 3580 // Build the operand list. 3581 SmallVector<SDValue, 8> Ops; 3582 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3583 if (OnlyLoad) { 3584 // We don't need to serialize loads against other loads. 3585 Ops.push_back(DAG.getRoot()); 3586 } else { 3587 Ops.push_back(getRoot()); 3588 } 3589 } 3590 3591 // Info is set by getTgtMemInstrinsic 3592 TargetLowering::IntrinsicInfo Info; 3593 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3594 3595 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3596 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3597 Info.opc == ISD::INTRINSIC_W_CHAIN) 3598 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3599 3600 // Add all operands of the call to the operand list. 3601 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3602 SDValue Op = getValue(I.getArgOperand(i)); 3603 Ops.push_back(Op); 3604 } 3605 3606 SmallVector<EVT, 4> ValueVTs; 3607 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3608 3609 if (HasChain) 3610 ValueVTs.push_back(MVT::Other); 3611 3612 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3613 3614 // Create the node. 3615 SDValue Result; 3616 if (IsTgtIntrinsic) { 3617 // This is target intrinsic that touches memory 3618 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3619 VTs, &Ops[0], Ops.size(), 3620 Info.memVT, 3621 MachinePointerInfo(Info.ptrVal, Info.offset), 3622 Info.align, Info.vol, 3623 Info.readMem, Info.writeMem); 3624 } else if (!HasChain) { 3625 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3626 VTs, &Ops[0], Ops.size()); 3627 } else if (!I.getType()->isVoidTy()) { 3628 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3629 VTs, &Ops[0], Ops.size()); 3630 } else { 3631 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3632 VTs, &Ops[0], Ops.size()); 3633 } 3634 3635 if (HasChain) { 3636 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3637 if (OnlyLoad) 3638 PendingLoads.push_back(Chain); 3639 else 3640 DAG.setRoot(Chain); 3641 } 3642 3643 if (!I.getType()->isVoidTy()) { 3644 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3645 EVT VT = TLI.getValueType(PTy); 3646 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3647 } 3648 3649 setValue(&I, Result); 3650 } else { 3651 // Assign order to result here. If the intrinsic does not produce a result, 3652 // it won't be mapped to a SDNode and visit() will not assign it an order 3653 // number. 3654 ++SDNodeOrder; 3655 AssignOrderingToNode(Result.getNode()); 3656 } 3657} 3658 3659/// GetSignificand - Get the significand and build it into a floating-point 3660/// number with exponent of 1: 3661/// 3662/// Op = (Op & 0x007fffff) | 0x3f800000; 3663/// 3664/// where Op is the hexidecimal representation of floating point value. 3665static SDValue 3666GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3667 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3668 DAG.getConstant(0x007fffff, MVT::i32)); 3669 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3670 DAG.getConstant(0x3f800000, MVT::i32)); 3671 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3672} 3673 3674/// GetExponent - Get the exponent: 3675/// 3676/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3677/// 3678/// where Op is the hexidecimal representation of floating point value. 3679static SDValue 3680GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3681 DebugLoc dl) { 3682 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3683 DAG.getConstant(0x7f800000, MVT::i32)); 3684 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3685 DAG.getConstant(23, TLI.getPointerTy())); 3686 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3687 DAG.getConstant(127, MVT::i32)); 3688 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3689} 3690 3691/// getF32Constant - Get 32-bit floating point constant. 3692static SDValue 3693getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3694 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3695} 3696 3697/// expandExp - Lower an exp intrinsic. Handles the special sequences for 3698/// limited-precision mode. 3699static SDValue expandExp(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3700 const TargetLowering &TLI) { 3701 if (Op.getValueType() == MVT::f32 && 3702 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3703 3704 // Put the exponent in the right bit position for later addition to the 3705 // final result: 3706 // 3707 // #define LOG2OFe 1.4426950f 3708 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3709 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3710 getF32Constant(DAG, 0x3fb8aa3b)); 3711 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3712 3713 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3714 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3715 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3716 3717 // IntegerPartOfX <<= 23; 3718 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3719 DAG.getConstant(23, TLI.getPointerTy())); 3720 3721 SDValue TwoToFracPartOfX; 3722 if (LimitFloatPrecision <= 6) { 3723 // For floating-point precision of 6: 3724 // 3725 // TwoToFractionalPartOfX = 3726 // 0.997535578f + 3727 // (0.735607626f + 0.252464424f * x) * x; 3728 // 3729 // error 0.0144103317, which is 6 bits 3730 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3731 getF32Constant(DAG, 0x3e814304)); 3732 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3733 getF32Constant(DAG, 0x3f3c50c8)); 3734 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3735 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3736 getF32Constant(DAG, 0x3f7f5e7e)); 3737 } else if (LimitFloatPrecision <= 12) { 3738 // For floating-point precision of 12: 3739 // 3740 // TwoToFractionalPartOfX = 3741 // 0.999892986f + 3742 // (0.696457318f + 3743 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3744 // 3745 // 0.000107046256 error, which is 13 to 14 bits 3746 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3747 getF32Constant(DAG, 0x3da235e3)); 3748 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3749 getF32Constant(DAG, 0x3e65b8f3)); 3750 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3751 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3752 getF32Constant(DAG, 0x3f324b07)); 3753 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3754 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3755 getF32Constant(DAG, 0x3f7ff8fd)); 3756 } else { // LimitFloatPrecision <= 18 3757 // For floating-point precision of 18: 3758 // 3759 // TwoToFractionalPartOfX = 3760 // 0.999999982f + 3761 // (0.693148872f + 3762 // (0.240227044f + 3763 // (0.554906021e-1f + 3764 // (0.961591928e-2f + 3765 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3766 // 3767 // error 2.47208000*10^(-7), which is better than 18 bits 3768 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3769 getF32Constant(DAG, 0x3924b03e)); 3770 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3771 getF32Constant(DAG, 0x3ab24b87)); 3772 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3773 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3774 getF32Constant(DAG, 0x3c1d8c17)); 3775 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3776 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3777 getF32Constant(DAG, 0x3d634a1d)); 3778 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3779 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3780 getF32Constant(DAG, 0x3e75fe14)); 3781 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3782 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3783 getF32Constant(DAG, 0x3f317234)); 3784 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3785 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3786 getF32Constant(DAG, 0x3f800000)); 3787 } 3788 3789 // Add the exponent into the result in integer domain. 3790 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX); 3791 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3792 DAG.getNode(ISD::ADD, dl, MVT::i32, 3793 t13, IntegerPartOfX)); 3794 } 3795 3796 // No special expansion. 3797 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op); 3798} 3799 3800/// expandLog - Lower a log intrinsic. Handles the special sequences for 3801/// limited-precision mode. 3802static SDValue expandLog(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3803 const TargetLowering &TLI) { 3804 if (Op.getValueType() == MVT::f32 && 3805 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3806 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3807 3808 // Scale the exponent by log(2) [0.69314718f]. 3809 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3810 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3811 getF32Constant(DAG, 0x3f317218)); 3812 3813 // Get the significand and build it into a floating-point number with 3814 // exponent of 1. 3815 SDValue X = GetSignificand(DAG, Op1, dl); 3816 3817 SDValue LogOfMantissa; 3818 if (LimitFloatPrecision <= 6) { 3819 // For floating-point precision of 6: 3820 // 3821 // LogofMantissa = 3822 // -1.1609546f + 3823 // (1.4034025f - 0.23903021f * x) * x; 3824 // 3825 // error 0.0034276066, which is better than 8 bits 3826 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3827 getF32Constant(DAG, 0xbe74c456)); 3828 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3829 getF32Constant(DAG, 0x3fb3a2b1)); 3830 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3831 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3832 getF32Constant(DAG, 0x3f949a29)); 3833 } else if (LimitFloatPrecision <= 12) { 3834 // For floating-point precision of 12: 3835 // 3836 // LogOfMantissa = 3837 // -1.7417939f + 3838 // (2.8212026f + 3839 // (-1.4699568f + 3840 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3841 // 3842 // error 0.000061011436, which is 14 bits 3843 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3844 getF32Constant(DAG, 0xbd67b6d6)); 3845 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3846 getF32Constant(DAG, 0x3ee4f4b8)); 3847 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3848 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3849 getF32Constant(DAG, 0x3fbc278b)); 3850 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3851 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3852 getF32Constant(DAG, 0x40348e95)); 3853 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3854 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3855 getF32Constant(DAG, 0x3fdef31a)); 3856 } else { // LimitFloatPrecision <= 18 3857 // For floating-point precision of 18: 3858 // 3859 // LogOfMantissa = 3860 // -2.1072184f + 3861 // (4.2372794f + 3862 // (-3.7029485f + 3863 // (2.2781945f + 3864 // (-0.87823314f + 3865 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3866 // 3867 // error 0.0000023660568, which is better than 18 bits 3868 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3869 getF32Constant(DAG, 0xbc91e5ac)); 3870 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3871 getF32Constant(DAG, 0x3e4350aa)); 3872 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3873 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3874 getF32Constant(DAG, 0x3f60d3e3)); 3875 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3876 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3877 getF32Constant(DAG, 0x4011cdf0)); 3878 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3879 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3880 getF32Constant(DAG, 0x406cfd1c)); 3881 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3882 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3883 getF32Constant(DAG, 0x408797cb)); 3884 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3885 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3886 getF32Constant(DAG, 0x4006dcab)); 3887 } 3888 3889 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa); 3890 } 3891 3892 // No special expansion. 3893 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op); 3894} 3895 3896/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for 3897/// limited-precision mode. 3898static SDValue expandLog2(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3899 const TargetLowering &TLI) { 3900 if (Op.getValueType() == MVT::f32 && 3901 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3902 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3903 3904 // Get the exponent. 3905 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3906 3907 // Get the significand and build it into a floating-point number with 3908 // exponent of 1. 3909 SDValue X = GetSignificand(DAG, Op1, dl); 3910 3911 // Different possible minimax approximations of significand in 3912 // floating-point for various degrees of accuracy over [1,2]. 3913 SDValue Log2ofMantissa; 3914 if (LimitFloatPrecision <= 6) { 3915 // For floating-point precision of 6: 3916 // 3917 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3918 // 3919 // error 0.0049451742, which is more than 7 bits 3920 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3921 getF32Constant(DAG, 0xbeb08fe0)); 3922 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3923 getF32Constant(DAG, 0x40019463)); 3924 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3925 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3926 getF32Constant(DAG, 0x3fd6633d)); 3927 } else if (LimitFloatPrecision <= 12) { 3928 // For floating-point precision of 12: 3929 // 3930 // Log2ofMantissa = 3931 // -2.51285454f + 3932 // (4.07009056f + 3933 // (-2.12067489f + 3934 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3935 // 3936 // error 0.0000876136000, which is better than 13 bits 3937 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3938 getF32Constant(DAG, 0xbda7262e)); 3939 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3940 getF32Constant(DAG, 0x3f25280b)); 3941 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3942 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3943 getF32Constant(DAG, 0x4007b923)); 3944 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3945 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3946 getF32Constant(DAG, 0x40823e2f)); 3947 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3948 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3949 getF32Constant(DAG, 0x4020d29c)); 3950 } else { // LimitFloatPrecision <= 18 3951 // For floating-point precision of 18: 3952 // 3953 // Log2ofMantissa = 3954 // -3.0400495f + 3955 // (6.1129976f + 3956 // (-5.3420409f + 3957 // (3.2865683f + 3958 // (-1.2669343f + 3959 // (0.27515199f - 3960 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3961 // 3962 // error 0.0000018516, which is better than 18 bits 3963 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3964 getF32Constant(DAG, 0xbcd2769e)); 3965 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3966 getF32Constant(DAG, 0x3e8ce0b9)); 3967 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3968 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3969 getF32Constant(DAG, 0x3fa22ae7)); 3970 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3971 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3972 getF32Constant(DAG, 0x40525723)); 3973 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3974 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3975 getF32Constant(DAG, 0x40aaf200)); 3976 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3977 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3978 getF32Constant(DAG, 0x40c39dad)); 3979 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3980 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3981 getF32Constant(DAG, 0x4042902c)); 3982 } 3983 3984 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa); 3985 } 3986 3987 // No special expansion. 3988 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op); 3989} 3990 3991/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for 3992/// limited-precision mode. 3993static SDValue expandLog10(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 3994 const TargetLowering &TLI) { 3995 if (Op.getValueType() == MVT::f32 && 3996 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3997 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3998 3999 // Scale the exponent by log10(2) [0.30102999f]. 4000 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 4001 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 4002 getF32Constant(DAG, 0x3e9a209a)); 4003 4004 // Get the significand and build it into a floating-point number with 4005 // exponent of 1. 4006 SDValue X = GetSignificand(DAG, Op1, dl); 4007 4008 SDValue Log10ofMantissa; 4009 if (LimitFloatPrecision <= 6) { 4010 // For floating-point precision of 6: 4011 // 4012 // Log10ofMantissa = 4013 // -0.50419619f + 4014 // (0.60948995f - 0.10380950f * x) * x; 4015 // 4016 // error 0.0014886165, which is 6 bits 4017 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4018 getF32Constant(DAG, 0xbdd49a13)); 4019 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4020 getF32Constant(DAG, 0x3f1c0789)); 4021 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4022 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4023 getF32Constant(DAG, 0x3f011300)); 4024 } else if (LimitFloatPrecision <= 12) { 4025 // For floating-point precision of 12: 4026 // 4027 // Log10ofMantissa = 4028 // -0.64831180f + 4029 // (0.91751397f + 4030 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4031 // 4032 // error 0.00019228036, which is better than 12 bits 4033 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4034 getF32Constant(DAG, 0x3d431f31)); 4035 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4036 getF32Constant(DAG, 0x3ea21fb2)); 4037 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4038 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4039 getF32Constant(DAG, 0x3f6ae232)); 4040 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4041 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4042 getF32Constant(DAG, 0x3f25f7c3)); 4043 } else { // LimitFloatPrecision <= 18 4044 // For floating-point precision of 18: 4045 // 4046 // Log10ofMantissa = 4047 // -0.84299375f + 4048 // (1.5327582f + 4049 // (-1.0688956f + 4050 // (0.49102474f + 4051 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4052 // 4053 // error 0.0000037995730, which is better than 18 bits 4054 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4055 getF32Constant(DAG, 0x3c5d51ce)); 4056 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4057 getF32Constant(DAG, 0x3e00685a)); 4058 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4059 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4060 getF32Constant(DAG, 0x3efb6798)); 4061 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4062 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4063 getF32Constant(DAG, 0x3f88d192)); 4064 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4065 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4066 getF32Constant(DAG, 0x3fc4316c)); 4067 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4068 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4069 getF32Constant(DAG, 0x3f57ce70)); 4070 } 4071 4072 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa); 4073 } 4074 4075 // No special expansion. 4076 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op); 4077} 4078 4079/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4080/// limited-precision mode. 4081static SDValue expandExp2(DebugLoc dl, SDValue Op, SelectionDAG &DAG, 4082 const TargetLowering &TLI) { 4083 if (Op.getValueType() == MVT::f32 && 4084 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4085 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4086 4087 // FractionalPartOfX = x - (float)IntegerPartOfX; 4088 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4089 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4090 4091 // IntegerPartOfX <<= 23; 4092 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4093 DAG.getConstant(23, TLI.getPointerTy())); 4094 4095 SDValue TwoToFractionalPartOfX; 4096 if (LimitFloatPrecision <= 6) { 4097 // For floating-point precision of 6: 4098 // 4099 // TwoToFractionalPartOfX = 4100 // 0.997535578f + 4101 // (0.735607626f + 0.252464424f * x) * x; 4102 // 4103 // error 0.0144103317, which is 6 bits 4104 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4105 getF32Constant(DAG, 0x3e814304)); 4106 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4107 getF32Constant(DAG, 0x3f3c50c8)); 4108 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4109 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4110 getF32Constant(DAG, 0x3f7f5e7e)); 4111 } else if (LimitFloatPrecision <= 12) { 4112 // For floating-point precision of 12: 4113 // 4114 // TwoToFractionalPartOfX = 4115 // 0.999892986f + 4116 // (0.696457318f + 4117 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4118 // 4119 // error 0.000107046256, which is 13 to 14 bits 4120 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4121 getF32Constant(DAG, 0x3da235e3)); 4122 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4123 getF32Constant(DAG, 0x3e65b8f3)); 4124 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4125 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4126 getF32Constant(DAG, 0x3f324b07)); 4127 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4128 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4129 getF32Constant(DAG, 0x3f7ff8fd)); 4130 } else { // LimitFloatPrecision <= 18 4131 // For floating-point precision of 18: 4132 // 4133 // TwoToFractionalPartOfX = 4134 // 0.999999982f + 4135 // (0.693148872f + 4136 // (0.240227044f + 4137 // (0.554906021e-1f + 4138 // (0.961591928e-2f + 4139 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4140 // error 2.47208000*10^(-7), which is better than 18 bits 4141 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4142 getF32Constant(DAG, 0x3924b03e)); 4143 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4144 getF32Constant(DAG, 0x3ab24b87)); 4145 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4146 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4147 getF32Constant(DAG, 0x3c1d8c17)); 4148 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4149 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4150 getF32Constant(DAG, 0x3d634a1d)); 4151 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4152 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4153 getF32Constant(DAG, 0x3e75fe14)); 4154 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4155 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4156 getF32Constant(DAG, 0x3f317234)); 4157 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4158 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4159 getF32Constant(DAG, 0x3f800000)); 4160 } 4161 4162 // Add the exponent into the result in integer domain. 4163 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, 4164 TwoToFractionalPartOfX); 4165 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4166 DAG.getNode(ISD::ADD, dl, MVT::i32, 4167 t13, IntegerPartOfX)); 4168 } 4169 4170 // No special expansion. 4171 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op); 4172} 4173 4174/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4175/// limited-precision mode with x == 10.0f. 4176static SDValue expandPow(DebugLoc dl, SDValue LHS, SDValue RHS, 4177 SelectionDAG &DAG, const TargetLowering &TLI) { 4178 bool IsExp10 = false; 4179 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 && 4180 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4181 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) { 4182 APFloat Ten(10.0f); 4183 IsExp10 = LHSC->isExactlyValue(Ten); 4184 } 4185 } 4186 4187 if (IsExp10) { 4188 // Put the exponent in the right bit position for later addition to the 4189 // final result: 4190 // 4191 // #define LOG2OF10 3.3219281f 4192 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4193 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS, 4194 getF32Constant(DAG, 0x40549a78)); 4195 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4196 4197 // FractionalPartOfX = x - (float)IntegerPartOfX; 4198 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4199 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4200 4201 // IntegerPartOfX <<= 23; 4202 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4203 DAG.getConstant(23, TLI.getPointerTy())); 4204 4205 SDValue TwoToFractionalPartOfX; 4206 if (LimitFloatPrecision <= 6) { 4207 // For floating-point precision of 6: 4208 // 4209 // twoToFractionalPartOfX = 4210 // 0.997535578f + 4211 // (0.735607626f + 0.252464424f * x) * x; 4212 // 4213 // error 0.0144103317, which is 6 bits 4214 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4215 getF32Constant(DAG, 0x3e814304)); 4216 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4217 getF32Constant(DAG, 0x3f3c50c8)); 4218 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4219 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4220 getF32Constant(DAG, 0x3f7f5e7e)); 4221 } else if (LimitFloatPrecision <= 12) { 4222 // For floating-point precision of 12: 4223 // 4224 // TwoToFractionalPartOfX = 4225 // 0.999892986f + 4226 // (0.696457318f + 4227 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4228 // 4229 // error 0.000107046256, which is 13 to 14 bits 4230 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4231 getF32Constant(DAG, 0x3da235e3)); 4232 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4233 getF32Constant(DAG, 0x3e65b8f3)); 4234 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4235 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4236 getF32Constant(DAG, 0x3f324b07)); 4237 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4238 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4239 getF32Constant(DAG, 0x3f7ff8fd)); 4240 } else { // LimitFloatPrecision <= 18 4241 // For floating-point precision of 18: 4242 // 4243 // TwoToFractionalPartOfX = 4244 // 0.999999982f + 4245 // (0.693148872f + 4246 // (0.240227044f + 4247 // (0.554906021e-1f + 4248 // (0.961591928e-2f + 4249 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4250 // error 2.47208000*10^(-7), which is better than 18 bits 4251 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4252 getF32Constant(DAG, 0x3924b03e)); 4253 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4254 getF32Constant(DAG, 0x3ab24b87)); 4255 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4256 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4257 getF32Constant(DAG, 0x3c1d8c17)); 4258 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4259 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4260 getF32Constant(DAG, 0x3d634a1d)); 4261 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4262 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4263 getF32Constant(DAG, 0x3e75fe14)); 4264 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4265 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4266 getF32Constant(DAG, 0x3f317234)); 4267 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4268 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4269 getF32Constant(DAG, 0x3f800000)); 4270 } 4271 4272 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX); 4273 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4274 DAG.getNode(ISD::ADD, dl, MVT::i32, 4275 t13, IntegerPartOfX)); 4276 } 4277 4278 // No special expansion. 4279 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS); 4280} 4281 4282 4283/// ExpandPowI - Expand a llvm.powi intrinsic. 4284static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4285 SelectionDAG &DAG) { 4286 // If RHS is a constant, we can expand this out to a multiplication tree, 4287 // otherwise we end up lowering to a call to __powidf2 (for example). When 4288 // optimizing for size, we only want to do this if the expansion would produce 4289 // a small number of multiplies, otherwise we do the full expansion. 4290 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4291 // Get the exponent as a positive value. 4292 unsigned Val = RHSC->getSExtValue(); 4293 if ((int)Val < 0) Val = -Val; 4294 4295 // powi(x, 0) -> 1.0 4296 if (Val == 0) 4297 return DAG.getConstantFP(1.0, LHS.getValueType()); 4298 4299 const Function *F = DAG.getMachineFunction().getFunction(); 4300 if (!F->getFnAttributes().hasAttribute(Attributes::OptimizeForSize) || 4301 // If optimizing for size, don't insert too many multiplies. This 4302 // inserts up to 5 multiplies. 4303 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4304 // We use the simple binary decomposition method to generate the multiply 4305 // sequence. There are more optimal ways to do this (for example, 4306 // powi(x,15) generates one more multiply than it should), but this has 4307 // the benefit of being both really simple and much better than a libcall. 4308 SDValue Res; // Logically starts equal to 1.0 4309 SDValue CurSquare = LHS; 4310 while (Val) { 4311 if (Val & 1) { 4312 if (Res.getNode()) 4313 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4314 else 4315 Res = CurSquare; // 1.0*CurSquare. 4316 } 4317 4318 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4319 CurSquare, CurSquare); 4320 Val >>= 1; 4321 } 4322 4323 // If the original was negative, invert the result, producing 1/(x*x*x). 4324 if (RHSC->getSExtValue() < 0) 4325 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4326 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4327 return Res; 4328 } 4329 } 4330 4331 // Otherwise, expand to a libcall. 4332 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4333} 4334 4335// getTruncatedArgReg - Find underlying register used for an truncated 4336// argument. 4337static unsigned getTruncatedArgReg(const SDValue &N) { 4338 if (N.getOpcode() != ISD::TRUNCATE) 4339 return 0; 4340 4341 const SDValue &Ext = N.getOperand(0); 4342 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4343 const SDValue &CFR = Ext.getOperand(0); 4344 if (CFR.getOpcode() == ISD::CopyFromReg) 4345 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4346 if (CFR.getOpcode() == ISD::TRUNCATE) 4347 return getTruncatedArgReg(CFR); 4348 } 4349 return 0; 4350} 4351 4352/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4353/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4354/// At the end of instruction selection, they will be inserted to the entry BB. 4355bool 4356SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4357 int64_t Offset, 4358 const SDValue &N) { 4359 const Argument *Arg = dyn_cast<Argument>(V); 4360 if (!Arg) 4361 return false; 4362 4363 MachineFunction &MF = DAG.getMachineFunction(); 4364 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4365 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4366 4367 // Ignore inlined function arguments here. 4368 DIVariable DV(Variable); 4369 if (DV.isInlinedFnArgument(MF.getFunction())) 4370 return false; 4371 4372 unsigned Reg = 0; 4373 // Some arguments' frame index is recorded during argument lowering. 4374 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4375 if (Offset) 4376 Reg = TRI->getFrameRegister(MF); 4377 4378 if (!Reg && N.getNode()) { 4379 if (N.getOpcode() == ISD::CopyFromReg) 4380 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4381 else 4382 Reg = getTruncatedArgReg(N); 4383 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4384 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4385 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4386 if (PR) 4387 Reg = PR; 4388 } 4389 } 4390 4391 if (!Reg) { 4392 // Check if ValueMap has reg number. 4393 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4394 if (VMI != FuncInfo.ValueMap.end()) 4395 Reg = VMI->second; 4396 } 4397 4398 if (!Reg && N.getNode()) { 4399 // Check if frame index is available. 4400 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4401 if (FrameIndexSDNode *FINode = 4402 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4403 Reg = TRI->getFrameRegister(MF); 4404 Offset = FINode->getIndex(); 4405 } 4406 } 4407 4408 if (!Reg) 4409 return false; 4410 4411 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4412 TII->get(TargetOpcode::DBG_VALUE)) 4413 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4414 FuncInfo.ArgDbgValues.push_back(&*MIB); 4415 return true; 4416} 4417 4418// VisualStudio defines setjmp as _setjmp 4419#if defined(_MSC_VER) && defined(setjmp) && \ 4420 !defined(setjmp_undefined_for_msvc) 4421# pragma push_macro("setjmp") 4422# undef setjmp 4423# define setjmp_undefined_for_msvc 4424#endif 4425 4426/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4427/// we want to emit this as a call to a named external function, return the name 4428/// otherwise lower it and return null. 4429const char * 4430SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4431 DebugLoc dl = getCurDebugLoc(); 4432 SDValue Res; 4433 4434 switch (Intrinsic) { 4435 default: 4436 // By default, turn this into a target intrinsic node. 4437 visitTargetIntrinsic(I, Intrinsic); 4438 return 0; 4439 case Intrinsic::vastart: visitVAStart(I); return 0; 4440 case Intrinsic::vaend: visitVAEnd(I); return 0; 4441 case Intrinsic::vacopy: visitVACopy(I); return 0; 4442 case Intrinsic::returnaddress: 4443 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4444 getValue(I.getArgOperand(0)))); 4445 return 0; 4446 case Intrinsic::frameaddress: 4447 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4448 getValue(I.getArgOperand(0)))); 4449 return 0; 4450 case Intrinsic::setjmp: 4451 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()]; 4452 case Intrinsic::longjmp: 4453 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()]; 4454 case Intrinsic::memcpy: { 4455 // Assert for address < 256 since we support only user defined address 4456 // spaces. 4457 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4458 < 256 && 4459 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4460 < 256 && 4461 "Unknown address space"); 4462 SDValue Op1 = getValue(I.getArgOperand(0)); 4463 SDValue Op2 = getValue(I.getArgOperand(1)); 4464 SDValue Op3 = getValue(I.getArgOperand(2)); 4465 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4466 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4467 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4468 MachinePointerInfo(I.getArgOperand(0)), 4469 MachinePointerInfo(I.getArgOperand(1)))); 4470 return 0; 4471 } 4472 case Intrinsic::memset: { 4473 // Assert for address < 256 since we support only user defined address 4474 // spaces. 4475 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4476 < 256 && 4477 "Unknown address space"); 4478 SDValue Op1 = getValue(I.getArgOperand(0)); 4479 SDValue Op2 = getValue(I.getArgOperand(1)); 4480 SDValue Op3 = getValue(I.getArgOperand(2)); 4481 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4482 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4483 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4484 MachinePointerInfo(I.getArgOperand(0)))); 4485 return 0; 4486 } 4487 case Intrinsic::memmove: { 4488 // Assert for address < 256 since we support only user defined address 4489 // spaces. 4490 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4491 < 256 && 4492 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4493 < 256 && 4494 "Unknown address space"); 4495 SDValue Op1 = getValue(I.getArgOperand(0)); 4496 SDValue Op2 = getValue(I.getArgOperand(1)); 4497 SDValue Op3 = getValue(I.getArgOperand(2)); 4498 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4499 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4500 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4501 MachinePointerInfo(I.getArgOperand(0)), 4502 MachinePointerInfo(I.getArgOperand(1)))); 4503 return 0; 4504 } 4505 case Intrinsic::dbg_declare: { 4506 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4507 MDNode *Variable = DI.getVariable(); 4508 const Value *Address = DI.getAddress(); 4509 if (!Address || !DIVariable(Variable).Verify()) { 4510 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4511 return 0; 4512 } 4513 4514 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4515 // but do not always have a corresponding SDNode built. The SDNodeOrder 4516 // absolute, but not relative, values are different depending on whether 4517 // debug info exists. 4518 ++SDNodeOrder; 4519 4520 // Check if address has undef value. 4521 if (isa<UndefValue>(Address) || 4522 (Address->use_empty() && !isa<Argument>(Address))) { 4523 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4524 return 0; 4525 } 4526 4527 SDValue &N = NodeMap[Address]; 4528 if (!N.getNode() && isa<Argument>(Address)) 4529 // Check unused arguments map. 4530 N = UnusedArgNodeMap[Address]; 4531 SDDbgValue *SDV; 4532 if (N.getNode()) { 4533 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4534 Address = BCI->getOperand(0); 4535 // Parameters are handled specially. 4536 bool isParameter = 4537 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4538 isa<Argument>(Address)); 4539 4540 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4541 4542 if (isParameter && !AI) { 4543 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4544 if (FINode) 4545 // Byval parameter. We have a frame index at this point. 4546 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4547 0, dl, SDNodeOrder); 4548 else { 4549 // Address is an argument, so try to emit its dbg value using 4550 // virtual register info from the FuncInfo.ValueMap. 4551 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4552 return 0; 4553 } 4554 } else if (AI) 4555 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4556 0, dl, SDNodeOrder); 4557 else { 4558 // Can't do anything with other non-AI cases yet. 4559 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4560 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4561 DEBUG(Address->dump()); 4562 return 0; 4563 } 4564 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4565 } else { 4566 // If Address is an argument then try to emit its dbg value using 4567 // virtual register info from the FuncInfo.ValueMap. 4568 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4569 // If variable is pinned by a alloca in dominating bb then 4570 // use StaticAllocaMap. 4571 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4572 if (AI->getParent() != DI.getParent()) { 4573 DenseMap<const AllocaInst*, int>::iterator SI = 4574 FuncInfo.StaticAllocaMap.find(AI); 4575 if (SI != FuncInfo.StaticAllocaMap.end()) { 4576 SDV = DAG.getDbgValue(Variable, SI->second, 4577 0, dl, SDNodeOrder); 4578 DAG.AddDbgValue(SDV, 0, false); 4579 return 0; 4580 } 4581 } 4582 } 4583 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4584 } 4585 } 4586 return 0; 4587 } 4588 case Intrinsic::dbg_value: { 4589 const DbgValueInst &DI = cast<DbgValueInst>(I); 4590 if (!DIVariable(DI.getVariable()).Verify()) 4591 return 0; 4592 4593 MDNode *Variable = DI.getVariable(); 4594 uint64_t Offset = DI.getOffset(); 4595 const Value *V = DI.getValue(); 4596 if (!V) 4597 return 0; 4598 4599 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4600 // but do not always have a corresponding SDNode built. The SDNodeOrder 4601 // absolute, but not relative, values are different depending on whether 4602 // debug info exists. 4603 ++SDNodeOrder; 4604 SDDbgValue *SDV; 4605 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4606 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4607 DAG.AddDbgValue(SDV, 0, false); 4608 } else { 4609 // Do not use getValue() in here; we don't want to generate code at 4610 // this point if it hasn't been done yet. 4611 SDValue N = NodeMap[V]; 4612 if (!N.getNode() && isa<Argument>(V)) 4613 // Check unused arguments map. 4614 N = UnusedArgNodeMap[V]; 4615 if (N.getNode()) { 4616 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4617 SDV = DAG.getDbgValue(Variable, N.getNode(), 4618 N.getResNo(), Offset, dl, SDNodeOrder); 4619 DAG.AddDbgValue(SDV, N.getNode(), false); 4620 } 4621 } else if (!V->use_empty() ) { 4622 // Do not call getValue(V) yet, as we don't want to generate code. 4623 // Remember it for later. 4624 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4625 DanglingDebugInfoMap[V] = DDI; 4626 } else { 4627 // We may expand this to cover more cases. One case where we have no 4628 // data available is an unreferenced parameter. 4629 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4630 } 4631 } 4632 4633 // Build a debug info table entry. 4634 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4635 V = BCI->getOperand(0); 4636 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4637 // Don't handle byval struct arguments or VLAs, for example. 4638 if (!AI) { 4639 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4640 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4641 return 0; 4642 } 4643 DenseMap<const AllocaInst*, int>::iterator SI = 4644 FuncInfo.StaticAllocaMap.find(AI); 4645 if (SI == FuncInfo.StaticAllocaMap.end()) 4646 return 0; // VLAs. 4647 int FI = SI->second; 4648 4649 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4650 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4651 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4652 return 0; 4653 } 4654 4655 case Intrinsic::eh_typeid_for: { 4656 // Find the type id for the given typeinfo. 4657 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4658 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4659 Res = DAG.getConstant(TypeID, MVT::i32); 4660 setValue(&I, Res); 4661 return 0; 4662 } 4663 4664 case Intrinsic::eh_return_i32: 4665 case Intrinsic::eh_return_i64: 4666 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4667 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4668 MVT::Other, 4669 getControlRoot(), 4670 getValue(I.getArgOperand(0)), 4671 getValue(I.getArgOperand(1)))); 4672 return 0; 4673 case Intrinsic::eh_unwind_init: 4674 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4675 return 0; 4676 case Intrinsic::eh_dwarf_cfa: { 4677 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4678 TLI.getPointerTy()); 4679 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4680 TLI.getPointerTy(), 4681 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4682 TLI.getPointerTy()), 4683 CfaArg); 4684 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4685 TLI.getPointerTy(), 4686 DAG.getConstant(0, TLI.getPointerTy())); 4687 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4688 FA, Offset)); 4689 return 0; 4690 } 4691 case Intrinsic::eh_sjlj_callsite: { 4692 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4693 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4694 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4695 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4696 4697 MMI.setCurrentCallSite(CI->getZExtValue()); 4698 return 0; 4699 } 4700 case Intrinsic::eh_sjlj_functioncontext: { 4701 // Get and store the index of the function context. 4702 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4703 AllocaInst *FnCtx = 4704 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4705 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4706 MFI->setFunctionContextIndex(FI); 4707 return 0; 4708 } 4709 case Intrinsic::eh_sjlj_setjmp: { 4710 SDValue Ops[2]; 4711 Ops[0] = getRoot(); 4712 Ops[1] = getValue(I.getArgOperand(0)); 4713 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4714 DAG.getVTList(MVT::i32, MVT::Other), 4715 Ops, 2); 4716 setValue(&I, Op.getValue(0)); 4717 DAG.setRoot(Op.getValue(1)); 4718 return 0; 4719 } 4720 case Intrinsic::eh_sjlj_longjmp: { 4721 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4722 getRoot(), getValue(I.getArgOperand(0)))); 4723 return 0; 4724 } 4725 4726 case Intrinsic::x86_mmx_pslli_w: 4727 case Intrinsic::x86_mmx_pslli_d: 4728 case Intrinsic::x86_mmx_pslli_q: 4729 case Intrinsic::x86_mmx_psrli_w: 4730 case Intrinsic::x86_mmx_psrli_d: 4731 case Intrinsic::x86_mmx_psrli_q: 4732 case Intrinsic::x86_mmx_psrai_w: 4733 case Intrinsic::x86_mmx_psrai_d: { 4734 SDValue ShAmt = getValue(I.getArgOperand(1)); 4735 if (isa<ConstantSDNode>(ShAmt)) { 4736 visitTargetIntrinsic(I, Intrinsic); 4737 return 0; 4738 } 4739 unsigned NewIntrinsic = 0; 4740 EVT ShAmtVT = MVT::v2i32; 4741 switch (Intrinsic) { 4742 case Intrinsic::x86_mmx_pslli_w: 4743 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4744 break; 4745 case Intrinsic::x86_mmx_pslli_d: 4746 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4747 break; 4748 case Intrinsic::x86_mmx_pslli_q: 4749 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4750 break; 4751 case Intrinsic::x86_mmx_psrli_w: 4752 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4753 break; 4754 case Intrinsic::x86_mmx_psrli_d: 4755 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4756 break; 4757 case Intrinsic::x86_mmx_psrli_q: 4758 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4759 break; 4760 case Intrinsic::x86_mmx_psrai_w: 4761 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4762 break; 4763 case Intrinsic::x86_mmx_psrai_d: 4764 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4765 break; 4766 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4767 } 4768 4769 // The vector shift intrinsics with scalars uses 32b shift amounts but 4770 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4771 // to be zero. 4772 // We must do this early because v2i32 is not a legal type. 4773 SDValue ShOps[2]; 4774 ShOps[0] = ShAmt; 4775 ShOps[1] = DAG.getConstant(0, MVT::i32); 4776 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4777 EVT DestVT = TLI.getValueType(I.getType()); 4778 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4779 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4780 DAG.getConstant(NewIntrinsic, MVT::i32), 4781 getValue(I.getArgOperand(0)), ShAmt); 4782 setValue(&I, Res); 4783 return 0; 4784 } 4785 case Intrinsic::x86_avx_vinsertf128_pd_256: 4786 case Intrinsic::x86_avx_vinsertf128_ps_256: 4787 case Intrinsic::x86_avx_vinsertf128_si_256: 4788 case Intrinsic::x86_avx2_vinserti128: { 4789 EVT DestVT = TLI.getValueType(I.getType()); 4790 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType()); 4791 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4792 ElVT.getVectorNumElements(); 4793 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT, 4794 getValue(I.getArgOperand(0)), 4795 getValue(I.getArgOperand(1)), 4796 DAG.getIntPtrConstant(Idx)); 4797 setValue(&I, Res); 4798 return 0; 4799 } 4800 case Intrinsic::x86_avx_vextractf128_pd_256: 4801 case Intrinsic::x86_avx_vextractf128_ps_256: 4802 case Intrinsic::x86_avx_vextractf128_si_256: 4803 case Intrinsic::x86_avx2_vextracti128: { 4804 EVT DestVT = TLI.getValueType(I.getType()); 4805 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) * 4806 DestVT.getVectorNumElements(); 4807 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, 4808 getValue(I.getArgOperand(0)), 4809 DAG.getIntPtrConstant(Idx)); 4810 setValue(&I, Res); 4811 return 0; 4812 } 4813 case Intrinsic::convertff: 4814 case Intrinsic::convertfsi: 4815 case Intrinsic::convertfui: 4816 case Intrinsic::convertsif: 4817 case Intrinsic::convertuif: 4818 case Intrinsic::convertss: 4819 case Intrinsic::convertsu: 4820 case Intrinsic::convertus: 4821 case Intrinsic::convertuu: { 4822 ISD::CvtCode Code = ISD::CVT_INVALID; 4823 switch (Intrinsic) { 4824 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4825 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4826 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4827 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4828 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4829 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4830 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4831 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4832 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4833 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4834 } 4835 EVT DestVT = TLI.getValueType(I.getType()); 4836 const Value *Op1 = I.getArgOperand(0); 4837 Res = DAG.getConvertRndSat(DestVT, dl, getValue(Op1), 4838 DAG.getValueType(DestVT), 4839 DAG.getValueType(getValue(Op1).getValueType()), 4840 getValue(I.getArgOperand(1)), 4841 getValue(I.getArgOperand(2)), 4842 Code); 4843 setValue(&I, Res); 4844 return 0; 4845 } 4846 case Intrinsic::powi: 4847 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4848 getValue(I.getArgOperand(1)), DAG)); 4849 return 0; 4850 case Intrinsic::log: 4851 setValue(&I, expandLog(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4852 return 0; 4853 case Intrinsic::log2: 4854 setValue(&I, expandLog2(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4855 return 0; 4856 case Intrinsic::log10: 4857 setValue(&I, expandLog10(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4858 return 0; 4859 case Intrinsic::exp: 4860 setValue(&I, expandExp(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4861 return 0; 4862 case Intrinsic::exp2: 4863 setValue(&I, expandExp2(dl, getValue(I.getArgOperand(0)), DAG, TLI)); 4864 return 0; 4865 case Intrinsic::pow: 4866 setValue(&I, expandPow(dl, getValue(I.getArgOperand(0)), 4867 getValue(I.getArgOperand(1)), DAG, TLI)); 4868 return 0; 4869 case Intrinsic::sqrt: 4870 case Intrinsic::fabs: 4871 case Intrinsic::sin: 4872 case Intrinsic::cos: 4873 case Intrinsic::floor: 4874 case Intrinsic::ceil: 4875 case Intrinsic::trunc: 4876 case Intrinsic::rint: 4877 case Intrinsic::nearbyint: { 4878 unsigned Opcode; 4879 switch (Intrinsic) { 4880 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4881 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 4882 case Intrinsic::fabs: Opcode = ISD::FABS; break; 4883 case Intrinsic::sin: Opcode = ISD::FSIN; break; 4884 case Intrinsic::cos: Opcode = ISD::FCOS; break; 4885 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; 4886 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; 4887 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; 4888 case Intrinsic::rint: Opcode = ISD::FRINT; break; 4889 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; 4890 } 4891 4892 setValue(&I, DAG.getNode(Opcode, dl, 4893 getValue(I.getArgOperand(0)).getValueType(), 4894 getValue(I.getArgOperand(0)))); 4895 return 0; 4896 } 4897 case Intrinsic::fma: 4898 setValue(&I, DAG.getNode(ISD::FMA, dl, 4899 getValue(I.getArgOperand(0)).getValueType(), 4900 getValue(I.getArgOperand(0)), 4901 getValue(I.getArgOperand(1)), 4902 getValue(I.getArgOperand(2)))); 4903 return 0; 4904 case Intrinsic::fmuladd: { 4905 EVT VT = TLI.getValueType(I.getType()); 4906 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && 4907 TLI.isOperationLegalOrCustom(ISD::FMA, VT) && 4908 TLI.isFMAFasterThanMulAndAdd(VT)){ 4909 setValue(&I, DAG.getNode(ISD::FMA, dl, 4910 getValue(I.getArgOperand(0)).getValueType(), 4911 getValue(I.getArgOperand(0)), 4912 getValue(I.getArgOperand(1)), 4913 getValue(I.getArgOperand(2)))); 4914 } else { 4915 SDValue Mul = DAG.getNode(ISD::FMUL, dl, 4916 getValue(I.getArgOperand(0)).getValueType(), 4917 getValue(I.getArgOperand(0)), 4918 getValue(I.getArgOperand(1))); 4919 SDValue Add = DAG.getNode(ISD::FADD, dl, 4920 getValue(I.getArgOperand(0)).getValueType(), 4921 Mul, 4922 getValue(I.getArgOperand(2))); 4923 setValue(&I, Add); 4924 } 4925 return 0; 4926 } 4927 case Intrinsic::convert_to_fp16: 4928 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4929 MVT::i16, getValue(I.getArgOperand(0)))); 4930 return 0; 4931 case Intrinsic::convert_from_fp16: 4932 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4933 MVT::f32, getValue(I.getArgOperand(0)))); 4934 return 0; 4935 case Intrinsic::pcmarker: { 4936 SDValue Tmp = getValue(I.getArgOperand(0)); 4937 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4938 return 0; 4939 } 4940 case Intrinsic::readcyclecounter: { 4941 SDValue Op = getRoot(); 4942 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4943 DAG.getVTList(MVT::i64, MVT::Other), 4944 &Op, 1); 4945 setValue(&I, Res); 4946 DAG.setRoot(Res.getValue(1)); 4947 return 0; 4948 } 4949 case Intrinsic::bswap: 4950 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4951 getValue(I.getArgOperand(0)).getValueType(), 4952 getValue(I.getArgOperand(0)))); 4953 return 0; 4954 case Intrinsic::cttz: { 4955 SDValue Arg = getValue(I.getArgOperand(0)); 4956 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4957 EVT Ty = Arg.getValueType(); 4958 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4959 dl, Ty, Arg)); 4960 return 0; 4961 } 4962 case Intrinsic::ctlz: { 4963 SDValue Arg = getValue(I.getArgOperand(0)); 4964 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4965 EVT Ty = Arg.getValueType(); 4966 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4967 dl, Ty, Arg)); 4968 return 0; 4969 } 4970 case Intrinsic::ctpop: { 4971 SDValue Arg = getValue(I.getArgOperand(0)); 4972 EVT Ty = Arg.getValueType(); 4973 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4974 return 0; 4975 } 4976 case Intrinsic::stacksave: { 4977 SDValue Op = getRoot(); 4978 Res = DAG.getNode(ISD::STACKSAVE, dl, 4979 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4980 setValue(&I, Res); 4981 DAG.setRoot(Res.getValue(1)); 4982 return 0; 4983 } 4984 case Intrinsic::stackrestore: { 4985 Res = getValue(I.getArgOperand(0)); 4986 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4987 return 0; 4988 } 4989 case Intrinsic::stackprotector: { 4990 // Emit code into the DAG to store the stack guard onto the stack. 4991 MachineFunction &MF = DAG.getMachineFunction(); 4992 MachineFrameInfo *MFI = MF.getFrameInfo(); 4993 EVT PtrTy = TLI.getPointerTy(); 4994 4995 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4996 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4997 4998 int FI = FuncInfo.StaticAllocaMap[Slot]; 4999 MFI->setStackProtectorIndex(FI); 5000 5001 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5002 5003 // Store the stack protector onto the stack. 5004 Res = DAG.getStore(getRoot(), dl, Src, FIN, 5005 MachinePointerInfo::getFixedStack(FI), 5006 true, false, 0); 5007 setValue(&I, Res); 5008 DAG.setRoot(Res); 5009 return 0; 5010 } 5011 case Intrinsic::objectsize: { 5012 // If we don't know by now, we're never going to know. 5013 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5014 5015 assert(CI && "Non-constant type in __builtin_object_size?"); 5016 5017 SDValue Arg = getValue(I.getCalledValue()); 5018 EVT Ty = Arg.getValueType(); 5019 5020 if (CI->isZero()) 5021 Res = DAG.getConstant(-1ULL, Ty); 5022 else 5023 Res = DAG.getConstant(0, Ty); 5024 5025 setValue(&I, Res); 5026 return 0; 5027 } 5028 case Intrinsic::var_annotation: 5029 // Discard annotate attributes 5030 return 0; 5031 5032 case Intrinsic::init_trampoline: { 5033 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5034 5035 SDValue Ops[6]; 5036 Ops[0] = getRoot(); 5037 Ops[1] = getValue(I.getArgOperand(0)); 5038 Ops[2] = getValue(I.getArgOperand(1)); 5039 Ops[3] = getValue(I.getArgOperand(2)); 5040 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5041 Ops[5] = DAG.getSrcValue(F); 5042 5043 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5044 5045 DAG.setRoot(Res); 5046 return 0; 5047 } 5048 case Intrinsic::adjust_trampoline: { 5049 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5050 TLI.getPointerTy(), 5051 getValue(I.getArgOperand(0)))); 5052 return 0; 5053 } 5054 case Intrinsic::gcroot: 5055 if (GFI) { 5056 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 5057 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5058 5059 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5060 GFI->addStackRoot(FI->getIndex(), TypeMap); 5061 } 5062 return 0; 5063 case Intrinsic::gcread: 5064 case Intrinsic::gcwrite: 5065 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5066 case Intrinsic::flt_rounds: 5067 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5068 return 0; 5069 5070 case Intrinsic::expect: { 5071 // Just replace __builtin_expect(exp, c) with EXP. 5072 setValue(&I, getValue(I.getArgOperand(0))); 5073 return 0; 5074 } 5075 5076 case Intrinsic::debugtrap: 5077 case Intrinsic::trap: { 5078 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5079 if (TrapFuncName.empty()) { 5080 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ? 5081 ISD::TRAP : ISD::DEBUGTRAP; 5082 DAG.setRoot(DAG.getNode(Op, dl,MVT::Other, getRoot())); 5083 return 0; 5084 } 5085 TargetLowering::ArgListTy Args; 5086 TargetLowering:: 5087 CallLoweringInfo CLI(getRoot(), I.getType(), 5088 false, false, false, false, 0, CallingConv::C, 5089 /*isTailCall=*/false, 5090 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5091 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5092 Args, DAG, dl); 5093 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI); 5094 DAG.setRoot(Result.second); 5095 return 0; 5096 } 5097 5098 case Intrinsic::uadd_with_overflow: 5099 case Intrinsic::sadd_with_overflow: 5100 case Intrinsic::usub_with_overflow: 5101 case Intrinsic::ssub_with_overflow: 5102 case Intrinsic::umul_with_overflow: 5103 case Intrinsic::smul_with_overflow: { 5104 ISD::NodeType Op; 5105 switch (Intrinsic) { 5106 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5107 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 5108 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 5109 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 5110 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 5111 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 5112 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 5113 } 5114 SDValue Op1 = getValue(I.getArgOperand(0)); 5115 SDValue Op2 = getValue(I.getArgOperand(1)); 5116 5117 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5118 setValue(&I, DAG.getNode(Op, dl, VTs, Op1, Op2)); 5119 return 0; 5120 } 5121 case Intrinsic::prefetch: { 5122 SDValue Ops[5]; 5123 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5124 Ops[0] = getRoot(); 5125 Ops[1] = getValue(I.getArgOperand(0)); 5126 Ops[2] = getValue(I.getArgOperand(1)); 5127 Ops[3] = getValue(I.getArgOperand(2)); 5128 Ops[4] = getValue(I.getArgOperand(3)); 5129 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5130 DAG.getVTList(MVT::Other), 5131 &Ops[0], 5, 5132 EVT::getIntegerVT(*Context, 8), 5133 MachinePointerInfo(I.getArgOperand(0)), 5134 0, /* align */ 5135 false, /* volatile */ 5136 rw==0, /* read */ 5137 rw==1)); /* write */ 5138 return 0; 5139 } 5140 case Intrinsic::lifetime_start: 5141 case Intrinsic::lifetime_end: { 5142 bool IsStart = (Intrinsic == Intrinsic::lifetime_start); 5143 // Stack coloring is not enabled in O0, discard region information. 5144 if (TM.getOptLevel() == CodeGenOpt::None) 5145 return 0; 5146 5147 SmallVector<Value *, 4> Allocas; 5148 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD); 5149 5150 for (SmallVector<Value*, 4>::iterator Object = Allocas.begin(), 5151 E = Allocas.end(); Object != E; ++Object) { 5152 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object); 5153 5154 // Could not find an Alloca. 5155 if (!LifetimeObject) 5156 continue; 5157 5158 int FI = FuncInfo.StaticAllocaMap[LifetimeObject]; 5159 5160 SDValue Ops[2]; 5161 Ops[0] = getRoot(); 5162 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true); 5163 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END); 5164 5165 Res = DAG.getNode(Opcode, dl, MVT::Other, Ops, 2); 5166 DAG.setRoot(Res); 5167 } 5168 } 5169 case Intrinsic::invariant_start: 5170 // Discard region information. 5171 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5172 return 0; 5173 case Intrinsic::invariant_end: 5174 // Discard region information. 5175 return 0; 5176 case Intrinsic::donothing: 5177 // ignore 5178 return 0; 5179 } 5180} 5181 5182void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5183 bool isTailCall, 5184 MachineBasicBlock *LandingPad) { 5185 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5186 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5187 Type *RetTy = FTy->getReturnType(); 5188 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5189 MCSymbol *BeginLabel = 0; 5190 5191 TargetLowering::ArgListTy Args; 5192 TargetLowering::ArgListEntry Entry; 5193 Args.reserve(CS.arg_size()); 5194 5195 // Check whether the function can return without sret-demotion. 5196 SmallVector<ISD::OutputArg, 4> Outs; 5197 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5198 Outs, TLI); 5199 5200 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5201 DAG.getMachineFunction(), 5202 FTy->isVarArg(), Outs, 5203 FTy->getContext()); 5204 5205 SDValue DemoteStackSlot; 5206 int DemoteStackIdx = -100; 5207 5208 if (!CanLowerReturn) { 5209 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize( 5210 FTy->getReturnType()); 5211 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment( 5212 FTy->getReturnType()); 5213 MachineFunction &MF = DAG.getMachineFunction(); 5214 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5215 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5216 5217 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5218 Entry.Node = DemoteStackSlot; 5219 Entry.Ty = StackSlotPtrType; 5220 Entry.isSExt = false; 5221 Entry.isZExt = false; 5222 Entry.isInReg = false; 5223 Entry.isSRet = true; 5224 Entry.isNest = false; 5225 Entry.isByVal = false; 5226 Entry.Alignment = Align; 5227 Args.push_back(Entry); 5228 RetTy = Type::getVoidTy(FTy->getContext()); 5229 } 5230 5231 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5232 i != e; ++i) { 5233 const Value *V = *i; 5234 5235 // Skip empty types 5236 if (V->getType()->isEmptyTy()) 5237 continue; 5238 5239 SDValue ArgNode = getValue(V); 5240 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5241 5242 unsigned attrInd = i - CS.arg_begin() + 1; 5243 Entry.isSExt = CS.paramHasAttr(attrInd, Attributes::SExt); 5244 Entry.isZExt = CS.paramHasAttr(attrInd, Attributes::ZExt); 5245 Entry.isInReg = CS.paramHasAttr(attrInd, Attributes::InReg); 5246 Entry.isSRet = CS.paramHasAttr(attrInd, Attributes::StructRet); 5247 Entry.isNest = CS.paramHasAttr(attrInd, Attributes::Nest); 5248 Entry.isByVal = CS.paramHasAttr(attrInd, Attributes::ByVal); 5249 Entry.Alignment = CS.getParamAlignment(attrInd); 5250 Args.push_back(Entry); 5251 } 5252 5253 if (LandingPad) { 5254 // Insert a label before the invoke call to mark the try range. This can be 5255 // used to detect deletion of the invoke via the MachineModuleInfo. 5256 BeginLabel = MMI.getContext().CreateTempSymbol(); 5257 5258 // For SjLj, keep track of which landing pads go with which invokes 5259 // so as to maintain the ordering of pads in the LSDA. 5260 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5261 if (CallSiteIndex) { 5262 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5263 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5264 5265 // Now that the call site is handled, stop tracking it. 5266 MMI.setCurrentCallSite(0); 5267 } 5268 5269 // Both PendingLoads and PendingExports must be flushed here; 5270 // this call might not return. 5271 (void)getRoot(); 5272 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5273 } 5274 5275 // Check if target-independent constraints permit a tail call here. 5276 // Target-dependent constraints are checked within TLI.LowerCallTo. 5277 if (isTailCall && 5278 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5279 isTailCall = false; 5280 5281 TargetLowering:: 5282 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, 5283 getCurDebugLoc(), CS); 5284 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI); 5285 assert((isTailCall || Result.second.getNode()) && 5286 "Non-null chain expected with non-tail call!"); 5287 assert((Result.second.getNode() || !Result.first.getNode()) && 5288 "Null value expected with tail call!"); 5289 if (Result.first.getNode()) { 5290 setValue(CS.getInstruction(), Result.first); 5291 } else if (!CanLowerReturn && Result.second.getNode()) { 5292 // The instruction result is the result of loading from the 5293 // hidden sret parameter. 5294 SmallVector<EVT, 1> PVTs; 5295 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5296 5297 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5298 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5299 EVT PtrVT = PVTs[0]; 5300 5301 SmallVector<EVT, 4> RetTys; 5302 SmallVector<uint64_t, 4> Offsets; 5303 RetTy = FTy->getReturnType(); 5304 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets); 5305 5306 unsigned NumValues = RetTys.size(); 5307 SmallVector<SDValue, 4> Values(NumValues); 5308 SmallVector<SDValue, 4> Chains(NumValues); 5309 5310 for (unsigned i = 0; i < NumValues; ++i) { 5311 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5312 DemoteStackSlot, 5313 DAG.getConstant(Offsets[i], PtrVT)); 5314 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add, 5315 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5316 false, false, false, 1); 5317 Values[i] = L; 5318 Chains[i] = L.getValue(1); 5319 } 5320 5321 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5322 MVT::Other, &Chains[0], NumValues); 5323 PendingLoads.push_back(Chain); 5324 5325 setValue(CS.getInstruction(), 5326 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5327 DAG.getVTList(&RetTys[0], RetTys.size()), 5328 &Values[0], Values.size())); 5329 } 5330 5331 // Assign order to nodes here. If the call does not produce a result, it won't 5332 // be mapped to a SDNode and visit() will not assign it an order number. 5333 if (!Result.second.getNode()) { 5334 // As a special case, a null chain means that a tail call has been emitted and 5335 // the DAG root is already updated. 5336 HasTailCall = true; 5337 ++SDNodeOrder; 5338 AssignOrderingToNode(DAG.getRoot().getNode()); 5339 } else { 5340 DAG.setRoot(Result.second); 5341 ++SDNodeOrder; 5342 AssignOrderingToNode(Result.second.getNode()); 5343 } 5344 5345 if (LandingPad) { 5346 // Insert a label at the end of the invoke call to mark the try range. This 5347 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5348 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5349 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5350 5351 // Inform MachineModuleInfo of range. 5352 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5353 } 5354} 5355 5356/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5357/// value is equal or not-equal to zero. 5358static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5359 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5360 UI != E; ++UI) { 5361 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5362 if (IC->isEquality()) 5363 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5364 if (C->isNullValue()) 5365 continue; 5366 // Unknown instruction. 5367 return false; 5368 } 5369 return true; 5370} 5371 5372static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5373 Type *LoadTy, 5374 SelectionDAGBuilder &Builder) { 5375 5376 // Check to see if this load can be trivially constant folded, e.g. if the 5377 // input is from a string literal. 5378 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5379 // Cast pointer to the type we really want to load. 5380 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5381 PointerType::getUnqual(LoadTy)); 5382 5383 if (const Constant *LoadCst = 5384 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5385 Builder.TD)) 5386 return Builder.getValue(LoadCst); 5387 } 5388 5389 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5390 // still constant memory, the input chain can be the entry node. 5391 SDValue Root; 5392 bool ConstantMemory = false; 5393 5394 // Do not serialize (non-volatile) loads of constant memory with anything. 5395 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5396 Root = Builder.DAG.getEntryNode(); 5397 ConstantMemory = true; 5398 } else { 5399 // Do not serialize non-volatile loads against each other. 5400 Root = Builder.DAG.getRoot(); 5401 } 5402 5403 SDValue Ptr = Builder.getValue(PtrVal); 5404 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5405 Ptr, MachinePointerInfo(PtrVal), 5406 false /*volatile*/, 5407 false /*nontemporal*/, 5408 false /*isinvariant*/, 1 /* align=1 */); 5409 5410 if (!ConstantMemory) 5411 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5412 return LoadVal; 5413} 5414 5415 5416/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5417/// If so, return true and lower it, otherwise return false and it will be 5418/// lowered like a normal call. 5419bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5420 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5421 if (I.getNumArgOperands() != 3) 5422 return false; 5423 5424 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5425 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5426 !I.getArgOperand(2)->getType()->isIntegerTy() || 5427 !I.getType()->isIntegerTy()) 5428 return false; 5429 5430 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5431 5432 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5433 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5434 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5435 bool ActuallyDoIt = true; 5436 MVT LoadVT; 5437 Type *LoadTy; 5438 switch (Size->getZExtValue()) { 5439 default: 5440 LoadVT = MVT::Other; 5441 LoadTy = 0; 5442 ActuallyDoIt = false; 5443 break; 5444 case 2: 5445 LoadVT = MVT::i16; 5446 LoadTy = Type::getInt16Ty(Size->getContext()); 5447 break; 5448 case 4: 5449 LoadVT = MVT::i32; 5450 LoadTy = Type::getInt32Ty(Size->getContext()); 5451 break; 5452 case 8: 5453 LoadVT = MVT::i64; 5454 LoadTy = Type::getInt64Ty(Size->getContext()); 5455 break; 5456 /* 5457 case 16: 5458 LoadVT = MVT::v4i32; 5459 LoadTy = Type::getInt32Ty(Size->getContext()); 5460 LoadTy = VectorType::get(LoadTy, 4); 5461 break; 5462 */ 5463 } 5464 5465 // This turns into unaligned loads. We only do this if the target natively 5466 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5467 // we'll only produce a small number of byte loads. 5468 5469 // Require that we can find a legal MVT, and only do this if the target 5470 // supports unaligned loads of that type. Expanding into byte loads would 5471 // bloat the code. 5472 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5473 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5474 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5475 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5476 ActuallyDoIt = false; 5477 } 5478 5479 if (ActuallyDoIt) { 5480 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5481 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5482 5483 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5484 ISD::SETNE); 5485 EVT CallVT = TLI.getValueType(I.getType(), true); 5486 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5487 return true; 5488 } 5489 } 5490 5491 5492 return false; 5493} 5494 5495/// visitUnaryFloatCall - If a call instruction is a unary floating-point 5496/// operation (as expected), translate it to an SDNode with the specified opcode 5497/// and return true. 5498bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I, 5499 unsigned Opcode) { 5500 // Sanity check that it really is a unary floating-point call. 5501 if (I.getNumArgOperands() != 1 || 5502 !I.getArgOperand(0)->getType()->isFloatingPointTy() || 5503 I.getType() != I.getArgOperand(0)->getType() || 5504 !I.onlyReadsMemory()) 5505 return false; 5506 5507 SDValue Tmp = getValue(I.getArgOperand(0)); 5508 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Tmp.getValueType(), Tmp)); 5509 return true; 5510} 5511 5512void SelectionDAGBuilder::visitCall(const CallInst &I) { 5513 // Handle inline assembly differently. 5514 if (isa<InlineAsm>(I.getCalledValue())) { 5515 visitInlineAsm(&I); 5516 return; 5517 } 5518 5519 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5520 ComputeUsesVAFloatArgument(I, &MMI); 5521 5522 const char *RenameFn = 0; 5523 if (Function *F = I.getCalledFunction()) { 5524 if (F->isDeclaration()) { 5525 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5526 if (unsigned IID = II->getIntrinsicID(F)) { 5527 RenameFn = visitIntrinsicCall(I, IID); 5528 if (!RenameFn) 5529 return; 5530 } 5531 } 5532 if (unsigned IID = F->getIntrinsicID()) { 5533 RenameFn = visitIntrinsicCall(I, IID); 5534 if (!RenameFn) 5535 return; 5536 } 5537 } 5538 5539 // Check for well-known libc/libm calls. If the function is internal, it 5540 // can't be a library call. 5541 LibFunc::Func Func; 5542 if (!F->hasLocalLinkage() && F->hasName() && 5543 LibInfo->getLibFunc(F->getName(), Func) && 5544 LibInfo->hasOptimizedCodeGen(Func)) { 5545 switch (Func) { 5546 default: break; 5547 case LibFunc::copysign: 5548 case LibFunc::copysignf: 5549 case LibFunc::copysignl: 5550 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5551 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5552 I.getType() == I.getArgOperand(0)->getType() && 5553 I.getType() == I.getArgOperand(1)->getType() && 5554 I.onlyReadsMemory()) { 5555 SDValue LHS = getValue(I.getArgOperand(0)); 5556 SDValue RHS = getValue(I.getArgOperand(1)); 5557 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5558 LHS.getValueType(), LHS, RHS)); 5559 return; 5560 } 5561 break; 5562 case LibFunc::fabs: 5563 case LibFunc::fabsf: 5564 case LibFunc::fabsl: 5565 if (visitUnaryFloatCall(I, ISD::FABS)) 5566 return; 5567 break; 5568 case LibFunc::sin: 5569 case LibFunc::sinf: 5570 case LibFunc::sinl: 5571 if (visitUnaryFloatCall(I, ISD::FSIN)) 5572 return; 5573 break; 5574 case LibFunc::cos: 5575 case LibFunc::cosf: 5576 case LibFunc::cosl: 5577 if (visitUnaryFloatCall(I, ISD::FCOS)) 5578 return; 5579 break; 5580 case LibFunc::sqrt: 5581 case LibFunc::sqrtf: 5582 case LibFunc::sqrtl: 5583 if (visitUnaryFloatCall(I, ISD::FSQRT)) 5584 return; 5585 break; 5586 case LibFunc::floor: 5587 case LibFunc::floorf: 5588 case LibFunc::floorl: 5589 if (visitUnaryFloatCall(I, ISD::FFLOOR)) 5590 return; 5591 break; 5592 case LibFunc::nearbyint: 5593 case LibFunc::nearbyintf: 5594 case LibFunc::nearbyintl: 5595 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) 5596 return; 5597 break; 5598 case LibFunc::ceil: 5599 case LibFunc::ceilf: 5600 case LibFunc::ceill: 5601 if (visitUnaryFloatCall(I, ISD::FCEIL)) 5602 return; 5603 break; 5604 case LibFunc::rint: 5605 case LibFunc::rintf: 5606 case LibFunc::rintl: 5607 if (visitUnaryFloatCall(I, ISD::FRINT)) 5608 return; 5609 break; 5610 case LibFunc::trunc: 5611 case LibFunc::truncf: 5612 case LibFunc::truncl: 5613 if (visitUnaryFloatCall(I, ISD::FTRUNC)) 5614 return; 5615 break; 5616 case LibFunc::log2: 5617 case LibFunc::log2f: 5618 case LibFunc::log2l: 5619 if (visitUnaryFloatCall(I, ISD::FLOG2)) 5620 return; 5621 break; 5622 case LibFunc::exp2: 5623 case LibFunc::exp2f: 5624 case LibFunc::exp2l: 5625 if (visitUnaryFloatCall(I, ISD::FEXP2)) 5626 return; 5627 break; 5628 case LibFunc::memcmp: 5629 if (visitMemCmpCall(I)) 5630 return; 5631 break; 5632 } 5633 } 5634 } 5635 5636 SDValue Callee; 5637 if (!RenameFn) 5638 Callee = getValue(I.getCalledValue()); 5639 else 5640 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5641 5642 // Check if we can potentially perform a tail call. More detailed checking is 5643 // be done within LowerCallTo, after more information about the call is known. 5644 LowerCallTo(&I, Callee, I.isTailCall()); 5645} 5646 5647namespace { 5648 5649/// AsmOperandInfo - This contains information for each constraint that we are 5650/// lowering. 5651class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5652public: 5653 /// CallOperand - If this is the result output operand or a clobber 5654 /// this is null, otherwise it is the incoming operand to the CallInst. 5655 /// This gets modified as the asm is processed. 5656 SDValue CallOperand; 5657 5658 /// AssignedRegs - If this is a register or register class operand, this 5659 /// contains the set of register corresponding to the operand. 5660 RegsForValue AssignedRegs; 5661 5662 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5663 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5664 } 5665 5666 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5667 /// corresponds to. If there is no Value* for this operand, it returns 5668 /// MVT::Other. 5669 EVT getCallOperandValEVT(LLVMContext &Context, 5670 const TargetLowering &TLI, 5671 const DataLayout *TD) const { 5672 if (CallOperandVal == 0) return MVT::Other; 5673 5674 if (isa<BasicBlock>(CallOperandVal)) 5675 return TLI.getPointerTy(); 5676 5677 llvm::Type *OpTy = CallOperandVal->getType(); 5678 5679 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5680 // If this is an indirect operand, the operand is a pointer to the 5681 // accessed type. 5682 if (isIndirect) { 5683 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5684 if (!PtrTy) 5685 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5686 OpTy = PtrTy->getElementType(); 5687 } 5688 5689 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5690 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5691 if (STy->getNumElements() == 1) 5692 OpTy = STy->getElementType(0); 5693 5694 // If OpTy is not a single value, it may be a struct/union that we 5695 // can tile with integers. 5696 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5697 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5698 switch (BitSize) { 5699 default: break; 5700 case 1: 5701 case 8: 5702 case 16: 5703 case 32: 5704 case 64: 5705 case 128: 5706 OpTy = IntegerType::get(Context, BitSize); 5707 break; 5708 } 5709 } 5710 5711 return TLI.getValueType(OpTy, true); 5712 } 5713}; 5714 5715typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5716 5717} // end anonymous namespace 5718 5719/// GetRegistersForValue - Assign registers (virtual or physical) for the 5720/// specified operand. We prefer to assign virtual registers, to allow the 5721/// register allocator to handle the assignment process. However, if the asm 5722/// uses features that we can't model on machineinstrs, we have SDISel do the 5723/// allocation. This produces generally horrible, but correct, code. 5724/// 5725/// OpInfo describes the operand. 5726/// 5727static void GetRegistersForValue(SelectionDAG &DAG, 5728 const TargetLowering &TLI, 5729 DebugLoc DL, 5730 SDISelAsmOperandInfo &OpInfo) { 5731 LLVMContext &Context = *DAG.getContext(); 5732 5733 MachineFunction &MF = DAG.getMachineFunction(); 5734 SmallVector<unsigned, 4> Regs; 5735 5736 // If this is a constraint for a single physreg, or a constraint for a 5737 // register class, find it. 5738 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5739 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5740 OpInfo.ConstraintVT); 5741 5742 unsigned NumRegs = 1; 5743 if (OpInfo.ConstraintVT != MVT::Other) { 5744 // If this is a FP input in an integer register (or visa versa) insert a bit 5745 // cast of the input value. More generally, handle any case where the input 5746 // value disagrees with the register class we plan to stick this in. 5747 if (OpInfo.Type == InlineAsm::isInput && 5748 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5749 // Try to convert to the first EVT that the reg class contains. If the 5750 // types are identical size, use a bitcast to convert (e.g. two differing 5751 // vector types). 5752 EVT RegVT = *PhysReg.second->vt_begin(); 5753 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5754 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5755 RegVT, OpInfo.CallOperand); 5756 OpInfo.ConstraintVT = RegVT; 5757 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5758 // If the input is a FP value and we want it in FP registers, do a 5759 // bitcast to the corresponding integer type. This turns an f64 value 5760 // into i64, which can be passed with two i32 values on a 32-bit 5761 // machine. 5762 RegVT = EVT::getIntegerVT(Context, 5763 OpInfo.ConstraintVT.getSizeInBits()); 5764 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5765 RegVT, OpInfo.CallOperand); 5766 OpInfo.ConstraintVT = RegVT; 5767 } 5768 } 5769 5770 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5771 } 5772 5773 EVT RegVT; 5774 EVT ValueVT = OpInfo.ConstraintVT; 5775 5776 // If this is a constraint for a specific physical register, like {r17}, 5777 // assign it now. 5778 if (unsigned AssignedReg = PhysReg.first) { 5779 const TargetRegisterClass *RC = PhysReg.second; 5780 if (OpInfo.ConstraintVT == MVT::Other) 5781 ValueVT = *RC->vt_begin(); 5782 5783 // Get the actual register value type. This is important, because the user 5784 // may have asked for (e.g.) the AX register in i32 type. We need to 5785 // remember that AX is actually i16 to get the right extension. 5786 RegVT = *RC->vt_begin(); 5787 5788 // This is a explicit reference to a physical register. 5789 Regs.push_back(AssignedReg); 5790 5791 // If this is an expanded reference, add the rest of the regs to Regs. 5792 if (NumRegs != 1) { 5793 TargetRegisterClass::iterator I = RC->begin(); 5794 for (; *I != AssignedReg; ++I) 5795 assert(I != RC->end() && "Didn't find reg!"); 5796 5797 // Already added the first reg. 5798 --NumRegs; ++I; 5799 for (; NumRegs; --NumRegs, ++I) { 5800 assert(I != RC->end() && "Ran out of registers to allocate!"); 5801 Regs.push_back(*I); 5802 } 5803 } 5804 5805 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5806 return; 5807 } 5808 5809 // Otherwise, if this was a reference to an LLVM register class, create vregs 5810 // for this reference. 5811 if (const TargetRegisterClass *RC = PhysReg.second) { 5812 RegVT = *RC->vt_begin(); 5813 if (OpInfo.ConstraintVT == MVT::Other) 5814 ValueVT = RegVT; 5815 5816 // Create the appropriate number of virtual registers. 5817 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5818 for (; NumRegs; --NumRegs) 5819 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5820 5821 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5822 return; 5823 } 5824 5825 // Otherwise, we couldn't allocate enough registers for this. 5826} 5827 5828/// visitInlineAsm - Handle a call to an InlineAsm object. 5829/// 5830void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5831 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5832 5833 /// ConstraintOperands - Information about all of the constraints. 5834 SDISelAsmOperandInfoVector ConstraintOperands; 5835 5836 TargetLowering::AsmOperandInfoVector 5837 TargetConstraints = TLI.ParseConstraints(CS); 5838 5839 bool hasMemory = false; 5840 5841 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5842 unsigned ResNo = 0; // ResNo - The result number of the next output. 5843 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5844 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5845 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5846 5847 EVT OpVT = MVT::Other; 5848 5849 // Compute the value type for each operand. 5850 switch (OpInfo.Type) { 5851 case InlineAsm::isOutput: 5852 // Indirect outputs just consume an argument. 5853 if (OpInfo.isIndirect) { 5854 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5855 break; 5856 } 5857 5858 // The return value of the call is this value. As such, there is no 5859 // corresponding argument. 5860 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5861 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5862 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5863 } else { 5864 assert(ResNo == 0 && "Asm only has one result!"); 5865 OpVT = TLI.getValueType(CS.getType()); 5866 } 5867 ++ResNo; 5868 break; 5869 case InlineAsm::isInput: 5870 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5871 break; 5872 case InlineAsm::isClobber: 5873 // Nothing to do. 5874 break; 5875 } 5876 5877 // If this is an input or an indirect output, process the call argument. 5878 // BasicBlocks are labels, currently appearing only in asm's. 5879 if (OpInfo.CallOperandVal) { 5880 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5881 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5882 } else { 5883 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5884 } 5885 5886 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5887 } 5888 5889 OpInfo.ConstraintVT = OpVT; 5890 5891 // Indirect operand accesses access memory. 5892 if (OpInfo.isIndirect) 5893 hasMemory = true; 5894 else { 5895 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5896 TargetLowering::ConstraintType 5897 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5898 if (CType == TargetLowering::C_Memory) { 5899 hasMemory = true; 5900 break; 5901 } 5902 } 5903 } 5904 } 5905 5906 SDValue Chain, Flag; 5907 5908 // We won't need to flush pending loads if this asm doesn't touch 5909 // memory and is nonvolatile. 5910 if (hasMemory || IA->hasSideEffects()) 5911 Chain = getRoot(); 5912 else 5913 Chain = DAG.getRoot(); 5914 5915 // Second pass over the constraints: compute which constraint option to use 5916 // and assign registers to constraints that want a specific physreg. 5917 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5918 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5919 5920 // If this is an output operand with a matching input operand, look up the 5921 // matching input. If their types mismatch, e.g. one is an integer, the 5922 // other is floating point, or their sizes are different, flag it as an 5923 // error. 5924 if (OpInfo.hasMatchingInput()) { 5925 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5926 5927 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5928 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5929 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5930 OpInfo.ConstraintVT); 5931 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5932 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5933 Input.ConstraintVT); 5934 if ((OpInfo.ConstraintVT.isInteger() != 5935 Input.ConstraintVT.isInteger()) || 5936 (MatchRC.second != InputRC.second)) { 5937 report_fatal_error("Unsupported asm: input constraint" 5938 " with a matching output constraint of" 5939 " incompatible type!"); 5940 } 5941 Input.ConstraintVT = OpInfo.ConstraintVT; 5942 } 5943 } 5944 5945 // Compute the constraint code and ConstraintType to use. 5946 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5947 5948 // If this is a memory input, and if the operand is not indirect, do what we 5949 // need to to provide an address for the memory input. 5950 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5951 !OpInfo.isIndirect) { 5952 assert((OpInfo.isMultipleAlternative || 5953 (OpInfo.Type == InlineAsm::isInput)) && 5954 "Can only indirectify direct input operands!"); 5955 5956 // Memory operands really want the address of the value. If we don't have 5957 // an indirect input, put it in the constpool if we can, otherwise spill 5958 // it to a stack slot. 5959 // TODO: This isn't quite right. We need to handle these according to 5960 // the addressing mode that the constraint wants. Also, this may take 5961 // an additional register for the computation and we don't want that 5962 // either. 5963 5964 // If the operand is a float, integer, or vector constant, spill to a 5965 // constant pool entry to get its address. 5966 const Value *OpVal = OpInfo.CallOperandVal; 5967 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5968 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 5969 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5970 TLI.getPointerTy()); 5971 } else { 5972 // Otherwise, create a stack slot and emit a store to it before the 5973 // asm. 5974 Type *Ty = OpVal->getType(); 5975 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty); 5976 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty); 5977 MachineFunction &MF = DAG.getMachineFunction(); 5978 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5979 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5980 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5981 OpInfo.CallOperand, StackSlot, 5982 MachinePointerInfo::getFixedStack(SSFI), 5983 false, false, 0); 5984 OpInfo.CallOperand = StackSlot; 5985 } 5986 5987 // There is no longer a Value* corresponding to this operand. 5988 OpInfo.CallOperandVal = 0; 5989 5990 // It is now an indirect operand. 5991 OpInfo.isIndirect = true; 5992 } 5993 5994 // If this constraint is for a specific register, allocate it before 5995 // anything else. 5996 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5997 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 5998 } 5999 6000 // Second pass - Loop over all of the operands, assigning virtual or physregs 6001 // to register class operands. 6002 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6003 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6004 6005 // C_Register operands have already been allocated, Other/Memory don't need 6006 // to be. 6007 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6008 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo); 6009 } 6010 6011 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6012 std::vector<SDValue> AsmNodeOperands; 6013 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6014 AsmNodeOperands.push_back( 6015 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6016 TLI.getPointerTy())); 6017 6018 // If we have a !srcloc metadata node associated with it, we want to attach 6019 // this to the ultimately generated inline asm machineinstr. To do this, we 6020 // pass in the third operand as this (potentially null) inline asm MDNode. 6021 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6022 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6023 6024 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore 6025 // bits as operand 3. 6026 unsigned ExtraInfo = 0; 6027 if (IA->hasSideEffects()) 6028 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6029 if (IA->isAlignStack()) 6030 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6031 // Set the asm dialect. 6032 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect; 6033 6034 // Determine if this InlineAsm MayLoad or MayStore based on the constraints. 6035 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 6036 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; 6037 6038 // Compute the constraint code and ConstraintType to use. 6039 TLI.ComputeConstraintToUse(OpInfo, SDValue()); 6040 6041 // Ideally, we would only check against memory constraints. However, the 6042 // meaning of an other constraint can be target-specific and we can't easily 6043 // reason about it. Therefore, be conservative and set MayLoad/MayStore 6044 // for other constriants as well. 6045 if (OpInfo.ConstraintType == TargetLowering::C_Memory || 6046 OpInfo.ConstraintType == TargetLowering::C_Other) { 6047 if (OpInfo.Type == InlineAsm::isInput) 6048 ExtraInfo |= InlineAsm::Extra_MayLoad; 6049 else if (OpInfo.Type == InlineAsm::isOutput) 6050 ExtraInfo |= InlineAsm::Extra_MayStore; 6051 } 6052 } 6053 6054 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6055 TLI.getPointerTy())); 6056 6057 // Loop over all of the inputs, copying the operand values into the 6058 // appropriate registers and processing the output regs. 6059 RegsForValue RetValRegs; 6060 6061 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6062 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6063 6064 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6065 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6066 6067 switch (OpInfo.Type) { 6068 case InlineAsm::isOutput: { 6069 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6070 OpInfo.ConstraintType != TargetLowering::C_Register) { 6071 // Memory output, or 'other' output (e.g. 'X' constraint). 6072 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6073 6074 // Add information to the INLINEASM node to know about this output. 6075 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6076 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6077 TLI.getPointerTy())); 6078 AsmNodeOperands.push_back(OpInfo.CallOperand); 6079 break; 6080 } 6081 6082 // Otherwise, this is a register or register class output. 6083 6084 // Copy the output from the appropriate register. Find a register that 6085 // we can use. 6086 if (OpInfo.AssignedRegs.Regs.empty()) { 6087 LLVMContext &Ctx = *DAG.getContext(); 6088 Ctx.emitError(CS.getInstruction(), 6089 "couldn't allocate output register for constraint '" + 6090 Twine(OpInfo.ConstraintCode) + "'"); 6091 break; 6092 } 6093 6094 // If this is an indirect operand, store through the pointer after the 6095 // asm. 6096 if (OpInfo.isIndirect) { 6097 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6098 OpInfo.CallOperandVal)); 6099 } else { 6100 // This is the result value of the call. 6101 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6102 // Concatenate this output onto the outputs list. 6103 RetValRegs.append(OpInfo.AssignedRegs); 6104 } 6105 6106 // Add information to the INLINEASM node to know that this register is 6107 // set. 6108 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6109 InlineAsm::Kind_RegDefEarlyClobber : 6110 InlineAsm::Kind_RegDef, 6111 false, 6112 0, 6113 DAG, 6114 AsmNodeOperands); 6115 break; 6116 } 6117 case InlineAsm::isInput: { 6118 SDValue InOperandVal = OpInfo.CallOperand; 6119 6120 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6121 // If this is required to match an output register we have already set, 6122 // just use its register. 6123 unsigned OperandNo = OpInfo.getMatchedOperand(); 6124 6125 // Scan until we find the definition we already emitted of this operand. 6126 // When we find it, create a RegsForValue operand. 6127 unsigned CurOp = InlineAsm::Op_FirstOperand; 6128 for (; OperandNo; --OperandNo) { 6129 // Advance to the next operand. 6130 unsigned OpFlag = 6131 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6132 assert((InlineAsm::isRegDefKind(OpFlag) || 6133 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6134 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6135 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6136 } 6137 6138 unsigned OpFlag = 6139 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6140 if (InlineAsm::isRegDefKind(OpFlag) || 6141 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6142 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6143 if (OpInfo.isIndirect) { 6144 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6145 LLVMContext &Ctx = *DAG.getContext(); 6146 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6147 " don't know how to handle tied " 6148 "indirect register inputs"); 6149 } 6150 6151 RegsForValue MatchedRegs; 6152 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6153 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); 6154 MatchedRegs.RegVTs.push_back(RegVT); 6155 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6156 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6157 i != e; ++i) 6158 MatchedRegs.Regs.push_back 6159 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6160 6161 // Use the produced MatchedRegs object to 6162 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6163 Chain, &Flag, CS.getInstruction()); 6164 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6165 true, OpInfo.getMatchedOperand(), 6166 DAG, AsmNodeOperands); 6167 break; 6168 } 6169 6170 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6171 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6172 "Unexpected number of operands"); 6173 // Add information to the INLINEASM node to know about this input. 6174 // See InlineAsm.h isUseOperandTiedToDef. 6175 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6176 OpInfo.getMatchedOperand()); 6177 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6178 TLI.getPointerTy())); 6179 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6180 break; 6181 } 6182 6183 // Treat indirect 'X' constraint as memory. 6184 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6185 OpInfo.isIndirect) 6186 OpInfo.ConstraintType = TargetLowering::C_Memory; 6187 6188 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6189 std::vector<SDValue> Ops; 6190 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6191 Ops, DAG); 6192 if (Ops.empty()) { 6193 LLVMContext &Ctx = *DAG.getContext(); 6194 Ctx.emitError(CS.getInstruction(), 6195 "invalid operand for inline asm constraint '" + 6196 Twine(OpInfo.ConstraintCode) + "'"); 6197 break; 6198 } 6199 6200 // Add information to the INLINEASM node to know about this input. 6201 unsigned ResOpType = 6202 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6203 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6204 TLI.getPointerTy())); 6205 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6206 break; 6207 } 6208 6209 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6210 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6211 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6212 "Memory operands expect pointer values"); 6213 6214 // Add information to the INLINEASM node to know about this input. 6215 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6216 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6217 TLI.getPointerTy())); 6218 AsmNodeOperands.push_back(InOperandVal); 6219 break; 6220 } 6221 6222 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6223 OpInfo.ConstraintType == TargetLowering::C_Register) && 6224 "Unknown constraint type!"); 6225 6226 // TODO: Support this. 6227 if (OpInfo.isIndirect) { 6228 LLVMContext &Ctx = *DAG.getContext(); 6229 Ctx.emitError(CS.getInstruction(), 6230 "Don't know how to handle indirect register inputs yet " 6231 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'"); 6232 break; 6233 } 6234 6235 // Copy the input into the appropriate registers. 6236 if (OpInfo.AssignedRegs.Regs.empty()) { 6237 LLVMContext &Ctx = *DAG.getContext(); 6238 Ctx.emitError(CS.getInstruction(), 6239 "couldn't allocate input reg for constraint '" + 6240 Twine(OpInfo.ConstraintCode) + "'"); 6241 break; 6242 } 6243 6244 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6245 Chain, &Flag, CS.getInstruction()); 6246 6247 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6248 DAG, AsmNodeOperands); 6249 break; 6250 } 6251 case InlineAsm::isClobber: { 6252 // Add the clobbered value to the operand list, so that the register 6253 // allocator is aware that the physreg got clobbered. 6254 if (!OpInfo.AssignedRegs.Regs.empty()) 6255 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6256 false, 0, DAG, 6257 AsmNodeOperands); 6258 break; 6259 } 6260 } 6261 } 6262 6263 // Finish up input operands. Set the input chain and add the flag last. 6264 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6265 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6266 6267 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6268 DAG.getVTList(MVT::Other, MVT::Glue), 6269 &AsmNodeOperands[0], AsmNodeOperands.size()); 6270 Flag = Chain.getValue(1); 6271 6272 // If this asm returns a register value, copy the result from that register 6273 // and set it as the value of the call. 6274 if (!RetValRegs.Regs.empty()) { 6275 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6276 Chain, &Flag, CS.getInstruction()); 6277 6278 // FIXME: Why don't we do this for inline asms with MRVs? 6279 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6280 EVT ResultType = TLI.getValueType(CS.getType()); 6281 6282 // If any of the results of the inline asm is a vector, it may have the 6283 // wrong width/num elts. This can happen for register classes that can 6284 // contain multiple different value types. The preg or vreg allocated may 6285 // not have the same VT as was expected. Convert it to the right type 6286 // with bit_convert. 6287 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6288 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6289 ResultType, Val); 6290 6291 } else if (ResultType != Val.getValueType() && 6292 ResultType.isInteger() && Val.getValueType().isInteger()) { 6293 // If a result value was tied to an input value, the computed result may 6294 // have a wider width than the expected result. Extract the relevant 6295 // portion. 6296 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6297 } 6298 6299 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6300 } 6301 6302 setValue(CS.getInstruction(), Val); 6303 // Don't need to use this as a chain in this case. 6304 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6305 return; 6306 } 6307 6308 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6309 6310 // Process indirect outputs, first output all of the flagged copies out of 6311 // physregs. 6312 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6313 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6314 const Value *Ptr = IndirectStoresToEmit[i].second; 6315 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6316 Chain, &Flag, IA); 6317 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6318 } 6319 6320 // Emit the non-flagged stores from the physregs. 6321 SmallVector<SDValue, 8> OutChains; 6322 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6323 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6324 StoresToEmit[i].first, 6325 getValue(StoresToEmit[i].second), 6326 MachinePointerInfo(StoresToEmit[i].second), 6327 false, false, 0); 6328 OutChains.push_back(Val); 6329 } 6330 6331 if (!OutChains.empty()) 6332 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6333 &OutChains[0], OutChains.size()); 6334 6335 DAG.setRoot(Chain); 6336} 6337 6338void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6339 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6340 MVT::Other, getRoot(), 6341 getValue(I.getArgOperand(0)), 6342 DAG.getSrcValue(I.getArgOperand(0)))); 6343} 6344 6345void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6346 const DataLayout &TD = *TLI.getDataLayout(); 6347 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6348 getRoot(), getValue(I.getOperand(0)), 6349 DAG.getSrcValue(I.getOperand(0)), 6350 TD.getABITypeAlignment(I.getType())); 6351 setValue(&I, V); 6352 DAG.setRoot(V.getValue(1)); 6353} 6354 6355void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6356 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6357 MVT::Other, getRoot(), 6358 getValue(I.getArgOperand(0)), 6359 DAG.getSrcValue(I.getArgOperand(0)))); 6360} 6361 6362void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6363 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6364 MVT::Other, getRoot(), 6365 getValue(I.getArgOperand(0)), 6366 getValue(I.getArgOperand(1)), 6367 DAG.getSrcValue(I.getArgOperand(0)), 6368 DAG.getSrcValue(I.getArgOperand(1)))); 6369} 6370 6371/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6372/// implementation, which just calls LowerCall. 6373/// FIXME: When all targets are 6374/// migrated to using LowerCall, this hook should be integrated into SDISel. 6375std::pair<SDValue, SDValue> 6376TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { 6377 // Handle all of the outgoing arguments. 6378 CLI.Outs.clear(); 6379 CLI.OutVals.clear(); 6380 ArgListTy &Args = CLI.Args; 6381 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6382 SmallVector<EVT, 4> ValueVTs; 6383 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6384 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6385 Value != NumValues; ++Value) { 6386 EVT VT = ValueVTs[Value]; 6387 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); 6388 SDValue Op = SDValue(Args[i].Node.getNode(), 6389 Args[i].Node.getResNo() + Value); 6390 ISD::ArgFlagsTy Flags; 6391 unsigned OriginalAlignment = 6392 getDataLayout()->getABITypeAlignment(ArgTy); 6393 6394 if (Args[i].isZExt) 6395 Flags.setZExt(); 6396 if (Args[i].isSExt) 6397 Flags.setSExt(); 6398 if (Args[i].isInReg) 6399 Flags.setInReg(); 6400 if (Args[i].isSRet) 6401 Flags.setSRet(); 6402 if (Args[i].isByVal) { 6403 Flags.setByVal(); 6404 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6405 Type *ElementTy = Ty->getElementType(); 6406 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy)); 6407 // For ByVal, alignment should come from FE. BE will guess if this 6408 // info is not there but there are cases it cannot get right. 6409 unsigned FrameAlign; 6410 if (Args[i].Alignment) 6411 FrameAlign = Args[i].Alignment; 6412 else 6413 FrameAlign = getByValTypeAlignment(ElementTy); 6414 Flags.setByValAlign(FrameAlign); 6415 } 6416 if (Args[i].isNest) 6417 Flags.setNest(); 6418 Flags.setOrigAlign(OriginalAlignment); 6419 6420 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); 6421 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT); 6422 SmallVector<SDValue, 4> Parts(NumParts); 6423 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6424 6425 if (Args[i].isSExt) 6426 ExtendKind = ISD::SIGN_EXTEND; 6427 else if (Args[i].isZExt) 6428 ExtendKind = ISD::ZERO_EXTEND; 6429 6430 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, 6431 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind); 6432 6433 for (unsigned j = 0; j != NumParts; ++j) { 6434 // if it isn't first piece, alignment must be 1 6435 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6436 i < CLI.NumFixedArgs, 6437 i, j*Parts[j].getValueType().getStoreSize()); 6438 if (NumParts > 1 && j == 0) 6439 MyFlags.Flags.setSplit(); 6440 else if (j != 0) 6441 MyFlags.Flags.setOrigAlign(1); 6442 6443 CLI.Outs.push_back(MyFlags); 6444 CLI.OutVals.push_back(Parts[j]); 6445 } 6446 } 6447 } 6448 6449 // Handle the incoming return values from the call. 6450 CLI.Ins.clear(); 6451 SmallVector<EVT, 4> RetTys; 6452 ComputeValueVTs(*this, CLI.RetTy, RetTys); 6453 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6454 EVT VT = RetTys[I]; 6455 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6456 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6457 for (unsigned i = 0; i != NumRegs; ++i) { 6458 ISD::InputArg MyFlags; 6459 MyFlags.VT = RegisterVT; 6460 MyFlags.Used = CLI.IsReturnValueUsed; 6461 if (CLI.RetSExt) 6462 MyFlags.Flags.setSExt(); 6463 if (CLI.RetZExt) 6464 MyFlags.Flags.setZExt(); 6465 if (CLI.IsInReg) 6466 MyFlags.Flags.setInReg(); 6467 CLI.Ins.push_back(MyFlags); 6468 } 6469 } 6470 6471 SmallVector<SDValue, 4> InVals; 6472 CLI.Chain = LowerCall(CLI, InVals); 6473 6474 // Verify that the target's LowerCall behaved as expected. 6475 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && 6476 "LowerCall didn't return a valid chain!"); 6477 assert((!CLI.IsTailCall || InVals.empty()) && 6478 "LowerCall emitted a return value for a tail call!"); 6479 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 6480 "LowerCall didn't emit the correct number of values!"); 6481 6482 // For a tail call, the return value is merely live-out and there aren't 6483 // any nodes in the DAG representing it. Return a special value to 6484 // indicate that a tail call has been emitted and no more Instructions 6485 // should be processed in the current block. 6486 if (CLI.IsTailCall) { 6487 CLI.DAG.setRoot(CLI.Chain); 6488 return std::make_pair(SDValue(), SDValue()); 6489 } 6490 6491 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 6492 assert(InVals[i].getNode() && 6493 "LowerCall emitted a null value!"); 6494 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 6495 "LowerCall emitted a value with the wrong type!"); 6496 }); 6497 6498 // Collect the legal value parts into potentially illegal values 6499 // that correspond to the original function's return values. 6500 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6501 if (CLI.RetSExt) 6502 AssertOp = ISD::AssertSext; 6503 else if (CLI.RetZExt) 6504 AssertOp = ISD::AssertZext; 6505 SmallVector<SDValue, 4> ReturnValues; 6506 unsigned CurReg = 0; 6507 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6508 EVT VT = RetTys[I]; 6509 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6510 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 6511 6512 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], 6513 NumRegs, RegisterVT, VT, NULL, 6514 AssertOp)); 6515 CurReg += NumRegs; 6516 } 6517 6518 // For a function returning void, there is no return value. We can't create 6519 // such a node, so we just return a null return value in that case. In 6520 // that case, nothing will actually look at the value. 6521 if (ReturnValues.empty()) 6522 return std::make_pair(SDValue(), CLI.Chain); 6523 6524 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, 6525 CLI.DAG.getVTList(&RetTys[0], RetTys.size()), 6526 &ReturnValues[0], ReturnValues.size()); 6527 return std::make_pair(Res, CLI.Chain); 6528} 6529 6530void TargetLowering::LowerOperationWrapper(SDNode *N, 6531 SmallVectorImpl<SDValue> &Results, 6532 SelectionDAG &DAG) const { 6533 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6534 if (Res.getNode()) 6535 Results.push_back(Res); 6536} 6537 6538SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6539 llvm_unreachable("LowerOperation not implemented for this target!"); 6540} 6541 6542void 6543SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6544 SDValue Op = getNonRegisterValue(V); 6545 assert((Op.getOpcode() != ISD::CopyFromReg || 6546 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6547 "Copy from a reg to the same reg!"); 6548 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6549 6550 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6551 SDValue Chain = DAG.getEntryNode(); 6552 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0, V); 6553 PendingExports.push_back(Chain); 6554} 6555 6556#include "llvm/CodeGen/SelectionDAGISel.h" 6557 6558/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6559/// entry block, return true. This includes arguments used by switches, since 6560/// the switch may expand into multiple basic blocks. 6561static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6562 // With FastISel active, we may be splitting blocks, so force creation 6563 // of virtual registers for all non-dead arguments. 6564 if (FastISel) 6565 return A->use_empty(); 6566 6567 const BasicBlock *Entry = A->getParent()->begin(); 6568 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6569 UI != E; ++UI) { 6570 const User *U = *UI; 6571 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6572 return false; // Use not in entry block. 6573 } 6574 return true; 6575} 6576 6577void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6578 // If this is the entry block, emit arguments. 6579 const Function &F = *LLVMBB->getParent(); 6580 SelectionDAG &DAG = SDB->DAG; 6581 DebugLoc dl = SDB->getCurDebugLoc(); 6582 const DataLayout *TD = TLI.getDataLayout(); 6583 SmallVector<ISD::InputArg, 16> Ins; 6584 6585 // Check whether the function can return without sret-demotion. 6586 SmallVector<ISD::OutputArg, 4> Outs; 6587 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6588 Outs, TLI); 6589 6590 if (!FuncInfo->CanLowerReturn) { 6591 // Put in an sret pointer parameter before all the other parameters. 6592 SmallVector<EVT, 1> ValueVTs; 6593 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6594 6595 // NOTE: Assuming that a pointer will never break down to more than one VT 6596 // or one register. 6597 ISD::ArgFlagsTy Flags; 6598 Flags.setSRet(); 6599 MVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6600 ISD::InputArg RetArg(Flags, RegisterVT, true, 0, 0); 6601 Ins.push_back(RetArg); 6602 } 6603 6604 // Set up the incoming argument description vector. 6605 unsigned Idx = 1; 6606 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6607 I != E; ++I, ++Idx) { 6608 SmallVector<EVT, 4> ValueVTs; 6609 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6610 bool isArgValueUsed = !I->use_empty(); 6611 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6612 Value != NumValues; ++Value) { 6613 EVT VT = ValueVTs[Value]; 6614 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6615 ISD::ArgFlagsTy Flags; 6616 unsigned OriginalAlignment = 6617 TD->getABITypeAlignment(ArgTy); 6618 6619 if (F.getParamAttributes(Idx).hasAttribute(Attributes::ZExt)) 6620 Flags.setZExt(); 6621 if (F.getParamAttributes(Idx).hasAttribute(Attributes::SExt)) 6622 Flags.setSExt(); 6623 if (F.getParamAttributes(Idx).hasAttribute(Attributes::InReg)) 6624 Flags.setInReg(); 6625 if (F.getParamAttributes(Idx).hasAttribute(Attributes::StructRet)) 6626 Flags.setSRet(); 6627 if (F.getParamAttributes(Idx).hasAttribute(Attributes::ByVal)) { 6628 Flags.setByVal(); 6629 PointerType *Ty = cast<PointerType>(I->getType()); 6630 Type *ElementTy = Ty->getElementType(); 6631 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6632 // For ByVal, alignment should be passed from FE. BE will guess if 6633 // this info is not there but there are cases it cannot get right. 6634 unsigned FrameAlign; 6635 if (F.getParamAlignment(Idx)) 6636 FrameAlign = F.getParamAlignment(Idx); 6637 else 6638 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6639 Flags.setByValAlign(FrameAlign); 6640 } 6641 if (F.getParamAttributes(Idx).hasAttribute(Attributes::Nest)) 6642 Flags.setNest(); 6643 Flags.setOrigAlign(OriginalAlignment); 6644 6645 MVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6646 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6647 for (unsigned i = 0; i != NumRegs; ++i) { 6648 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed, 6649 Idx-1, i*RegisterVT.getStoreSize()); 6650 if (NumRegs > 1 && i == 0) 6651 MyFlags.Flags.setSplit(); 6652 // if it isn't first piece, alignment must be 1 6653 else if (i > 0) 6654 MyFlags.Flags.setOrigAlign(1); 6655 Ins.push_back(MyFlags); 6656 } 6657 } 6658 } 6659 6660 // Call the target to set up the argument values. 6661 SmallVector<SDValue, 8> InVals; 6662 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6663 F.isVarArg(), Ins, 6664 dl, DAG, InVals); 6665 6666 // Verify that the target's LowerFormalArguments behaved as expected. 6667 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6668 "LowerFormalArguments didn't return a valid chain!"); 6669 assert(InVals.size() == Ins.size() && 6670 "LowerFormalArguments didn't emit the correct number of values!"); 6671 DEBUG({ 6672 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6673 assert(InVals[i].getNode() && 6674 "LowerFormalArguments emitted a null value!"); 6675 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6676 "LowerFormalArguments emitted a value with the wrong type!"); 6677 } 6678 }); 6679 6680 // Update the DAG with the new chain value resulting from argument lowering. 6681 DAG.setRoot(NewRoot); 6682 6683 // Set up the argument values. 6684 unsigned i = 0; 6685 Idx = 1; 6686 if (!FuncInfo->CanLowerReturn) { 6687 // Create a virtual register for the sret pointer, and put in a copy 6688 // from the sret argument into it. 6689 SmallVector<EVT, 1> ValueVTs; 6690 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6691 MVT VT = ValueVTs[0].getSimpleVT(); 6692 MVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6693 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6694 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6695 RegVT, VT, NULL, AssertOp); 6696 6697 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6698 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6699 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6700 FuncInfo->DemoteRegister = SRetReg; 6701 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6702 SRetReg, ArgValue); 6703 DAG.setRoot(NewRoot); 6704 6705 // i indexes lowered arguments. Bump it past the hidden sret argument. 6706 // Idx indexes LLVM arguments. Don't touch it. 6707 ++i; 6708 } 6709 6710 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6711 ++I, ++Idx) { 6712 SmallVector<SDValue, 4> ArgValues; 6713 SmallVector<EVT, 4> ValueVTs; 6714 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6715 unsigned NumValues = ValueVTs.size(); 6716 6717 // If this argument is unused then remember its value. It is used to generate 6718 // debugging information. 6719 if (I->use_empty() && NumValues) 6720 SDB->setUnusedArgValue(I, InVals[i]); 6721 6722 for (unsigned Val = 0; Val != NumValues; ++Val) { 6723 EVT VT = ValueVTs[Val]; 6724 MVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6725 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6726 6727 if (!I->use_empty()) { 6728 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6729 if (F.getParamAttributes(Idx).hasAttribute(Attributes::SExt)) 6730 AssertOp = ISD::AssertSext; 6731 else if (F.getParamAttributes(Idx).hasAttribute(Attributes::ZExt)) 6732 AssertOp = ISD::AssertZext; 6733 6734 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6735 NumParts, PartVT, VT, 6736 NULL, AssertOp)); 6737 } 6738 6739 i += NumParts; 6740 } 6741 6742 // We don't need to do anything else for unused arguments. 6743 if (ArgValues.empty()) 6744 continue; 6745 6746 // Note down frame index. 6747 if (FrameIndexSDNode *FI = 6748 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6749 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6750 6751 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6752 SDB->getCurDebugLoc()); 6753 6754 SDB->setValue(I, Res); 6755 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6756 if (LoadSDNode *LNode = 6757 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6758 if (FrameIndexSDNode *FI = 6759 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6760 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6761 } 6762 6763 // If this argument is live outside of the entry block, insert a copy from 6764 // wherever we got it to the vreg that other BB's will reference it as. 6765 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6766 // If we can, though, try to skip creating an unnecessary vreg. 6767 // FIXME: This isn't very clean... it would be nice to make this more 6768 // general. It's also subtly incompatible with the hacks FastISel 6769 // uses with vregs. 6770 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6771 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6772 FuncInfo->ValueMap[I] = Reg; 6773 continue; 6774 } 6775 } 6776 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6777 FuncInfo->InitializeRegForValue(I); 6778 SDB->CopyToExportRegsIfNeeded(I); 6779 } 6780 } 6781 6782 assert(i == InVals.size() && "Argument register count mismatch!"); 6783 6784 // Finally, if the target has anything special to do, allow it to do so. 6785 // FIXME: this should insert code into the DAG! 6786 EmitFunctionEntryCode(); 6787} 6788 6789/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6790/// ensure constants are generated when needed. Remember the virtual registers 6791/// that need to be added to the Machine PHI nodes as input. We cannot just 6792/// directly add them, because expansion might result in multiple MBB's for one 6793/// BB. As such, the start of the BB might correspond to a different MBB than 6794/// the end. 6795/// 6796void 6797SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6798 const TerminatorInst *TI = LLVMBB->getTerminator(); 6799 6800 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6801 6802 // Check successor nodes' PHI nodes that expect a constant to be available 6803 // from this block. 6804 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6805 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6806 if (!isa<PHINode>(SuccBB->begin())) continue; 6807 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6808 6809 // If this terminator has multiple identical successors (common for 6810 // switches), only handle each succ once. 6811 if (!SuccsHandled.insert(SuccMBB)) continue; 6812 6813 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6814 6815 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6816 // nodes and Machine PHI nodes, but the incoming operands have not been 6817 // emitted yet. 6818 for (BasicBlock::const_iterator I = SuccBB->begin(); 6819 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6820 // Ignore dead phi's. 6821 if (PN->use_empty()) continue; 6822 6823 // Skip empty types 6824 if (PN->getType()->isEmptyTy()) 6825 continue; 6826 6827 unsigned Reg; 6828 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6829 6830 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6831 unsigned &RegOut = ConstantsOut[C]; 6832 if (RegOut == 0) { 6833 RegOut = FuncInfo.CreateRegs(C->getType()); 6834 CopyValueToVirtualRegister(C, RegOut); 6835 } 6836 Reg = RegOut; 6837 } else { 6838 DenseMap<const Value *, unsigned>::iterator I = 6839 FuncInfo.ValueMap.find(PHIOp); 6840 if (I != FuncInfo.ValueMap.end()) 6841 Reg = I->second; 6842 else { 6843 assert(isa<AllocaInst>(PHIOp) && 6844 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6845 "Didn't codegen value into a register!??"); 6846 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6847 CopyValueToVirtualRegister(PHIOp, Reg); 6848 } 6849 } 6850 6851 // Remember that this register needs to added to the machine PHI node as 6852 // the input for this MBB. 6853 SmallVector<EVT, 4> ValueVTs; 6854 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6855 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6856 EVT VT = ValueVTs[vti]; 6857 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6858 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6859 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6860 Reg += NumRegisters; 6861 } 6862 } 6863 } 6864 ConstantsOut.clear(); 6865} 6866