SelectionDAGBuilder.cpp revision 55ba816883842e793cdeb32fcb805c4e011b527f
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getIntPtrConstant(1)); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209 return SDValue(); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert(PartVT.isInteger() && ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 } 361 } else if (PartBits == ValueVT.getSizeInBits()) { 362 // Different types of the same size. 363 assert(NumParts == 1 && PartVT != ValueVT); 364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 366 // If the parts cover less bits than value has, truncate the value. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Unknown mismatch!"); 369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 371 } 372 373 // The value may have changed - recompute ValueVT. 374 ValueVT = Val.getValueType(); 375 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 376 "Failed to tile the value with PartVT!"); 377 378 if (NumParts == 1) { 379 assert(PartVT == ValueVT && "Type conversion failed!"); 380 Parts[0] = Val; 381 return; 382 } 383 384 // Expand the value into multiple parts. 385 if (NumParts & (NumParts - 1)) { 386 // The number of parts is not a power of 2. Split off and copy the tail. 387 assert(PartVT.isInteger() && ValueVT.isInteger() && 388 "Do not know what to expand to!"); 389 unsigned RoundParts = 1 << Log2_32(NumParts); 390 unsigned RoundBits = RoundParts * PartBits; 391 unsigned OddParts = NumParts - RoundParts; 392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 393 DAG.getIntPtrConstant(RoundBits)); 394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 395 396 if (TLI.isBigEndian()) 397 // The odd parts were reversed by getCopyToParts - unreverse them. 398 std::reverse(Parts + RoundParts, Parts + NumParts); 399 400 NumParts = RoundParts; 401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 403 } 404 405 // The number of parts is a power of 2. Repeatedly bisect the value using 406 // EXTRACT_ELEMENT. 407 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 408 EVT::getIntegerVT(*DAG.getContext(), 409 ValueVT.getSizeInBits()), 410 Val); 411 412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 413 for (unsigned i = 0; i < NumParts; i += StepSize) { 414 unsigned ThisBits = StepSize * PartBits / 2; 415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 416 SDValue &Part0 = Parts[i]; 417 SDValue &Part1 = Parts[i+StepSize/2]; 418 419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 420 ThisVT, Part0, DAG.getIntPtrConstant(1)); 421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 422 ThisVT, Part0, DAG.getIntPtrConstant(0)); 423 424 if (ThisBits == PartBits && ThisVT != PartVT) { 425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 427 } 428 } 429 } 430 431 if (TLI.isBigEndian()) 432 std::reverse(Parts, Parts + OrigNumParts); 433} 434 435 436/// getCopyToPartsVector - Create a series of nodes that contain the specified 437/// value split into legal parts. 438static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 439 SDValue Val, SDValue *Parts, unsigned NumParts, 440 EVT PartVT) { 441 EVT ValueVT = Val.getValueType(); 442 assert(ValueVT.isVector() && "Not a vector"); 443 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 444 445 if (NumParts == 1) { 446 if (PartVT == ValueVT) { 447 // Nothing to do. 448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 449 // Bitconvert vector->vector case. 450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 451 } else if (PartVT.isVector() && 452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 454 EVT ElementVT = PartVT.getVectorElementType(); 455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 456 // undef elements. 457 SmallVector<SDValue, 16> Ops; 458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 460 ElementVT, Val, DAG.getIntPtrConstant(i))); 461 462 for (unsigned i = ValueVT.getVectorNumElements(), 463 e = PartVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getUNDEF(ElementVT)); 465 466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 467 468 // FIXME: Use CONCAT for 2x -> 4x. 469 470 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 472 } else if (PartVT.isVector() && 473 PartVT.getVectorElementType().bitsGE( 474 ValueVT.getVectorElementType()) && 475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 476 477 // Promoted vector extract 478 bool Smaller = PartVT.bitsLE(ValueVT); 479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 480 DL, PartVT, Val); 481 } else{ 482 // Vector -> scalar conversion. 483 assert(ValueVT.getVectorNumElements() == 1 && 484 "Only trivial vector-to-scalar conversions should get here!"); 485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 PartVT, Val, DAG.getIntPtrConstant(0)); 487 488 bool Smaller = ValueVT.bitsLE(PartVT); 489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 490 DL, PartVT, Val); 491 } 492 493 Parts[0] = Val; 494 return; 495 } 496 497 // Handle a multi-element vector. 498 EVT IntermediateVT, RegisterVT; 499 unsigned NumIntermediates; 500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 501 IntermediateVT, 502 NumIntermediates, RegisterVT); 503 unsigned NumElements = ValueVT.getVectorNumElements(); 504 505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 506 NumParts = NumRegs; // Silence a compiler warning. 507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 508 509 // Split the vector into intermediate operands. 510 SmallVector<SDValue, 8> Ops(NumIntermediates); 511 for (unsigned i = 0; i != NumIntermediates; ++i) { 512 if (IntermediateVT.isVector()) 513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 514 IntermediateVT, Val, 515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 516 else 517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 519 } 520 521 // Split the intermediate operands into legal parts. 522 if (NumParts == NumIntermediates) { 523 // If the register was not expanded, promote or copy the value, 524 // as appropriate. 525 for (unsigned i = 0; i != NumParts; ++i) 526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 527 } else if (NumParts > 0) { 528 // If the intermediate type was expanded, split each the value into 529 // legal parts. 530 assert(NumParts % NumIntermediates == 0 && 531 "Must expand into a divisible number of parts!"); 532 unsigned Factor = NumParts / NumIntermediates; 533 for (unsigned i = 0; i != NumIntermediates; ++i) 534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 535 } 536} 537 538 539 540 541namespace { 542 /// RegsForValue - This struct represents the registers (physical or virtual) 543 /// that a particular set of values is assigned, and the type information 544 /// about the value. The most common situation is to represent one value at a 545 /// time, but struct or array values are handled element-wise as multiple 546 /// values. The splitting of aggregates is performed recursively, so that we 547 /// never have aggregate-typed registers. The values at this point do not 548 /// necessarily have legal types, so each value may require one or more 549 /// registers of some legal type. 550 /// 551 struct RegsForValue { 552 /// ValueVTs - The value types of the values, which may not be legal, and 553 /// may need be promoted or synthesized from one or more registers. 554 /// 555 SmallVector<EVT, 4> ValueVTs; 556 557 /// RegVTs - The value types of the registers. This is the same size as 558 /// ValueVTs and it records, for each value, what the type of the assigned 559 /// register or registers are. (Individual values are never synthesized 560 /// from more than one type of register.) 561 /// 562 /// With virtual registers, the contents of RegVTs is redundant with TLI's 563 /// getRegisterType member function, however when with physical registers 564 /// it is necessary to have a separate record of the types. 565 /// 566 SmallVector<EVT, 4> RegVTs; 567 568 /// Regs - This list holds the registers assigned to the values. 569 /// Each legal or promoted value requires one register, and each 570 /// expanded value requires multiple registers. 571 /// 572 SmallVector<unsigned, 4> Regs; 573 574 RegsForValue() {} 575 576 RegsForValue(const SmallVector<unsigned, 4> ®s, 577 EVT regvt, EVT valuevt) 578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 579 580 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 581 unsigned Reg, Type *Ty) { 582 ComputeValueVTs(tli, Ty, ValueVTs); 583 584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 585 EVT ValueVT = ValueVTs[Value]; 586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 588 for (unsigned i = 0; i != NumRegs; ++i) 589 Regs.push_back(Reg + i); 590 RegVTs.push_back(RegisterVT); 591 Reg += NumRegs; 592 } 593 } 594 595 /// areValueTypesLegal - Return true if types of all the values are legal. 596 bool areValueTypesLegal(const TargetLowering &TLI) { 597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 598 EVT RegisterVT = RegVTs[Value]; 599 if (!TLI.isTypeLegal(RegisterVT)) 600 return false; 601 } 602 return true; 603 } 604 605 /// append - Add the specified values to this one. 606 void append(const RegsForValue &RHS) { 607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 609 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 610 } 611 612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 613 /// this value and returns the result as a ValueVTs value. This uses 614 /// Chain/Flag as the input and updates them for the output Chain/Flag. 615 /// If the Flag pointer is NULL, no flag is used. 616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 617 DebugLoc dl, 618 SDValue &Chain, SDValue *Flag) const; 619 620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 621 /// specified value into the registers specified by this object. This uses 622 /// Chain/Flag as the input and updates them for the output Chain/Flag. 623 /// If the Flag pointer is NULL, no flag is used. 624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 625 SDValue &Chain, SDValue *Flag) const; 626 627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 628 /// operand list. This adds the code marker, matching input operand index 629 /// (if applicable), and includes the number of values added into it. 630 void AddInlineAsmOperands(unsigned Kind, 631 bool HasMatching, unsigned MatchingIdx, 632 SelectionDAG &DAG, 633 std::vector<SDValue> &Ops) const; 634 }; 635} 636 637/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 638/// this value and returns the result as a ValueVT value. This uses 639/// Chain/Flag as the input and updates them for the output Chain/Flag. 640/// If the Flag pointer is NULL, no flag is used. 641SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 642 FunctionLoweringInfo &FuncInfo, 643 DebugLoc dl, 644 SDValue &Chain, SDValue *Flag) const { 645 // A Value with type {} or [0 x %t] needs no registers. 646 if (ValueVTs.empty()) 647 return SDValue(); 648 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 650 651 // Assemble the legal parts into the final values. 652 SmallVector<SDValue, 4> Values(ValueVTs.size()); 653 SmallVector<SDValue, 8> Parts; 654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 655 // Copy the legal parts from the registers. 656 EVT ValueVT = ValueVTs[Value]; 657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 658 EVT RegisterVT = RegVTs[Value]; 659 660 Parts.resize(NumRegs); 661 for (unsigned i = 0; i != NumRegs; ++i) { 662 SDValue P; 663 if (Flag == 0) { 664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 665 } else { 666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 667 *Flag = P.getValue(2); 668 } 669 670 Chain = P.getValue(1); 671 Parts[i] = P; 672 673 // If the source register was virtual and if we know something about it, 674 // add an assert node. 675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 676 !RegisterVT.isInteger() || RegisterVT.isVector()) 677 continue; 678 679 const FunctionLoweringInfo::LiveOutInfo *LOI = 680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 681 if (!LOI) 682 continue; 683 684 unsigned RegSize = RegisterVT.getSizeInBits(); 685 unsigned NumSignBits = LOI->NumSignBits; 686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 687 688 // FIXME: We capture more information than the dag can represent. For 689 // now, just use the tightest assertzext/assertsext possible. 690 bool isSExt = true; 691 EVT FromVT(MVT::Other); 692 if (NumSignBits == RegSize) 693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 694 else if (NumZeroBits >= RegSize-1) 695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 696 else if (NumSignBits > RegSize-8) 697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 698 else if (NumZeroBits >= RegSize-8) 699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 700 else if (NumSignBits > RegSize-16) 701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 702 else if (NumZeroBits >= RegSize-16) 703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 704 else if (NumSignBits > RegSize-32) 705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 706 else if (NumZeroBits >= RegSize-32) 707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 708 else 709 continue; 710 711 // Add an assertion node. 712 assert(FromVT != MVT::Other); 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 714 RegisterVT, P, DAG.getValueType(FromVT)); 715 } 716 717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 718 NumRegs, RegisterVT, ValueVT); 719 Part += NumRegs; 720 Parts.clear(); 721 } 722 723 return DAG.getNode(ISD::MERGE_VALUES, dl, 724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 725 &Values[0], ValueVTs.size()); 726} 727 728/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 729/// specified value into the registers specified by this object. This uses 730/// Chain/Flag as the input and updates them for the output Chain/Flag. 731/// If the Flag pointer is NULL, no flag is used. 732void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 733 SDValue &Chain, SDValue *Flag) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 // Get the list of the values's legal parts. 737 unsigned NumRegs = Regs.size(); 738 SmallVector<SDValue, 8> Parts(NumRegs); 739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 740 EVT ValueVT = ValueVTs[Value]; 741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 742 EVT RegisterVT = RegVTs[Value]; 743 744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 745 &Parts[Part], NumParts, RegisterVT); 746 Part += NumParts; 747 } 748 749 // Copy the parts into the registers. 750 SmallVector<SDValue, 8> Chains(NumRegs); 751 for (unsigned i = 0; i != NumRegs; ++i) { 752 SDValue Part; 753 if (Flag == 0) { 754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 755 } else { 756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 757 *Flag = Part.getValue(1); 758 } 759 760 Chains[i] = Part.getValue(0); 761 } 762 763 if (NumRegs == 1 || Flag) 764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 765 // flagged to it. That is the CopyToReg nodes and the user are considered 766 // a single scheduling unit. If we create a TokenFactor and return it as 767 // chain, then the TokenFactor is both a predecessor (operand) of the 768 // user as well as a successor (the TF operands are flagged to the user). 769 // c1, f1 = CopyToReg 770 // c2, f2 = CopyToReg 771 // c3 = TokenFactor c1, c2 772 // ... 773 // = op c3, ..., f2 774 Chain = Chains[NumRegs-1]; 775 else 776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 777} 778 779/// AddInlineAsmOperands - Add this value to the specified inlineasm node 780/// operand list. This adds the code marker and includes the number of 781/// values added into it. 782void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 783 unsigned MatchingIdx, 784 SelectionDAG &DAG, 785 std::vector<SDValue> &Ops) const { 786 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 787 788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 789 if (HasMatching) 790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 792 Ops.push_back(Res); 793 794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 796 EVT RegisterVT = RegVTs[Value]; 797 for (unsigned i = 0; i != NumRegs; ++i) { 798 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 800 } 801 } 802} 803 804void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 805 AA = &aa; 806 GFI = gfi; 807 TD = DAG.getTarget().getTargetData(); 808} 809 810/// clear - Clear out the current SelectionDAG and the associated 811/// state and prepare this SelectionDAGBuilder object to be used 812/// for a new block. This doesn't clear out information about 813/// additional blocks that are needed to complete switch lowering 814/// or PHI node updating; that information is cleared out as it is 815/// consumed. 816void SelectionDAGBuilder::clear() { 817 NodeMap.clear(); 818 UnusedArgNodeMap.clear(); 819 PendingLoads.clear(); 820 PendingExports.clear(); 821 CurDebugLoc = DebugLoc(); 822 HasTailCall = false; 823} 824 825/// clearDanglingDebugInfo - Clear the dangling debug information 826/// map. This function is seperated from the clear so that debug 827/// information that is dangling in a basic block can be properly 828/// resolved in a different basic block. This allows the 829/// SelectionDAG to resolve dangling debug information attached 830/// to PHI nodes. 831void SelectionDAGBuilder::clearDanglingDebugInfo() { 832 DanglingDebugInfoMap.clear(); 833} 834 835/// getRoot - Return the current virtual root of the Selection DAG, 836/// flushing any PendingLoad items. This must be done before emitting 837/// a store or any other node that may need to be ordered after any 838/// prior load instructions. 839/// 840SDValue SelectionDAGBuilder::getRoot() { 841 if (PendingLoads.empty()) 842 return DAG.getRoot(); 843 844 if (PendingLoads.size() == 1) { 845 SDValue Root = PendingLoads[0]; 846 DAG.setRoot(Root); 847 PendingLoads.clear(); 848 return Root; 849 } 850 851 // Otherwise, we have to make a token factor node. 852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 853 &PendingLoads[0], PendingLoads.size()); 854 PendingLoads.clear(); 855 DAG.setRoot(Root); 856 return Root; 857} 858 859/// getControlRoot - Similar to getRoot, but instead of flushing all the 860/// PendingLoad items, flush all the PendingExports items. It is necessary 861/// to do this before emitting a terminator instruction. 862/// 863SDValue SelectionDAGBuilder::getControlRoot() { 864 SDValue Root = DAG.getRoot(); 865 866 if (PendingExports.empty()) 867 return Root; 868 869 // Turn all of the CopyToReg chains into one factored node. 870 if (Root.getOpcode() != ISD::EntryToken) { 871 unsigned i = 0, e = PendingExports.size(); 872 for (; i != e; ++i) { 873 assert(PendingExports[i].getNode()->getNumOperands() > 1); 874 if (PendingExports[i].getNode()->getOperand(0) == Root) 875 break; // Don't add the root if we already indirectly depend on it. 876 } 877 878 if (i == e) 879 PendingExports.push_back(Root); 880 } 881 882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 883 &PendingExports[0], 884 PendingExports.size()); 885 PendingExports.clear(); 886 DAG.setRoot(Root); 887 return Root; 888} 889 890void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 892 DAG.AssignOrdering(Node, SDNodeOrder); 893 894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 895 AssignOrderingToNode(Node->getOperand(I).getNode()); 896} 897 898void SelectionDAGBuilder::visit(const Instruction &I) { 899 // Set up outgoing PHI node register values before emitting the terminator. 900 if (isa<TerminatorInst>(&I)) 901 HandlePHINodesInSuccessorBlocks(I.getParent()); 902 903 CurDebugLoc = I.getDebugLoc(); 904 905 visit(I.getOpcode(), I); 906 907 if (!isa<TerminatorInst>(&I) && !HasTailCall) 908 CopyToExportRegsIfNeeded(&I); 909 910 CurDebugLoc = DebugLoc(); 911} 912 913void SelectionDAGBuilder::visitPHI(const PHINode &) { 914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 915} 916 917void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 918 // Note: this doesn't use InstVisitor, because it has to work with 919 // ConstantExpr's in addition to instructions. 920 switch (Opcode) { 921 default: llvm_unreachable("Unknown instruction type encountered!"); 922 // Build the switch statement using the Instruction.def file. 923#define HANDLE_INST(NUM, OPCODE, CLASS) \ 924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 925#include "llvm/Instruction.def" 926 } 927 928 // Assign the ordering to the freshly created DAG nodes. 929 if (NodeMap.count(&I)) { 930 ++SDNodeOrder; 931 AssignOrderingToNode(getValue(&I).getNode()); 932 } 933} 934 935// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 936// generate the debug data structures now that we've seen its definition. 937void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 938 SDValue Val) { 939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 940 if (DDI.getDI()) { 941 const DbgValueInst *DI = DDI.getDI(); 942 DebugLoc dl = DDI.getdl(); 943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 944 MDNode *Variable = DI->getVariable(); 945 uint64_t Offset = DI->getOffset(); 946 SDDbgValue *SDV; 947 if (Val.getNode()) { 948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 949 SDV = DAG.getDbgValue(Variable, Val.getNode(), 950 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 951 DAG.AddDbgValue(SDV, Val.getNode(), false); 952 } 953 } else 954 DEBUG(dbgs() << "Dropping debug info for " << DI); 955 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 956 } 957} 958 959// getValue - Return an SDValue for the given Value. 960SDValue SelectionDAGBuilder::getValue(const Value *V) { 961 // If we already have an SDValue for this value, use it. It's important 962 // to do this first, so that we don't create a CopyFromReg if we already 963 // have a regular SDValue. 964 SDValue &N = NodeMap[V]; 965 if (N.getNode()) return N; 966 967 // If there's a virtual register allocated and initialized for this 968 // value, use it. 969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 970 if (It != FuncInfo.ValueMap.end()) { 971 unsigned InReg = It->second; 972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 973 SDValue Chain = DAG.getEntryNode(); 974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 975 resolveDanglingDebugInfo(V, N); 976 return N; 977 } 978 979 // Otherwise create a new SDValue and remember it. 980 SDValue Val = getValueImpl(V); 981 NodeMap[V] = Val; 982 resolveDanglingDebugInfo(V, Val); 983 return Val; 984} 985 986/// getNonRegisterValue - Return an SDValue for the given Value, but 987/// don't look in FuncInfo.ValueMap for a virtual register. 988SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 989 // If we already have an SDValue for this value, use it. 990 SDValue &N = NodeMap[V]; 991 if (N.getNode()) return N; 992 993 // Otherwise create a new SDValue and remember it. 994 SDValue Val = getValueImpl(V); 995 NodeMap[V] = Val; 996 resolveDanglingDebugInfo(V, Val); 997 return Val; 998} 999 1000/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1001/// Create an SDValue for the given value. 1002SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1003 if (const Constant *C = dyn_cast<Constant>(V)) { 1004 EVT VT = TLI.getValueType(V->getType(), true); 1005 1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1007 return DAG.getConstant(*CI, VT); 1008 1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1011 1012 if (isa<ConstantPointerNull>(C)) 1013 return DAG.getConstant(0, TLI.getPointerTy()); 1014 1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1016 return DAG.getConstantFP(*CFP, VT); 1017 1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1019 return DAG.getUNDEF(VT); 1020 1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1022 visit(CE->getOpcode(), *CE); 1023 SDValue N1 = NodeMap[V]; 1024 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1025 return N1; 1026 } 1027 1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1029 SmallVector<SDValue, 4> Constants; 1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1031 OI != OE; ++OI) { 1032 SDNode *Val = getValue(*OI).getNode(); 1033 // If the operand is an empty aggregate, there are no values. 1034 if (!Val) continue; 1035 // Add each leaf value from the operand to the Constants list 1036 // to form a flattened list of all the values. 1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1038 Constants.push_back(SDValue(Val, i)); 1039 } 1040 1041 return DAG.getMergeValues(&Constants[0], Constants.size(), 1042 getCurDebugLoc()); 1043 } 1044 1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1047 "Unknown struct or array constant!"); 1048 1049 SmallVector<EVT, 4> ValueVTs; 1050 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1051 unsigned NumElts = ValueVTs.size(); 1052 if (NumElts == 0) 1053 return SDValue(); // empty struct 1054 SmallVector<SDValue, 4> Constants(NumElts); 1055 for (unsigned i = 0; i != NumElts; ++i) { 1056 EVT EltVT = ValueVTs[i]; 1057 if (isa<UndefValue>(C)) 1058 Constants[i] = DAG.getUNDEF(EltVT); 1059 else if (EltVT.isFloatingPoint()) 1060 Constants[i] = DAG.getConstantFP(0, EltVT); 1061 else 1062 Constants[i] = DAG.getConstant(0, EltVT); 1063 } 1064 1065 return DAG.getMergeValues(&Constants[0], NumElts, 1066 getCurDebugLoc()); 1067 } 1068 1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1070 return DAG.getBlockAddress(BA, VT); 1071 1072 VectorType *VecTy = cast<VectorType>(V->getType()); 1073 unsigned NumElements = VecTy->getNumElements(); 1074 1075 // Now that we know the number and type of the elements, get that number of 1076 // elements into the Ops array based on what kind of constant it is. 1077 SmallVector<SDValue, 16> Ops; 1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1079 for (unsigned i = 0; i != NumElements; ++i) 1080 Ops.push_back(getValue(CP->getOperand(i))); 1081 } else { 1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1083 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1084 1085 SDValue Op; 1086 if (EltVT.isFloatingPoint()) 1087 Op = DAG.getConstantFP(0, EltVT); 1088 else 1089 Op = DAG.getConstant(0, EltVT); 1090 Ops.assign(NumElements, Op); 1091 } 1092 1093 // Create a BUILD_VECTOR node. 1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1095 VT, &Ops[0], Ops.size()); 1096 } 1097 1098 // If this is a static alloca, generate it as the frameindex instead of 1099 // computation. 1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1101 DenseMap<const AllocaInst*, int>::iterator SI = 1102 FuncInfo.StaticAllocaMap.find(AI); 1103 if (SI != FuncInfo.StaticAllocaMap.end()) 1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1105 } 1106 1107 // If this is an instruction which fast-isel has deferred, select it now. 1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1111 SDValue Chain = DAG.getEntryNode(); 1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1113 } 1114 1115 llvm_unreachable("Can't get register for value!"); 1116 return SDValue(); 1117} 1118 1119void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1120 SDValue Chain = getControlRoot(); 1121 SmallVector<ISD::OutputArg, 8> Outs; 1122 SmallVector<SDValue, 8> OutVals; 1123 1124 if (!FuncInfo.CanLowerReturn) { 1125 unsigned DemoteReg = FuncInfo.DemoteRegister; 1126 const Function *F = I.getParent()->getParent(); 1127 1128 // Emit a store of the return value through the virtual register. 1129 // Leave Outs empty so that LowerReturn won't try to load return 1130 // registers the usual way. 1131 SmallVector<EVT, 1> PtrValueVTs; 1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1133 PtrValueVTs); 1134 1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1136 SDValue RetOp = getValue(I.getOperand(0)); 1137 1138 SmallVector<EVT, 4> ValueVTs; 1139 SmallVector<uint64_t, 4> Offsets; 1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1141 unsigned NumValues = ValueVTs.size(); 1142 1143 SmallVector<SDValue, 4> Chains(NumValues); 1144 for (unsigned i = 0; i != NumValues; ++i) { 1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1146 RetPtr.getValueType(), RetPtr, 1147 DAG.getIntPtrConstant(Offsets[i])); 1148 Chains[i] = 1149 DAG.getStore(Chain, getCurDebugLoc(), 1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1151 // FIXME: better loc info would be nice. 1152 Add, MachinePointerInfo(), false, false, 0); 1153 } 1154 1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1156 MVT::Other, &Chains[0], NumValues); 1157 } else if (I.getNumOperands() != 0) { 1158 SmallVector<EVT, 4> ValueVTs; 1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1160 unsigned NumValues = ValueVTs.size(); 1161 if (NumValues) { 1162 SDValue RetOp = getValue(I.getOperand(0)); 1163 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1164 EVT VT = ValueVTs[j]; 1165 1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1167 1168 const Function *F = I.getParent()->getParent(); 1169 if (F->paramHasAttr(0, Attribute::SExt)) 1170 ExtendKind = ISD::SIGN_EXTEND; 1171 else if (F->paramHasAttr(0, Attribute::ZExt)) 1172 ExtendKind = ISD::ZERO_EXTEND; 1173 1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1176 1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1179 SmallVector<SDValue, 4> Parts(NumParts); 1180 getCopyToParts(DAG, getCurDebugLoc(), 1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1182 &Parts[0], NumParts, PartVT, ExtendKind); 1183 1184 // 'inreg' on function refers to return value 1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1186 if (F->paramHasAttr(0, Attribute::InReg)) 1187 Flags.setInReg(); 1188 1189 // Propagate extension type if any 1190 if (ExtendKind == ISD::SIGN_EXTEND) 1191 Flags.setSExt(); 1192 else if (ExtendKind == ISD::ZERO_EXTEND) 1193 Flags.setZExt(); 1194 1195 for (unsigned i = 0; i < NumParts; ++i) { 1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1197 /*isfixed=*/true)); 1198 OutVals.push_back(Parts[i]); 1199 } 1200 } 1201 } 1202 } 1203 1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1205 CallingConv::ID CallConv = 1206 DAG.getMachineFunction().getFunction()->getCallingConv(); 1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1208 Outs, OutVals, getCurDebugLoc(), DAG); 1209 1210 // Verify that the target's LowerReturn behaved as expected. 1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1212 "LowerReturn didn't return a valid chain!"); 1213 1214 // Update the DAG with the new chain value resulting from return lowering. 1215 DAG.setRoot(Chain); 1216} 1217 1218/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1219/// created for it, emit nodes to copy the value into the virtual 1220/// registers. 1221void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1222 // Skip empty types 1223 if (V->getType()->isEmptyTy()) 1224 return; 1225 1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1227 if (VMI != FuncInfo.ValueMap.end()) { 1228 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1229 CopyValueToVirtualRegister(V, VMI->second); 1230 } 1231} 1232 1233/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1234/// the current basic block, add it to ValueMap now so that we'll get a 1235/// CopyTo/FromReg. 1236void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1237 // No need to export constants. 1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1239 1240 // Already exported? 1241 if (FuncInfo.isExportedInst(V)) return; 1242 1243 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1244 CopyValueToVirtualRegister(V, Reg); 1245} 1246 1247bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1248 const BasicBlock *FromBB) { 1249 // The operands of the setcc have to be in this block. We don't know 1250 // how to export them from some other block. 1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1252 // Can export from current BB. 1253 if (VI->getParent() == FromBB) 1254 return true; 1255 1256 // Is already exported, noop. 1257 return FuncInfo.isExportedInst(V); 1258 } 1259 1260 // If this is an argument, we can export it if the BB is the entry block or 1261 // if it is already exported. 1262 if (isa<Argument>(V)) { 1263 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1264 return true; 1265 1266 // Otherwise, can only export this if it is already exported. 1267 return FuncInfo.isExportedInst(V); 1268 } 1269 1270 // Otherwise, constants can always be exported. 1271 return true; 1272} 1273 1274/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1275uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src, 1276 MachineBasicBlock *Dst) { 1277 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1278 if (!BPI) 1279 return 0; 1280 BasicBlock *SrcBB = const_cast<BasicBlock*>(Src->getBasicBlock()); 1281 BasicBlock *DstBB = const_cast<BasicBlock*>(Dst->getBasicBlock()); 1282 return BPI->getEdgeWeight(SrcBB, DstBB); 1283} 1284 1285void SelectionDAGBuilder::addSuccessorWithWeight(MachineBasicBlock *Src, 1286 MachineBasicBlock *Dst) { 1287 uint32_t weight = getEdgeWeight(Src, Dst); 1288 Src->addSuccessor(Dst, weight); 1289} 1290 1291 1292static bool InBlock(const Value *V, const BasicBlock *BB) { 1293 if (const Instruction *I = dyn_cast<Instruction>(V)) 1294 return I->getParent() == BB; 1295 return true; 1296} 1297 1298/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1299/// This function emits a branch and is used at the leaves of an OR or an 1300/// AND operator tree. 1301/// 1302void 1303SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1304 MachineBasicBlock *TBB, 1305 MachineBasicBlock *FBB, 1306 MachineBasicBlock *CurBB, 1307 MachineBasicBlock *SwitchBB) { 1308 const BasicBlock *BB = CurBB->getBasicBlock(); 1309 1310 // If the leaf of the tree is a comparison, merge the condition into 1311 // the caseblock. 1312 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1313 // The operands of the cmp have to be in this block. We don't know 1314 // how to export them from some other block. If this is the first block 1315 // of the sequence, no exporting is needed. 1316 if (CurBB == SwitchBB || 1317 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1318 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1319 ISD::CondCode Condition; 1320 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1321 Condition = getICmpCondCode(IC->getPredicate()); 1322 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1323 Condition = getFCmpCondCode(FC->getPredicate()); 1324 } else { 1325 Condition = ISD::SETEQ; // silence warning. 1326 llvm_unreachable("Unknown compare instruction"); 1327 } 1328 1329 CaseBlock CB(Condition, BOp->getOperand(0), 1330 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1331 SwitchCases.push_back(CB); 1332 return; 1333 } 1334 } 1335 1336 // Create a CaseBlock record representing this branch. 1337 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1338 NULL, TBB, FBB, CurBB); 1339 SwitchCases.push_back(CB); 1340} 1341 1342/// FindMergedConditions - If Cond is an expression like 1343void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1344 MachineBasicBlock *TBB, 1345 MachineBasicBlock *FBB, 1346 MachineBasicBlock *CurBB, 1347 MachineBasicBlock *SwitchBB, 1348 unsigned Opc) { 1349 // If this node is not part of the or/and tree, emit it as a branch. 1350 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1351 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1352 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1353 BOp->getParent() != CurBB->getBasicBlock() || 1354 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1355 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1356 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1357 return; 1358 } 1359 1360 // Create TmpBB after CurBB. 1361 MachineFunction::iterator BBI = CurBB; 1362 MachineFunction &MF = DAG.getMachineFunction(); 1363 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1364 CurBB->getParent()->insert(++BBI, TmpBB); 1365 1366 if (Opc == Instruction::Or) { 1367 // Codegen X | Y as: 1368 // jmp_if_X TBB 1369 // jmp TmpBB 1370 // TmpBB: 1371 // jmp_if_Y TBB 1372 // jmp FBB 1373 // 1374 1375 // Emit the LHS condition. 1376 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1377 1378 // Emit the RHS condition into TmpBB. 1379 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1380 } else { 1381 assert(Opc == Instruction::And && "Unknown merge op!"); 1382 // Codegen X & Y as: 1383 // jmp_if_X TmpBB 1384 // jmp FBB 1385 // TmpBB: 1386 // jmp_if_Y TBB 1387 // jmp FBB 1388 // 1389 // This requires creation of TmpBB after CurBB. 1390 1391 // Emit the LHS condition. 1392 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1393 1394 // Emit the RHS condition into TmpBB. 1395 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1396 } 1397} 1398 1399/// If the set of cases should be emitted as a series of branches, return true. 1400/// If we should emit this as a bunch of and/or'd together conditions, return 1401/// false. 1402bool 1403SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1404 if (Cases.size() != 2) return true; 1405 1406 // If this is two comparisons of the same values or'd or and'd together, they 1407 // will get folded into a single comparison, so don't emit two blocks. 1408 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1409 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1410 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1411 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1412 return false; 1413 } 1414 1415 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1416 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1417 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1418 Cases[0].CC == Cases[1].CC && 1419 isa<Constant>(Cases[0].CmpRHS) && 1420 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1421 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1422 return false; 1423 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1424 return false; 1425 } 1426 1427 return true; 1428} 1429 1430void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1431 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1432 1433 // Update machine-CFG edges. 1434 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1435 1436 // Figure out which block is immediately after the current one. 1437 MachineBasicBlock *NextBlock = 0; 1438 MachineFunction::iterator BBI = BrMBB; 1439 if (++BBI != FuncInfo.MF->end()) 1440 NextBlock = BBI; 1441 1442 if (I.isUnconditional()) { 1443 // Update machine-CFG edges. 1444 BrMBB->addSuccessor(Succ0MBB); 1445 1446 // If this is not a fall-through branch, emit the branch. 1447 if (Succ0MBB != NextBlock) 1448 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1449 MVT::Other, getControlRoot(), 1450 DAG.getBasicBlock(Succ0MBB))); 1451 1452 return; 1453 } 1454 1455 // If this condition is one of the special cases we handle, do special stuff 1456 // now. 1457 const Value *CondVal = I.getCondition(); 1458 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1459 1460 // If this is a series of conditions that are or'd or and'd together, emit 1461 // this as a sequence of branches instead of setcc's with and/or operations. 1462 // As long as jumps are not expensive, this should improve performance. 1463 // For example, instead of something like: 1464 // cmp A, B 1465 // C = seteq 1466 // cmp D, E 1467 // F = setle 1468 // or C, F 1469 // jnz foo 1470 // Emit: 1471 // cmp A, B 1472 // je foo 1473 // cmp D, E 1474 // jle foo 1475 // 1476 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1477 if (!TLI.isJumpExpensive() && 1478 BOp->hasOneUse() && 1479 (BOp->getOpcode() == Instruction::And || 1480 BOp->getOpcode() == Instruction::Or)) { 1481 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1482 BOp->getOpcode()); 1483 // If the compares in later blocks need to use values not currently 1484 // exported from this block, export them now. This block should always 1485 // be the first entry. 1486 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1487 1488 // Allow some cases to be rejected. 1489 if (ShouldEmitAsBranches(SwitchCases)) { 1490 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1491 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1492 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1493 } 1494 1495 // Emit the branch for this block. 1496 visitSwitchCase(SwitchCases[0], BrMBB); 1497 SwitchCases.erase(SwitchCases.begin()); 1498 return; 1499 } 1500 1501 // Okay, we decided not to do this, remove any inserted MBB's and clear 1502 // SwitchCases. 1503 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1504 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1505 1506 SwitchCases.clear(); 1507 } 1508 } 1509 1510 // Create a CaseBlock record representing this branch. 1511 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1512 NULL, Succ0MBB, Succ1MBB, BrMBB); 1513 1514 // Use visitSwitchCase to actually insert the fast branch sequence for this 1515 // cond branch. 1516 visitSwitchCase(CB, BrMBB); 1517} 1518 1519/// visitSwitchCase - Emits the necessary code to represent a single node in 1520/// the binary search tree resulting from lowering a switch instruction. 1521void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1522 MachineBasicBlock *SwitchBB) { 1523 SDValue Cond; 1524 SDValue CondLHS = getValue(CB.CmpLHS); 1525 DebugLoc dl = getCurDebugLoc(); 1526 1527 // Build the setcc now. 1528 if (CB.CmpMHS == NULL) { 1529 // Fold "(X == true)" to X and "(X == false)" to !X to 1530 // handle common cases produced by branch lowering. 1531 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1532 CB.CC == ISD::SETEQ) 1533 Cond = CondLHS; 1534 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1535 CB.CC == ISD::SETEQ) { 1536 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1537 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1538 } else 1539 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1540 } else { 1541 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1542 1543 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1544 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1545 1546 SDValue CmpOp = getValue(CB.CmpMHS); 1547 EVT VT = CmpOp.getValueType(); 1548 1549 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1550 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1551 ISD::SETLE); 1552 } else { 1553 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1554 VT, CmpOp, DAG.getConstant(Low, VT)); 1555 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1556 DAG.getConstant(High-Low, VT), ISD::SETULE); 1557 } 1558 } 1559 1560 // Update successor info 1561 addSuccessorWithWeight(SwitchBB, CB.TrueBB); 1562 addSuccessorWithWeight(SwitchBB, CB.FalseBB); 1563 1564 // Set NextBlock to be the MBB immediately after the current one, if any. 1565 // This is used to avoid emitting unnecessary branches to the next block. 1566 MachineBasicBlock *NextBlock = 0; 1567 MachineFunction::iterator BBI = SwitchBB; 1568 if (++BBI != FuncInfo.MF->end()) 1569 NextBlock = BBI; 1570 1571 // If the lhs block is the next block, invert the condition so that we can 1572 // fall through to the lhs instead of the rhs block. 1573 if (CB.TrueBB == NextBlock) { 1574 std::swap(CB.TrueBB, CB.FalseBB); 1575 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1576 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1577 } 1578 1579 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1580 MVT::Other, getControlRoot(), Cond, 1581 DAG.getBasicBlock(CB.TrueBB)); 1582 1583 // Insert the false branch. Do this even if it's a fall through branch, 1584 // this makes it easier to do DAG optimizations which require inverting 1585 // the branch condition. 1586 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1587 DAG.getBasicBlock(CB.FalseBB)); 1588 1589 DAG.setRoot(BrCond); 1590} 1591 1592/// visitJumpTable - Emit JumpTable node in the current MBB 1593void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1594 // Emit the code for the jump table 1595 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1596 EVT PTy = TLI.getPointerTy(); 1597 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1598 JT.Reg, PTy); 1599 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1600 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1601 MVT::Other, Index.getValue(1), 1602 Table, Index); 1603 DAG.setRoot(BrJumpTable); 1604} 1605 1606/// visitJumpTableHeader - This function emits necessary code to produce index 1607/// in the JumpTable from switch case. 1608void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1609 JumpTableHeader &JTH, 1610 MachineBasicBlock *SwitchBB) { 1611 // Subtract the lowest switch case value from the value being switched on and 1612 // conditional branch to default mbb if the result is greater than the 1613 // difference between smallest and largest cases. 1614 SDValue SwitchOp = getValue(JTH.SValue); 1615 EVT VT = SwitchOp.getValueType(); 1616 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1617 DAG.getConstant(JTH.First, VT)); 1618 1619 // The SDNode we just created, which holds the value being switched on minus 1620 // the smallest case value, needs to be copied to a virtual register so it 1621 // can be used as an index into the jump table in a subsequent basic block. 1622 // This value may be smaller or larger than the target's pointer type, and 1623 // therefore require extension or truncating. 1624 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1625 1626 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1627 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1628 JumpTableReg, SwitchOp); 1629 JT.Reg = JumpTableReg; 1630 1631 // Emit the range check for the jump table, and branch to the default block 1632 // for the switch statement if the value being switched on exceeds the largest 1633 // case in the switch. 1634 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1635 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1636 DAG.getConstant(JTH.Last-JTH.First,VT), 1637 ISD::SETUGT); 1638 1639 // Set NextBlock to be the MBB immediately after the current one, if any. 1640 // This is used to avoid emitting unnecessary branches to the next block. 1641 MachineBasicBlock *NextBlock = 0; 1642 MachineFunction::iterator BBI = SwitchBB; 1643 1644 if (++BBI != FuncInfo.MF->end()) 1645 NextBlock = BBI; 1646 1647 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1648 MVT::Other, CopyTo, CMP, 1649 DAG.getBasicBlock(JT.Default)); 1650 1651 if (JT.MBB != NextBlock) 1652 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1653 DAG.getBasicBlock(JT.MBB)); 1654 1655 DAG.setRoot(BrCond); 1656} 1657 1658/// visitBitTestHeader - This function emits necessary code to produce value 1659/// suitable for "bit tests" 1660void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1661 MachineBasicBlock *SwitchBB) { 1662 // Subtract the minimum value 1663 SDValue SwitchOp = getValue(B.SValue); 1664 EVT VT = SwitchOp.getValueType(); 1665 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1666 DAG.getConstant(B.First, VT)); 1667 1668 // Check range 1669 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1670 TLI.getSetCCResultType(Sub.getValueType()), 1671 Sub, DAG.getConstant(B.Range, VT), 1672 ISD::SETUGT); 1673 1674 // Determine the type of the test operands. 1675 bool UsePtrType = false; 1676 if (!TLI.isTypeLegal(VT)) 1677 UsePtrType = true; 1678 else { 1679 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1680 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1681 // Switch table case range are encoded into series of masks. 1682 // Just use pointer type, it's guaranteed to fit. 1683 UsePtrType = true; 1684 break; 1685 } 1686 } 1687 if (UsePtrType) { 1688 VT = TLI.getPointerTy(); 1689 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1690 } 1691 1692 B.RegVT = VT; 1693 B.Reg = FuncInfo.CreateReg(VT); 1694 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1695 B.Reg, Sub); 1696 1697 // Set NextBlock to be the MBB immediately after the current one, if any. 1698 // This is used to avoid emitting unnecessary branches to the next block. 1699 MachineBasicBlock *NextBlock = 0; 1700 MachineFunction::iterator BBI = SwitchBB; 1701 if (++BBI != FuncInfo.MF->end()) 1702 NextBlock = BBI; 1703 1704 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1705 1706 addSuccessorWithWeight(SwitchBB, B.Default); 1707 addSuccessorWithWeight(SwitchBB, MBB); 1708 1709 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1710 MVT::Other, CopyTo, RangeCmp, 1711 DAG.getBasicBlock(B.Default)); 1712 1713 if (MBB != NextBlock) 1714 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1715 DAG.getBasicBlock(MBB)); 1716 1717 DAG.setRoot(BrRange); 1718} 1719 1720/// visitBitTestCase - this function produces one "bit test" 1721void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1722 MachineBasicBlock* NextMBB, 1723 unsigned Reg, 1724 BitTestCase &B, 1725 MachineBasicBlock *SwitchBB) { 1726 EVT VT = BB.RegVT; 1727 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1728 Reg, VT); 1729 SDValue Cmp; 1730 unsigned PopCount = CountPopulation_64(B.Mask); 1731 if (PopCount == 1) { 1732 // Testing for a single bit; just compare the shift count with what it 1733 // would need to be to shift a 1 bit in that position. 1734 Cmp = DAG.getSetCC(getCurDebugLoc(), 1735 TLI.getSetCCResultType(VT), 1736 ShiftOp, 1737 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1738 ISD::SETEQ); 1739 } else if (PopCount == BB.Range) { 1740 // There is only one zero bit in the range, test for it directly. 1741 Cmp = DAG.getSetCC(getCurDebugLoc(), 1742 TLI.getSetCCResultType(VT), 1743 ShiftOp, 1744 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1745 ISD::SETNE); 1746 } else { 1747 // Make desired shift 1748 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1749 DAG.getConstant(1, VT), ShiftOp); 1750 1751 // Emit bit tests and jumps 1752 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1753 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1754 Cmp = DAG.getSetCC(getCurDebugLoc(), 1755 TLI.getSetCCResultType(VT), 1756 AndOp, DAG.getConstant(0, VT), 1757 ISD::SETNE); 1758 } 1759 1760 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1761 addSuccessorWithWeight(SwitchBB, NextMBB); 1762 1763 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1764 MVT::Other, getControlRoot(), 1765 Cmp, DAG.getBasicBlock(B.TargetBB)); 1766 1767 // Set NextBlock to be the MBB immediately after the current one, if any. 1768 // This is used to avoid emitting unnecessary branches to the next block. 1769 MachineBasicBlock *NextBlock = 0; 1770 MachineFunction::iterator BBI = SwitchBB; 1771 if (++BBI != FuncInfo.MF->end()) 1772 NextBlock = BBI; 1773 1774 if (NextMBB != NextBlock) 1775 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1776 DAG.getBasicBlock(NextMBB)); 1777 1778 DAG.setRoot(BrAnd); 1779} 1780 1781void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1782 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1783 1784 // Retrieve successors. 1785 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1786 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1787 1788 const Value *Callee(I.getCalledValue()); 1789 if (isa<InlineAsm>(Callee)) 1790 visitInlineAsm(&I); 1791 else 1792 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1793 1794 // If the value of the invoke is used outside of its defining block, make it 1795 // available as a virtual register. 1796 CopyToExportRegsIfNeeded(&I); 1797 1798 // Update successor info 1799 InvokeMBB->addSuccessor(Return); 1800 InvokeMBB->addSuccessor(LandingPad); 1801 1802 // Drop into normal successor. 1803 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1804 MVT::Other, getControlRoot(), 1805 DAG.getBasicBlock(Return))); 1806} 1807 1808void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1809} 1810 1811void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1812 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1813} 1814 1815void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1816 // FIXME: Handle this 1817 assert(FuncInfo.MBB->isLandingPad() && 1818 "Call to landingpad not in landing pad!"); 1819 1820 MachineBasicBlock *MBB = FuncInfo.MBB; 1821 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1822 AddLandingPadInfo(LP, MMI, MBB); 1823 1824 SmallVector<EVT, 2> ValueVTs; 1825 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1826 1827 // Insert the EXCEPTIONADDR instruction. 1828 assert(FuncInfo.MBB->isLandingPad() && 1829 "Call to eh.exception not in landing pad!"); 1830 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1831 SDValue Ops[2]; 1832 Ops[0] = DAG.getRoot(); 1833 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1834 SDValue Chain = Op1.getValue(1); 1835 1836 // Insert the EHSELECTION instruction. 1837 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1838 Ops[0] = Op1; 1839 Ops[1] = Chain; 1840 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1841 Chain = Op2.getValue(1); 1842 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1843 1844 Ops[0] = Op1; 1845 Ops[1] = Op2; 1846 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1847 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1848 &Ops[0], 2); 1849 1850 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1851 setValue(&LP, RetPair.first); 1852 DAG.setRoot(RetPair.second); 1853} 1854 1855/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1856/// small case ranges). 1857bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1858 CaseRecVector& WorkList, 1859 const Value* SV, 1860 MachineBasicBlock *Default, 1861 MachineBasicBlock *SwitchBB) { 1862 Case& BackCase = *(CR.Range.second-1); 1863 1864 // Size is the number of Cases represented by this range. 1865 size_t Size = CR.Range.second - CR.Range.first; 1866 if (Size > 3) 1867 return false; 1868 1869 // Get the MachineFunction which holds the current MBB. This is used when 1870 // inserting any additional MBBs necessary to represent the switch. 1871 MachineFunction *CurMF = FuncInfo.MF; 1872 1873 // Figure out which block is immediately after the current one. 1874 MachineBasicBlock *NextBlock = 0; 1875 MachineFunction::iterator BBI = CR.CaseBB; 1876 1877 if (++BBI != FuncInfo.MF->end()) 1878 NextBlock = BBI; 1879 1880 // If any two of the cases has the same destination, and if one value 1881 // is the same as the other, but has one bit unset that the other has set, 1882 // use bit manipulation to do two compares at once. For example: 1883 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1884 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1885 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1886 if (Size == 2 && CR.CaseBB == SwitchBB) { 1887 Case &Small = *CR.Range.first; 1888 Case &Big = *(CR.Range.second-1); 1889 1890 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1891 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1892 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1893 1894 // Check that there is only one bit different. 1895 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1896 (SmallValue | BigValue) == BigValue) { 1897 // Isolate the common bit. 1898 APInt CommonBit = BigValue & ~SmallValue; 1899 assert((SmallValue | CommonBit) == BigValue && 1900 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1901 1902 SDValue CondLHS = getValue(SV); 1903 EVT VT = CondLHS.getValueType(); 1904 DebugLoc DL = getCurDebugLoc(); 1905 1906 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1907 DAG.getConstant(CommonBit, VT)); 1908 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1909 Or, DAG.getConstant(BigValue, VT), 1910 ISD::SETEQ); 1911 1912 // Update successor info. 1913 SwitchBB->addSuccessor(Small.BB); 1914 SwitchBB->addSuccessor(Default); 1915 1916 // Insert the true branch. 1917 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1918 getControlRoot(), Cond, 1919 DAG.getBasicBlock(Small.BB)); 1920 1921 // Insert the false branch. 1922 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1923 DAG.getBasicBlock(Default)); 1924 1925 DAG.setRoot(BrCond); 1926 return true; 1927 } 1928 } 1929 } 1930 1931 // Rearrange the case blocks so that the last one falls through if possible. 1932 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1933 // The last case block won't fall through into 'NextBlock' if we emit the 1934 // branches in this order. See if rearranging a case value would help. 1935 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1936 if (I->BB == NextBlock) { 1937 std::swap(*I, BackCase); 1938 break; 1939 } 1940 } 1941 } 1942 1943 // Create a CaseBlock record representing a conditional branch to 1944 // the Case's target mbb if the value being switched on SV is equal 1945 // to C. 1946 MachineBasicBlock *CurBlock = CR.CaseBB; 1947 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1948 MachineBasicBlock *FallThrough; 1949 if (I != E-1) { 1950 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1951 CurMF->insert(BBI, FallThrough); 1952 1953 // Put SV in a virtual register to make it available from the new blocks. 1954 ExportFromCurrentBlock(SV); 1955 } else { 1956 // If the last case doesn't match, go to the default block. 1957 FallThrough = Default; 1958 } 1959 1960 const Value *RHS, *LHS, *MHS; 1961 ISD::CondCode CC; 1962 if (I->High == I->Low) { 1963 // This is just small small case range :) containing exactly 1 case 1964 CC = ISD::SETEQ; 1965 LHS = SV; RHS = I->High; MHS = NULL; 1966 } else { 1967 CC = ISD::SETLE; 1968 LHS = I->Low; MHS = SV; RHS = I->High; 1969 } 1970 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1971 1972 // If emitting the first comparison, just call visitSwitchCase to emit the 1973 // code into the current block. Otherwise, push the CaseBlock onto the 1974 // vector to be later processed by SDISel, and insert the node's MBB 1975 // before the next MBB. 1976 if (CurBlock == SwitchBB) 1977 visitSwitchCase(CB, SwitchBB); 1978 else 1979 SwitchCases.push_back(CB); 1980 1981 CurBlock = FallThrough; 1982 } 1983 1984 return true; 1985} 1986 1987static inline bool areJTsAllowed(const TargetLowering &TLI) { 1988 return !DisableJumpTables && 1989 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1990 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1991} 1992 1993static APInt ComputeRange(const APInt &First, const APInt &Last) { 1994 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1995 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 1996 return (LastExt - FirstExt + 1ULL); 1997} 1998 1999/// handleJTSwitchCase - Emit jumptable for current switch case range 2000bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 2001 CaseRecVector& WorkList, 2002 const Value* SV, 2003 MachineBasicBlock* Default, 2004 MachineBasicBlock *SwitchBB) { 2005 Case& FrontCase = *CR.Range.first; 2006 Case& BackCase = *(CR.Range.second-1); 2007 2008 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2009 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2010 2011 APInt TSize(First.getBitWidth(), 0); 2012 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2013 I!=E; ++I) 2014 TSize += I->size(); 2015 2016 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2017 return false; 2018 2019 APInt Range = ComputeRange(First, Last); 2020 double Density = TSize.roundToDouble() / Range.roundToDouble(); 2021 if (Density < 0.4) 2022 return false; 2023 2024 DEBUG(dbgs() << "Lowering jump table\n" 2025 << "First entry: " << First << ". Last entry: " << Last << '\n' 2026 << "Range: " << Range 2027 << ". Size: " << TSize << ". Density: " << Density << "\n\n"); 2028 2029 // Get the MachineFunction which holds the current MBB. This is used when 2030 // inserting any additional MBBs necessary to represent the switch. 2031 MachineFunction *CurMF = FuncInfo.MF; 2032 2033 // Figure out which block is immediately after the current one. 2034 MachineFunction::iterator BBI = CR.CaseBB; 2035 ++BBI; 2036 2037 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2038 2039 // Create a new basic block to hold the code for loading the address 2040 // of the jump table, and jumping to it. Update successor information; 2041 // we will either branch to the default case for the switch, or the jump 2042 // table. 2043 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2044 CurMF->insert(BBI, JumpTableBB); 2045 2046 addSuccessorWithWeight(CR.CaseBB, Default); 2047 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2048 2049 // Build a vector of destination BBs, corresponding to each target 2050 // of the jump table. If the value of the jump table slot corresponds to 2051 // a case statement, push the case's BB onto the vector, otherwise, push 2052 // the default BB. 2053 std::vector<MachineBasicBlock*> DestBBs; 2054 APInt TEI = First; 2055 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2056 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2057 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2058 2059 if (Low.sle(TEI) && TEI.sle(High)) { 2060 DestBBs.push_back(I->BB); 2061 if (TEI==High) 2062 ++I; 2063 } else { 2064 DestBBs.push_back(Default); 2065 } 2066 } 2067 2068 // Update successor info. Add one edge to each unique successor. 2069 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2070 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2071 E = DestBBs.end(); I != E; ++I) { 2072 if (!SuccsHandled[(*I)->getNumber()]) { 2073 SuccsHandled[(*I)->getNumber()] = true; 2074 addSuccessorWithWeight(JumpTableBB, *I); 2075 } 2076 } 2077 2078 // Create a jump table index for this jump table. 2079 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2080 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2081 ->createJumpTableIndex(DestBBs); 2082 2083 // Set the jump table information so that we can codegen it as a second 2084 // MachineBasicBlock 2085 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2086 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2087 if (CR.CaseBB == SwitchBB) 2088 visitJumpTableHeader(JT, JTH, SwitchBB); 2089 2090 JTCases.push_back(JumpTableBlock(JTH, JT)); 2091 2092 return true; 2093} 2094 2095/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2096/// 2 subtrees. 2097bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2098 CaseRecVector& WorkList, 2099 const Value* SV, 2100 MachineBasicBlock *Default, 2101 MachineBasicBlock *SwitchBB) { 2102 // Get the MachineFunction which holds the current MBB. This is used when 2103 // inserting any additional MBBs necessary to represent the switch. 2104 MachineFunction *CurMF = FuncInfo.MF; 2105 2106 // Figure out which block is immediately after the current one. 2107 MachineFunction::iterator BBI = CR.CaseBB; 2108 ++BBI; 2109 2110 Case& FrontCase = *CR.Range.first; 2111 Case& BackCase = *(CR.Range.second-1); 2112 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2113 2114 // Size is the number of Cases represented by this range. 2115 unsigned Size = CR.Range.second - CR.Range.first; 2116 2117 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2118 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2119 double FMetric = 0; 2120 CaseItr Pivot = CR.Range.first + Size/2; 2121 2122 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2123 // (heuristically) allow us to emit JumpTable's later. 2124 APInt TSize(First.getBitWidth(), 0); 2125 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2126 I!=E; ++I) 2127 TSize += I->size(); 2128 2129 APInt LSize = FrontCase.size(); 2130 APInt RSize = TSize-LSize; 2131 DEBUG(dbgs() << "Selecting best pivot: \n" 2132 << "First: " << First << ", Last: " << Last <<'\n' 2133 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2134 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2135 J!=E; ++I, ++J) { 2136 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2137 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2138 APInt Range = ComputeRange(LEnd, RBegin); 2139 assert((Range - 2ULL).isNonNegative() && 2140 "Invalid case distance"); 2141 // Use volatile double here to avoid excess precision issues on some hosts, 2142 // e.g. that use 80-bit X87 registers. 2143 volatile double LDensity = 2144 (double)LSize.roundToDouble() / 2145 (LEnd - First + 1ULL).roundToDouble(); 2146 volatile double RDensity = 2147 (double)RSize.roundToDouble() / 2148 (Last - RBegin + 1ULL).roundToDouble(); 2149 double Metric = Range.logBase2()*(LDensity+RDensity); 2150 // Should always split in some non-trivial place 2151 DEBUG(dbgs() <<"=>Step\n" 2152 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2153 << "LDensity: " << LDensity 2154 << ", RDensity: " << RDensity << '\n' 2155 << "Metric: " << Metric << '\n'); 2156 if (FMetric < Metric) { 2157 Pivot = J; 2158 FMetric = Metric; 2159 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2160 } 2161 2162 LSize += J->size(); 2163 RSize -= J->size(); 2164 } 2165 if (areJTsAllowed(TLI)) { 2166 // If our case is dense we *really* should handle it earlier! 2167 assert((FMetric > 0) && "Should handle dense range earlier!"); 2168 } else { 2169 Pivot = CR.Range.first + Size/2; 2170 } 2171 2172 CaseRange LHSR(CR.Range.first, Pivot); 2173 CaseRange RHSR(Pivot, CR.Range.second); 2174 Constant *C = Pivot->Low; 2175 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2176 2177 // We know that we branch to the LHS if the Value being switched on is 2178 // less than the Pivot value, C. We use this to optimize our binary 2179 // tree a bit, by recognizing that if SV is greater than or equal to the 2180 // LHS's Case Value, and that Case Value is exactly one less than the 2181 // Pivot's Value, then we can branch directly to the LHS's Target, 2182 // rather than creating a leaf node for it. 2183 if ((LHSR.second - LHSR.first) == 1 && 2184 LHSR.first->High == CR.GE && 2185 cast<ConstantInt>(C)->getValue() == 2186 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2187 TrueBB = LHSR.first->BB; 2188 } else { 2189 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2190 CurMF->insert(BBI, TrueBB); 2191 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2192 2193 // Put SV in a virtual register to make it available from the new blocks. 2194 ExportFromCurrentBlock(SV); 2195 } 2196 2197 // Similar to the optimization above, if the Value being switched on is 2198 // known to be less than the Constant CR.LT, and the current Case Value 2199 // is CR.LT - 1, then we can branch directly to the target block for 2200 // the current Case Value, rather than emitting a RHS leaf node for it. 2201 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2202 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2203 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2204 FalseBB = RHSR.first->BB; 2205 } else { 2206 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2207 CurMF->insert(BBI, FalseBB); 2208 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2209 2210 // Put SV in a virtual register to make it available from the new blocks. 2211 ExportFromCurrentBlock(SV); 2212 } 2213 2214 // Create a CaseBlock record representing a conditional branch to 2215 // the LHS node if the value being switched on SV is less than C. 2216 // Otherwise, branch to LHS. 2217 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2218 2219 if (CR.CaseBB == SwitchBB) 2220 visitSwitchCase(CB, SwitchBB); 2221 else 2222 SwitchCases.push_back(CB); 2223 2224 return true; 2225} 2226 2227/// handleBitTestsSwitchCase - if current case range has few destination and 2228/// range span less, than machine word bitwidth, encode case range into series 2229/// of masks and emit bit tests with these masks. 2230bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2231 CaseRecVector& WorkList, 2232 const Value* SV, 2233 MachineBasicBlock* Default, 2234 MachineBasicBlock *SwitchBB){ 2235 EVT PTy = TLI.getPointerTy(); 2236 unsigned IntPtrBits = PTy.getSizeInBits(); 2237 2238 Case& FrontCase = *CR.Range.first; 2239 Case& BackCase = *(CR.Range.second-1); 2240 2241 // Get the MachineFunction which holds the current MBB. This is used when 2242 // inserting any additional MBBs necessary to represent the switch. 2243 MachineFunction *CurMF = FuncInfo.MF; 2244 2245 // If target does not have legal shift left, do not emit bit tests at all. 2246 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2247 return false; 2248 2249 size_t numCmps = 0; 2250 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2251 I!=E; ++I) { 2252 // Single case counts one, case range - two. 2253 numCmps += (I->Low == I->High ? 1 : 2); 2254 } 2255 2256 // Count unique destinations 2257 SmallSet<MachineBasicBlock*, 4> Dests; 2258 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2259 Dests.insert(I->BB); 2260 if (Dests.size() > 3) 2261 // Don't bother the code below, if there are too much unique destinations 2262 return false; 2263 } 2264 DEBUG(dbgs() << "Total number of unique destinations: " 2265 << Dests.size() << '\n' 2266 << "Total number of comparisons: " << numCmps << '\n'); 2267 2268 // Compute span of values. 2269 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2270 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2271 APInt cmpRange = maxValue - minValue; 2272 2273 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2274 << "Low bound: " << minValue << '\n' 2275 << "High bound: " << maxValue << '\n'); 2276 2277 if (cmpRange.uge(IntPtrBits) || 2278 (!(Dests.size() == 1 && numCmps >= 3) && 2279 !(Dests.size() == 2 && numCmps >= 5) && 2280 !(Dests.size() >= 3 && numCmps >= 6))) 2281 return false; 2282 2283 DEBUG(dbgs() << "Emitting bit tests\n"); 2284 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2285 2286 // Optimize the case where all the case values fit in a 2287 // word without having to subtract minValue. In this case, 2288 // we can optimize away the subtraction. 2289 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2290 cmpRange = maxValue; 2291 } else { 2292 lowBound = minValue; 2293 } 2294 2295 CaseBitsVector CasesBits; 2296 unsigned i, count = 0; 2297 2298 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2299 MachineBasicBlock* Dest = I->BB; 2300 for (i = 0; i < count; ++i) 2301 if (Dest == CasesBits[i].BB) 2302 break; 2303 2304 if (i == count) { 2305 assert((count < 3) && "Too much destinations to test!"); 2306 CasesBits.push_back(CaseBits(0, Dest, 0)); 2307 count++; 2308 } 2309 2310 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2311 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2312 2313 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2314 uint64_t hi = (highValue - lowBound).getZExtValue(); 2315 2316 for (uint64_t j = lo; j <= hi; j++) { 2317 CasesBits[i].Mask |= 1ULL << j; 2318 CasesBits[i].Bits++; 2319 } 2320 2321 } 2322 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2323 2324 BitTestInfo BTC; 2325 2326 // Figure out which block is immediately after the current one. 2327 MachineFunction::iterator BBI = CR.CaseBB; 2328 ++BBI; 2329 2330 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2331 2332 DEBUG(dbgs() << "Cases:\n"); 2333 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2334 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2335 << ", Bits: " << CasesBits[i].Bits 2336 << ", BB: " << CasesBits[i].BB << '\n'); 2337 2338 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2339 CurMF->insert(BBI, CaseBB); 2340 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2341 CaseBB, 2342 CasesBits[i].BB)); 2343 2344 // Put SV in a virtual register to make it available from the new blocks. 2345 ExportFromCurrentBlock(SV); 2346 } 2347 2348 BitTestBlock BTB(lowBound, cmpRange, SV, 2349 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2350 CR.CaseBB, Default, BTC); 2351 2352 if (CR.CaseBB == SwitchBB) 2353 visitBitTestHeader(BTB, SwitchBB); 2354 2355 BitTestCases.push_back(BTB); 2356 2357 return true; 2358} 2359 2360/// Clusterify - Transform simple list of Cases into list of CaseRange's 2361size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2362 const SwitchInst& SI) { 2363 size_t numCmps = 0; 2364 2365 // Start with "simple" cases 2366 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2367 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2368 Cases.push_back(Case(SI.getSuccessorValue(i), 2369 SI.getSuccessorValue(i), 2370 SMBB)); 2371 } 2372 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2373 2374 // Merge case into clusters 2375 if (Cases.size() >= 2) 2376 // Must recompute end() each iteration because it may be 2377 // invalidated by erase if we hold on to it 2378 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2379 J != Cases.end(); ) { 2380 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2381 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2382 MachineBasicBlock* nextBB = J->BB; 2383 MachineBasicBlock* currentBB = I->BB; 2384 2385 // If the two neighboring cases go to the same destination, merge them 2386 // into a single case. 2387 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2388 I->High = J->High; 2389 J = Cases.erase(J); 2390 } else { 2391 I = J++; 2392 } 2393 } 2394 2395 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2396 if (I->Low != I->High) 2397 // A range counts double, since it requires two compares. 2398 ++numCmps; 2399 } 2400 2401 return numCmps; 2402} 2403 2404void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2405 MachineBasicBlock *Last) { 2406 // Update JTCases. 2407 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2408 if (JTCases[i].first.HeaderBB == First) 2409 JTCases[i].first.HeaderBB = Last; 2410 2411 // Update BitTestCases. 2412 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2413 if (BitTestCases[i].Parent == First) 2414 BitTestCases[i].Parent = Last; 2415} 2416 2417void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2418 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2419 2420 // Figure out which block is immediately after the current one. 2421 MachineBasicBlock *NextBlock = 0; 2422 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2423 2424 // If there is only the default destination, branch to it if it is not the 2425 // next basic block. Otherwise, just fall through. 2426 if (SI.getNumOperands() == 2) { 2427 // Update machine-CFG edges. 2428 2429 // If this is not a fall-through branch, emit the branch. 2430 SwitchMBB->addSuccessor(Default); 2431 if (Default != NextBlock) 2432 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2433 MVT::Other, getControlRoot(), 2434 DAG.getBasicBlock(Default))); 2435 2436 return; 2437 } 2438 2439 // If there are any non-default case statements, create a vector of Cases 2440 // representing each one, and sort the vector so that we can efficiently 2441 // create a binary search tree from them. 2442 CaseVector Cases; 2443 size_t numCmps = Clusterify(Cases, SI); 2444 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2445 << ". Total compares: " << numCmps << '\n'); 2446 numCmps = 0; 2447 2448 // Get the Value to be switched on and default basic blocks, which will be 2449 // inserted into CaseBlock records, representing basic blocks in the binary 2450 // search tree. 2451 const Value *SV = SI.getOperand(0); 2452 2453 // Push the initial CaseRec onto the worklist 2454 CaseRecVector WorkList; 2455 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2456 CaseRange(Cases.begin(),Cases.end()))); 2457 2458 while (!WorkList.empty()) { 2459 // Grab a record representing a case range to process off the worklist 2460 CaseRec CR = WorkList.back(); 2461 WorkList.pop_back(); 2462 2463 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2464 continue; 2465 2466 // If the range has few cases (two or less) emit a series of specific 2467 // tests. 2468 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2469 continue; 2470 2471 // If the switch has more than 5 blocks, and at least 40% dense, and the 2472 // target supports indirect branches, then emit a jump table rather than 2473 // lowering the switch to a binary tree of conditional branches. 2474 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2475 continue; 2476 2477 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2478 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2479 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2480 } 2481} 2482 2483void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2484 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2485 2486 // Update machine-CFG edges with unique successors. 2487 SmallVector<BasicBlock*, 32> succs; 2488 succs.reserve(I.getNumSuccessors()); 2489 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2490 succs.push_back(I.getSuccessor(i)); 2491 array_pod_sort(succs.begin(), succs.end()); 2492 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2493 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2494 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2495 addSuccessorWithWeight(IndirectBrMBB, Succ); 2496 } 2497 2498 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2499 MVT::Other, getControlRoot(), 2500 getValue(I.getAddress()))); 2501} 2502 2503void SelectionDAGBuilder::visitFSub(const User &I) { 2504 // -0.0 - X --> fneg 2505 Type *Ty = I.getType(); 2506 if (isa<Constant>(I.getOperand(0)) && 2507 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2508 SDValue Op2 = getValue(I.getOperand(1)); 2509 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2510 Op2.getValueType(), Op2)); 2511 return; 2512 } 2513 2514 visitBinary(I, ISD::FSUB); 2515} 2516 2517void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2518 SDValue Op1 = getValue(I.getOperand(0)); 2519 SDValue Op2 = getValue(I.getOperand(1)); 2520 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2521 Op1.getValueType(), Op1, Op2)); 2522} 2523 2524void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2525 SDValue Op1 = getValue(I.getOperand(0)); 2526 SDValue Op2 = getValue(I.getOperand(1)); 2527 2528 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2529 2530 // Coerce the shift amount to the right type if we can. 2531 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2532 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2533 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2534 DebugLoc DL = getCurDebugLoc(); 2535 2536 // If the operand is smaller than the shift count type, promote it. 2537 if (ShiftSize > Op2Size) 2538 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2539 2540 // If the operand is larger than the shift count type but the shift 2541 // count type has enough bits to represent any shift value, truncate 2542 // it now. This is a common case and it exposes the truncate to 2543 // optimization early. 2544 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2545 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2546 // Otherwise we'll need to temporarily settle for some other convenient 2547 // type. Type legalization will make adjustments once the shiftee is split. 2548 else 2549 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2550 } 2551 2552 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2553 Op1.getValueType(), Op1, Op2)); 2554} 2555 2556void SelectionDAGBuilder::visitSDiv(const User &I) { 2557 SDValue Op1 = getValue(I.getOperand(0)); 2558 SDValue Op2 = getValue(I.getOperand(1)); 2559 2560 // Turn exact SDivs into multiplications. 2561 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2562 // exact bit. 2563 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2564 !isa<ConstantSDNode>(Op1) && 2565 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2566 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2567 else 2568 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2569 Op1, Op2)); 2570} 2571 2572void SelectionDAGBuilder::visitICmp(const User &I) { 2573 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2574 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2575 predicate = IC->getPredicate(); 2576 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2577 predicate = ICmpInst::Predicate(IC->getPredicate()); 2578 SDValue Op1 = getValue(I.getOperand(0)); 2579 SDValue Op2 = getValue(I.getOperand(1)); 2580 ISD::CondCode Opcode = getICmpCondCode(predicate); 2581 2582 EVT DestVT = TLI.getValueType(I.getType()); 2583 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2584} 2585 2586void SelectionDAGBuilder::visitFCmp(const User &I) { 2587 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2588 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2589 predicate = FC->getPredicate(); 2590 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2591 predicate = FCmpInst::Predicate(FC->getPredicate()); 2592 SDValue Op1 = getValue(I.getOperand(0)); 2593 SDValue Op2 = getValue(I.getOperand(1)); 2594 ISD::CondCode Condition = getFCmpCondCode(predicate); 2595 EVT DestVT = TLI.getValueType(I.getType()); 2596 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2597} 2598 2599void SelectionDAGBuilder::visitSelect(const User &I) { 2600 SmallVector<EVT, 4> ValueVTs; 2601 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2602 unsigned NumValues = ValueVTs.size(); 2603 if (NumValues == 0) return; 2604 2605 SmallVector<SDValue, 4> Values(NumValues); 2606 SDValue Cond = getValue(I.getOperand(0)); 2607 SDValue TrueVal = getValue(I.getOperand(1)); 2608 SDValue FalseVal = getValue(I.getOperand(2)); 2609 2610 for (unsigned i = 0; i != NumValues; ++i) 2611 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2612 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2613 Cond, 2614 SDValue(TrueVal.getNode(), 2615 TrueVal.getResNo() + i), 2616 SDValue(FalseVal.getNode(), 2617 FalseVal.getResNo() + i)); 2618 2619 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2620 DAG.getVTList(&ValueVTs[0], NumValues), 2621 &Values[0], NumValues)); 2622} 2623 2624void SelectionDAGBuilder::visitTrunc(const User &I) { 2625 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2626 SDValue N = getValue(I.getOperand(0)); 2627 EVT DestVT = TLI.getValueType(I.getType()); 2628 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2629} 2630 2631void SelectionDAGBuilder::visitZExt(const User &I) { 2632 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2633 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2634 SDValue N = getValue(I.getOperand(0)); 2635 EVT DestVT = TLI.getValueType(I.getType()); 2636 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2637} 2638 2639void SelectionDAGBuilder::visitSExt(const User &I) { 2640 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2641 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2642 SDValue N = getValue(I.getOperand(0)); 2643 EVT DestVT = TLI.getValueType(I.getType()); 2644 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2645} 2646 2647void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2648 // FPTrunc is never a no-op cast, no need to check 2649 SDValue N = getValue(I.getOperand(0)); 2650 EVT DestVT = TLI.getValueType(I.getType()); 2651 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2652 DestVT, N, DAG.getIntPtrConstant(0))); 2653} 2654 2655void SelectionDAGBuilder::visitFPExt(const User &I){ 2656 // FPTrunc is never a no-op cast, no need to check 2657 SDValue N = getValue(I.getOperand(0)); 2658 EVT DestVT = TLI.getValueType(I.getType()); 2659 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2660} 2661 2662void SelectionDAGBuilder::visitFPToUI(const User &I) { 2663 // FPToUI is never a no-op cast, no need to check 2664 SDValue N = getValue(I.getOperand(0)); 2665 EVT DestVT = TLI.getValueType(I.getType()); 2666 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2667} 2668 2669void SelectionDAGBuilder::visitFPToSI(const User &I) { 2670 // FPToSI is never a no-op cast, no need to check 2671 SDValue N = getValue(I.getOperand(0)); 2672 EVT DestVT = TLI.getValueType(I.getType()); 2673 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2674} 2675 2676void SelectionDAGBuilder::visitUIToFP(const User &I) { 2677 // UIToFP is never a no-op cast, no need to check 2678 SDValue N = getValue(I.getOperand(0)); 2679 EVT DestVT = TLI.getValueType(I.getType()); 2680 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2681} 2682 2683void SelectionDAGBuilder::visitSIToFP(const User &I){ 2684 // SIToFP is never a no-op cast, no need to check 2685 SDValue N = getValue(I.getOperand(0)); 2686 EVT DestVT = TLI.getValueType(I.getType()); 2687 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2688} 2689 2690void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2691 // What to do depends on the size of the integer and the size of the pointer. 2692 // We can either truncate, zero extend, or no-op, accordingly. 2693 SDValue N = getValue(I.getOperand(0)); 2694 EVT DestVT = TLI.getValueType(I.getType()); 2695 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2696} 2697 2698void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2699 // What to do depends on the size of the integer and the size of the pointer. 2700 // We can either truncate, zero extend, or no-op, accordingly. 2701 SDValue N = getValue(I.getOperand(0)); 2702 EVT DestVT = TLI.getValueType(I.getType()); 2703 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2704} 2705 2706void SelectionDAGBuilder::visitBitCast(const User &I) { 2707 SDValue N = getValue(I.getOperand(0)); 2708 EVT DestVT = TLI.getValueType(I.getType()); 2709 2710 // BitCast assures us that source and destination are the same size so this is 2711 // either a BITCAST or a no-op. 2712 if (DestVT != N.getValueType()) 2713 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2714 DestVT, N)); // convert types. 2715 else 2716 setValue(&I, N); // noop cast. 2717} 2718 2719void SelectionDAGBuilder::visitInsertElement(const User &I) { 2720 SDValue InVec = getValue(I.getOperand(0)); 2721 SDValue InVal = getValue(I.getOperand(1)); 2722 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2723 TLI.getPointerTy(), 2724 getValue(I.getOperand(2))); 2725 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2726 TLI.getValueType(I.getType()), 2727 InVec, InVal, InIdx)); 2728} 2729 2730void SelectionDAGBuilder::visitExtractElement(const User &I) { 2731 SDValue InVec = getValue(I.getOperand(0)); 2732 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2733 TLI.getPointerTy(), 2734 getValue(I.getOperand(1))); 2735 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2736 TLI.getValueType(I.getType()), InVec, InIdx)); 2737} 2738 2739// Utility for visitShuffleVector - Returns true if the mask is mask starting 2740// from SIndx and increasing to the element length (undefs are allowed). 2741static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2742 unsigned MaskNumElts = Mask.size(); 2743 for (unsigned i = 0; i != MaskNumElts; ++i) 2744 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2745 return false; 2746 return true; 2747} 2748 2749void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2750 SmallVector<int, 8> Mask; 2751 SDValue Src1 = getValue(I.getOperand(0)); 2752 SDValue Src2 = getValue(I.getOperand(1)); 2753 2754 // Convert the ConstantVector mask operand into an array of ints, with -1 2755 // representing undef values. 2756 SmallVector<Constant*, 8> MaskElts; 2757 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2758 unsigned MaskNumElts = MaskElts.size(); 2759 for (unsigned i = 0; i != MaskNumElts; ++i) { 2760 if (isa<UndefValue>(MaskElts[i])) 2761 Mask.push_back(-1); 2762 else 2763 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2764 } 2765 2766 EVT VT = TLI.getValueType(I.getType()); 2767 EVT SrcVT = Src1.getValueType(); 2768 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2769 2770 if (SrcNumElts == MaskNumElts) { 2771 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2772 &Mask[0])); 2773 return; 2774 } 2775 2776 // Normalize the shuffle vector since mask and vector length don't match. 2777 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2778 // Mask is longer than the source vectors and is a multiple of the source 2779 // vectors. We can use concatenate vector to make the mask and vectors 2780 // lengths match. 2781 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2782 // The shuffle is concatenating two vectors together. 2783 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2784 VT, Src1, Src2)); 2785 return; 2786 } 2787 2788 // Pad both vectors with undefs to make them the same length as the mask. 2789 unsigned NumConcat = MaskNumElts / SrcNumElts; 2790 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2791 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2792 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2793 2794 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2795 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2796 MOps1[0] = Src1; 2797 MOps2[0] = Src2; 2798 2799 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2800 getCurDebugLoc(), VT, 2801 &MOps1[0], NumConcat); 2802 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2803 getCurDebugLoc(), VT, 2804 &MOps2[0], NumConcat); 2805 2806 // Readjust mask for new input vector length. 2807 SmallVector<int, 8> MappedOps; 2808 for (unsigned i = 0; i != MaskNumElts; ++i) { 2809 int Idx = Mask[i]; 2810 if (Idx < (int)SrcNumElts) 2811 MappedOps.push_back(Idx); 2812 else 2813 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2814 } 2815 2816 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2817 &MappedOps[0])); 2818 return; 2819 } 2820 2821 if (SrcNumElts > MaskNumElts) { 2822 // Analyze the access pattern of the vector to see if we can extract 2823 // two subvectors and do the shuffle. The analysis is done by calculating 2824 // the range of elements the mask access on both vectors. 2825 int MinRange[2] = { static_cast<int>(SrcNumElts+1), 2826 static_cast<int>(SrcNumElts+1)}; 2827 int MaxRange[2] = {-1, -1}; 2828 2829 for (unsigned i = 0; i != MaskNumElts; ++i) { 2830 int Idx = Mask[i]; 2831 int Input = 0; 2832 if (Idx < 0) 2833 continue; 2834 2835 if (Idx >= (int)SrcNumElts) { 2836 Input = 1; 2837 Idx -= SrcNumElts; 2838 } 2839 if (Idx > MaxRange[Input]) 2840 MaxRange[Input] = Idx; 2841 if (Idx < MinRange[Input]) 2842 MinRange[Input] = Idx; 2843 } 2844 2845 // Check if the access is smaller than the vector size and can we find 2846 // a reasonable extract index. 2847 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2848 // Extract. 2849 int StartIdx[2]; // StartIdx to extract from 2850 for (int Input=0; Input < 2; ++Input) { 2851 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2852 RangeUse[Input] = 0; // Unused 2853 StartIdx[Input] = 0; 2854 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2855 // Fits within range but we should see if we can find a good 2856 // start index that is a multiple of the mask length. 2857 if (MaxRange[Input] < (int)MaskNumElts) { 2858 RangeUse[Input] = 1; // Extract from beginning of the vector 2859 StartIdx[Input] = 0; 2860 } else { 2861 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2862 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2863 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2864 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2865 } 2866 } 2867 } 2868 2869 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2870 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2871 return; 2872 } 2873 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2874 // Extract appropriate subvector and generate a vector shuffle 2875 for (int Input=0; Input < 2; ++Input) { 2876 SDValue &Src = Input == 0 ? Src1 : Src2; 2877 if (RangeUse[Input] == 0) 2878 Src = DAG.getUNDEF(VT); 2879 else 2880 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2881 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2882 } 2883 2884 // Calculate new mask. 2885 SmallVector<int, 8> MappedOps; 2886 for (unsigned i = 0; i != MaskNumElts; ++i) { 2887 int Idx = Mask[i]; 2888 if (Idx < 0) 2889 MappedOps.push_back(Idx); 2890 else if (Idx < (int)SrcNumElts) 2891 MappedOps.push_back(Idx - StartIdx[0]); 2892 else 2893 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2894 } 2895 2896 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2897 &MappedOps[0])); 2898 return; 2899 } 2900 } 2901 2902 // We can't use either concat vectors or extract subvectors so fall back to 2903 // replacing the shuffle with extract and build vector. 2904 // to insert and build vector. 2905 EVT EltVT = VT.getVectorElementType(); 2906 EVT PtrVT = TLI.getPointerTy(); 2907 SmallVector<SDValue,8> Ops; 2908 for (unsigned i = 0; i != MaskNumElts; ++i) { 2909 if (Mask[i] < 0) { 2910 Ops.push_back(DAG.getUNDEF(EltVT)); 2911 } else { 2912 int Idx = Mask[i]; 2913 SDValue Res; 2914 2915 if (Idx < (int)SrcNumElts) 2916 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2917 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2918 else 2919 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2920 EltVT, Src2, 2921 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2922 2923 Ops.push_back(Res); 2924 } 2925 } 2926 2927 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2928 VT, &Ops[0], Ops.size())); 2929} 2930 2931void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2932 const Value *Op0 = I.getOperand(0); 2933 const Value *Op1 = I.getOperand(1); 2934 Type *AggTy = I.getType(); 2935 Type *ValTy = Op1->getType(); 2936 bool IntoUndef = isa<UndefValue>(Op0); 2937 bool FromUndef = isa<UndefValue>(Op1); 2938 2939 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2940 2941 SmallVector<EVT, 4> AggValueVTs; 2942 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2943 SmallVector<EVT, 4> ValValueVTs; 2944 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2945 2946 unsigned NumAggValues = AggValueVTs.size(); 2947 unsigned NumValValues = ValValueVTs.size(); 2948 SmallVector<SDValue, 4> Values(NumAggValues); 2949 2950 SDValue Agg = getValue(Op0); 2951 unsigned i = 0; 2952 // Copy the beginning value(s) from the original aggregate. 2953 for (; i != LinearIndex; ++i) 2954 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2955 SDValue(Agg.getNode(), Agg.getResNo() + i); 2956 // Copy values from the inserted value(s). 2957 if (NumValValues) { 2958 SDValue Val = getValue(Op1); 2959 for (; i != LinearIndex + NumValValues; ++i) 2960 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2961 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2962 } 2963 // Copy remaining value(s) from the original aggregate. 2964 for (; i != NumAggValues; ++i) 2965 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2966 SDValue(Agg.getNode(), Agg.getResNo() + i); 2967 2968 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2969 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2970 &Values[0], NumAggValues)); 2971} 2972 2973void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2974 const Value *Op0 = I.getOperand(0); 2975 Type *AggTy = Op0->getType(); 2976 Type *ValTy = I.getType(); 2977 bool OutOfUndef = isa<UndefValue>(Op0); 2978 2979 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2980 2981 SmallVector<EVT, 4> ValValueVTs; 2982 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2983 2984 unsigned NumValValues = ValValueVTs.size(); 2985 2986 // Ignore a extractvalue that produces an empty object 2987 if (!NumValValues) { 2988 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 2989 return; 2990 } 2991 2992 SmallVector<SDValue, 4> Values(NumValValues); 2993 2994 SDValue Agg = getValue(Op0); 2995 // Copy out the selected value(s). 2996 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2997 Values[i - LinearIndex] = 2998 OutOfUndef ? 2999 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3000 SDValue(Agg.getNode(), Agg.getResNo() + i); 3001 3002 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3003 DAG.getVTList(&ValValueVTs[0], NumValValues), 3004 &Values[0], NumValValues)); 3005} 3006 3007void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3008 SDValue N = getValue(I.getOperand(0)); 3009 Type *Ty = I.getOperand(0)->getType(); 3010 3011 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3012 OI != E; ++OI) { 3013 const Value *Idx = *OI; 3014 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3015 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3016 if (Field) { 3017 // N = N + Offset 3018 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3019 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3020 DAG.getIntPtrConstant(Offset)); 3021 } 3022 3023 Ty = StTy->getElementType(Field); 3024 } else { 3025 Ty = cast<SequentialType>(Ty)->getElementType(); 3026 3027 // If this is a constant subscript, handle it quickly. 3028 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3029 if (CI->isZero()) continue; 3030 uint64_t Offs = 3031 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3032 SDValue OffsVal; 3033 EVT PTy = TLI.getPointerTy(); 3034 unsigned PtrBits = PTy.getSizeInBits(); 3035 if (PtrBits < 64) 3036 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3037 TLI.getPointerTy(), 3038 DAG.getConstant(Offs, MVT::i64)); 3039 else 3040 OffsVal = DAG.getIntPtrConstant(Offs); 3041 3042 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3043 OffsVal); 3044 continue; 3045 } 3046 3047 // N = N + Idx * ElementSize; 3048 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3049 TD->getTypeAllocSize(Ty)); 3050 SDValue IdxN = getValue(Idx); 3051 3052 // If the index is smaller or larger than intptr_t, truncate or extend 3053 // it. 3054 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3055 3056 // If this is a multiply by a power of two, turn it into a shl 3057 // immediately. This is a very common case. 3058 if (ElementSize != 1) { 3059 if (ElementSize.isPowerOf2()) { 3060 unsigned Amt = ElementSize.logBase2(); 3061 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3062 N.getValueType(), IdxN, 3063 DAG.getConstant(Amt, TLI.getPointerTy())); 3064 } else { 3065 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3066 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3067 N.getValueType(), IdxN, Scale); 3068 } 3069 } 3070 3071 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3072 N.getValueType(), N, IdxN); 3073 } 3074 } 3075 3076 setValue(&I, N); 3077} 3078 3079void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3080 // If this is a fixed sized alloca in the entry block of the function, 3081 // allocate it statically on the stack. 3082 if (FuncInfo.StaticAllocaMap.count(&I)) 3083 return; // getValue will auto-populate this. 3084 3085 Type *Ty = I.getAllocatedType(); 3086 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3087 unsigned Align = 3088 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3089 I.getAlignment()); 3090 3091 SDValue AllocSize = getValue(I.getArraySize()); 3092 3093 EVT IntPtr = TLI.getPointerTy(); 3094 if (AllocSize.getValueType() != IntPtr) 3095 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3096 3097 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3098 AllocSize, 3099 DAG.getConstant(TySize, IntPtr)); 3100 3101 // Handle alignment. If the requested alignment is less than or equal to 3102 // the stack alignment, ignore it. If the size is greater than or equal to 3103 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3104 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3105 if (Align <= StackAlign) 3106 Align = 0; 3107 3108 // Round the size of the allocation up to the stack alignment size 3109 // by add SA-1 to the size. 3110 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3111 AllocSize.getValueType(), AllocSize, 3112 DAG.getIntPtrConstant(StackAlign-1)); 3113 3114 // Mask out the low bits for alignment purposes. 3115 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3116 AllocSize.getValueType(), AllocSize, 3117 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3118 3119 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3120 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3121 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3122 VTs, Ops, 3); 3123 setValue(&I, DSA); 3124 DAG.setRoot(DSA.getValue(1)); 3125 3126 // Inform the Frame Information that we have just allocated a variable-sized 3127 // object. 3128 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3129} 3130 3131void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3132 const Value *SV = I.getOperand(0); 3133 SDValue Ptr = getValue(SV); 3134 3135 Type *Ty = I.getType(); 3136 3137 bool isVolatile = I.isVolatile(); 3138 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3139 unsigned Alignment = I.getAlignment(); 3140 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3141 3142 SmallVector<EVT, 4> ValueVTs; 3143 SmallVector<uint64_t, 4> Offsets; 3144 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3145 unsigned NumValues = ValueVTs.size(); 3146 if (NumValues == 0) 3147 return; 3148 3149 SDValue Root; 3150 bool ConstantMemory = false; 3151 if (I.isVolatile() || NumValues > MaxParallelChains) 3152 // Serialize volatile loads with other side effects. 3153 Root = getRoot(); 3154 else if (AA->pointsToConstantMemory( 3155 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3156 // Do not serialize (non-volatile) loads of constant memory with anything. 3157 Root = DAG.getEntryNode(); 3158 ConstantMemory = true; 3159 } else { 3160 // Do not serialize non-volatile loads against each other. 3161 Root = DAG.getRoot(); 3162 } 3163 3164 SmallVector<SDValue, 4> Values(NumValues); 3165 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3166 NumValues)); 3167 EVT PtrVT = Ptr.getValueType(); 3168 unsigned ChainI = 0; 3169 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3170 // Serializing loads here may result in excessive register pressure, and 3171 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3172 // could recover a bit by hoisting nodes upward in the chain by recognizing 3173 // they are side-effect free or do not alias. The optimizer should really 3174 // avoid this case by converting large object/array copies to llvm.memcpy 3175 // (MaxParallelChains should always remain as failsafe). 3176 if (ChainI == MaxParallelChains) { 3177 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3178 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3179 MVT::Other, &Chains[0], ChainI); 3180 Root = Chain; 3181 ChainI = 0; 3182 } 3183 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3184 PtrVT, Ptr, 3185 DAG.getConstant(Offsets[i], PtrVT)); 3186 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3187 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3188 isNonTemporal, Alignment, TBAAInfo); 3189 3190 Values[i] = L; 3191 Chains[ChainI] = L.getValue(1); 3192 } 3193 3194 if (!ConstantMemory) { 3195 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3196 MVT::Other, &Chains[0], ChainI); 3197 if (isVolatile) 3198 DAG.setRoot(Chain); 3199 else 3200 PendingLoads.push_back(Chain); 3201 } 3202 3203 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3204 DAG.getVTList(&ValueVTs[0], NumValues), 3205 &Values[0], NumValues)); 3206} 3207 3208void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3209 const Value *SrcV = I.getOperand(0); 3210 const Value *PtrV = I.getOperand(1); 3211 3212 SmallVector<EVT, 4> ValueVTs; 3213 SmallVector<uint64_t, 4> Offsets; 3214 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3215 unsigned NumValues = ValueVTs.size(); 3216 if (NumValues == 0) 3217 return; 3218 3219 // Get the lowered operands. Note that we do this after 3220 // checking if NumResults is zero, because with zero results 3221 // the operands won't have values in the map. 3222 SDValue Src = getValue(SrcV); 3223 SDValue Ptr = getValue(PtrV); 3224 3225 SDValue Root = getRoot(); 3226 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3227 NumValues)); 3228 EVT PtrVT = Ptr.getValueType(); 3229 bool isVolatile = I.isVolatile(); 3230 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3231 unsigned Alignment = I.getAlignment(); 3232 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3233 3234 unsigned ChainI = 0; 3235 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3236 // See visitLoad comments. 3237 if (ChainI == MaxParallelChains) { 3238 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3239 MVT::Other, &Chains[0], ChainI); 3240 Root = Chain; 3241 ChainI = 0; 3242 } 3243 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3244 DAG.getConstant(Offsets[i], PtrVT)); 3245 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3246 SDValue(Src.getNode(), Src.getResNo() + i), 3247 Add, MachinePointerInfo(PtrV, Offsets[i]), 3248 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3249 Chains[ChainI] = St; 3250 } 3251 3252 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3253 MVT::Other, &Chains[0], ChainI); 3254 ++SDNodeOrder; 3255 AssignOrderingToNode(StoreNode.getNode()); 3256 DAG.setRoot(StoreNode); 3257} 3258 3259void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3260 SDValue Root = getRoot(); 3261 SDValue L = 3262 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 3263 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3264 Root, 3265 getValue(I.getPointerOperand()), 3266 getValue(I.getCompareOperand()), 3267 getValue(I.getNewValOperand()), 3268 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3269 I.getOrdering(), I.getSynchScope()); 3270 setValue(&I, L); 3271 DAG.setRoot(L.getValue(1)); 3272} 3273 3274void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3275 ISD::NodeType NT; 3276 switch (I.getOperation()) { 3277 default: llvm_unreachable("Unknown atomicrmw operation"); return; 3278 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3279 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3280 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3281 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3282 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3283 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3284 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3285 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3286 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3287 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3288 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3289 } 3290 SDValue L = 3291 DAG.getAtomic(NT, getCurDebugLoc(), 3292 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3293 getRoot(), 3294 getValue(I.getPointerOperand()), 3295 getValue(I.getValOperand()), 3296 I.getPointerOperand(), 0 /* Alignment */, 3297 I.getOrdering(), I.getSynchScope()); 3298 setValue(&I, L); 3299 DAG.setRoot(L.getValue(1)); 3300} 3301 3302void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3303 DebugLoc dl = getCurDebugLoc(); 3304 SDValue Ops[3]; 3305 Ops[0] = getRoot(); 3306 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3307 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3308 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3309} 3310 3311/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3312/// node. 3313void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3314 unsigned Intrinsic) { 3315 bool HasChain = !I.doesNotAccessMemory(); 3316 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3317 3318 // Build the operand list. 3319 SmallVector<SDValue, 8> Ops; 3320 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3321 if (OnlyLoad) { 3322 // We don't need to serialize loads against other loads. 3323 Ops.push_back(DAG.getRoot()); 3324 } else { 3325 Ops.push_back(getRoot()); 3326 } 3327 } 3328 3329 // Info is set by getTgtMemInstrinsic 3330 TargetLowering::IntrinsicInfo Info; 3331 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3332 3333 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3334 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3335 Info.opc == ISD::INTRINSIC_W_CHAIN) 3336 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3337 3338 // Add all operands of the call to the operand list. 3339 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3340 SDValue Op = getValue(I.getArgOperand(i)); 3341 assert(TLI.isTypeLegal(Op.getValueType()) && 3342 "Intrinsic uses a non-legal type?"); 3343 Ops.push_back(Op); 3344 } 3345 3346 SmallVector<EVT, 4> ValueVTs; 3347 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3348#ifndef NDEBUG 3349 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3350 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3351 "Intrinsic uses a non-legal type?"); 3352 } 3353#endif // NDEBUG 3354 3355 if (HasChain) 3356 ValueVTs.push_back(MVT::Other); 3357 3358 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3359 3360 // Create the node. 3361 SDValue Result; 3362 if (IsTgtIntrinsic) { 3363 // This is target intrinsic that touches memory 3364 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3365 VTs, &Ops[0], Ops.size(), 3366 Info.memVT, 3367 MachinePointerInfo(Info.ptrVal, Info.offset), 3368 Info.align, Info.vol, 3369 Info.readMem, Info.writeMem); 3370 } else if (!HasChain) { 3371 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3372 VTs, &Ops[0], Ops.size()); 3373 } else if (!I.getType()->isVoidTy()) { 3374 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3375 VTs, &Ops[0], Ops.size()); 3376 } else { 3377 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3378 VTs, &Ops[0], Ops.size()); 3379 } 3380 3381 if (HasChain) { 3382 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3383 if (OnlyLoad) 3384 PendingLoads.push_back(Chain); 3385 else 3386 DAG.setRoot(Chain); 3387 } 3388 3389 if (!I.getType()->isVoidTy()) { 3390 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3391 EVT VT = TLI.getValueType(PTy); 3392 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3393 } 3394 3395 setValue(&I, Result); 3396 } 3397} 3398 3399/// GetSignificand - Get the significand and build it into a floating-point 3400/// number with exponent of 1: 3401/// 3402/// Op = (Op & 0x007fffff) | 0x3f800000; 3403/// 3404/// where Op is the hexidecimal representation of floating point value. 3405static SDValue 3406GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3407 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3408 DAG.getConstant(0x007fffff, MVT::i32)); 3409 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3410 DAG.getConstant(0x3f800000, MVT::i32)); 3411 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3412} 3413 3414/// GetExponent - Get the exponent: 3415/// 3416/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3417/// 3418/// where Op is the hexidecimal representation of floating point value. 3419static SDValue 3420GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3421 DebugLoc dl) { 3422 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3423 DAG.getConstant(0x7f800000, MVT::i32)); 3424 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3425 DAG.getConstant(23, TLI.getPointerTy())); 3426 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3427 DAG.getConstant(127, MVT::i32)); 3428 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3429} 3430 3431/// getF32Constant - Get 32-bit floating point constant. 3432static SDValue 3433getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3434 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3435} 3436 3437/// Inlined utility function to implement binary input atomic intrinsics for 3438/// visitIntrinsicCall: I is a call instruction 3439/// Op is the associated NodeType for I 3440const char * 3441SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3442 ISD::NodeType Op) { 3443 SDValue Root = getRoot(); 3444 SDValue L = 3445 DAG.getAtomic(Op, getCurDebugLoc(), 3446 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3447 Root, 3448 getValue(I.getArgOperand(0)), 3449 getValue(I.getArgOperand(1)), 3450 I.getArgOperand(0), 0 /* Alignment */, 3451 Monotonic, CrossThread); 3452 setValue(&I, L); 3453 DAG.setRoot(L.getValue(1)); 3454 return 0; 3455} 3456 3457// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3458const char * 3459SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3460 SDValue Op1 = getValue(I.getArgOperand(0)); 3461 SDValue Op2 = getValue(I.getArgOperand(1)); 3462 3463 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3464 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3465 return 0; 3466} 3467 3468/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3469/// limited-precision mode. 3470void 3471SelectionDAGBuilder::visitExp(const CallInst &I) { 3472 SDValue result; 3473 DebugLoc dl = getCurDebugLoc(); 3474 3475 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3476 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3477 SDValue Op = getValue(I.getArgOperand(0)); 3478 3479 // Put the exponent in the right bit position for later addition to the 3480 // final result: 3481 // 3482 // #define LOG2OFe 1.4426950f 3483 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3484 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3485 getF32Constant(DAG, 0x3fb8aa3b)); 3486 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3487 3488 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3489 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3490 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3491 3492 // IntegerPartOfX <<= 23; 3493 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3494 DAG.getConstant(23, TLI.getPointerTy())); 3495 3496 if (LimitFloatPrecision <= 6) { 3497 // For floating-point precision of 6: 3498 // 3499 // TwoToFractionalPartOfX = 3500 // 0.997535578f + 3501 // (0.735607626f + 0.252464424f * x) * x; 3502 // 3503 // error 0.0144103317, which is 6 bits 3504 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3505 getF32Constant(DAG, 0x3e814304)); 3506 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3507 getF32Constant(DAG, 0x3f3c50c8)); 3508 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3509 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3510 getF32Constant(DAG, 0x3f7f5e7e)); 3511 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3512 3513 // Add the exponent into the result in integer domain. 3514 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3515 TwoToFracPartOfX, IntegerPartOfX); 3516 3517 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3518 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3519 // For floating-point precision of 12: 3520 // 3521 // TwoToFractionalPartOfX = 3522 // 0.999892986f + 3523 // (0.696457318f + 3524 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3525 // 3526 // 0.000107046256 error, which is 13 to 14 bits 3527 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3528 getF32Constant(DAG, 0x3da235e3)); 3529 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3530 getF32Constant(DAG, 0x3e65b8f3)); 3531 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3532 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3533 getF32Constant(DAG, 0x3f324b07)); 3534 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3535 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3536 getF32Constant(DAG, 0x3f7ff8fd)); 3537 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3538 3539 // Add the exponent into the result in integer domain. 3540 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3541 TwoToFracPartOfX, IntegerPartOfX); 3542 3543 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3544 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3545 // For floating-point precision of 18: 3546 // 3547 // TwoToFractionalPartOfX = 3548 // 0.999999982f + 3549 // (0.693148872f + 3550 // (0.240227044f + 3551 // (0.554906021e-1f + 3552 // (0.961591928e-2f + 3553 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3554 // 3555 // error 2.47208000*10^(-7), which is better than 18 bits 3556 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3557 getF32Constant(DAG, 0x3924b03e)); 3558 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3559 getF32Constant(DAG, 0x3ab24b87)); 3560 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3561 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3562 getF32Constant(DAG, 0x3c1d8c17)); 3563 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3564 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3565 getF32Constant(DAG, 0x3d634a1d)); 3566 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3567 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3568 getF32Constant(DAG, 0x3e75fe14)); 3569 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3570 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3571 getF32Constant(DAG, 0x3f317234)); 3572 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3573 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3574 getF32Constant(DAG, 0x3f800000)); 3575 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3576 MVT::i32, t13); 3577 3578 // Add the exponent into the result in integer domain. 3579 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3580 TwoToFracPartOfX, IntegerPartOfX); 3581 3582 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3583 } 3584 } else { 3585 // No special expansion. 3586 result = DAG.getNode(ISD::FEXP, dl, 3587 getValue(I.getArgOperand(0)).getValueType(), 3588 getValue(I.getArgOperand(0))); 3589 } 3590 3591 setValue(&I, result); 3592} 3593 3594/// visitLog - Lower a log intrinsic. Handles the special sequences for 3595/// limited-precision mode. 3596void 3597SelectionDAGBuilder::visitLog(const CallInst &I) { 3598 SDValue result; 3599 DebugLoc dl = getCurDebugLoc(); 3600 3601 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3602 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3603 SDValue Op = getValue(I.getArgOperand(0)); 3604 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3605 3606 // Scale the exponent by log(2) [0.69314718f]. 3607 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3608 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3609 getF32Constant(DAG, 0x3f317218)); 3610 3611 // Get the significand and build it into a floating-point number with 3612 // exponent of 1. 3613 SDValue X = GetSignificand(DAG, Op1, dl); 3614 3615 if (LimitFloatPrecision <= 6) { 3616 // For floating-point precision of 6: 3617 // 3618 // LogofMantissa = 3619 // -1.1609546f + 3620 // (1.4034025f - 0.23903021f * x) * x; 3621 // 3622 // error 0.0034276066, which is better than 8 bits 3623 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3624 getF32Constant(DAG, 0xbe74c456)); 3625 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3626 getF32Constant(DAG, 0x3fb3a2b1)); 3627 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3628 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3629 getF32Constant(DAG, 0x3f949a29)); 3630 3631 result = DAG.getNode(ISD::FADD, dl, 3632 MVT::f32, LogOfExponent, LogOfMantissa); 3633 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3634 // For floating-point precision of 12: 3635 // 3636 // LogOfMantissa = 3637 // -1.7417939f + 3638 // (2.8212026f + 3639 // (-1.4699568f + 3640 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3641 // 3642 // error 0.000061011436, which is 14 bits 3643 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3644 getF32Constant(DAG, 0xbd67b6d6)); 3645 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3646 getF32Constant(DAG, 0x3ee4f4b8)); 3647 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3648 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3649 getF32Constant(DAG, 0x3fbc278b)); 3650 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3651 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3652 getF32Constant(DAG, 0x40348e95)); 3653 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3654 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3655 getF32Constant(DAG, 0x3fdef31a)); 3656 3657 result = DAG.getNode(ISD::FADD, dl, 3658 MVT::f32, LogOfExponent, LogOfMantissa); 3659 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3660 // For floating-point precision of 18: 3661 // 3662 // LogOfMantissa = 3663 // -2.1072184f + 3664 // (4.2372794f + 3665 // (-3.7029485f + 3666 // (2.2781945f + 3667 // (-0.87823314f + 3668 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3669 // 3670 // error 0.0000023660568, which is better than 18 bits 3671 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3672 getF32Constant(DAG, 0xbc91e5ac)); 3673 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3674 getF32Constant(DAG, 0x3e4350aa)); 3675 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3676 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3677 getF32Constant(DAG, 0x3f60d3e3)); 3678 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3679 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3680 getF32Constant(DAG, 0x4011cdf0)); 3681 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3682 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3683 getF32Constant(DAG, 0x406cfd1c)); 3684 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3685 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3686 getF32Constant(DAG, 0x408797cb)); 3687 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3688 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3689 getF32Constant(DAG, 0x4006dcab)); 3690 3691 result = DAG.getNode(ISD::FADD, dl, 3692 MVT::f32, LogOfExponent, LogOfMantissa); 3693 } 3694 } else { 3695 // No special expansion. 3696 result = DAG.getNode(ISD::FLOG, dl, 3697 getValue(I.getArgOperand(0)).getValueType(), 3698 getValue(I.getArgOperand(0))); 3699 } 3700 3701 setValue(&I, result); 3702} 3703 3704/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3705/// limited-precision mode. 3706void 3707SelectionDAGBuilder::visitLog2(const CallInst &I) { 3708 SDValue result; 3709 DebugLoc dl = getCurDebugLoc(); 3710 3711 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3712 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3713 SDValue Op = getValue(I.getArgOperand(0)); 3714 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3715 3716 // Get the exponent. 3717 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3718 3719 // Get the significand and build it into a floating-point number with 3720 // exponent of 1. 3721 SDValue X = GetSignificand(DAG, Op1, dl); 3722 3723 // Different possible minimax approximations of significand in 3724 // floating-point for various degrees of accuracy over [1,2]. 3725 if (LimitFloatPrecision <= 6) { 3726 // For floating-point precision of 6: 3727 // 3728 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3729 // 3730 // error 0.0049451742, which is more than 7 bits 3731 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3732 getF32Constant(DAG, 0xbeb08fe0)); 3733 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3734 getF32Constant(DAG, 0x40019463)); 3735 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3736 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3737 getF32Constant(DAG, 0x3fd6633d)); 3738 3739 result = DAG.getNode(ISD::FADD, dl, 3740 MVT::f32, LogOfExponent, Log2ofMantissa); 3741 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3742 // For floating-point precision of 12: 3743 // 3744 // Log2ofMantissa = 3745 // -2.51285454f + 3746 // (4.07009056f + 3747 // (-2.12067489f + 3748 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3749 // 3750 // error 0.0000876136000, which is better than 13 bits 3751 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3752 getF32Constant(DAG, 0xbda7262e)); 3753 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3754 getF32Constant(DAG, 0x3f25280b)); 3755 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3756 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3757 getF32Constant(DAG, 0x4007b923)); 3758 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3759 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3760 getF32Constant(DAG, 0x40823e2f)); 3761 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3762 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3763 getF32Constant(DAG, 0x4020d29c)); 3764 3765 result = DAG.getNode(ISD::FADD, dl, 3766 MVT::f32, LogOfExponent, Log2ofMantissa); 3767 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3768 // For floating-point precision of 18: 3769 // 3770 // Log2ofMantissa = 3771 // -3.0400495f + 3772 // (6.1129976f + 3773 // (-5.3420409f + 3774 // (3.2865683f + 3775 // (-1.2669343f + 3776 // (0.27515199f - 3777 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3778 // 3779 // error 0.0000018516, which is better than 18 bits 3780 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3781 getF32Constant(DAG, 0xbcd2769e)); 3782 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3783 getF32Constant(DAG, 0x3e8ce0b9)); 3784 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3785 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3786 getF32Constant(DAG, 0x3fa22ae7)); 3787 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3788 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3789 getF32Constant(DAG, 0x40525723)); 3790 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3791 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3792 getF32Constant(DAG, 0x40aaf200)); 3793 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3794 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3795 getF32Constant(DAG, 0x40c39dad)); 3796 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3797 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3798 getF32Constant(DAG, 0x4042902c)); 3799 3800 result = DAG.getNode(ISD::FADD, dl, 3801 MVT::f32, LogOfExponent, Log2ofMantissa); 3802 } 3803 } else { 3804 // No special expansion. 3805 result = DAG.getNode(ISD::FLOG2, dl, 3806 getValue(I.getArgOperand(0)).getValueType(), 3807 getValue(I.getArgOperand(0))); 3808 } 3809 3810 setValue(&I, result); 3811} 3812 3813/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3814/// limited-precision mode. 3815void 3816SelectionDAGBuilder::visitLog10(const CallInst &I) { 3817 SDValue result; 3818 DebugLoc dl = getCurDebugLoc(); 3819 3820 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3821 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3822 SDValue Op = getValue(I.getArgOperand(0)); 3823 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3824 3825 // Scale the exponent by log10(2) [0.30102999f]. 3826 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3827 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3828 getF32Constant(DAG, 0x3e9a209a)); 3829 3830 // Get the significand and build it into a floating-point number with 3831 // exponent of 1. 3832 SDValue X = GetSignificand(DAG, Op1, dl); 3833 3834 if (LimitFloatPrecision <= 6) { 3835 // For floating-point precision of 6: 3836 // 3837 // Log10ofMantissa = 3838 // -0.50419619f + 3839 // (0.60948995f - 0.10380950f * x) * x; 3840 // 3841 // error 0.0014886165, which is 6 bits 3842 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3843 getF32Constant(DAG, 0xbdd49a13)); 3844 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3845 getF32Constant(DAG, 0x3f1c0789)); 3846 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3847 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3848 getF32Constant(DAG, 0x3f011300)); 3849 3850 result = DAG.getNode(ISD::FADD, dl, 3851 MVT::f32, LogOfExponent, Log10ofMantissa); 3852 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3853 // For floating-point precision of 12: 3854 // 3855 // Log10ofMantissa = 3856 // -0.64831180f + 3857 // (0.91751397f + 3858 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3859 // 3860 // error 0.00019228036, which is better than 12 bits 3861 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3862 getF32Constant(DAG, 0x3d431f31)); 3863 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3864 getF32Constant(DAG, 0x3ea21fb2)); 3865 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3866 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3867 getF32Constant(DAG, 0x3f6ae232)); 3868 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3869 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3870 getF32Constant(DAG, 0x3f25f7c3)); 3871 3872 result = DAG.getNode(ISD::FADD, dl, 3873 MVT::f32, LogOfExponent, Log10ofMantissa); 3874 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3875 // For floating-point precision of 18: 3876 // 3877 // Log10ofMantissa = 3878 // -0.84299375f + 3879 // (1.5327582f + 3880 // (-1.0688956f + 3881 // (0.49102474f + 3882 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3883 // 3884 // error 0.0000037995730, which is better than 18 bits 3885 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3886 getF32Constant(DAG, 0x3c5d51ce)); 3887 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3888 getF32Constant(DAG, 0x3e00685a)); 3889 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3890 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3891 getF32Constant(DAG, 0x3efb6798)); 3892 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3893 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3894 getF32Constant(DAG, 0x3f88d192)); 3895 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3896 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3897 getF32Constant(DAG, 0x3fc4316c)); 3898 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3899 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3900 getF32Constant(DAG, 0x3f57ce70)); 3901 3902 result = DAG.getNode(ISD::FADD, dl, 3903 MVT::f32, LogOfExponent, Log10ofMantissa); 3904 } 3905 } else { 3906 // No special expansion. 3907 result = DAG.getNode(ISD::FLOG10, dl, 3908 getValue(I.getArgOperand(0)).getValueType(), 3909 getValue(I.getArgOperand(0))); 3910 } 3911 3912 setValue(&I, result); 3913} 3914 3915/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3916/// limited-precision mode. 3917void 3918SelectionDAGBuilder::visitExp2(const CallInst &I) { 3919 SDValue result; 3920 DebugLoc dl = getCurDebugLoc(); 3921 3922 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3923 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3924 SDValue Op = getValue(I.getArgOperand(0)); 3925 3926 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3927 3928 // FractionalPartOfX = x - (float)IntegerPartOfX; 3929 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3930 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3931 3932 // IntegerPartOfX <<= 23; 3933 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3934 DAG.getConstant(23, TLI.getPointerTy())); 3935 3936 if (LimitFloatPrecision <= 6) { 3937 // For floating-point precision of 6: 3938 // 3939 // TwoToFractionalPartOfX = 3940 // 0.997535578f + 3941 // (0.735607626f + 0.252464424f * x) * x; 3942 // 3943 // error 0.0144103317, which is 6 bits 3944 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3945 getF32Constant(DAG, 0x3e814304)); 3946 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3947 getF32Constant(DAG, 0x3f3c50c8)); 3948 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3949 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3950 getF32Constant(DAG, 0x3f7f5e7e)); 3951 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3952 SDValue TwoToFractionalPartOfX = 3953 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3954 3955 result = DAG.getNode(ISD::BITCAST, dl, 3956 MVT::f32, TwoToFractionalPartOfX); 3957 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3958 // For floating-point precision of 12: 3959 // 3960 // TwoToFractionalPartOfX = 3961 // 0.999892986f + 3962 // (0.696457318f + 3963 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3964 // 3965 // error 0.000107046256, which is 13 to 14 bits 3966 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3967 getF32Constant(DAG, 0x3da235e3)); 3968 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3969 getF32Constant(DAG, 0x3e65b8f3)); 3970 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3971 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3972 getF32Constant(DAG, 0x3f324b07)); 3973 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3974 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3975 getF32Constant(DAG, 0x3f7ff8fd)); 3976 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3977 SDValue TwoToFractionalPartOfX = 3978 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3979 3980 result = DAG.getNode(ISD::BITCAST, dl, 3981 MVT::f32, TwoToFractionalPartOfX); 3982 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3983 // For floating-point precision of 18: 3984 // 3985 // TwoToFractionalPartOfX = 3986 // 0.999999982f + 3987 // (0.693148872f + 3988 // (0.240227044f + 3989 // (0.554906021e-1f + 3990 // (0.961591928e-2f + 3991 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3992 // error 2.47208000*10^(-7), which is better than 18 bits 3993 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3994 getF32Constant(DAG, 0x3924b03e)); 3995 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3996 getF32Constant(DAG, 0x3ab24b87)); 3997 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3998 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3999 getF32Constant(DAG, 0x3c1d8c17)); 4000 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4001 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4002 getF32Constant(DAG, 0x3d634a1d)); 4003 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4004 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4005 getF32Constant(DAG, 0x3e75fe14)); 4006 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4007 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4008 getF32Constant(DAG, 0x3f317234)); 4009 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4010 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4011 getF32Constant(DAG, 0x3f800000)); 4012 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4013 SDValue TwoToFractionalPartOfX = 4014 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4015 4016 result = DAG.getNode(ISD::BITCAST, dl, 4017 MVT::f32, TwoToFractionalPartOfX); 4018 } 4019 } else { 4020 // No special expansion. 4021 result = DAG.getNode(ISD::FEXP2, dl, 4022 getValue(I.getArgOperand(0)).getValueType(), 4023 getValue(I.getArgOperand(0))); 4024 } 4025 4026 setValue(&I, result); 4027} 4028 4029/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4030/// limited-precision mode with x == 10.0f. 4031void 4032SelectionDAGBuilder::visitPow(const CallInst &I) { 4033 SDValue result; 4034 const Value *Val = I.getArgOperand(0); 4035 DebugLoc dl = getCurDebugLoc(); 4036 bool IsExp10 = false; 4037 4038 if (getValue(Val).getValueType() == MVT::f32 && 4039 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4040 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4041 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4042 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4043 APFloat Ten(10.0f); 4044 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4045 } 4046 } 4047 } 4048 4049 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4050 SDValue Op = getValue(I.getArgOperand(1)); 4051 4052 // Put the exponent in the right bit position for later addition to the 4053 // final result: 4054 // 4055 // #define LOG2OF10 3.3219281f 4056 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4057 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4058 getF32Constant(DAG, 0x40549a78)); 4059 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4060 4061 // FractionalPartOfX = x - (float)IntegerPartOfX; 4062 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4063 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4064 4065 // IntegerPartOfX <<= 23; 4066 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4067 DAG.getConstant(23, TLI.getPointerTy())); 4068 4069 if (LimitFloatPrecision <= 6) { 4070 // For floating-point precision of 6: 4071 // 4072 // twoToFractionalPartOfX = 4073 // 0.997535578f + 4074 // (0.735607626f + 0.252464424f * x) * x; 4075 // 4076 // error 0.0144103317, which is 6 bits 4077 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4078 getF32Constant(DAG, 0x3e814304)); 4079 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4080 getF32Constant(DAG, 0x3f3c50c8)); 4081 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4082 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4083 getF32Constant(DAG, 0x3f7f5e7e)); 4084 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4085 SDValue TwoToFractionalPartOfX = 4086 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4087 4088 result = DAG.getNode(ISD::BITCAST, dl, 4089 MVT::f32, TwoToFractionalPartOfX); 4090 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4091 // For floating-point precision of 12: 4092 // 4093 // TwoToFractionalPartOfX = 4094 // 0.999892986f + 4095 // (0.696457318f + 4096 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4097 // 4098 // error 0.000107046256, which is 13 to 14 bits 4099 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4100 getF32Constant(DAG, 0x3da235e3)); 4101 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4102 getF32Constant(DAG, 0x3e65b8f3)); 4103 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4104 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4105 getF32Constant(DAG, 0x3f324b07)); 4106 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4107 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4108 getF32Constant(DAG, 0x3f7ff8fd)); 4109 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4110 SDValue TwoToFractionalPartOfX = 4111 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4112 4113 result = DAG.getNode(ISD::BITCAST, dl, 4114 MVT::f32, TwoToFractionalPartOfX); 4115 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4116 // For floating-point precision of 18: 4117 // 4118 // TwoToFractionalPartOfX = 4119 // 0.999999982f + 4120 // (0.693148872f + 4121 // (0.240227044f + 4122 // (0.554906021e-1f + 4123 // (0.961591928e-2f + 4124 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4125 // error 2.47208000*10^(-7), which is better than 18 bits 4126 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4127 getF32Constant(DAG, 0x3924b03e)); 4128 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4129 getF32Constant(DAG, 0x3ab24b87)); 4130 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4131 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4132 getF32Constant(DAG, 0x3c1d8c17)); 4133 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4134 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4135 getF32Constant(DAG, 0x3d634a1d)); 4136 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4137 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4138 getF32Constant(DAG, 0x3e75fe14)); 4139 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4140 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4141 getF32Constant(DAG, 0x3f317234)); 4142 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4143 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4144 getF32Constant(DAG, 0x3f800000)); 4145 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4146 SDValue TwoToFractionalPartOfX = 4147 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4148 4149 result = DAG.getNode(ISD::BITCAST, dl, 4150 MVT::f32, TwoToFractionalPartOfX); 4151 } 4152 } else { 4153 // No special expansion. 4154 result = DAG.getNode(ISD::FPOW, dl, 4155 getValue(I.getArgOperand(0)).getValueType(), 4156 getValue(I.getArgOperand(0)), 4157 getValue(I.getArgOperand(1))); 4158 } 4159 4160 setValue(&I, result); 4161} 4162 4163 4164/// ExpandPowI - Expand a llvm.powi intrinsic. 4165static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4166 SelectionDAG &DAG) { 4167 // If RHS is a constant, we can expand this out to a multiplication tree, 4168 // otherwise we end up lowering to a call to __powidf2 (for example). When 4169 // optimizing for size, we only want to do this if the expansion would produce 4170 // a small number of multiplies, otherwise we do the full expansion. 4171 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4172 // Get the exponent as a positive value. 4173 unsigned Val = RHSC->getSExtValue(); 4174 if ((int)Val < 0) Val = -Val; 4175 4176 // powi(x, 0) -> 1.0 4177 if (Val == 0) 4178 return DAG.getConstantFP(1.0, LHS.getValueType()); 4179 4180 const Function *F = DAG.getMachineFunction().getFunction(); 4181 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4182 // If optimizing for size, don't insert too many multiplies. This 4183 // inserts up to 5 multiplies. 4184 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4185 // We use the simple binary decomposition method to generate the multiply 4186 // sequence. There are more optimal ways to do this (for example, 4187 // powi(x,15) generates one more multiply than it should), but this has 4188 // the benefit of being both really simple and much better than a libcall. 4189 SDValue Res; // Logically starts equal to 1.0 4190 SDValue CurSquare = LHS; 4191 while (Val) { 4192 if (Val & 1) { 4193 if (Res.getNode()) 4194 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4195 else 4196 Res = CurSquare; // 1.0*CurSquare. 4197 } 4198 4199 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4200 CurSquare, CurSquare); 4201 Val >>= 1; 4202 } 4203 4204 // If the original was negative, invert the result, producing 1/(x*x*x). 4205 if (RHSC->getSExtValue() < 0) 4206 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4207 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4208 return Res; 4209 } 4210 } 4211 4212 // Otherwise, expand to a libcall. 4213 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4214} 4215 4216// getTruncatedArgReg - Find underlying register used for an truncated 4217// argument. 4218static unsigned getTruncatedArgReg(const SDValue &N) { 4219 if (N.getOpcode() != ISD::TRUNCATE) 4220 return 0; 4221 4222 const SDValue &Ext = N.getOperand(0); 4223 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4224 const SDValue &CFR = Ext.getOperand(0); 4225 if (CFR.getOpcode() == ISD::CopyFromReg) 4226 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4227 else 4228 if (CFR.getOpcode() == ISD::TRUNCATE) 4229 return getTruncatedArgReg(CFR); 4230 } 4231 return 0; 4232} 4233 4234/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4235/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4236/// At the end of instruction selection, they will be inserted to the entry BB. 4237bool 4238SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4239 int64_t Offset, 4240 const SDValue &N) { 4241 const Argument *Arg = dyn_cast<Argument>(V); 4242 if (!Arg) 4243 return false; 4244 4245 MachineFunction &MF = DAG.getMachineFunction(); 4246 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4247 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4248 4249 // Ignore inlined function arguments here. 4250 DIVariable DV(Variable); 4251 if (DV.isInlinedFnArgument(MF.getFunction())) 4252 return false; 4253 4254 unsigned Reg = 0; 4255 if (Arg->hasByValAttr()) { 4256 // Byval arguments' frame index is recorded during argument lowering. 4257 // Use this info directly. 4258 Reg = TRI->getFrameRegister(MF); 4259 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 4260 // If byval argument ofset is not recorded then ignore this. 4261 if (!Offset) 4262 Reg = 0; 4263 } 4264 4265 if (N.getNode()) { 4266 if (N.getOpcode() == ISD::CopyFromReg) 4267 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4268 else 4269 Reg = getTruncatedArgReg(N); 4270 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4271 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4272 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4273 if (PR) 4274 Reg = PR; 4275 } 4276 } 4277 4278 if (!Reg) { 4279 // Check if ValueMap has reg number. 4280 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4281 if (VMI != FuncInfo.ValueMap.end()) 4282 Reg = VMI->second; 4283 } 4284 4285 if (!Reg && N.getNode()) { 4286 // Check if frame index is available. 4287 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4288 if (FrameIndexSDNode *FINode = 4289 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4290 Reg = TRI->getFrameRegister(MF); 4291 Offset = FINode->getIndex(); 4292 } 4293 } 4294 4295 if (!Reg) 4296 return false; 4297 4298 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4299 TII->get(TargetOpcode::DBG_VALUE)) 4300 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4301 FuncInfo.ArgDbgValues.push_back(&*MIB); 4302 return true; 4303} 4304 4305// VisualStudio defines setjmp as _setjmp 4306#if defined(_MSC_VER) && defined(setjmp) && \ 4307 !defined(setjmp_undefined_for_msvc) 4308# pragma push_macro("setjmp") 4309# undef setjmp 4310# define setjmp_undefined_for_msvc 4311#endif 4312 4313/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4314/// we want to emit this as a call to a named external function, return the name 4315/// otherwise lower it and return null. 4316const char * 4317SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4318 DebugLoc dl = getCurDebugLoc(); 4319 SDValue Res; 4320 4321 switch (Intrinsic) { 4322 default: 4323 // By default, turn this into a target intrinsic node. 4324 visitTargetIntrinsic(I, Intrinsic); 4325 return 0; 4326 case Intrinsic::vastart: visitVAStart(I); return 0; 4327 case Intrinsic::vaend: visitVAEnd(I); return 0; 4328 case Intrinsic::vacopy: visitVACopy(I); return 0; 4329 case Intrinsic::returnaddress: 4330 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4331 getValue(I.getArgOperand(0)))); 4332 return 0; 4333 case Intrinsic::frameaddress: 4334 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4335 getValue(I.getArgOperand(0)))); 4336 return 0; 4337 case Intrinsic::setjmp: 4338 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4339 case Intrinsic::longjmp: 4340 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4341 case Intrinsic::memcpy: { 4342 // Assert for address < 256 since we support only user defined address 4343 // spaces. 4344 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4345 < 256 && 4346 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4347 < 256 && 4348 "Unknown address space"); 4349 SDValue Op1 = getValue(I.getArgOperand(0)); 4350 SDValue Op2 = getValue(I.getArgOperand(1)); 4351 SDValue Op3 = getValue(I.getArgOperand(2)); 4352 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4353 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4354 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4355 MachinePointerInfo(I.getArgOperand(0)), 4356 MachinePointerInfo(I.getArgOperand(1)))); 4357 return 0; 4358 } 4359 case Intrinsic::memset: { 4360 // Assert for address < 256 since we support only user defined address 4361 // spaces. 4362 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4363 < 256 && 4364 "Unknown address space"); 4365 SDValue Op1 = getValue(I.getArgOperand(0)); 4366 SDValue Op2 = getValue(I.getArgOperand(1)); 4367 SDValue Op3 = getValue(I.getArgOperand(2)); 4368 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4369 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4370 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4371 MachinePointerInfo(I.getArgOperand(0)))); 4372 return 0; 4373 } 4374 case Intrinsic::memmove: { 4375 // Assert for address < 256 since we support only user defined address 4376 // spaces. 4377 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4378 < 256 && 4379 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4380 < 256 && 4381 "Unknown address space"); 4382 SDValue Op1 = getValue(I.getArgOperand(0)); 4383 SDValue Op2 = getValue(I.getArgOperand(1)); 4384 SDValue Op3 = getValue(I.getArgOperand(2)); 4385 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4386 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4387 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4388 MachinePointerInfo(I.getArgOperand(0)), 4389 MachinePointerInfo(I.getArgOperand(1)))); 4390 return 0; 4391 } 4392 case Intrinsic::dbg_declare: { 4393 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4394 MDNode *Variable = DI.getVariable(); 4395 const Value *Address = DI.getAddress(); 4396 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4397 return 0; 4398 4399 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4400 // but do not always have a corresponding SDNode built. The SDNodeOrder 4401 // absolute, but not relative, values are different depending on whether 4402 // debug info exists. 4403 ++SDNodeOrder; 4404 4405 // Check if address has undef value. 4406 if (isa<UndefValue>(Address) || 4407 (Address->use_empty() && !isa<Argument>(Address))) { 4408 DEBUG(dbgs() << "Dropping debug info for " << DI); 4409 return 0; 4410 } 4411 4412 SDValue &N = NodeMap[Address]; 4413 if (!N.getNode() && isa<Argument>(Address)) 4414 // Check unused arguments map. 4415 N = UnusedArgNodeMap[Address]; 4416 SDDbgValue *SDV; 4417 if (N.getNode()) { 4418 // Parameters are handled specially. 4419 bool isParameter = 4420 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4421 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4422 Address = BCI->getOperand(0); 4423 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4424 4425 if (isParameter && !AI) { 4426 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4427 if (FINode) 4428 // Byval parameter. We have a frame index at this point. 4429 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4430 0, dl, SDNodeOrder); 4431 else { 4432 // Address is an argument, so try to emit its dbg value using 4433 // virtual register info from the FuncInfo.ValueMap. 4434 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4435 return 0; 4436 } 4437 } else if (AI) 4438 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4439 0, dl, SDNodeOrder); 4440 else { 4441 // Can't do anything with other non-AI cases yet. 4442 DEBUG(dbgs() << "Dropping debug info for " << DI); 4443 return 0; 4444 } 4445 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4446 } else { 4447 // If Address is an argument then try to emit its dbg value using 4448 // virtual register info from the FuncInfo.ValueMap. 4449 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4450 // If variable is pinned by a alloca in dominating bb then 4451 // use StaticAllocaMap. 4452 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4453 if (AI->getParent() != DI.getParent()) { 4454 DenseMap<const AllocaInst*, int>::iterator SI = 4455 FuncInfo.StaticAllocaMap.find(AI); 4456 if (SI != FuncInfo.StaticAllocaMap.end()) { 4457 SDV = DAG.getDbgValue(Variable, SI->second, 4458 0, dl, SDNodeOrder); 4459 DAG.AddDbgValue(SDV, 0, false); 4460 return 0; 4461 } 4462 } 4463 } 4464 DEBUG(dbgs() << "Dropping debug info for " << DI); 4465 } 4466 } 4467 return 0; 4468 } 4469 case Intrinsic::dbg_value: { 4470 const DbgValueInst &DI = cast<DbgValueInst>(I); 4471 if (!DIVariable(DI.getVariable()).Verify()) 4472 return 0; 4473 4474 MDNode *Variable = DI.getVariable(); 4475 uint64_t Offset = DI.getOffset(); 4476 const Value *V = DI.getValue(); 4477 if (!V) 4478 return 0; 4479 4480 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4481 // but do not always have a corresponding SDNode built. The SDNodeOrder 4482 // absolute, but not relative, values are different depending on whether 4483 // debug info exists. 4484 ++SDNodeOrder; 4485 SDDbgValue *SDV; 4486 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4487 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4488 DAG.AddDbgValue(SDV, 0, false); 4489 } else { 4490 // Do not use getValue() in here; we don't want to generate code at 4491 // this point if it hasn't been done yet. 4492 SDValue N = NodeMap[V]; 4493 if (!N.getNode() && isa<Argument>(V)) 4494 // Check unused arguments map. 4495 N = UnusedArgNodeMap[V]; 4496 if (N.getNode()) { 4497 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4498 SDV = DAG.getDbgValue(Variable, N.getNode(), 4499 N.getResNo(), Offset, dl, SDNodeOrder); 4500 DAG.AddDbgValue(SDV, N.getNode(), false); 4501 } 4502 } else if (!V->use_empty() ) { 4503 // Do not call getValue(V) yet, as we don't want to generate code. 4504 // Remember it for later. 4505 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4506 DanglingDebugInfoMap[V] = DDI; 4507 } else { 4508 // We may expand this to cover more cases. One case where we have no 4509 // data available is an unreferenced parameter. 4510 DEBUG(dbgs() << "Dropping debug info for " << DI); 4511 } 4512 } 4513 4514 // Build a debug info table entry. 4515 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4516 V = BCI->getOperand(0); 4517 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4518 // Don't handle byval struct arguments or VLAs, for example. 4519 if (!AI) 4520 return 0; 4521 DenseMap<const AllocaInst*, int>::iterator SI = 4522 FuncInfo.StaticAllocaMap.find(AI); 4523 if (SI == FuncInfo.StaticAllocaMap.end()) 4524 return 0; // VLAs. 4525 int FI = SI->second; 4526 4527 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4528 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4529 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4530 return 0; 4531 } 4532 case Intrinsic::eh_exception: { 4533 // Insert the EXCEPTIONADDR instruction. 4534 assert(FuncInfo.MBB->isLandingPad() && 4535 "Call to eh.exception not in landing pad!"); 4536 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4537 SDValue Ops[1]; 4538 Ops[0] = DAG.getRoot(); 4539 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4540 setValue(&I, Op); 4541 DAG.setRoot(Op.getValue(1)); 4542 return 0; 4543 } 4544 4545 case Intrinsic::eh_selector: { 4546 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4547 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4548 if (CallMBB->isLandingPad()) 4549 AddCatchInfo(I, &MMI, CallMBB); 4550 else { 4551#ifndef NDEBUG 4552 FuncInfo.CatchInfoLost.insert(&I); 4553#endif 4554 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4555 unsigned Reg = TLI.getExceptionSelectorRegister(); 4556 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4557 } 4558 4559 // Insert the EHSELECTION instruction. 4560 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4561 SDValue Ops[2]; 4562 Ops[0] = getValue(I.getArgOperand(0)); 4563 Ops[1] = getRoot(); 4564 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4565 DAG.setRoot(Op.getValue(1)); 4566 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4567 return 0; 4568 } 4569 4570 case Intrinsic::eh_typeid_for: { 4571 // Find the type id for the given typeinfo. 4572 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4573 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4574 Res = DAG.getConstant(TypeID, MVT::i32); 4575 setValue(&I, Res); 4576 return 0; 4577 } 4578 4579 case Intrinsic::eh_return_i32: 4580 case Intrinsic::eh_return_i64: 4581 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4582 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4583 MVT::Other, 4584 getControlRoot(), 4585 getValue(I.getArgOperand(0)), 4586 getValue(I.getArgOperand(1)))); 4587 return 0; 4588 case Intrinsic::eh_unwind_init: 4589 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4590 return 0; 4591 case Intrinsic::eh_dwarf_cfa: { 4592 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4593 TLI.getPointerTy()); 4594 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4595 TLI.getPointerTy(), 4596 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4597 TLI.getPointerTy()), 4598 CfaArg); 4599 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4600 TLI.getPointerTy(), 4601 DAG.getConstant(0, TLI.getPointerTy())); 4602 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4603 FA, Offset)); 4604 return 0; 4605 } 4606 case Intrinsic::eh_sjlj_callsite: { 4607 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4608 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4609 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4610 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4611 4612 MMI.setCurrentCallSite(CI->getZExtValue()); 4613 return 0; 4614 } 4615 case Intrinsic::eh_sjlj_setjmp: { 4616 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4617 getValue(I.getArgOperand(0)))); 4618 return 0; 4619 } 4620 case Intrinsic::eh_sjlj_longjmp: { 4621 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4622 getRoot(), getValue(I.getArgOperand(0)))); 4623 return 0; 4624 } 4625 case Intrinsic::eh_sjlj_dispatch_setup: { 4626 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4627 getRoot(), getValue(I.getArgOperand(0)))); 4628 return 0; 4629 } 4630 4631 case Intrinsic::x86_mmx_pslli_w: 4632 case Intrinsic::x86_mmx_pslli_d: 4633 case Intrinsic::x86_mmx_pslli_q: 4634 case Intrinsic::x86_mmx_psrli_w: 4635 case Intrinsic::x86_mmx_psrli_d: 4636 case Intrinsic::x86_mmx_psrli_q: 4637 case Intrinsic::x86_mmx_psrai_w: 4638 case Intrinsic::x86_mmx_psrai_d: { 4639 SDValue ShAmt = getValue(I.getArgOperand(1)); 4640 if (isa<ConstantSDNode>(ShAmt)) { 4641 visitTargetIntrinsic(I, Intrinsic); 4642 return 0; 4643 } 4644 unsigned NewIntrinsic = 0; 4645 EVT ShAmtVT = MVT::v2i32; 4646 switch (Intrinsic) { 4647 case Intrinsic::x86_mmx_pslli_w: 4648 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4649 break; 4650 case Intrinsic::x86_mmx_pslli_d: 4651 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4652 break; 4653 case Intrinsic::x86_mmx_pslli_q: 4654 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4655 break; 4656 case Intrinsic::x86_mmx_psrli_w: 4657 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4658 break; 4659 case Intrinsic::x86_mmx_psrli_d: 4660 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4661 break; 4662 case Intrinsic::x86_mmx_psrli_q: 4663 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4664 break; 4665 case Intrinsic::x86_mmx_psrai_w: 4666 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4667 break; 4668 case Intrinsic::x86_mmx_psrai_d: 4669 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4670 break; 4671 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4672 } 4673 4674 // The vector shift intrinsics with scalars uses 32b shift amounts but 4675 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4676 // to be zero. 4677 // We must do this early because v2i32 is not a legal type. 4678 DebugLoc dl = getCurDebugLoc(); 4679 SDValue ShOps[2]; 4680 ShOps[0] = ShAmt; 4681 ShOps[1] = DAG.getConstant(0, MVT::i32); 4682 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4683 EVT DestVT = TLI.getValueType(I.getType()); 4684 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4685 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4686 DAG.getConstant(NewIntrinsic, MVT::i32), 4687 getValue(I.getArgOperand(0)), ShAmt); 4688 setValue(&I, Res); 4689 return 0; 4690 } 4691 case Intrinsic::convertff: 4692 case Intrinsic::convertfsi: 4693 case Intrinsic::convertfui: 4694 case Intrinsic::convertsif: 4695 case Intrinsic::convertuif: 4696 case Intrinsic::convertss: 4697 case Intrinsic::convertsu: 4698 case Intrinsic::convertus: 4699 case Intrinsic::convertuu: { 4700 ISD::CvtCode Code = ISD::CVT_INVALID; 4701 switch (Intrinsic) { 4702 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4703 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4704 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4705 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4706 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4707 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4708 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4709 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4710 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4711 } 4712 EVT DestVT = TLI.getValueType(I.getType()); 4713 const Value *Op1 = I.getArgOperand(0); 4714 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4715 DAG.getValueType(DestVT), 4716 DAG.getValueType(getValue(Op1).getValueType()), 4717 getValue(I.getArgOperand(1)), 4718 getValue(I.getArgOperand(2)), 4719 Code); 4720 setValue(&I, Res); 4721 return 0; 4722 } 4723 case Intrinsic::sqrt: 4724 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4725 getValue(I.getArgOperand(0)).getValueType(), 4726 getValue(I.getArgOperand(0)))); 4727 return 0; 4728 case Intrinsic::powi: 4729 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4730 getValue(I.getArgOperand(1)), DAG)); 4731 return 0; 4732 case Intrinsic::sin: 4733 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4734 getValue(I.getArgOperand(0)).getValueType(), 4735 getValue(I.getArgOperand(0)))); 4736 return 0; 4737 case Intrinsic::cos: 4738 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4739 getValue(I.getArgOperand(0)).getValueType(), 4740 getValue(I.getArgOperand(0)))); 4741 return 0; 4742 case Intrinsic::log: 4743 visitLog(I); 4744 return 0; 4745 case Intrinsic::log2: 4746 visitLog2(I); 4747 return 0; 4748 case Intrinsic::log10: 4749 visitLog10(I); 4750 return 0; 4751 case Intrinsic::exp: 4752 visitExp(I); 4753 return 0; 4754 case Intrinsic::exp2: 4755 visitExp2(I); 4756 return 0; 4757 case Intrinsic::pow: 4758 visitPow(I); 4759 return 0; 4760 case Intrinsic::fma: 4761 setValue(&I, DAG.getNode(ISD::FMA, dl, 4762 getValue(I.getArgOperand(0)).getValueType(), 4763 getValue(I.getArgOperand(0)), 4764 getValue(I.getArgOperand(1)), 4765 getValue(I.getArgOperand(2)))); 4766 return 0; 4767 case Intrinsic::convert_to_fp16: 4768 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4769 MVT::i16, getValue(I.getArgOperand(0)))); 4770 return 0; 4771 case Intrinsic::convert_from_fp16: 4772 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4773 MVT::f32, getValue(I.getArgOperand(0)))); 4774 return 0; 4775 case Intrinsic::pcmarker: { 4776 SDValue Tmp = getValue(I.getArgOperand(0)); 4777 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4778 return 0; 4779 } 4780 case Intrinsic::readcyclecounter: { 4781 SDValue Op = getRoot(); 4782 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4783 DAG.getVTList(MVT::i64, MVT::Other), 4784 &Op, 1); 4785 setValue(&I, Res); 4786 DAG.setRoot(Res.getValue(1)); 4787 return 0; 4788 } 4789 case Intrinsic::bswap: 4790 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4791 getValue(I.getArgOperand(0)).getValueType(), 4792 getValue(I.getArgOperand(0)))); 4793 return 0; 4794 case Intrinsic::cttz: { 4795 SDValue Arg = getValue(I.getArgOperand(0)); 4796 EVT Ty = Arg.getValueType(); 4797 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4798 return 0; 4799 } 4800 case Intrinsic::ctlz: { 4801 SDValue Arg = getValue(I.getArgOperand(0)); 4802 EVT Ty = Arg.getValueType(); 4803 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4804 return 0; 4805 } 4806 case Intrinsic::ctpop: { 4807 SDValue Arg = getValue(I.getArgOperand(0)); 4808 EVT Ty = Arg.getValueType(); 4809 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4810 return 0; 4811 } 4812 case Intrinsic::stacksave: { 4813 SDValue Op = getRoot(); 4814 Res = DAG.getNode(ISD::STACKSAVE, dl, 4815 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4816 setValue(&I, Res); 4817 DAG.setRoot(Res.getValue(1)); 4818 return 0; 4819 } 4820 case Intrinsic::stackrestore: { 4821 Res = getValue(I.getArgOperand(0)); 4822 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4823 return 0; 4824 } 4825 case Intrinsic::stackprotector: { 4826 // Emit code into the DAG to store the stack guard onto the stack. 4827 MachineFunction &MF = DAG.getMachineFunction(); 4828 MachineFrameInfo *MFI = MF.getFrameInfo(); 4829 EVT PtrTy = TLI.getPointerTy(); 4830 4831 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4832 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4833 4834 int FI = FuncInfo.StaticAllocaMap[Slot]; 4835 MFI->setStackProtectorIndex(FI); 4836 4837 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4838 4839 // Store the stack protector onto the stack. 4840 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4841 MachinePointerInfo::getFixedStack(FI), 4842 true, false, 0); 4843 setValue(&I, Res); 4844 DAG.setRoot(Res); 4845 return 0; 4846 } 4847 case Intrinsic::objectsize: { 4848 // If we don't know by now, we're never going to know. 4849 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4850 4851 assert(CI && "Non-constant type in __builtin_object_size?"); 4852 4853 SDValue Arg = getValue(I.getCalledValue()); 4854 EVT Ty = Arg.getValueType(); 4855 4856 if (CI->isZero()) 4857 Res = DAG.getConstant(-1ULL, Ty); 4858 else 4859 Res = DAG.getConstant(0, Ty); 4860 4861 setValue(&I, Res); 4862 return 0; 4863 } 4864 case Intrinsic::var_annotation: 4865 // Discard annotate attributes 4866 return 0; 4867 4868 case Intrinsic::init_trampoline: { 4869 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4870 4871 SDValue Ops[6]; 4872 Ops[0] = getRoot(); 4873 Ops[1] = getValue(I.getArgOperand(0)); 4874 Ops[2] = getValue(I.getArgOperand(1)); 4875 Ops[3] = getValue(I.getArgOperand(2)); 4876 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4877 Ops[5] = DAG.getSrcValue(F); 4878 4879 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4880 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4881 Ops, 6); 4882 4883 setValue(&I, Res); 4884 DAG.setRoot(Res.getValue(1)); 4885 return 0; 4886 } 4887 case Intrinsic::gcroot: 4888 if (GFI) { 4889 const Value *Alloca = I.getArgOperand(0); 4890 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4891 4892 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4893 GFI->addStackRoot(FI->getIndex(), TypeMap); 4894 } 4895 return 0; 4896 case Intrinsic::gcread: 4897 case Intrinsic::gcwrite: 4898 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4899 return 0; 4900 case Intrinsic::flt_rounds: 4901 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4902 return 0; 4903 4904 case Intrinsic::expect: { 4905 // Just replace __builtin_expect(exp, c) with EXP. 4906 setValue(&I, getValue(I.getArgOperand(0))); 4907 return 0; 4908 } 4909 4910 case Intrinsic::trap: { 4911 StringRef TrapFuncName = getTrapFunctionName(); 4912 if (TrapFuncName.empty()) { 4913 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4914 return 0; 4915 } 4916 TargetLowering::ArgListTy Args; 4917 std::pair<SDValue, SDValue> Result = 4918 TLI.LowerCallTo(getRoot(), I.getType(), 4919 false, false, false, false, 0, CallingConv::C, 4920 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 4921 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 4922 Args, DAG, getCurDebugLoc()); 4923 DAG.setRoot(Result.second); 4924 return 0; 4925 } 4926 case Intrinsic::uadd_with_overflow: 4927 return implVisitAluOverflow(I, ISD::UADDO); 4928 case Intrinsic::sadd_with_overflow: 4929 return implVisitAluOverflow(I, ISD::SADDO); 4930 case Intrinsic::usub_with_overflow: 4931 return implVisitAluOverflow(I, ISD::USUBO); 4932 case Intrinsic::ssub_with_overflow: 4933 return implVisitAluOverflow(I, ISD::SSUBO); 4934 case Intrinsic::umul_with_overflow: 4935 return implVisitAluOverflow(I, ISD::UMULO); 4936 case Intrinsic::smul_with_overflow: 4937 return implVisitAluOverflow(I, ISD::SMULO); 4938 4939 case Intrinsic::prefetch: { 4940 SDValue Ops[5]; 4941 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 4942 Ops[0] = getRoot(); 4943 Ops[1] = getValue(I.getArgOperand(0)); 4944 Ops[2] = getValue(I.getArgOperand(1)); 4945 Ops[3] = getValue(I.getArgOperand(2)); 4946 Ops[4] = getValue(I.getArgOperand(3)); 4947 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 4948 DAG.getVTList(MVT::Other), 4949 &Ops[0], 5, 4950 EVT::getIntegerVT(*Context, 8), 4951 MachinePointerInfo(I.getArgOperand(0)), 4952 0, /* align */ 4953 false, /* volatile */ 4954 rw==0, /* read */ 4955 rw==1)); /* write */ 4956 return 0; 4957 } 4958 case Intrinsic::memory_barrier: { 4959 SDValue Ops[6]; 4960 Ops[0] = getRoot(); 4961 for (int x = 1; x < 6; ++x) 4962 Ops[x] = getValue(I.getArgOperand(x - 1)); 4963 4964 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4965 return 0; 4966 } 4967 case Intrinsic::atomic_cmp_swap: { 4968 SDValue Root = getRoot(); 4969 SDValue L = 4970 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4971 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4972 Root, 4973 getValue(I.getArgOperand(0)), 4974 getValue(I.getArgOperand(1)), 4975 getValue(I.getArgOperand(2)), 4976 MachinePointerInfo(I.getArgOperand(0)), 0 /* Alignment */, 4977 Monotonic, CrossThread); 4978 setValue(&I, L); 4979 DAG.setRoot(L.getValue(1)); 4980 return 0; 4981 } 4982 case Intrinsic::atomic_load_add: 4983 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4984 case Intrinsic::atomic_load_sub: 4985 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4986 case Intrinsic::atomic_load_or: 4987 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4988 case Intrinsic::atomic_load_xor: 4989 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4990 case Intrinsic::atomic_load_and: 4991 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4992 case Intrinsic::atomic_load_nand: 4993 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4994 case Intrinsic::atomic_load_max: 4995 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4996 case Intrinsic::atomic_load_min: 4997 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4998 case Intrinsic::atomic_load_umin: 4999 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 5000 case Intrinsic::atomic_load_umax: 5001 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 5002 case Intrinsic::atomic_swap: 5003 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 5004 5005 case Intrinsic::invariant_start: 5006 case Intrinsic::lifetime_start: 5007 // Discard region information. 5008 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5009 return 0; 5010 case Intrinsic::invariant_end: 5011 case Intrinsic::lifetime_end: 5012 // Discard region information. 5013 return 0; 5014 } 5015} 5016 5017void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5018 bool isTailCall, 5019 MachineBasicBlock *LandingPad) { 5020 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5021 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5022 Type *RetTy = FTy->getReturnType(); 5023 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5024 MCSymbol *BeginLabel = 0; 5025 5026 TargetLowering::ArgListTy Args; 5027 TargetLowering::ArgListEntry Entry; 5028 Args.reserve(CS.arg_size()); 5029 5030 // Check whether the function can return without sret-demotion. 5031 SmallVector<ISD::OutputArg, 4> Outs; 5032 SmallVector<uint64_t, 4> Offsets; 5033 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5034 Outs, TLI, &Offsets); 5035 5036 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5037 DAG.getMachineFunction(), 5038 FTy->isVarArg(), Outs, 5039 FTy->getContext()); 5040 5041 SDValue DemoteStackSlot; 5042 int DemoteStackIdx = -100; 5043 5044 if (!CanLowerReturn) { 5045 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5046 FTy->getReturnType()); 5047 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5048 FTy->getReturnType()); 5049 MachineFunction &MF = DAG.getMachineFunction(); 5050 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5051 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5052 5053 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5054 Entry.Node = DemoteStackSlot; 5055 Entry.Ty = StackSlotPtrType; 5056 Entry.isSExt = false; 5057 Entry.isZExt = false; 5058 Entry.isInReg = false; 5059 Entry.isSRet = true; 5060 Entry.isNest = false; 5061 Entry.isByVal = false; 5062 Entry.Alignment = Align; 5063 Args.push_back(Entry); 5064 RetTy = Type::getVoidTy(FTy->getContext()); 5065 } 5066 5067 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5068 i != e; ++i) { 5069 const Value *V = *i; 5070 5071 // Skip empty types 5072 if (V->getType()->isEmptyTy()) 5073 continue; 5074 5075 SDValue ArgNode = getValue(V); 5076 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5077 5078 unsigned attrInd = i - CS.arg_begin() + 1; 5079 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5080 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5081 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5082 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5083 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5084 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5085 Entry.Alignment = CS.getParamAlignment(attrInd); 5086 Args.push_back(Entry); 5087 } 5088 5089 if (LandingPad) { 5090 // Insert a label before the invoke call to mark the try range. This can be 5091 // used to detect deletion of the invoke via the MachineModuleInfo. 5092 BeginLabel = MMI.getContext().CreateTempSymbol(); 5093 5094 // For SjLj, keep track of which landing pads go with which invokes 5095 // so as to maintain the ordering of pads in the LSDA. 5096 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5097 if (CallSiteIndex) { 5098 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5099 // Now that the call site is handled, stop tracking it. 5100 MMI.setCurrentCallSite(0); 5101 } 5102 5103 // Both PendingLoads and PendingExports must be flushed here; 5104 // this call might not return. 5105 (void)getRoot(); 5106 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5107 } 5108 5109 // Check if target-independent constraints permit a tail call here. 5110 // Target-dependent constraints are checked within TLI.LowerCallTo. 5111 if (isTailCall && 5112 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5113 isTailCall = false; 5114 5115 // If there's a possibility that fast-isel has already selected some amount 5116 // of the current basic block, don't emit a tail call. 5117 if (isTailCall && EnableFastISel) 5118 isTailCall = false; 5119 5120 std::pair<SDValue,SDValue> Result = 5121 TLI.LowerCallTo(getRoot(), RetTy, 5122 CS.paramHasAttr(0, Attribute::SExt), 5123 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5124 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5125 CS.getCallingConv(), 5126 isTailCall, 5127 !CS.getInstruction()->use_empty(), 5128 Callee, Args, DAG, getCurDebugLoc()); 5129 assert((isTailCall || Result.second.getNode()) && 5130 "Non-null chain expected with non-tail call!"); 5131 assert((Result.second.getNode() || !Result.first.getNode()) && 5132 "Null value expected with tail call!"); 5133 if (Result.first.getNode()) { 5134 setValue(CS.getInstruction(), Result.first); 5135 } else if (!CanLowerReturn && Result.second.getNode()) { 5136 // The instruction result is the result of loading from the 5137 // hidden sret parameter. 5138 SmallVector<EVT, 1> PVTs; 5139 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5140 5141 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5142 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5143 EVT PtrVT = PVTs[0]; 5144 unsigned NumValues = Outs.size(); 5145 SmallVector<SDValue, 4> Values(NumValues); 5146 SmallVector<SDValue, 4> Chains(NumValues); 5147 5148 for (unsigned i = 0; i < NumValues; ++i) { 5149 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5150 DemoteStackSlot, 5151 DAG.getConstant(Offsets[i], PtrVT)); 5152 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5153 Add, 5154 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5155 false, false, 1); 5156 Values[i] = L; 5157 Chains[i] = L.getValue(1); 5158 } 5159 5160 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5161 MVT::Other, &Chains[0], NumValues); 5162 PendingLoads.push_back(Chain); 5163 5164 // Collect the legal value parts into potentially illegal values 5165 // that correspond to the original function's return values. 5166 SmallVector<EVT, 4> RetTys; 5167 RetTy = FTy->getReturnType(); 5168 ComputeValueVTs(TLI, RetTy, RetTys); 5169 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5170 SmallVector<SDValue, 4> ReturnValues; 5171 unsigned CurReg = 0; 5172 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5173 EVT VT = RetTys[I]; 5174 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5175 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5176 5177 SDValue ReturnValue = 5178 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5179 RegisterVT, VT, AssertOp); 5180 ReturnValues.push_back(ReturnValue); 5181 CurReg += NumRegs; 5182 } 5183 5184 setValue(CS.getInstruction(), 5185 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5186 DAG.getVTList(&RetTys[0], RetTys.size()), 5187 &ReturnValues[0], ReturnValues.size())); 5188 } 5189 5190 // Assign order to nodes here. If the call does not produce a result, it won't 5191 // be mapped to a SDNode and visit() will not assign it an order number. 5192 if (!Result.second.getNode()) { 5193 // As a special case, a null chain means that a tail call has been emitted and 5194 // the DAG root is already updated. 5195 HasTailCall = true; 5196 ++SDNodeOrder; 5197 AssignOrderingToNode(DAG.getRoot().getNode()); 5198 } else { 5199 DAG.setRoot(Result.second); 5200 ++SDNodeOrder; 5201 AssignOrderingToNode(Result.second.getNode()); 5202 } 5203 5204 if (LandingPad) { 5205 // Insert a label at the end of the invoke call to mark the try range. This 5206 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5207 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5208 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5209 5210 // Inform MachineModuleInfo of range. 5211 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5212 } 5213} 5214 5215/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5216/// value is equal or not-equal to zero. 5217static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5218 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5219 UI != E; ++UI) { 5220 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5221 if (IC->isEquality()) 5222 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5223 if (C->isNullValue()) 5224 continue; 5225 // Unknown instruction. 5226 return false; 5227 } 5228 return true; 5229} 5230 5231static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5232 Type *LoadTy, 5233 SelectionDAGBuilder &Builder) { 5234 5235 // Check to see if this load can be trivially constant folded, e.g. if the 5236 // input is from a string literal. 5237 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5238 // Cast pointer to the type we really want to load. 5239 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5240 PointerType::getUnqual(LoadTy)); 5241 5242 if (const Constant *LoadCst = 5243 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5244 Builder.TD)) 5245 return Builder.getValue(LoadCst); 5246 } 5247 5248 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5249 // still constant memory, the input chain can be the entry node. 5250 SDValue Root; 5251 bool ConstantMemory = false; 5252 5253 // Do not serialize (non-volatile) loads of constant memory with anything. 5254 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5255 Root = Builder.DAG.getEntryNode(); 5256 ConstantMemory = true; 5257 } else { 5258 // Do not serialize non-volatile loads against each other. 5259 Root = Builder.DAG.getRoot(); 5260 } 5261 5262 SDValue Ptr = Builder.getValue(PtrVal); 5263 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5264 Ptr, MachinePointerInfo(PtrVal), 5265 false /*volatile*/, 5266 false /*nontemporal*/, 1 /* align=1 */); 5267 5268 if (!ConstantMemory) 5269 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5270 return LoadVal; 5271} 5272 5273 5274/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5275/// If so, return true and lower it, otherwise return false and it will be 5276/// lowered like a normal call. 5277bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5278 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5279 if (I.getNumArgOperands() != 3) 5280 return false; 5281 5282 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5283 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5284 !I.getArgOperand(2)->getType()->isIntegerTy() || 5285 !I.getType()->isIntegerTy()) 5286 return false; 5287 5288 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5289 5290 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5291 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5292 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5293 bool ActuallyDoIt = true; 5294 MVT LoadVT; 5295 Type *LoadTy; 5296 switch (Size->getZExtValue()) { 5297 default: 5298 LoadVT = MVT::Other; 5299 LoadTy = 0; 5300 ActuallyDoIt = false; 5301 break; 5302 case 2: 5303 LoadVT = MVT::i16; 5304 LoadTy = Type::getInt16Ty(Size->getContext()); 5305 break; 5306 case 4: 5307 LoadVT = MVT::i32; 5308 LoadTy = Type::getInt32Ty(Size->getContext()); 5309 break; 5310 case 8: 5311 LoadVT = MVT::i64; 5312 LoadTy = Type::getInt64Ty(Size->getContext()); 5313 break; 5314 /* 5315 case 16: 5316 LoadVT = MVT::v4i32; 5317 LoadTy = Type::getInt32Ty(Size->getContext()); 5318 LoadTy = VectorType::get(LoadTy, 4); 5319 break; 5320 */ 5321 } 5322 5323 // This turns into unaligned loads. We only do this if the target natively 5324 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5325 // we'll only produce a small number of byte loads. 5326 5327 // Require that we can find a legal MVT, and only do this if the target 5328 // supports unaligned loads of that type. Expanding into byte loads would 5329 // bloat the code. 5330 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5331 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5332 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5333 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5334 ActuallyDoIt = false; 5335 } 5336 5337 if (ActuallyDoIt) { 5338 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5339 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5340 5341 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5342 ISD::SETNE); 5343 EVT CallVT = TLI.getValueType(I.getType(), true); 5344 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5345 return true; 5346 } 5347 } 5348 5349 5350 return false; 5351} 5352 5353 5354void SelectionDAGBuilder::visitCall(const CallInst &I) { 5355 // Handle inline assembly differently. 5356 if (isa<InlineAsm>(I.getCalledValue())) { 5357 visitInlineAsm(&I); 5358 return; 5359 } 5360 5361 // See if any floating point values are being passed to this function. This is 5362 // used to emit an undefined reference to fltused on Windows. 5363 FunctionType *FT = 5364 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5365 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5366 if (FT->isVarArg() && 5367 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5368 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5369 Type* T = I.getArgOperand(i)->getType(); 5370 for (po_iterator<Type*> i = po_begin(T), e = po_end(T); 5371 i != e; ++i) { 5372 if (!i->isFloatingPointTy()) continue; 5373 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5374 break; 5375 } 5376 } 5377 } 5378 5379 const char *RenameFn = 0; 5380 if (Function *F = I.getCalledFunction()) { 5381 if (F->isDeclaration()) { 5382 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5383 if (unsigned IID = II->getIntrinsicID(F)) { 5384 RenameFn = visitIntrinsicCall(I, IID); 5385 if (!RenameFn) 5386 return; 5387 } 5388 } 5389 if (unsigned IID = F->getIntrinsicID()) { 5390 RenameFn = visitIntrinsicCall(I, IID); 5391 if (!RenameFn) 5392 return; 5393 } 5394 } 5395 5396 // Check for well-known libc/libm calls. If the function is internal, it 5397 // can't be a library call. 5398 if (!F->hasLocalLinkage() && F->hasName()) { 5399 StringRef Name = F->getName(); 5400 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5401 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5402 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5403 I.getType() == I.getArgOperand(0)->getType() && 5404 I.getType() == I.getArgOperand(1)->getType()) { 5405 SDValue LHS = getValue(I.getArgOperand(0)); 5406 SDValue RHS = getValue(I.getArgOperand(1)); 5407 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5408 LHS.getValueType(), LHS, RHS)); 5409 return; 5410 } 5411 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5412 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5413 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5414 I.getType() == I.getArgOperand(0)->getType()) { 5415 SDValue Tmp = getValue(I.getArgOperand(0)); 5416 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5417 Tmp.getValueType(), Tmp)); 5418 return; 5419 } 5420 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5421 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5422 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5423 I.getType() == I.getArgOperand(0)->getType() && 5424 I.onlyReadsMemory()) { 5425 SDValue Tmp = getValue(I.getArgOperand(0)); 5426 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5427 Tmp.getValueType(), Tmp)); 5428 return; 5429 } 5430 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5431 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5432 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5433 I.getType() == I.getArgOperand(0)->getType() && 5434 I.onlyReadsMemory()) { 5435 SDValue Tmp = getValue(I.getArgOperand(0)); 5436 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5437 Tmp.getValueType(), Tmp)); 5438 return; 5439 } 5440 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5441 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5442 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5443 I.getType() == I.getArgOperand(0)->getType() && 5444 I.onlyReadsMemory()) { 5445 SDValue Tmp = getValue(I.getArgOperand(0)); 5446 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5447 Tmp.getValueType(), Tmp)); 5448 return; 5449 } 5450 } else if (Name == "memcmp") { 5451 if (visitMemCmpCall(I)) 5452 return; 5453 } 5454 } 5455 } 5456 5457 SDValue Callee; 5458 if (!RenameFn) 5459 Callee = getValue(I.getCalledValue()); 5460 else 5461 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5462 5463 // Check if we can potentially perform a tail call. More detailed checking is 5464 // be done within LowerCallTo, after more information about the call is known. 5465 LowerCallTo(&I, Callee, I.isTailCall()); 5466} 5467 5468namespace { 5469 5470/// AsmOperandInfo - This contains information for each constraint that we are 5471/// lowering. 5472class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5473public: 5474 /// CallOperand - If this is the result output operand or a clobber 5475 /// this is null, otherwise it is the incoming operand to the CallInst. 5476 /// This gets modified as the asm is processed. 5477 SDValue CallOperand; 5478 5479 /// AssignedRegs - If this is a register or register class operand, this 5480 /// contains the set of register corresponding to the operand. 5481 RegsForValue AssignedRegs; 5482 5483 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5484 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5485 } 5486 5487 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5488 /// busy in OutputRegs/InputRegs. 5489 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5490 std::set<unsigned> &OutputRegs, 5491 std::set<unsigned> &InputRegs, 5492 const TargetRegisterInfo &TRI) const { 5493 if (isOutReg) { 5494 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5495 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5496 } 5497 if (isInReg) { 5498 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5499 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5500 } 5501 } 5502 5503 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5504 /// corresponds to. If there is no Value* for this operand, it returns 5505 /// MVT::Other. 5506 EVT getCallOperandValEVT(LLVMContext &Context, 5507 const TargetLowering &TLI, 5508 const TargetData *TD) const { 5509 if (CallOperandVal == 0) return MVT::Other; 5510 5511 if (isa<BasicBlock>(CallOperandVal)) 5512 return TLI.getPointerTy(); 5513 5514 llvm::Type *OpTy = CallOperandVal->getType(); 5515 5516 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5517 // If this is an indirect operand, the operand is a pointer to the 5518 // accessed type. 5519 if (isIndirect) { 5520 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5521 if (!PtrTy) 5522 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5523 OpTy = PtrTy->getElementType(); 5524 } 5525 5526 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5527 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5528 if (STy->getNumElements() == 1) 5529 OpTy = STy->getElementType(0); 5530 5531 // If OpTy is not a single value, it may be a struct/union that we 5532 // can tile with integers. 5533 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5534 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5535 switch (BitSize) { 5536 default: break; 5537 case 1: 5538 case 8: 5539 case 16: 5540 case 32: 5541 case 64: 5542 case 128: 5543 OpTy = IntegerType::get(Context, BitSize); 5544 break; 5545 } 5546 } 5547 5548 return TLI.getValueType(OpTy, true); 5549 } 5550 5551private: 5552 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5553 /// specified set. 5554 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5555 const TargetRegisterInfo &TRI) { 5556 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5557 Regs.insert(Reg); 5558 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5559 for (; *Aliases; ++Aliases) 5560 Regs.insert(*Aliases); 5561 } 5562}; 5563 5564typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5565 5566} // end anonymous namespace 5567 5568/// GetRegistersForValue - Assign registers (virtual or physical) for the 5569/// specified operand. We prefer to assign virtual registers, to allow the 5570/// register allocator to handle the assignment process. However, if the asm 5571/// uses features that we can't model on machineinstrs, we have SDISel do the 5572/// allocation. This produces generally horrible, but correct, code. 5573/// 5574/// OpInfo describes the operand. 5575/// Input and OutputRegs are the set of already allocated physical registers. 5576/// 5577static void GetRegistersForValue(SelectionDAG &DAG, 5578 const TargetLowering &TLI, 5579 DebugLoc DL, 5580 SDISelAsmOperandInfo &OpInfo, 5581 std::set<unsigned> &OutputRegs, 5582 std::set<unsigned> &InputRegs) { 5583 LLVMContext &Context = *DAG.getContext(); 5584 5585 // Compute whether this value requires an input register, an output register, 5586 // or both. 5587 bool isOutReg = false; 5588 bool isInReg = false; 5589 switch (OpInfo.Type) { 5590 case InlineAsm::isOutput: 5591 isOutReg = true; 5592 5593 // If there is an input constraint that matches this, we need to reserve 5594 // the input register so no other inputs allocate to it. 5595 isInReg = OpInfo.hasMatchingInput(); 5596 break; 5597 case InlineAsm::isInput: 5598 isInReg = true; 5599 isOutReg = false; 5600 break; 5601 case InlineAsm::isClobber: 5602 isOutReg = true; 5603 isInReg = true; 5604 break; 5605 } 5606 5607 5608 MachineFunction &MF = DAG.getMachineFunction(); 5609 SmallVector<unsigned, 4> Regs; 5610 5611 // If this is a constraint for a single physreg, or a constraint for a 5612 // register class, find it. 5613 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5614 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5615 OpInfo.ConstraintVT); 5616 5617 unsigned NumRegs = 1; 5618 if (OpInfo.ConstraintVT != MVT::Other) { 5619 // If this is a FP input in an integer register (or visa versa) insert a bit 5620 // cast of the input value. More generally, handle any case where the input 5621 // value disagrees with the register class we plan to stick this in. 5622 if (OpInfo.Type == InlineAsm::isInput && 5623 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5624 // Try to convert to the first EVT that the reg class contains. If the 5625 // types are identical size, use a bitcast to convert (e.g. two differing 5626 // vector types). 5627 EVT RegVT = *PhysReg.second->vt_begin(); 5628 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5629 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5630 RegVT, OpInfo.CallOperand); 5631 OpInfo.ConstraintVT = RegVT; 5632 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5633 // If the input is a FP value and we want it in FP registers, do a 5634 // bitcast to the corresponding integer type. This turns an f64 value 5635 // into i64, which can be passed with two i32 values on a 32-bit 5636 // machine. 5637 RegVT = EVT::getIntegerVT(Context, 5638 OpInfo.ConstraintVT.getSizeInBits()); 5639 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5640 RegVT, OpInfo.CallOperand); 5641 OpInfo.ConstraintVT = RegVT; 5642 } 5643 } 5644 5645 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5646 } 5647 5648 EVT RegVT; 5649 EVT ValueVT = OpInfo.ConstraintVT; 5650 5651 // If this is a constraint for a specific physical register, like {r17}, 5652 // assign it now. 5653 if (unsigned AssignedReg = PhysReg.first) { 5654 const TargetRegisterClass *RC = PhysReg.second; 5655 if (OpInfo.ConstraintVT == MVT::Other) 5656 ValueVT = *RC->vt_begin(); 5657 5658 // Get the actual register value type. This is important, because the user 5659 // may have asked for (e.g.) the AX register in i32 type. We need to 5660 // remember that AX is actually i16 to get the right extension. 5661 RegVT = *RC->vt_begin(); 5662 5663 // This is a explicit reference to a physical register. 5664 Regs.push_back(AssignedReg); 5665 5666 // If this is an expanded reference, add the rest of the regs to Regs. 5667 if (NumRegs != 1) { 5668 TargetRegisterClass::iterator I = RC->begin(); 5669 for (; *I != AssignedReg; ++I) 5670 assert(I != RC->end() && "Didn't find reg!"); 5671 5672 // Already added the first reg. 5673 --NumRegs; ++I; 5674 for (; NumRegs; --NumRegs, ++I) { 5675 assert(I != RC->end() && "Ran out of registers to allocate!"); 5676 Regs.push_back(*I); 5677 } 5678 } 5679 5680 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5681 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5682 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5683 return; 5684 } 5685 5686 // Otherwise, if this was a reference to an LLVM register class, create vregs 5687 // for this reference. 5688 if (const TargetRegisterClass *RC = PhysReg.second) { 5689 RegVT = *RC->vt_begin(); 5690 if (OpInfo.ConstraintVT == MVT::Other) 5691 ValueVT = RegVT; 5692 5693 // Create the appropriate number of virtual registers. 5694 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5695 for (; NumRegs; --NumRegs) 5696 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5697 5698 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5699 return; 5700 } 5701 5702 // Otherwise, we couldn't allocate enough registers for this. 5703} 5704 5705/// visitInlineAsm - Handle a call to an InlineAsm object. 5706/// 5707void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5708 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5709 5710 /// ConstraintOperands - Information about all of the constraints. 5711 SDISelAsmOperandInfoVector ConstraintOperands; 5712 5713 std::set<unsigned> OutputRegs, InputRegs; 5714 5715 TargetLowering::AsmOperandInfoVector 5716 TargetConstraints = TLI.ParseConstraints(CS); 5717 5718 bool hasMemory = false; 5719 5720 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5721 unsigned ResNo = 0; // ResNo - The result number of the next output. 5722 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5723 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5724 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5725 5726 EVT OpVT = MVT::Other; 5727 5728 // Compute the value type for each operand. 5729 switch (OpInfo.Type) { 5730 case InlineAsm::isOutput: 5731 // Indirect outputs just consume an argument. 5732 if (OpInfo.isIndirect) { 5733 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5734 break; 5735 } 5736 5737 // The return value of the call is this value. As such, there is no 5738 // corresponding argument. 5739 assert(!CS.getType()->isVoidTy() && 5740 "Bad inline asm!"); 5741 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5742 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5743 } else { 5744 assert(ResNo == 0 && "Asm only has one result!"); 5745 OpVT = TLI.getValueType(CS.getType()); 5746 } 5747 ++ResNo; 5748 break; 5749 case InlineAsm::isInput: 5750 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5751 break; 5752 case InlineAsm::isClobber: 5753 // Nothing to do. 5754 break; 5755 } 5756 5757 // If this is an input or an indirect output, process the call argument. 5758 // BasicBlocks are labels, currently appearing only in asm's. 5759 if (OpInfo.CallOperandVal) { 5760 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5761 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5762 } else { 5763 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5764 } 5765 5766 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5767 } 5768 5769 OpInfo.ConstraintVT = OpVT; 5770 5771 // Indirect operand accesses access memory. 5772 if (OpInfo.isIndirect) 5773 hasMemory = true; 5774 else { 5775 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5776 TargetLowering::ConstraintType 5777 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5778 if (CType == TargetLowering::C_Memory) { 5779 hasMemory = true; 5780 break; 5781 } 5782 } 5783 } 5784 } 5785 5786 SDValue Chain, Flag; 5787 5788 // We won't need to flush pending loads if this asm doesn't touch 5789 // memory and is nonvolatile. 5790 if (hasMemory || IA->hasSideEffects()) 5791 Chain = getRoot(); 5792 else 5793 Chain = DAG.getRoot(); 5794 5795 // Second pass over the constraints: compute which constraint option to use 5796 // and assign registers to constraints that want a specific physreg. 5797 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5798 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5799 5800 // If this is an output operand with a matching input operand, look up the 5801 // matching input. If their types mismatch, e.g. one is an integer, the 5802 // other is floating point, or their sizes are different, flag it as an 5803 // error. 5804 if (OpInfo.hasMatchingInput()) { 5805 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5806 5807 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5808 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5809 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); 5810 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5811 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT); 5812 if ((OpInfo.ConstraintVT.isInteger() != 5813 Input.ConstraintVT.isInteger()) || 5814 (MatchRC.second != InputRC.second)) { 5815 report_fatal_error("Unsupported asm: input constraint" 5816 " with a matching output constraint of" 5817 " incompatible type!"); 5818 } 5819 Input.ConstraintVT = OpInfo.ConstraintVT; 5820 } 5821 } 5822 5823 // Compute the constraint code and ConstraintType to use. 5824 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5825 5826 // If this is a memory input, and if the operand is not indirect, do what we 5827 // need to to provide an address for the memory input. 5828 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5829 !OpInfo.isIndirect) { 5830 assert((OpInfo.isMultipleAlternative || 5831 (OpInfo.Type == InlineAsm::isInput)) && 5832 "Can only indirectify direct input operands!"); 5833 5834 // Memory operands really want the address of the value. If we don't have 5835 // an indirect input, put it in the constpool if we can, otherwise spill 5836 // it to a stack slot. 5837 // TODO: This isn't quite right. We need to handle these according to 5838 // the addressing mode that the constraint wants. Also, this may take 5839 // an additional register for the computation and we don't want that 5840 // either. 5841 5842 // If the operand is a float, integer, or vector constant, spill to a 5843 // constant pool entry to get its address. 5844 const Value *OpVal = OpInfo.CallOperandVal; 5845 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5846 isa<ConstantVector>(OpVal)) { 5847 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5848 TLI.getPointerTy()); 5849 } else { 5850 // Otherwise, create a stack slot and emit a store to it before the 5851 // asm. 5852 Type *Ty = OpVal->getType(); 5853 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5854 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5855 MachineFunction &MF = DAG.getMachineFunction(); 5856 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5857 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5858 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5859 OpInfo.CallOperand, StackSlot, 5860 MachinePointerInfo::getFixedStack(SSFI), 5861 false, false, 0); 5862 OpInfo.CallOperand = StackSlot; 5863 } 5864 5865 // There is no longer a Value* corresponding to this operand. 5866 OpInfo.CallOperandVal = 0; 5867 5868 // It is now an indirect operand. 5869 OpInfo.isIndirect = true; 5870 } 5871 5872 // If this constraint is for a specific register, allocate it before 5873 // anything else. 5874 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5875 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5876 InputRegs); 5877 } 5878 5879 // Second pass - Loop over all of the operands, assigning virtual or physregs 5880 // to register class operands. 5881 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5882 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5883 5884 // C_Register operands have already been allocated, Other/Memory don't need 5885 // to be. 5886 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5887 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5888 InputRegs); 5889 } 5890 5891 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5892 std::vector<SDValue> AsmNodeOperands; 5893 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5894 AsmNodeOperands.push_back( 5895 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5896 TLI.getPointerTy())); 5897 5898 // If we have a !srcloc metadata node associated with it, we want to attach 5899 // this to the ultimately generated inline asm machineinstr. To do this, we 5900 // pass in the third operand as this (potentially null) inline asm MDNode. 5901 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5902 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5903 5904 // Remember the HasSideEffect and AlignStack bits as operand 3. 5905 unsigned ExtraInfo = 0; 5906 if (IA->hasSideEffects()) 5907 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 5908 if (IA->isAlignStack()) 5909 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 5910 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 5911 TLI.getPointerTy())); 5912 5913 // Loop over all of the inputs, copying the operand values into the 5914 // appropriate registers and processing the output regs. 5915 RegsForValue RetValRegs; 5916 5917 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5918 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5919 5920 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5921 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5922 5923 switch (OpInfo.Type) { 5924 case InlineAsm::isOutput: { 5925 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5926 OpInfo.ConstraintType != TargetLowering::C_Register) { 5927 // Memory output, or 'other' output (e.g. 'X' constraint). 5928 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5929 5930 // Add information to the INLINEASM node to know about this output. 5931 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5932 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5933 TLI.getPointerTy())); 5934 AsmNodeOperands.push_back(OpInfo.CallOperand); 5935 break; 5936 } 5937 5938 // Otherwise, this is a register or register class output. 5939 5940 // Copy the output from the appropriate register. Find a register that 5941 // we can use. 5942 if (OpInfo.AssignedRegs.Regs.empty()) 5943 report_fatal_error("Couldn't allocate output reg for constraint '" + 5944 Twine(OpInfo.ConstraintCode) + "'!"); 5945 5946 // If this is an indirect operand, store through the pointer after the 5947 // asm. 5948 if (OpInfo.isIndirect) { 5949 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5950 OpInfo.CallOperandVal)); 5951 } else { 5952 // This is the result value of the call. 5953 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5954 // Concatenate this output onto the outputs list. 5955 RetValRegs.append(OpInfo.AssignedRegs); 5956 } 5957 5958 // Add information to the INLINEASM node to know that this register is 5959 // set. 5960 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5961 InlineAsm::Kind_RegDefEarlyClobber : 5962 InlineAsm::Kind_RegDef, 5963 false, 5964 0, 5965 DAG, 5966 AsmNodeOperands); 5967 break; 5968 } 5969 case InlineAsm::isInput: { 5970 SDValue InOperandVal = OpInfo.CallOperand; 5971 5972 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5973 // If this is required to match an output register we have already set, 5974 // just use its register. 5975 unsigned OperandNo = OpInfo.getMatchedOperand(); 5976 5977 // Scan until we find the definition we already emitted of this operand. 5978 // When we find it, create a RegsForValue operand. 5979 unsigned CurOp = InlineAsm::Op_FirstOperand; 5980 for (; OperandNo; --OperandNo) { 5981 // Advance to the next operand. 5982 unsigned OpFlag = 5983 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5984 assert((InlineAsm::isRegDefKind(OpFlag) || 5985 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5986 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5987 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5988 } 5989 5990 unsigned OpFlag = 5991 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5992 if (InlineAsm::isRegDefKind(OpFlag) || 5993 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5994 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5995 if (OpInfo.isIndirect) { 5996 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5997 LLVMContext &Ctx = *DAG.getContext(); 5998 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5999 " don't know how to handle tied " 6000 "indirect register inputs"); 6001 } 6002 6003 RegsForValue MatchedRegs; 6004 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6005 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6006 MatchedRegs.RegVTs.push_back(RegVT); 6007 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6008 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6009 i != e; ++i) 6010 MatchedRegs.Regs.push_back 6011 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6012 6013 // Use the produced MatchedRegs object to 6014 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6015 Chain, &Flag); 6016 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6017 true, OpInfo.getMatchedOperand(), 6018 DAG, AsmNodeOperands); 6019 break; 6020 } 6021 6022 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6023 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6024 "Unexpected number of operands"); 6025 // Add information to the INLINEASM node to know about this input. 6026 // See InlineAsm.h isUseOperandTiedToDef. 6027 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6028 OpInfo.getMatchedOperand()); 6029 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6030 TLI.getPointerTy())); 6031 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6032 break; 6033 } 6034 6035 // Treat indirect 'X' constraint as memory. 6036 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6037 OpInfo.isIndirect) 6038 OpInfo.ConstraintType = TargetLowering::C_Memory; 6039 6040 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6041 std::vector<SDValue> Ops; 6042 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6043 Ops, DAG); 6044 if (Ops.empty()) 6045 report_fatal_error("Invalid operand for inline asm constraint '" + 6046 Twine(OpInfo.ConstraintCode) + "'!"); 6047 6048 // Add information to the INLINEASM node to know about this input. 6049 unsigned ResOpType = 6050 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6051 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6052 TLI.getPointerTy())); 6053 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6054 break; 6055 } 6056 6057 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6058 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6059 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6060 "Memory operands expect pointer values"); 6061 6062 // Add information to the INLINEASM node to know about this input. 6063 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6064 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6065 TLI.getPointerTy())); 6066 AsmNodeOperands.push_back(InOperandVal); 6067 break; 6068 } 6069 6070 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6071 OpInfo.ConstraintType == TargetLowering::C_Register) && 6072 "Unknown constraint type!"); 6073 assert(!OpInfo.isIndirect && 6074 "Don't know how to handle indirect register inputs yet!"); 6075 6076 // Copy the input into the appropriate registers. 6077 if (OpInfo.AssignedRegs.Regs.empty()) 6078 report_fatal_error("Couldn't allocate input reg for constraint '" + 6079 Twine(OpInfo.ConstraintCode) + "'!"); 6080 6081 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6082 Chain, &Flag); 6083 6084 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6085 DAG, AsmNodeOperands); 6086 break; 6087 } 6088 case InlineAsm::isClobber: { 6089 // Add the clobbered value to the operand list, so that the register 6090 // allocator is aware that the physreg got clobbered. 6091 if (!OpInfo.AssignedRegs.Regs.empty()) 6092 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6093 false, 0, DAG, 6094 AsmNodeOperands); 6095 break; 6096 } 6097 } 6098 } 6099 6100 // Finish up input operands. Set the input chain and add the flag last. 6101 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6102 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6103 6104 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6105 DAG.getVTList(MVT::Other, MVT::Glue), 6106 &AsmNodeOperands[0], AsmNodeOperands.size()); 6107 Flag = Chain.getValue(1); 6108 6109 // If this asm returns a register value, copy the result from that register 6110 // and set it as the value of the call. 6111 if (!RetValRegs.Regs.empty()) { 6112 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6113 Chain, &Flag); 6114 6115 // FIXME: Why don't we do this for inline asms with MRVs? 6116 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6117 EVT ResultType = TLI.getValueType(CS.getType()); 6118 6119 // If any of the results of the inline asm is a vector, it may have the 6120 // wrong width/num elts. This can happen for register classes that can 6121 // contain multiple different value types. The preg or vreg allocated may 6122 // not have the same VT as was expected. Convert it to the right type 6123 // with bit_convert. 6124 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6125 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6126 ResultType, Val); 6127 6128 } else if (ResultType != Val.getValueType() && 6129 ResultType.isInteger() && Val.getValueType().isInteger()) { 6130 // If a result value was tied to an input value, the computed result may 6131 // have a wider width than the expected result. Extract the relevant 6132 // portion. 6133 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6134 } 6135 6136 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6137 } 6138 6139 setValue(CS.getInstruction(), Val); 6140 // Don't need to use this as a chain in this case. 6141 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6142 return; 6143 } 6144 6145 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6146 6147 // Process indirect outputs, first output all of the flagged copies out of 6148 // physregs. 6149 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6150 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6151 const Value *Ptr = IndirectStoresToEmit[i].second; 6152 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6153 Chain, &Flag); 6154 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6155 } 6156 6157 // Emit the non-flagged stores from the physregs. 6158 SmallVector<SDValue, 8> OutChains; 6159 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6160 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6161 StoresToEmit[i].first, 6162 getValue(StoresToEmit[i].second), 6163 MachinePointerInfo(StoresToEmit[i].second), 6164 false, false, 0); 6165 OutChains.push_back(Val); 6166 } 6167 6168 if (!OutChains.empty()) 6169 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6170 &OutChains[0], OutChains.size()); 6171 6172 DAG.setRoot(Chain); 6173} 6174 6175void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6176 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6177 MVT::Other, getRoot(), 6178 getValue(I.getArgOperand(0)), 6179 DAG.getSrcValue(I.getArgOperand(0)))); 6180} 6181 6182void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6183 const TargetData &TD = *TLI.getTargetData(); 6184 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6185 getRoot(), getValue(I.getOperand(0)), 6186 DAG.getSrcValue(I.getOperand(0)), 6187 TD.getABITypeAlignment(I.getType())); 6188 setValue(&I, V); 6189 DAG.setRoot(V.getValue(1)); 6190} 6191 6192void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6193 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6194 MVT::Other, getRoot(), 6195 getValue(I.getArgOperand(0)), 6196 DAG.getSrcValue(I.getArgOperand(0)))); 6197} 6198 6199void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6200 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6201 MVT::Other, getRoot(), 6202 getValue(I.getArgOperand(0)), 6203 getValue(I.getArgOperand(1)), 6204 DAG.getSrcValue(I.getArgOperand(0)), 6205 DAG.getSrcValue(I.getArgOperand(1)))); 6206} 6207 6208/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6209/// implementation, which just calls LowerCall. 6210/// FIXME: When all targets are 6211/// migrated to using LowerCall, this hook should be integrated into SDISel. 6212std::pair<SDValue, SDValue> 6213TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6214 bool RetSExt, bool RetZExt, bool isVarArg, 6215 bool isInreg, unsigned NumFixedArgs, 6216 CallingConv::ID CallConv, bool isTailCall, 6217 bool isReturnValueUsed, 6218 SDValue Callee, 6219 ArgListTy &Args, SelectionDAG &DAG, 6220 DebugLoc dl) const { 6221 // Handle all of the outgoing arguments. 6222 SmallVector<ISD::OutputArg, 32> Outs; 6223 SmallVector<SDValue, 32> OutVals; 6224 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6225 SmallVector<EVT, 4> ValueVTs; 6226 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6227 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6228 Value != NumValues; ++Value) { 6229 EVT VT = ValueVTs[Value]; 6230 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6231 SDValue Op = SDValue(Args[i].Node.getNode(), 6232 Args[i].Node.getResNo() + Value); 6233 ISD::ArgFlagsTy Flags; 6234 unsigned OriginalAlignment = 6235 getTargetData()->getABITypeAlignment(ArgTy); 6236 6237 if (Args[i].isZExt) 6238 Flags.setZExt(); 6239 if (Args[i].isSExt) 6240 Flags.setSExt(); 6241 if (Args[i].isInReg) 6242 Flags.setInReg(); 6243 if (Args[i].isSRet) 6244 Flags.setSRet(); 6245 if (Args[i].isByVal) { 6246 Flags.setByVal(); 6247 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6248 Type *ElementTy = Ty->getElementType(); 6249 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6250 // For ByVal, alignment should come from FE. BE will guess if this 6251 // info is not there but there are cases it cannot get right. 6252 unsigned FrameAlign; 6253 if (Args[i].Alignment) 6254 FrameAlign = Args[i].Alignment; 6255 else 6256 FrameAlign = getByValTypeAlignment(ElementTy); 6257 Flags.setByValAlign(FrameAlign); 6258 } 6259 if (Args[i].isNest) 6260 Flags.setNest(); 6261 Flags.setOrigAlign(OriginalAlignment); 6262 6263 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6264 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6265 SmallVector<SDValue, 4> Parts(NumParts); 6266 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6267 6268 if (Args[i].isSExt) 6269 ExtendKind = ISD::SIGN_EXTEND; 6270 else if (Args[i].isZExt) 6271 ExtendKind = ISD::ZERO_EXTEND; 6272 6273 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6274 PartVT, ExtendKind); 6275 6276 for (unsigned j = 0; j != NumParts; ++j) { 6277 // if it isn't first piece, alignment must be 1 6278 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6279 i < NumFixedArgs); 6280 if (NumParts > 1 && j == 0) 6281 MyFlags.Flags.setSplit(); 6282 else if (j != 0) 6283 MyFlags.Flags.setOrigAlign(1); 6284 6285 Outs.push_back(MyFlags); 6286 OutVals.push_back(Parts[j]); 6287 } 6288 } 6289 } 6290 6291 // Handle the incoming return values from the call. 6292 SmallVector<ISD::InputArg, 32> Ins; 6293 SmallVector<EVT, 4> RetTys; 6294 ComputeValueVTs(*this, RetTy, RetTys); 6295 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6296 EVT VT = RetTys[I]; 6297 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6298 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6299 for (unsigned i = 0; i != NumRegs; ++i) { 6300 ISD::InputArg MyFlags; 6301 MyFlags.VT = RegisterVT.getSimpleVT(); 6302 MyFlags.Used = isReturnValueUsed; 6303 if (RetSExt) 6304 MyFlags.Flags.setSExt(); 6305 if (RetZExt) 6306 MyFlags.Flags.setZExt(); 6307 if (isInreg) 6308 MyFlags.Flags.setInReg(); 6309 Ins.push_back(MyFlags); 6310 } 6311 } 6312 6313 SmallVector<SDValue, 4> InVals; 6314 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6315 Outs, OutVals, Ins, dl, DAG, InVals); 6316 6317 // Verify that the target's LowerCall behaved as expected. 6318 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6319 "LowerCall didn't return a valid chain!"); 6320 assert((!isTailCall || InVals.empty()) && 6321 "LowerCall emitted a return value for a tail call!"); 6322 assert((isTailCall || InVals.size() == Ins.size()) && 6323 "LowerCall didn't emit the correct number of values!"); 6324 6325 // For a tail call, the return value is merely live-out and there aren't 6326 // any nodes in the DAG representing it. Return a special value to 6327 // indicate that a tail call has been emitted and no more Instructions 6328 // should be processed in the current block. 6329 if (isTailCall) { 6330 DAG.setRoot(Chain); 6331 return std::make_pair(SDValue(), SDValue()); 6332 } 6333 6334 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6335 assert(InVals[i].getNode() && 6336 "LowerCall emitted a null value!"); 6337 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6338 "LowerCall emitted a value with the wrong type!"); 6339 }); 6340 6341 // Collect the legal value parts into potentially illegal values 6342 // that correspond to the original function's return values. 6343 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6344 if (RetSExt) 6345 AssertOp = ISD::AssertSext; 6346 else if (RetZExt) 6347 AssertOp = ISD::AssertZext; 6348 SmallVector<SDValue, 4> ReturnValues; 6349 unsigned CurReg = 0; 6350 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6351 EVT VT = RetTys[I]; 6352 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6353 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6354 6355 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6356 NumRegs, RegisterVT, VT, 6357 AssertOp)); 6358 CurReg += NumRegs; 6359 } 6360 6361 // For a function returning void, there is no return value. We can't create 6362 // such a node, so we just return a null return value in that case. In 6363 // that case, nothing will actually look at the value. 6364 if (ReturnValues.empty()) 6365 return std::make_pair(SDValue(), Chain); 6366 6367 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6368 DAG.getVTList(&RetTys[0], RetTys.size()), 6369 &ReturnValues[0], ReturnValues.size()); 6370 return std::make_pair(Res, Chain); 6371} 6372 6373void TargetLowering::LowerOperationWrapper(SDNode *N, 6374 SmallVectorImpl<SDValue> &Results, 6375 SelectionDAG &DAG) const { 6376 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6377 if (Res.getNode()) 6378 Results.push_back(Res); 6379} 6380 6381SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6382 llvm_unreachable("LowerOperation not implemented for this target!"); 6383 return SDValue(); 6384} 6385 6386void 6387SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6388 SDValue Op = getNonRegisterValue(V); 6389 assert((Op.getOpcode() != ISD::CopyFromReg || 6390 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6391 "Copy from a reg to the same reg!"); 6392 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6393 6394 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6395 SDValue Chain = DAG.getEntryNode(); 6396 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6397 PendingExports.push_back(Chain); 6398} 6399 6400#include "llvm/CodeGen/SelectionDAGISel.h" 6401 6402/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6403/// entry block, return true. This includes arguments used by switches, since 6404/// the switch may expand into multiple basic blocks. 6405static bool isOnlyUsedInEntryBlock(const Argument *A) { 6406 // With FastISel active, we may be splitting blocks, so force creation 6407 // of virtual registers for all non-dead arguments. 6408 if (EnableFastISel) 6409 return A->use_empty(); 6410 6411 const BasicBlock *Entry = A->getParent()->begin(); 6412 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6413 UI != E; ++UI) { 6414 const User *U = *UI; 6415 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6416 return false; // Use not in entry block. 6417 } 6418 return true; 6419} 6420 6421void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6422 // If this is the entry block, emit arguments. 6423 const Function &F = *LLVMBB->getParent(); 6424 SelectionDAG &DAG = SDB->DAG; 6425 DebugLoc dl = SDB->getCurDebugLoc(); 6426 const TargetData *TD = TLI.getTargetData(); 6427 SmallVector<ISD::InputArg, 16> Ins; 6428 6429 // Check whether the function can return without sret-demotion. 6430 SmallVector<ISD::OutputArg, 4> Outs; 6431 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6432 Outs, TLI); 6433 6434 if (!FuncInfo->CanLowerReturn) { 6435 // Put in an sret pointer parameter before all the other parameters. 6436 SmallVector<EVT, 1> ValueVTs; 6437 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6438 6439 // NOTE: Assuming that a pointer will never break down to more than one VT 6440 // or one register. 6441 ISD::ArgFlagsTy Flags; 6442 Flags.setSRet(); 6443 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6444 ISD::InputArg RetArg(Flags, RegisterVT, true); 6445 Ins.push_back(RetArg); 6446 } 6447 6448 // Set up the incoming argument description vector. 6449 unsigned Idx = 1; 6450 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6451 I != E; ++I, ++Idx) { 6452 SmallVector<EVT, 4> ValueVTs; 6453 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6454 bool isArgValueUsed = !I->use_empty(); 6455 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6456 Value != NumValues; ++Value) { 6457 EVT VT = ValueVTs[Value]; 6458 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6459 ISD::ArgFlagsTy Flags; 6460 unsigned OriginalAlignment = 6461 TD->getABITypeAlignment(ArgTy); 6462 6463 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6464 Flags.setZExt(); 6465 if (F.paramHasAttr(Idx, Attribute::SExt)) 6466 Flags.setSExt(); 6467 if (F.paramHasAttr(Idx, Attribute::InReg)) 6468 Flags.setInReg(); 6469 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6470 Flags.setSRet(); 6471 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6472 Flags.setByVal(); 6473 PointerType *Ty = cast<PointerType>(I->getType()); 6474 Type *ElementTy = Ty->getElementType(); 6475 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6476 // For ByVal, alignment should be passed from FE. BE will guess if 6477 // this info is not there but there are cases it cannot get right. 6478 unsigned FrameAlign; 6479 if (F.getParamAlignment(Idx)) 6480 FrameAlign = F.getParamAlignment(Idx); 6481 else 6482 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6483 Flags.setByValAlign(FrameAlign); 6484 } 6485 if (F.paramHasAttr(Idx, Attribute::Nest)) 6486 Flags.setNest(); 6487 Flags.setOrigAlign(OriginalAlignment); 6488 6489 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6490 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6491 for (unsigned i = 0; i != NumRegs; ++i) { 6492 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6493 if (NumRegs > 1 && i == 0) 6494 MyFlags.Flags.setSplit(); 6495 // if it isn't first piece, alignment must be 1 6496 else if (i > 0) 6497 MyFlags.Flags.setOrigAlign(1); 6498 Ins.push_back(MyFlags); 6499 } 6500 } 6501 } 6502 6503 // Call the target to set up the argument values. 6504 SmallVector<SDValue, 8> InVals; 6505 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6506 F.isVarArg(), Ins, 6507 dl, DAG, InVals); 6508 6509 // Verify that the target's LowerFormalArguments behaved as expected. 6510 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6511 "LowerFormalArguments didn't return a valid chain!"); 6512 assert(InVals.size() == Ins.size() && 6513 "LowerFormalArguments didn't emit the correct number of values!"); 6514 DEBUG({ 6515 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6516 assert(InVals[i].getNode() && 6517 "LowerFormalArguments emitted a null value!"); 6518 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6519 "LowerFormalArguments emitted a value with the wrong type!"); 6520 } 6521 }); 6522 6523 // Update the DAG with the new chain value resulting from argument lowering. 6524 DAG.setRoot(NewRoot); 6525 6526 // Set up the argument values. 6527 unsigned i = 0; 6528 Idx = 1; 6529 if (!FuncInfo->CanLowerReturn) { 6530 // Create a virtual register for the sret pointer, and put in a copy 6531 // from the sret argument into it. 6532 SmallVector<EVT, 1> ValueVTs; 6533 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6534 EVT VT = ValueVTs[0]; 6535 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6536 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6537 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6538 RegVT, VT, AssertOp); 6539 6540 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6541 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6542 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6543 FuncInfo->DemoteRegister = SRetReg; 6544 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6545 SRetReg, ArgValue); 6546 DAG.setRoot(NewRoot); 6547 6548 // i indexes lowered arguments. Bump it past the hidden sret argument. 6549 // Idx indexes LLVM arguments. Don't touch it. 6550 ++i; 6551 } 6552 6553 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6554 ++I, ++Idx) { 6555 SmallVector<SDValue, 4> ArgValues; 6556 SmallVector<EVT, 4> ValueVTs; 6557 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6558 unsigned NumValues = ValueVTs.size(); 6559 6560 // If this argument is unused then remember its value. It is used to generate 6561 // debugging information. 6562 if (I->use_empty() && NumValues) 6563 SDB->setUnusedArgValue(I, InVals[i]); 6564 6565 for (unsigned Val = 0; Val != NumValues; ++Val) { 6566 EVT VT = ValueVTs[Val]; 6567 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6568 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6569 6570 if (!I->use_empty()) { 6571 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6572 if (F.paramHasAttr(Idx, Attribute::SExt)) 6573 AssertOp = ISD::AssertSext; 6574 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6575 AssertOp = ISD::AssertZext; 6576 6577 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6578 NumParts, PartVT, VT, 6579 AssertOp)); 6580 } 6581 6582 i += NumParts; 6583 } 6584 6585 // We don't need to do anything else for unused arguments. 6586 if (ArgValues.empty()) 6587 continue; 6588 6589 // Note down frame index for byval arguments. 6590 if (I->hasByValAttr()) 6591 if (FrameIndexSDNode *FI = 6592 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6593 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6594 6595 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6596 SDB->getCurDebugLoc()); 6597 SDB->setValue(I, Res); 6598 6599 // If this argument is live outside of the entry block, insert a copy from 6600 // wherever we got it to the vreg that other BB's will reference it as. 6601 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6602 // If we can, though, try to skip creating an unnecessary vreg. 6603 // FIXME: This isn't very clean... it would be nice to make this more 6604 // general. It's also subtly incompatible with the hacks FastISel 6605 // uses with vregs. 6606 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6607 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6608 FuncInfo->ValueMap[I] = Reg; 6609 continue; 6610 } 6611 } 6612 if (!isOnlyUsedInEntryBlock(I)) { 6613 FuncInfo->InitializeRegForValue(I); 6614 SDB->CopyToExportRegsIfNeeded(I); 6615 } 6616 } 6617 6618 assert(i == InVals.size() && "Argument register count mismatch!"); 6619 6620 // Finally, if the target has anything special to do, allow it to do so. 6621 // FIXME: this should insert code into the DAG! 6622 EmitFunctionEntryCode(); 6623} 6624 6625/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6626/// ensure constants are generated when needed. Remember the virtual registers 6627/// that need to be added to the Machine PHI nodes as input. We cannot just 6628/// directly add them, because expansion might result in multiple MBB's for one 6629/// BB. As such, the start of the BB might correspond to a different MBB than 6630/// the end. 6631/// 6632void 6633SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6634 const TerminatorInst *TI = LLVMBB->getTerminator(); 6635 6636 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6637 6638 // Check successor nodes' PHI nodes that expect a constant to be available 6639 // from this block. 6640 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6641 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6642 if (!isa<PHINode>(SuccBB->begin())) continue; 6643 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6644 6645 // If this terminator has multiple identical successors (common for 6646 // switches), only handle each succ once. 6647 if (!SuccsHandled.insert(SuccMBB)) continue; 6648 6649 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6650 6651 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6652 // nodes and Machine PHI nodes, but the incoming operands have not been 6653 // emitted yet. 6654 for (BasicBlock::const_iterator I = SuccBB->begin(); 6655 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6656 // Ignore dead phi's. 6657 if (PN->use_empty()) continue; 6658 6659 // Skip empty types 6660 if (PN->getType()->isEmptyTy()) 6661 continue; 6662 6663 unsigned Reg; 6664 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6665 6666 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6667 unsigned &RegOut = ConstantsOut[C]; 6668 if (RegOut == 0) { 6669 RegOut = FuncInfo.CreateRegs(C->getType()); 6670 CopyValueToVirtualRegister(C, RegOut); 6671 } 6672 Reg = RegOut; 6673 } else { 6674 DenseMap<const Value *, unsigned>::iterator I = 6675 FuncInfo.ValueMap.find(PHIOp); 6676 if (I != FuncInfo.ValueMap.end()) 6677 Reg = I->second; 6678 else { 6679 assert(isa<AllocaInst>(PHIOp) && 6680 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6681 "Didn't codegen value into a register!??"); 6682 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6683 CopyValueToVirtualRegister(PHIOp, Reg); 6684 } 6685 } 6686 6687 // Remember that this register needs to added to the machine PHI node as 6688 // the input for this MBB. 6689 SmallVector<EVT, 4> ValueVTs; 6690 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6691 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6692 EVT VT = ValueVTs[vti]; 6693 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6694 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6695 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6696 Reg += NumRegisters; 6697 } 6698 } 6699 } 6700 ConstantsOut.clear(); 6701} 6702