SelectionDAGBuilder.cpp revision 5787124820f9f544216675c020ff0b33e090d181
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getIntPtrConstant(1)); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209 return SDValue(); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert(PartVT.isInteger() && ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 } 361 } else if (PartBits == ValueVT.getSizeInBits()) { 362 // Different types of the same size. 363 assert(NumParts == 1 && PartVT != ValueVT); 364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 366 // If the parts cover less bits than value has, truncate the value. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Unknown mismatch!"); 369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 371 } 372 373 // The value may have changed - recompute ValueVT. 374 ValueVT = Val.getValueType(); 375 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 376 "Failed to tile the value with PartVT!"); 377 378 if (NumParts == 1) { 379 assert(PartVT == ValueVT && "Type conversion failed!"); 380 Parts[0] = Val; 381 return; 382 } 383 384 // Expand the value into multiple parts. 385 if (NumParts & (NumParts - 1)) { 386 // The number of parts is not a power of 2. Split off and copy the tail. 387 assert(PartVT.isInteger() && ValueVT.isInteger() && 388 "Do not know what to expand to!"); 389 unsigned RoundParts = 1 << Log2_32(NumParts); 390 unsigned RoundBits = RoundParts * PartBits; 391 unsigned OddParts = NumParts - RoundParts; 392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 393 DAG.getIntPtrConstant(RoundBits)); 394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 395 396 if (TLI.isBigEndian()) 397 // The odd parts were reversed by getCopyToParts - unreverse them. 398 std::reverse(Parts + RoundParts, Parts + NumParts); 399 400 NumParts = RoundParts; 401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 403 } 404 405 // The number of parts is a power of 2. Repeatedly bisect the value using 406 // EXTRACT_ELEMENT. 407 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 408 EVT::getIntegerVT(*DAG.getContext(), 409 ValueVT.getSizeInBits()), 410 Val); 411 412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 413 for (unsigned i = 0; i < NumParts; i += StepSize) { 414 unsigned ThisBits = StepSize * PartBits / 2; 415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 416 SDValue &Part0 = Parts[i]; 417 SDValue &Part1 = Parts[i+StepSize/2]; 418 419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 420 ThisVT, Part0, DAG.getIntPtrConstant(1)); 421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 422 ThisVT, Part0, DAG.getIntPtrConstant(0)); 423 424 if (ThisBits == PartBits && ThisVT != PartVT) { 425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 427 } 428 } 429 } 430 431 if (TLI.isBigEndian()) 432 std::reverse(Parts, Parts + OrigNumParts); 433} 434 435 436/// getCopyToPartsVector - Create a series of nodes that contain the specified 437/// value split into legal parts. 438static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 439 SDValue Val, SDValue *Parts, unsigned NumParts, 440 EVT PartVT) { 441 EVT ValueVT = Val.getValueType(); 442 assert(ValueVT.isVector() && "Not a vector"); 443 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 444 445 if (NumParts == 1) { 446 if (PartVT == ValueVT) { 447 // Nothing to do. 448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 449 // Bitconvert vector->vector case. 450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 451 } else if (PartVT.isVector() && 452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 454 EVT ElementVT = PartVT.getVectorElementType(); 455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 456 // undef elements. 457 SmallVector<SDValue, 16> Ops; 458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 460 ElementVT, Val, DAG.getIntPtrConstant(i))); 461 462 for (unsigned i = ValueVT.getVectorNumElements(), 463 e = PartVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getUNDEF(ElementVT)); 465 466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 467 468 // FIXME: Use CONCAT for 2x -> 4x. 469 470 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 472 } else if (PartVT.isVector() && 473 PartVT.getVectorElementType().bitsGE( 474 ValueVT.getVectorElementType()) && 475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 476 477 // Promoted vector extract 478 bool Smaller = PartVT.bitsLE(ValueVT); 479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 480 DL, PartVT, Val); 481 } else{ 482 // Vector -> scalar conversion. 483 assert(ValueVT.getVectorNumElements() == 1 && 484 "Only trivial vector-to-scalar conversions should get here!"); 485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 PartVT, Val, DAG.getIntPtrConstant(0)); 487 488 bool Smaller = ValueVT.bitsLE(PartVT); 489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 490 DL, PartVT, Val); 491 } 492 493 Parts[0] = Val; 494 return; 495 } 496 497 // Handle a multi-element vector. 498 EVT IntermediateVT, RegisterVT; 499 unsigned NumIntermediates; 500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 501 IntermediateVT, 502 NumIntermediates, RegisterVT); 503 unsigned NumElements = ValueVT.getVectorNumElements(); 504 505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 506 NumParts = NumRegs; // Silence a compiler warning. 507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 508 509 // Split the vector into intermediate operands. 510 SmallVector<SDValue, 8> Ops(NumIntermediates); 511 for (unsigned i = 0; i != NumIntermediates; ++i) { 512 if (IntermediateVT.isVector()) 513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 514 IntermediateVT, Val, 515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 516 else 517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 519 } 520 521 // Split the intermediate operands into legal parts. 522 if (NumParts == NumIntermediates) { 523 // If the register was not expanded, promote or copy the value, 524 // as appropriate. 525 for (unsigned i = 0; i != NumParts; ++i) 526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 527 } else if (NumParts > 0) { 528 // If the intermediate type was expanded, split each the value into 529 // legal parts. 530 assert(NumParts % NumIntermediates == 0 && 531 "Must expand into a divisible number of parts!"); 532 unsigned Factor = NumParts / NumIntermediates; 533 for (unsigned i = 0; i != NumIntermediates; ++i) 534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 535 } 536} 537 538 539 540 541namespace { 542 /// RegsForValue - This struct represents the registers (physical or virtual) 543 /// that a particular set of values is assigned, and the type information 544 /// about the value. The most common situation is to represent one value at a 545 /// time, but struct or array values are handled element-wise as multiple 546 /// values. The splitting of aggregates is performed recursively, so that we 547 /// never have aggregate-typed registers. The values at this point do not 548 /// necessarily have legal types, so each value may require one or more 549 /// registers of some legal type. 550 /// 551 struct RegsForValue { 552 /// ValueVTs - The value types of the values, which may not be legal, and 553 /// may need be promoted or synthesized from one or more registers. 554 /// 555 SmallVector<EVT, 4> ValueVTs; 556 557 /// RegVTs - The value types of the registers. This is the same size as 558 /// ValueVTs and it records, for each value, what the type of the assigned 559 /// register or registers are. (Individual values are never synthesized 560 /// from more than one type of register.) 561 /// 562 /// With virtual registers, the contents of RegVTs is redundant with TLI's 563 /// getRegisterType member function, however when with physical registers 564 /// it is necessary to have a separate record of the types. 565 /// 566 SmallVector<EVT, 4> RegVTs; 567 568 /// Regs - This list holds the registers assigned to the values. 569 /// Each legal or promoted value requires one register, and each 570 /// expanded value requires multiple registers. 571 /// 572 SmallVector<unsigned, 4> Regs; 573 574 RegsForValue() {} 575 576 RegsForValue(const SmallVector<unsigned, 4> ®s, 577 EVT regvt, EVT valuevt) 578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 579 580 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 581 unsigned Reg, Type *Ty) { 582 ComputeValueVTs(tli, Ty, ValueVTs); 583 584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 585 EVT ValueVT = ValueVTs[Value]; 586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 588 for (unsigned i = 0; i != NumRegs; ++i) 589 Regs.push_back(Reg + i); 590 RegVTs.push_back(RegisterVT); 591 Reg += NumRegs; 592 } 593 } 594 595 /// areValueTypesLegal - Return true if types of all the values are legal. 596 bool areValueTypesLegal(const TargetLowering &TLI) { 597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 598 EVT RegisterVT = RegVTs[Value]; 599 if (!TLI.isTypeLegal(RegisterVT)) 600 return false; 601 } 602 return true; 603 } 604 605 /// append - Add the specified values to this one. 606 void append(const RegsForValue &RHS) { 607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 609 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 610 } 611 612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 613 /// this value and returns the result as a ValueVTs value. This uses 614 /// Chain/Flag as the input and updates them for the output Chain/Flag. 615 /// If the Flag pointer is NULL, no flag is used. 616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 617 DebugLoc dl, 618 SDValue &Chain, SDValue *Flag) const; 619 620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 621 /// specified value into the registers specified by this object. This uses 622 /// Chain/Flag as the input and updates them for the output Chain/Flag. 623 /// If the Flag pointer is NULL, no flag is used. 624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 625 SDValue &Chain, SDValue *Flag) const; 626 627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 628 /// operand list. This adds the code marker, matching input operand index 629 /// (if applicable), and includes the number of values added into it. 630 void AddInlineAsmOperands(unsigned Kind, 631 bool HasMatching, unsigned MatchingIdx, 632 SelectionDAG &DAG, 633 std::vector<SDValue> &Ops) const; 634 }; 635} 636 637/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 638/// this value and returns the result as a ValueVT value. This uses 639/// Chain/Flag as the input and updates them for the output Chain/Flag. 640/// If the Flag pointer is NULL, no flag is used. 641SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 642 FunctionLoweringInfo &FuncInfo, 643 DebugLoc dl, 644 SDValue &Chain, SDValue *Flag) const { 645 // A Value with type {} or [0 x %t] needs no registers. 646 if (ValueVTs.empty()) 647 return SDValue(); 648 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 650 651 // Assemble the legal parts into the final values. 652 SmallVector<SDValue, 4> Values(ValueVTs.size()); 653 SmallVector<SDValue, 8> Parts; 654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 655 // Copy the legal parts from the registers. 656 EVT ValueVT = ValueVTs[Value]; 657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 658 EVT RegisterVT = RegVTs[Value]; 659 660 Parts.resize(NumRegs); 661 for (unsigned i = 0; i != NumRegs; ++i) { 662 SDValue P; 663 if (Flag == 0) { 664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 665 } else { 666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 667 *Flag = P.getValue(2); 668 } 669 670 Chain = P.getValue(1); 671 Parts[i] = P; 672 673 // If the source register was virtual and if we know something about it, 674 // add an assert node. 675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 676 !RegisterVT.isInteger() || RegisterVT.isVector()) 677 continue; 678 679 const FunctionLoweringInfo::LiveOutInfo *LOI = 680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 681 if (!LOI) 682 continue; 683 684 unsigned RegSize = RegisterVT.getSizeInBits(); 685 unsigned NumSignBits = LOI->NumSignBits; 686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 687 688 // FIXME: We capture more information than the dag can represent. For 689 // now, just use the tightest assertzext/assertsext possible. 690 bool isSExt = true; 691 EVT FromVT(MVT::Other); 692 if (NumSignBits == RegSize) 693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 694 else if (NumZeroBits >= RegSize-1) 695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 696 else if (NumSignBits > RegSize-8) 697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 698 else if (NumZeroBits >= RegSize-8) 699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 700 else if (NumSignBits > RegSize-16) 701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 702 else if (NumZeroBits >= RegSize-16) 703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 704 else if (NumSignBits > RegSize-32) 705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 706 else if (NumZeroBits >= RegSize-32) 707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 708 else 709 continue; 710 711 // Add an assertion node. 712 assert(FromVT != MVT::Other); 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 714 RegisterVT, P, DAG.getValueType(FromVT)); 715 } 716 717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 718 NumRegs, RegisterVT, ValueVT); 719 Part += NumRegs; 720 Parts.clear(); 721 } 722 723 return DAG.getNode(ISD::MERGE_VALUES, dl, 724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 725 &Values[0], ValueVTs.size()); 726} 727 728/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 729/// specified value into the registers specified by this object. This uses 730/// Chain/Flag as the input and updates them for the output Chain/Flag. 731/// If the Flag pointer is NULL, no flag is used. 732void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 733 SDValue &Chain, SDValue *Flag) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 // Get the list of the values's legal parts. 737 unsigned NumRegs = Regs.size(); 738 SmallVector<SDValue, 8> Parts(NumRegs); 739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 740 EVT ValueVT = ValueVTs[Value]; 741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 742 EVT RegisterVT = RegVTs[Value]; 743 744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 745 &Parts[Part], NumParts, RegisterVT); 746 Part += NumParts; 747 } 748 749 // Copy the parts into the registers. 750 SmallVector<SDValue, 8> Chains(NumRegs); 751 for (unsigned i = 0; i != NumRegs; ++i) { 752 SDValue Part; 753 if (Flag == 0) { 754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 755 } else { 756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 757 *Flag = Part.getValue(1); 758 } 759 760 Chains[i] = Part.getValue(0); 761 } 762 763 if (NumRegs == 1 || Flag) 764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 765 // flagged to it. That is the CopyToReg nodes and the user are considered 766 // a single scheduling unit. If we create a TokenFactor and return it as 767 // chain, then the TokenFactor is both a predecessor (operand) of the 768 // user as well as a successor (the TF operands are flagged to the user). 769 // c1, f1 = CopyToReg 770 // c2, f2 = CopyToReg 771 // c3 = TokenFactor c1, c2 772 // ... 773 // = op c3, ..., f2 774 Chain = Chains[NumRegs-1]; 775 else 776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 777} 778 779/// AddInlineAsmOperands - Add this value to the specified inlineasm node 780/// operand list. This adds the code marker and includes the number of 781/// values added into it. 782void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 783 unsigned MatchingIdx, 784 SelectionDAG &DAG, 785 std::vector<SDValue> &Ops) const { 786 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 787 788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 789 if (HasMatching) 790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 792 Ops.push_back(Res); 793 794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 796 EVT RegisterVT = RegVTs[Value]; 797 for (unsigned i = 0; i != NumRegs; ++i) { 798 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 800 } 801 } 802} 803 804void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 805 AA = &aa; 806 GFI = gfi; 807 TD = DAG.getTarget().getTargetData(); 808} 809 810/// clear - Clear out the current SelectionDAG and the associated 811/// state and prepare this SelectionDAGBuilder object to be used 812/// for a new block. This doesn't clear out information about 813/// additional blocks that are needed to complete switch lowering 814/// or PHI node updating; that information is cleared out as it is 815/// consumed. 816void SelectionDAGBuilder::clear() { 817 NodeMap.clear(); 818 UnusedArgNodeMap.clear(); 819 PendingLoads.clear(); 820 PendingExports.clear(); 821 CurDebugLoc = DebugLoc(); 822 HasTailCall = false; 823} 824 825/// clearDanglingDebugInfo - Clear the dangling debug information 826/// map. This function is seperated from the clear so that debug 827/// information that is dangling in a basic block can be properly 828/// resolved in a different basic block. This allows the 829/// SelectionDAG to resolve dangling debug information attached 830/// to PHI nodes. 831void SelectionDAGBuilder::clearDanglingDebugInfo() { 832 DanglingDebugInfoMap.clear(); 833} 834 835/// getRoot - Return the current virtual root of the Selection DAG, 836/// flushing any PendingLoad items. This must be done before emitting 837/// a store or any other node that may need to be ordered after any 838/// prior load instructions. 839/// 840SDValue SelectionDAGBuilder::getRoot() { 841 if (PendingLoads.empty()) 842 return DAG.getRoot(); 843 844 if (PendingLoads.size() == 1) { 845 SDValue Root = PendingLoads[0]; 846 DAG.setRoot(Root); 847 PendingLoads.clear(); 848 return Root; 849 } 850 851 // Otherwise, we have to make a token factor node. 852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 853 &PendingLoads[0], PendingLoads.size()); 854 PendingLoads.clear(); 855 DAG.setRoot(Root); 856 return Root; 857} 858 859/// getControlRoot - Similar to getRoot, but instead of flushing all the 860/// PendingLoad items, flush all the PendingExports items. It is necessary 861/// to do this before emitting a terminator instruction. 862/// 863SDValue SelectionDAGBuilder::getControlRoot() { 864 SDValue Root = DAG.getRoot(); 865 866 if (PendingExports.empty()) 867 return Root; 868 869 // Turn all of the CopyToReg chains into one factored node. 870 if (Root.getOpcode() != ISD::EntryToken) { 871 unsigned i = 0, e = PendingExports.size(); 872 for (; i != e; ++i) { 873 assert(PendingExports[i].getNode()->getNumOperands() > 1); 874 if (PendingExports[i].getNode()->getOperand(0) == Root) 875 break; // Don't add the root if we already indirectly depend on it. 876 } 877 878 if (i == e) 879 PendingExports.push_back(Root); 880 } 881 882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 883 &PendingExports[0], 884 PendingExports.size()); 885 PendingExports.clear(); 886 DAG.setRoot(Root); 887 return Root; 888} 889 890void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 892 DAG.AssignOrdering(Node, SDNodeOrder); 893 894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 895 AssignOrderingToNode(Node->getOperand(I).getNode()); 896} 897 898void SelectionDAGBuilder::visit(const Instruction &I) { 899 // Set up outgoing PHI node register values before emitting the terminator. 900 if (isa<TerminatorInst>(&I)) 901 HandlePHINodesInSuccessorBlocks(I.getParent()); 902 903 CurDebugLoc = I.getDebugLoc(); 904 905 visit(I.getOpcode(), I); 906 907 if (!isa<TerminatorInst>(&I) && !HasTailCall) 908 CopyToExportRegsIfNeeded(&I); 909 910 CurDebugLoc = DebugLoc(); 911} 912 913void SelectionDAGBuilder::visitPHI(const PHINode &) { 914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 915} 916 917void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 918 // Note: this doesn't use InstVisitor, because it has to work with 919 // ConstantExpr's in addition to instructions. 920 switch (Opcode) { 921 default: llvm_unreachable("Unknown instruction type encountered!"); 922 // Build the switch statement using the Instruction.def file. 923#define HANDLE_INST(NUM, OPCODE, CLASS) \ 924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 925#include "llvm/Instruction.def" 926 } 927 928 // Assign the ordering to the freshly created DAG nodes. 929 if (NodeMap.count(&I)) { 930 ++SDNodeOrder; 931 AssignOrderingToNode(getValue(&I).getNode()); 932 } 933} 934 935// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 936// generate the debug data structures now that we've seen its definition. 937void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 938 SDValue Val) { 939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 940 if (DDI.getDI()) { 941 const DbgValueInst *DI = DDI.getDI(); 942 DebugLoc dl = DDI.getdl(); 943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 944 MDNode *Variable = DI->getVariable(); 945 uint64_t Offset = DI->getOffset(); 946 SDDbgValue *SDV; 947 if (Val.getNode()) { 948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 949 SDV = DAG.getDbgValue(Variable, Val.getNode(), 950 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 951 DAG.AddDbgValue(SDV, Val.getNode(), false); 952 } 953 } else 954 DEBUG(dbgs() << "Dropping debug info for " << DI); 955 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 956 } 957} 958 959// getValue - Return an SDValue for the given Value. 960SDValue SelectionDAGBuilder::getValue(const Value *V) { 961 // If we already have an SDValue for this value, use it. It's important 962 // to do this first, so that we don't create a CopyFromReg if we already 963 // have a regular SDValue. 964 SDValue &N = NodeMap[V]; 965 if (N.getNode()) return N; 966 967 // If there's a virtual register allocated and initialized for this 968 // value, use it. 969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 970 if (It != FuncInfo.ValueMap.end()) { 971 unsigned InReg = It->second; 972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 973 SDValue Chain = DAG.getEntryNode(); 974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 975 resolveDanglingDebugInfo(V, N); 976 return N; 977 } 978 979 // Otherwise create a new SDValue and remember it. 980 SDValue Val = getValueImpl(V); 981 NodeMap[V] = Val; 982 resolveDanglingDebugInfo(V, Val); 983 return Val; 984} 985 986/// getNonRegisterValue - Return an SDValue for the given Value, but 987/// don't look in FuncInfo.ValueMap for a virtual register. 988SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 989 // If we already have an SDValue for this value, use it. 990 SDValue &N = NodeMap[V]; 991 if (N.getNode()) return N; 992 993 // Otherwise create a new SDValue and remember it. 994 SDValue Val = getValueImpl(V); 995 NodeMap[V] = Val; 996 resolveDanglingDebugInfo(V, Val); 997 return Val; 998} 999 1000/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1001/// Create an SDValue for the given value. 1002SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1003 if (const Constant *C = dyn_cast<Constant>(V)) { 1004 EVT VT = TLI.getValueType(V->getType(), true); 1005 1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1007 return DAG.getConstant(*CI, VT); 1008 1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1011 1012 if (isa<ConstantPointerNull>(C)) 1013 return DAG.getConstant(0, TLI.getPointerTy()); 1014 1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1016 return DAG.getConstantFP(*CFP, VT); 1017 1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1019 return DAG.getUNDEF(VT); 1020 1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1022 visit(CE->getOpcode(), *CE); 1023 SDValue N1 = NodeMap[V]; 1024 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1025 return N1; 1026 } 1027 1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1029 SmallVector<SDValue, 4> Constants; 1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1031 OI != OE; ++OI) { 1032 SDNode *Val = getValue(*OI).getNode(); 1033 // If the operand is an empty aggregate, there are no values. 1034 if (!Val) continue; 1035 // Add each leaf value from the operand to the Constants list 1036 // to form a flattened list of all the values. 1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1038 Constants.push_back(SDValue(Val, i)); 1039 } 1040 1041 return DAG.getMergeValues(&Constants[0], Constants.size(), 1042 getCurDebugLoc()); 1043 } 1044 1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1047 "Unknown struct or array constant!"); 1048 1049 SmallVector<EVT, 4> ValueVTs; 1050 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1051 unsigned NumElts = ValueVTs.size(); 1052 if (NumElts == 0) 1053 return SDValue(); // empty struct 1054 SmallVector<SDValue, 4> Constants(NumElts); 1055 for (unsigned i = 0; i != NumElts; ++i) { 1056 EVT EltVT = ValueVTs[i]; 1057 if (isa<UndefValue>(C)) 1058 Constants[i] = DAG.getUNDEF(EltVT); 1059 else if (EltVT.isFloatingPoint()) 1060 Constants[i] = DAG.getConstantFP(0, EltVT); 1061 else 1062 Constants[i] = DAG.getConstant(0, EltVT); 1063 } 1064 1065 return DAG.getMergeValues(&Constants[0], NumElts, 1066 getCurDebugLoc()); 1067 } 1068 1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1070 return DAG.getBlockAddress(BA, VT); 1071 1072 VectorType *VecTy = cast<VectorType>(V->getType()); 1073 unsigned NumElements = VecTy->getNumElements(); 1074 1075 // Now that we know the number and type of the elements, get that number of 1076 // elements into the Ops array based on what kind of constant it is. 1077 SmallVector<SDValue, 16> Ops; 1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1079 for (unsigned i = 0; i != NumElements; ++i) 1080 Ops.push_back(getValue(CP->getOperand(i))); 1081 } else { 1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1083 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1084 1085 SDValue Op; 1086 if (EltVT.isFloatingPoint()) 1087 Op = DAG.getConstantFP(0, EltVT); 1088 else 1089 Op = DAG.getConstant(0, EltVT); 1090 Ops.assign(NumElements, Op); 1091 } 1092 1093 // Create a BUILD_VECTOR node. 1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1095 VT, &Ops[0], Ops.size()); 1096 } 1097 1098 // If this is a static alloca, generate it as the frameindex instead of 1099 // computation. 1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1101 DenseMap<const AllocaInst*, int>::iterator SI = 1102 FuncInfo.StaticAllocaMap.find(AI); 1103 if (SI != FuncInfo.StaticAllocaMap.end()) 1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1105 } 1106 1107 // If this is an instruction which fast-isel has deferred, select it now. 1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1111 SDValue Chain = DAG.getEntryNode(); 1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1113 } 1114 1115 llvm_unreachable("Can't get register for value!"); 1116 return SDValue(); 1117} 1118 1119void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1120 SDValue Chain = getControlRoot(); 1121 SmallVector<ISD::OutputArg, 8> Outs; 1122 SmallVector<SDValue, 8> OutVals; 1123 1124 if (!FuncInfo.CanLowerReturn) { 1125 unsigned DemoteReg = FuncInfo.DemoteRegister; 1126 const Function *F = I.getParent()->getParent(); 1127 1128 // Emit a store of the return value through the virtual register. 1129 // Leave Outs empty so that LowerReturn won't try to load return 1130 // registers the usual way. 1131 SmallVector<EVT, 1> PtrValueVTs; 1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1133 PtrValueVTs); 1134 1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1136 SDValue RetOp = getValue(I.getOperand(0)); 1137 1138 SmallVector<EVT, 4> ValueVTs; 1139 SmallVector<uint64_t, 4> Offsets; 1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1141 unsigned NumValues = ValueVTs.size(); 1142 1143 SmallVector<SDValue, 4> Chains(NumValues); 1144 for (unsigned i = 0; i != NumValues; ++i) { 1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1146 RetPtr.getValueType(), RetPtr, 1147 DAG.getIntPtrConstant(Offsets[i])); 1148 Chains[i] = 1149 DAG.getStore(Chain, getCurDebugLoc(), 1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1151 // FIXME: better loc info would be nice. 1152 Add, MachinePointerInfo(), false, false, 0); 1153 } 1154 1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1156 MVT::Other, &Chains[0], NumValues); 1157 } else if (I.getNumOperands() != 0) { 1158 SmallVector<EVT, 4> ValueVTs; 1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1160 unsigned NumValues = ValueVTs.size(); 1161 if (NumValues) { 1162 SDValue RetOp = getValue(I.getOperand(0)); 1163 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1164 EVT VT = ValueVTs[j]; 1165 1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1167 1168 const Function *F = I.getParent()->getParent(); 1169 if (F->paramHasAttr(0, Attribute::SExt)) 1170 ExtendKind = ISD::SIGN_EXTEND; 1171 else if (F->paramHasAttr(0, Attribute::ZExt)) 1172 ExtendKind = ISD::ZERO_EXTEND; 1173 1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1176 1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1179 SmallVector<SDValue, 4> Parts(NumParts); 1180 getCopyToParts(DAG, getCurDebugLoc(), 1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1182 &Parts[0], NumParts, PartVT, ExtendKind); 1183 1184 // 'inreg' on function refers to return value 1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1186 if (F->paramHasAttr(0, Attribute::InReg)) 1187 Flags.setInReg(); 1188 1189 // Propagate extension type if any 1190 if (ExtendKind == ISD::SIGN_EXTEND) 1191 Flags.setSExt(); 1192 else if (ExtendKind == ISD::ZERO_EXTEND) 1193 Flags.setZExt(); 1194 1195 for (unsigned i = 0; i < NumParts; ++i) { 1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1197 /*isfixed=*/true)); 1198 OutVals.push_back(Parts[i]); 1199 } 1200 } 1201 } 1202 } 1203 1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1205 CallingConv::ID CallConv = 1206 DAG.getMachineFunction().getFunction()->getCallingConv(); 1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1208 Outs, OutVals, getCurDebugLoc(), DAG); 1209 1210 // Verify that the target's LowerReturn behaved as expected. 1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1212 "LowerReturn didn't return a valid chain!"); 1213 1214 // Update the DAG with the new chain value resulting from return lowering. 1215 DAG.setRoot(Chain); 1216} 1217 1218/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1219/// created for it, emit nodes to copy the value into the virtual 1220/// registers. 1221void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1222 // Skip empty types 1223 if (V->getType()->isEmptyTy()) 1224 return; 1225 1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1227 if (VMI != FuncInfo.ValueMap.end()) { 1228 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1229 CopyValueToVirtualRegister(V, VMI->second); 1230 } 1231} 1232 1233/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1234/// the current basic block, add it to ValueMap now so that we'll get a 1235/// CopyTo/FromReg. 1236void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1237 // No need to export constants. 1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1239 1240 // Already exported? 1241 if (FuncInfo.isExportedInst(V)) return; 1242 1243 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1244 CopyValueToVirtualRegister(V, Reg); 1245} 1246 1247bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1248 const BasicBlock *FromBB) { 1249 // The operands of the setcc have to be in this block. We don't know 1250 // how to export them from some other block. 1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1252 // Can export from current BB. 1253 if (VI->getParent() == FromBB) 1254 return true; 1255 1256 // Is already exported, noop. 1257 return FuncInfo.isExportedInst(V); 1258 } 1259 1260 // If this is an argument, we can export it if the BB is the entry block or 1261 // if it is already exported. 1262 if (isa<Argument>(V)) { 1263 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1264 return true; 1265 1266 // Otherwise, can only export this if it is already exported. 1267 return FuncInfo.isExportedInst(V); 1268 } 1269 1270 // Otherwise, constants can always be exported. 1271 return true; 1272} 1273 1274/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1275uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src, 1276 MachineBasicBlock *Dst) { 1277 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1278 if (!BPI) 1279 return 0; 1280 const BasicBlock *SrcBB = Src->getBasicBlock(); 1281 const BasicBlock *DstBB = Dst->getBasicBlock(); 1282 return BPI->getEdgeWeight(SrcBB, DstBB); 1283} 1284 1285void SelectionDAGBuilder:: 1286addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1287 uint32_t Weight /* = 0 */) { 1288 if (!Weight) 1289 Weight = getEdgeWeight(Src, Dst); 1290 Src->addSuccessor(Dst, Weight); 1291} 1292 1293 1294static bool InBlock(const Value *V, const BasicBlock *BB) { 1295 if (const Instruction *I = dyn_cast<Instruction>(V)) 1296 return I->getParent() == BB; 1297 return true; 1298} 1299 1300/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1301/// This function emits a branch and is used at the leaves of an OR or an 1302/// AND operator tree. 1303/// 1304void 1305SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1306 MachineBasicBlock *TBB, 1307 MachineBasicBlock *FBB, 1308 MachineBasicBlock *CurBB, 1309 MachineBasicBlock *SwitchBB) { 1310 const BasicBlock *BB = CurBB->getBasicBlock(); 1311 1312 // If the leaf of the tree is a comparison, merge the condition into 1313 // the caseblock. 1314 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1315 // The operands of the cmp have to be in this block. We don't know 1316 // how to export them from some other block. If this is the first block 1317 // of the sequence, no exporting is needed. 1318 if (CurBB == SwitchBB || 1319 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1320 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1321 ISD::CondCode Condition; 1322 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1323 Condition = getICmpCondCode(IC->getPredicate()); 1324 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1325 Condition = getFCmpCondCode(FC->getPredicate()); 1326 } else { 1327 Condition = ISD::SETEQ; // silence warning. 1328 llvm_unreachable("Unknown compare instruction"); 1329 } 1330 1331 CaseBlock CB(Condition, BOp->getOperand(0), 1332 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1333 SwitchCases.push_back(CB); 1334 return; 1335 } 1336 } 1337 1338 // Create a CaseBlock record representing this branch. 1339 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1340 NULL, TBB, FBB, CurBB); 1341 SwitchCases.push_back(CB); 1342} 1343 1344/// FindMergedConditions - If Cond is an expression like 1345void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1346 MachineBasicBlock *TBB, 1347 MachineBasicBlock *FBB, 1348 MachineBasicBlock *CurBB, 1349 MachineBasicBlock *SwitchBB, 1350 unsigned Opc) { 1351 // If this node is not part of the or/and tree, emit it as a branch. 1352 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1353 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1354 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1355 BOp->getParent() != CurBB->getBasicBlock() || 1356 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1357 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1358 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1359 return; 1360 } 1361 1362 // Create TmpBB after CurBB. 1363 MachineFunction::iterator BBI = CurBB; 1364 MachineFunction &MF = DAG.getMachineFunction(); 1365 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1366 CurBB->getParent()->insert(++BBI, TmpBB); 1367 1368 if (Opc == Instruction::Or) { 1369 // Codegen X | Y as: 1370 // jmp_if_X TBB 1371 // jmp TmpBB 1372 // TmpBB: 1373 // jmp_if_Y TBB 1374 // jmp FBB 1375 // 1376 1377 // Emit the LHS condition. 1378 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1379 1380 // Emit the RHS condition into TmpBB. 1381 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1382 } else { 1383 assert(Opc == Instruction::And && "Unknown merge op!"); 1384 // Codegen X & Y as: 1385 // jmp_if_X TmpBB 1386 // jmp FBB 1387 // TmpBB: 1388 // jmp_if_Y TBB 1389 // jmp FBB 1390 // 1391 // This requires creation of TmpBB after CurBB. 1392 1393 // Emit the LHS condition. 1394 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1395 1396 // Emit the RHS condition into TmpBB. 1397 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1398 } 1399} 1400 1401/// If the set of cases should be emitted as a series of branches, return true. 1402/// If we should emit this as a bunch of and/or'd together conditions, return 1403/// false. 1404bool 1405SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1406 if (Cases.size() != 2) return true; 1407 1408 // If this is two comparisons of the same values or'd or and'd together, they 1409 // will get folded into a single comparison, so don't emit two blocks. 1410 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1411 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1412 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1413 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1414 return false; 1415 } 1416 1417 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1418 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1419 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1420 Cases[0].CC == Cases[1].CC && 1421 isa<Constant>(Cases[0].CmpRHS) && 1422 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1423 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1424 return false; 1425 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1426 return false; 1427 } 1428 1429 return true; 1430} 1431 1432void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1433 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1434 1435 // Update machine-CFG edges. 1436 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1437 1438 // Figure out which block is immediately after the current one. 1439 MachineBasicBlock *NextBlock = 0; 1440 MachineFunction::iterator BBI = BrMBB; 1441 if (++BBI != FuncInfo.MF->end()) 1442 NextBlock = BBI; 1443 1444 if (I.isUnconditional()) { 1445 // Update machine-CFG edges. 1446 BrMBB->addSuccessor(Succ0MBB); 1447 1448 // If this is not a fall-through branch, emit the branch. 1449 if (Succ0MBB != NextBlock) 1450 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1451 MVT::Other, getControlRoot(), 1452 DAG.getBasicBlock(Succ0MBB))); 1453 1454 return; 1455 } 1456 1457 // If this condition is one of the special cases we handle, do special stuff 1458 // now. 1459 const Value *CondVal = I.getCondition(); 1460 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1461 1462 // If this is a series of conditions that are or'd or and'd together, emit 1463 // this as a sequence of branches instead of setcc's with and/or operations. 1464 // As long as jumps are not expensive, this should improve performance. 1465 // For example, instead of something like: 1466 // cmp A, B 1467 // C = seteq 1468 // cmp D, E 1469 // F = setle 1470 // or C, F 1471 // jnz foo 1472 // Emit: 1473 // cmp A, B 1474 // je foo 1475 // cmp D, E 1476 // jle foo 1477 // 1478 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1479 if (!TLI.isJumpExpensive() && 1480 BOp->hasOneUse() && 1481 (BOp->getOpcode() == Instruction::And || 1482 BOp->getOpcode() == Instruction::Or)) { 1483 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1484 BOp->getOpcode()); 1485 // If the compares in later blocks need to use values not currently 1486 // exported from this block, export them now. This block should always 1487 // be the first entry. 1488 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1489 1490 // Allow some cases to be rejected. 1491 if (ShouldEmitAsBranches(SwitchCases)) { 1492 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1493 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1494 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1495 } 1496 1497 // Emit the branch for this block. 1498 visitSwitchCase(SwitchCases[0], BrMBB); 1499 SwitchCases.erase(SwitchCases.begin()); 1500 return; 1501 } 1502 1503 // Okay, we decided not to do this, remove any inserted MBB's and clear 1504 // SwitchCases. 1505 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1506 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1507 1508 SwitchCases.clear(); 1509 } 1510 } 1511 1512 // Create a CaseBlock record representing this branch. 1513 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1514 NULL, Succ0MBB, Succ1MBB, BrMBB); 1515 1516 // Use visitSwitchCase to actually insert the fast branch sequence for this 1517 // cond branch. 1518 visitSwitchCase(CB, BrMBB); 1519} 1520 1521/// visitSwitchCase - Emits the necessary code to represent a single node in 1522/// the binary search tree resulting from lowering a switch instruction. 1523void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1524 MachineBasicBlock *SwitchBB) { 1525 SDValue Cond; 1526 SDValue CondLHS = getValue(CB.CmpLHS); 1527 DebugLoc dl = getCurDebugLoc(); 1528 1529 // Build the setcc now. 1530 if (CB.CmpMHS == NULL) { 1531 // Fold "(X == true)" to X and "(X == false)" to !X to 1532 // handle common cases produced by branch lowering. 1533 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1534 CB.CC == ISD::SETEQ) 1535 Cond = CondLHS; 1536 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1537 CB.CC == ISD::SETEQ) { 1538 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1539 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1540 } else 1541 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1542 } else { 1543 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1544 1545 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1546 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1547 1548 SDValue CmpOp = getValue(CB.CmpMHS); 1549 EVT VT = CmpOp.getValueType(); 1550 1551 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1552 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1553 ISD::SETLE); 1554 } else { 1555 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1556 VT, CmpOp, DAG.getConstant(Low, VT)); 1557 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1558 DAG.getConstant(High-Low, VT), ISD::SETULE); 1559 } 1560 } 1561 1562 // Update successor info 1563 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1564 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1565 1566 // Set NextBlock to be the MBB immediately after the current one, if any. 1567 // This is used to avoid emitting unnecessary branches to the next block. 1568 MachineBasicBlock *NextBlock = 0; 1569 MachineFunction::iterator BBI = SwitchBB; 1570 if (++BBI != FuncInfo.MF->end()) 1571 NextBlock = BBI; 1572 1573 // If the lhs block is the next block, invert the condition so that we can 1574 // fall through to the lhs instead of the rhs block. 1575 if (CB.TrueBB == NextBlock) { 1576 std::swap(CB.TrueBB, CB.FalseBB); 1577 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1578 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1579 } 1580 1581 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1582 MVT::Other, getControlRoot(), Cond, 1583 DAG.getBasicBlock(CB.TrueBB)); 1584 1585 // Insert the false branch. Do this even if it's a fall through branch, 1586 // this makes it easier to do DAG optimizations which require inverting 1587 // the branch condition. 1588 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1589 DAG.getBasicBlock(CB.FalseBB)); 1590 1591 DAG.setRoot(BrCond); 1592} 1593 1594/// visitJumpTable - Emit JumpTable node in the current MBB 1595void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1596 // Emit the code for the jump table 1597 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1598 EVT PTy = TLI.getPointerTy(); 1599 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1600 JT.Reg, PTy); 1601 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1602 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1603 MVT::Other, Index.getValue(1), 1604 Table, Index); 1605 DAG.setRoot(BrJumpTable); 1606} 1607 1608/// visitJumpTableHeader - This function emits necessary code to produce index 1609/// in the JumpTable from switch case. 1610void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1611 JumpTableHeader &JTH, 1612 MachineBasicBlock *SwitchBB) { 1613 // Subtract the lowest switch case value from the value being switched on and 1614 // conditional branch to default mbb if the result is greater than the 1615 // difference between smallest and largest cases. 1616 SDValue SwitchOp = getValue(JTH.SValue); 1617 EVT VT = SwitchOp.getValueType(); 1618 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1619 DAG.getConstant(JTH.First, VT)); 1620 1621 // The SDNode we just created, which holds the value being switched on minus 1622 // the smallest case value, needs to be copied to a virtual register so it 1623 // can be used as an index into the jump table in a subsequent basic block. 1624 // This value may be smaller or larger than the target's pointer type, and 1625 // therefore require extension or truncating. 1626 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1627 1628 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1629 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1630 JumpTableReg, SwitchOp); 1631 JT.Reg = JumpTableReg; 1632 1633 // Emit the range check for the jump table, and branch to the default block 1634 // for the switch statement if the value being switched on exceeds the largest 1635 // case in the switch. 1636 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1637 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1638 DAG.getConstant(JTH.Last-JTH.First,VT), 1639 ISD::SETUGT); 1640 1641 // Set NextBlock to be the MBB immediately after the current one, if any. 1642 // This is used to avoid emitting unnecessary branches to the next block. 1643 MachineBasicBlock *NextBlock = 0; 1644 MachineFunction::iterator BBI = SwitchBB; 1645 1646 if (++BBI != FuncInfo.MF->end()) 1647 NextBlock = BBI; 1648 1649 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1650 MVT::Other, CopyTo, CMP, 1651 DAG.getBasicBlock(JT.Default)); 1652 1653 if (JT.MBB != NextBlock) 1654 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1655 DAG.getBasicBlock(JT.MBB)); 1656 1657 DAG.setRoot(BrCond); 1658} 1659 1660/// visitBitTestHeader - This function emits necessary code to produce value 1661/// suitable for "bit tests" 1662void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1663 MachineBasicBlock *SwitchBB) { 1664 // Subtract the minimum value 1665 SDValue SwitchOp = getValue(B.SValue); 1666 EVT VT = SwitchOp.getValueType(); 1667 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1668 DAG.getConstant(B.First, VT)); 1669 1670 // Check range 1671 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1672 TLI.getSetCCResultType(Sub.getValueType()), 1673 Sub, DAG.getConstant(B.Range, VT), 1674 ISD::SETUGT); 1675 1676 // Determine the type of the test operands. 1677 bool UsePtrType = false; 1678 if (!TLI.isTypeLegal(VT)) 1679 UsePtrType = true; 1680 else { 1681 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1682 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1683 // Switch table case range are encoded into series of masks. 1684 // Just use pointer type, it's guaranteed to fit. 1685 UsePtrType = true; 1686 break; 1687 } 1688 } 1689 if (UsePtrType) { 1690 VT = TLI.getPointerTy(); 1691 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1692 } 1693 1694 B.RegVT = VT; 1695 B.Reg = FuncInfo.CreateReg(VT); 1696 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1697 B.Reg, Sub); 1698 1699 // Set NextBlock to be the MBB immediately after the current one, if any. 1700 // This is used to avoid emitting unnecessary branches to the next block. 1701 MachineBasicBlock *NextBlock = 0; 1702 MachineFunction::iterator BBI = SwitchBB; 1703 if (++BBI != FuncInfo.MF->end()) 1704 NextBlock = BBI; 1705 1706 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1707 1708 addSuccessorWithWeight(SwitchBB, B.Default); 1709 addSuccessorWithWeight(SwitchBB, MBB); 1710 1711 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1712 MVT::Other, CopyTo, RangeCmp, 1713 DAG.getBasicBlock(B.Default)); 1714 1715 if (MBB != NextBlock) 1716 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1717 DAG.getBasicBlock(MBB)); 1718 1719 DAG.setRoot(BrRange); 1720} 1721 1722/// visitBitTestCase - this function produces one "bit test" 1723void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1724 MachineBasicBlock* NextMBB, 1725 unsigned Reg, 1726 BitTestCase &B, 1727 MachineBasicBlock *SwitchBB) { 1728 EVT VT = BB.RegVT; 1729 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1730 Reg, VT); 1731 SDValue Cmp; 1732 unsigned PopCount = CountPopulation_64(B.Mask); 1733 if (PopCount == 1) { 1734 // Testing for a single bit; just compare the shift count with what it 1735 // would need to be to shift a 1 bit in that position. 1736 Cmp = DAG.getSetCC(getCurDebugLoc(), 1737 TLI.getSetCCResultType(VT), 1738 ShiftOp, 1739 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1740 ISD::SETEQ); 1741 } else if (PopCount == BB.Range) { 1742 // There is only one zero bit in the range, test for it directly. 1743 Cmp = DAG.getSetCC(getCurDebugLoc(), 1744 TLI.getSetCCResultType(VT), 1745 ShiftOp, 1746 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1747 ISD::SETNE); 1748 } else { 1749 // Make desired shift 1750 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1751 DAG.getConstant(1, VT), ShiftOp); 1752 1753 // Emit bit tests and jumps 1754 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1755 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1756 Cmp = DAG.getSetCC(getCurDebugLoc(), 1757 TLI.getSetCCResultType(VT), 1758 AndOp, DAG.getConstant(0, VT), 1759 ISD::SETNE); 1760 } 1761 1762 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1763 addSuccessorWithWeight(SwitchBB, NextMBB); 1764 1765 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1766 MVT::Other, getControlRoot(), 1767 Cmp, DAG.getBasicBlock(B.TargetBB)); 1768 1769 // Set NextBlock to be the MBB immediately after the current one, if any. 1770 // This is used to avoid emitting unnecessary branches to the next block. 1771 MachineBasicBlock *NextBlock = 0; 1772 MachineFunction::iterator BBI = SwitchBB; 1773 if (++BBI != FuncInfo.MF->end()) 1774 NextBlock = BBI; 1775 1776 if (NextMBB != NextBlock) 1777 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1778 DAG.getBasicBlock(NextMBB)); 1779 1780 DAG.setRoot(BrAnd); 1781} 1782 1783void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1784 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1785 1786 // Retrieve successors. 1787 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1788 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1789 1790 const Value *Callee(I.getCalledValue()); 1791 if (isa<InlineAsm>(Callee)) 1792 visitInlineAsm(&I); 1793 else 1794 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1795 1796 // If the value of the invoke is used outside of its defining block, make it 1797 // available as a virtual register. 1798 CopyToExportRegsIfNeeded(&I); 1799 1800 // Update successor info 1801 InvokeMBB->addSuccessor(Return); 1802 InvokeMBB->addSuccessor(LandingPad); 1803 1804 // Drop into normal successor. 1805 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1806 MVT::Other, getControlRoot(), 1807 DAG.getBasicBlock(Return))); 1808} 1809 1810void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1811} 1812 1813void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1814 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1815} 1816 1817/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1818/// small case ranges). 1819bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1820 CaseRecVector& WorkList, 1821 const Value* SV, 1822 MachineBasicBlock *Default, 1823 MachineBasicBlock *SwitchBB) { 1824 Case& BackCase = *(CR.Range.second-1); 1825 1826 // Size is the number of Cases represented by this range. 1827 size_t Size = CR.Range.second - CR.Range.first; 1828 if (Size > 3) 1829 return false; 1830 1831 // Get the MachineFunction which holds the current MBB. This is used when 1832 // inserting any additional MBBs necessary to represent the switch. 1833 MachineFunction *CurMF = FuncInfo.MF; 1834 1835 // Figure out which block is immediately after the current one. 1836 MachineBasicBlock *NextBlock = 0; 1837 MachineFunction::iterator BBI = CR.CaseBB; 1838 1839 if (++BBI != FuncInfo.MF->end()) 1840 NextBlock = BBI; 1841 1842 // If any two of the cases has the same destination, and if one value 1843 // is the same as the other, but has one bit unset that the other has set, 1844 // use bit manipulation to do two compares at once. For example: 1845 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1846 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1847 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1848 if (Size == 2 && CR.CaseBB == SwitchBB) { 1849 Case &Small = *CR.Range.first; 1850 Case &Big = *(CR.Range.second-1); 1851 1852 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1853 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1854 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1855 1856 // Check that there is only one bit different. 1857 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1858 (SmallValue | BigValue) == BigValue) { 1859 // Isolate the common bit. 1860 APInt CommonBit = BigValue & ~SmallValue; 1861 assert((SmallValue | CommonBit) == BigValue && 1862 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1863 1864 SDValue CondLHS = getValue(SV); 1865 EVT VT = CondLHS.getValueType(); 1866 DebugLoc DL = getCurDebugLoc(); 1867 1868 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1869 DAG.getConstant(CommonBit, VT)); 1870 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1871 Or, DAG.getConstant(BigValue, VT), 1872 ISD::SETEQ); 1873 1874 // Update successor info. 1875 addSuccessorWithWeight(SwitchBB, Small.BB); 1876 addSuccessorWithWeight(SwitchBB, Default); 1877 1878 // Insert the true branch. 1879 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1880 getControlRoot(), Cond, 1881 DAG.getBasicBlock(Small.BB)); 1882 1883 // Insert the false branch. 1884 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1885 DAG.getBasicBlock(Default)); 1886 1887 DAG.setRoot(BrCond); 1888 return true; 1889 } 1890 } 1891 } 1892 1893 // Rearrange the case blocks so that the last one falls through if possible. 1894 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1895 // The last case block won't fall through into 'NextBlock' if we emit the 1896 // branches in this order. See if rearranging a case value would help. 1897 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1898 if (I->BB == NextBlock) { 1899 std::swap(*I, BackCase); 1900 break; 1901 } 1902 } 1903 } 1904 1905 // Create a CaseBlock record representing a conditional branch to 1906 // the Case's target mbb if the value being switched on SV is equal 1907 // to C. 1908 MachineBasicBlock *CurBlock = CR.CaseBB; 1909 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1910 MachineBasicBlock *FallThrough; 1911 if (I != E-1) { 1912 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1913 CurMF->insert(BBI, FallThrough); 1914 1915 // Put SV in a virtual register to make it available from the new blocks. 1916 ExportFromCurrentBlock(SV); 1917 } else { 1918 // If the last case doesn't match, go to the default block. 1919 FallThrough = Default; 1920 } 1921 1922 const Value *RHS, *LHS, *MHS; 1923 ISD::CondCode CC; 1924 if (I->High == I->Low) { 1925 // This is just small small case range :) containing exactly 1 case 1926 CC = ISD::SETEQ; 1927 LHS = SV; RHS = I->High; MHS = NULL; 1928 } else { 1929 CC = ISD::SETLE; 1930 LHS = I->Low; MHS = SV; RHS = I->High; 1931 } 1932 1933 uint32_t ExtraWeight = I->ExtraWeight; 1934 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 1935 /* me */ CurBlock, 1936 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 1937 1938 // If emitting the first comparison, just call visitSwitchCase to emit the 1939 // code into the current block. Otherwise, push the CaseBlock onto the 1940 // vector to be later processed by SDISel, and insert the node's MBB 1941 // before the next MBB. 1942 if (CurBlock == SwitchBB) 1943 visitSwitchCase(CB, SwitchBB); 1944 else 1945 SwitchCases.push_back(CB); 1946 1947 CurBlock = FallThrough; 1948 } 1949 1950 return true; 1951} 1952 1953static inline bool areJTsAllowed(const TargetLowering &TLI) { 1954 return !DisableJumpTables && 1955 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1956 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1957} 1958 1959static APInt ComputeRange(const APInt &First, const APInt &Last) { 1960 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1961 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 1962 return (LastExt - FirstExt + 1ULL); 1963} 1964 1965/// handleJTSwitchCase - Emit jumptable for current switch case range 1966bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1967 CaseRecVector& WorkList, 1968 const Value* SV, 1969 MachineBasicBlock* Default, 1970 MachineBasicBlock *SwitchBB) { 1971 Case& FrontCase = *CR.Range.first; 1972 Case& BackCase = *(CR.Range.second-1); 1973 1974 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1975 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1976 1977 APInt TSize(First.getBitWidth(), 0); 1978 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1979 I!=E; ++I) 1980 TSize += I->size(); 1981 1982 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1983 return false; 1984 1985 APInt Range = ComputeRange(First, Last); 1986 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1987 if (Density < 0.4) 1988 return false; 1989 1990 DEBUG(dbgs() << "Lowering jump table\n" 1991 << "First entry: " << First << ". Last entry: " << Last << '\n' 1992 << "Range: " << Range 1993 << ". Size: " << TSize << ". Density: " << Density << "\n\n"); 1994 1995 // Get the MachineFunction which holds the current MBB. This is used when 1996 // inserting any additional MBBs necessary to represent the switch. 1997 MachineFunction *CurMF = FuncInfo.MF; 1998 1999 // Figure out which block is immediately after the current one. 2000 MachineFunction::iterator BBI = CR.CaseBB; 2001 ++BBI; 2002 2003 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2004 2005 // Create a new basic block to hold the code for loading the address 2006 // of the jump table, and jumping to it. Update successor information; 2007 // we will either branch to the default case for the switch, or the jump 2008 // table. 2009 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2010 CurMF->insert(BBI, JumpTableBB); 2011 2012 addSuccessorWithWeight(CR.CaseBB, Default); 2013 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2014 2015 // Build a vector of destination BBs, corresponding to each target 2016 // of the jump table. If the value of the jump table slot corresponds to 2017 // a case statement, push the case's BB onto the vector, otherwise, push 2018 // the default BB. 2019 std::vector<MachineBasicBlock*> DestBBs; 2020 APInt TEI = First; 2021 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2022 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2023 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2024 2025 if (Low.sle(TEI) && TEI.sle(High)) { 2026 DestBBs.push_back(I->BB); 2027 if (TEI==High) 2028 ++I; 2029 } else { 2030 DestBBs.push_back(Default); 2031 } 2032 } 2033 2034 // Update successor info. Add one edge to each unique successor. 2035 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2036 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2037 E = DestBBs.end(); I != E; ++I) { 2038 if (!SuccsHandled[(*I)->getNumber()]) { 2039 SuccsHandled[(*I)->getNumber()] = true; 2040 addSuccessorWithWeight(JumpTableBB, *I); 2041 } 2042 } 2043 2044 // Create a jump table index for this jump table. 2045 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2046 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2047 ->createJumpTableIndex(DestBBs); 2048 2049 // Set the jump table information so that we can codegen it as a second 2050 // MachineBasicBlock 2051 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2052 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2053 if (CR.CaseBB == SwitchBB) 2054 visitJumpTableHeader(JT, JTH, SwitchBB); 2055 2056 JTCases.push_back(JumpTableBlock(JTH, JT)); 2057 2058 return true; 2059} 2060 2061/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2062/// 2 subtrees. 2063bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2064 CaseRecVector& WorkList, 2065 const Value* SV, 2066 MachineBasicBlock *Default, 2067 MachineBasicBlock *SwitchBB) { 2068 // Get the MachineFunction which holds the current MBB. This is used when 2069 // inserting any additional MBBs necessary to represent the switch. 2070 MachineFunction *CurMF = FuncInfo.MF; 2071 2072 // Figure out which block is immediately after the current one. 2073 MachineFunction::iterator BBI = CR.CaseBB; 2074 ++BBI; 2075 2076 Case& FrontCase = *CR.Range.first; 2077 Case& BackCase = *(CR.Range.second-1); 2078 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2079 2080 // Size is the number of Cases represented by this range. 2081 unsigned Size = CR.Range.second - CR.Range.first; 2082 2083 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2084 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2085 double FMetric = 0; 2086 CaseItr Pivot = CR.Range.first + Size/2; 2087 2088 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2089 // (heuristically) allow us to emit JumpTable's later. 2090 APInt TSize(First.getBitWidth(), 0); 2091 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2092 I!=E; ++I) 2093 TSize += I->size(); 2094 2095 APInt LSize = FrontCase.size(); 2096 APInt RSize = TSize-LSize; 2097 DEBUG(dbgs() << "Selecting best pivot: \n" 2098 << "First: " << First << ", Last: " << Last <<'\n' 2099 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2100 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2101 J!=E; ++I, ++J) { 2102 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2103 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2104 APInt Range = ComputeRange(LEnd, RBegin); 2105 assert((Range - 2ULL).isNonNegative() && 2106 "Invalid case distance"); 2107 // Use volatile double here to avoid excess precision issues on some hosts, 2108 // e.g. that use 80-bit X87 registers. 2109 volatile double LDensity = 2110 (double)LSize.roundToDouble() / 2111 (LEnd - First + 1ULL).roundToDouble(); 2112 volatile double RDensity = 2113 (double)RSize.roundToDouble() / 2114 (Last - RBegin + 1ULL).roundToDouble(); 2115 double Metric = Range.logBase2()*(LDensity+RDensity); 2116 // Should always split in some non-trivial place 2117 DEBUG(dbgs() <<"=>Step\n" 2118 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2119 << "LDensity: " << LDensity 2120 << ", RDensity: " << RDensity << '\n' 2121 << "Metric: " << Metric << '\n'); 2122 if (FMetric < Metric) { 2123 Pivot = J; 2124 FMetric = Metric; 2125 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2126 } 2127 2128 LSize += J->size(); 2129 RSize -= J->size(); 2130 } 2131 if (areJTsAllowed(TLI)) { 2132 // If our case is dense we *really* should handle it earlier! 2133 assert((FMetric > 0) && "Should handle dense range earlier!"); 2134 } else { 2135 Pivot = CR.Range.first + Size/2; 2136 } 2137 2138 CaseRange LHSR(CR.Range.first, Pivot); 2139 CaseRange RHSR(Pivot, CR.Range.second); 2140 Constant *C = Pivot->Low; 2141 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2142 2143 // We know that we branch to the LHS if the Value being switched on is 2144 // less than the Pivot value, C. We use this to optimize our binary 2145 // tree a bit, by recognizing that if SV is greater than or equal to the 2146 // LHS's Case Value, and that Case Value is exactly one less than the 2147 // Pivot's Value, then we can branch directly to the LHS's Target, 2148 // rather than creating a leaf node for it. 2149 if ((LHSR.second - LHSR.first) == 1 && 2150 LHSR.first->High == CR.GE && 2151 cast<ConstantInt>(C)->getValue() == 2152 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2153 TrueBB = LHSR.first->BB; 2154 } else { 2155 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2156 CurMF->insert(BBI, TrueBB); 2157 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2158 2159 // Put SV in a virtual register to make it available from the new blocks. 2160 ExportFromCurrentBlock(SV); 2161 } 2162 2163 // Similar to the optimization above, if the Value being switched on is 2164 // known to be less than the Constant CR.LT, and the current Case Value 2165 // is CR.LT - 1, then we can branch directly to the target block for 2166 // the current Case Value, rather than emitting a RHS leaf node for it. 2167 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2168 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2169 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2170 FalseBB = RHSR.first->BB; 2171 } else { 2172 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2173 CurMF->insert(BBI, FalseBB); 2174 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2175 2176 // Put SV in a virtual register to make it available from the new blocks. 2177 ExportFromCurrentBlock(SV); 2178 } 2179 2180 // Create a CaseBlock record representing a conditional branch to 2181 // the LHS node if the value being switched on SV is less than C. 2182 // Otherwise, branch to LHS. 2183 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2184 2185 if (CR.CaseBB == SwitchBB) 2186 visitSwitchCase(CB, SwitchBB); 2187 else 2188 SwitchCases.push_back(CB); 2189 2190 return true; 2191} 2192 2193/// handleBitTestsSwitchCase - if current case range has few destination and 2194/// range span less, than machine word bitwidth, encode case range into series 2195/// of masks and emit bit tests with these masks. 2196bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2197 CaseRecVector& WorkList, 2198 const Value* SV, 2199 MachineBasicBlock* Default, 2200 MachineBasicBlock *SwitchBB){ 2201 EVT PTy = TLI.getPointerTy(); 2202 unsigned IntPtrBits = PTy.getSizeInBits(); 2203 2204 Case& FrontCase = *CR.Range.first; 2205 Case& BackCase = *(CR.Range.second-1); 2206 2207 // Get the MachineFunction which holds the current MBB. This is used when 2208 // inserting any additional MBBs necessary to represent the switch. 2209 MachineFunction *CurMF = FuncInfo.MF; 2210 2211 // If target does not have legal shift left, do not emit bit tests at all. 2212 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2213 return false; 2214 2215 size_t numCmps = 0; 2216 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2217 I!=E; ++I) { 2218 // Single case counts one, case range - two. 2219 numCmps += (I->Low == I->High ? 1 : 2); 2220 } 2221 2222 // Count unique destinations 2223 SmallSet<MachineBasicBlock*, 4> Dests; 2224 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2225 Dests.insert(I->BB); 2226 if (Dests.size() > 3) 2227 // Don't bother the code below, if there are too much unique destinations 2228 return false; 2229 } 2230 DEBUG(dbgs() << "Total number of unique destinations: " 2231 << Dests.size() << '\n' 2232 << "Total number of comparisons: " << numCmps << '\n'); 2233 2234 // Compute span of values. 2235 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2236 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2237 APInt cmpRange = maxValue - minValue; 2238 2239 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2240 << "Low bound: " << minValue << '\n' 2241 << "High bound: " << maxValue << '\n'); 2242 2243 if (cmpRange.uge(IntPtrBits) || 2244 (!(Dests.size() == 1 && numCmps >= 3) && 2245 !(Dests.size() == 2 && numCmps >= 5) && 2246 !(Dests.size() >= 3 && numCmps >= 6))) 2247 return false; 2248 2249 DEBUG(dbgs() << "Emitting bit tests\n"); 2250 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2251 2252 // Optimize the case where all the case values fit in a 2253 // word without having to subtract minValue. In this case, 2254 // we can optimize away the subtraction. 2255 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2256 cmpRange = maxValue; 2257 } else { 2258 lowBound = minValue; 2259 } 2260 2261 CaseBitsVector CasesBits; 2262 unsigned i, count = 0; 2263 2264 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2265 MachineBasicBlock* Dest = I->BB; 2266 for (i = 0; i < count; ++i) 2267 if (Dest == CasesBits[i].BB) 2268 break; 2269 2270 if (i == count) { 2271 assert((count < 3) && "Too much destinations to test!"); 2272 CasesBits.push_back(CaseBits(0, Dest, 0)); 2273 count++; 2274 } 2275 2276 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2277 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2278 2279 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2280 uint64_t hi = (highValue - lowBound).getZExtValue(); 2281 2282 for (uint64_t j = lo; j <= hi; j++) { 2283 CasesBits[i].Mask |= 1ULL << j; 2284 CasesBits[i].Bits++; 2285 } 2286 2287 } 2288 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2289 2290 BitTestInfo BTC; 2291 2292 // Figure out which block is immediately after the current one. 2293 MachineFunction::iterator BBI = CR.CaseBB; 2294 ++BBI; 2295 2296 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2297 2298 DEBUG(dbgs() << "Cases:\n"); 2299 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2300 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2301 << ", Bits: " << CasesBits[i].Bits 2302 << ", BB: " << CasesBits[i].BB << '\n'); 2303 2304 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2305 CurMF->insert(BBI, CaseBB); 2306 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2307 CaseBB, 2308 CasesBits[i].BB)); 2309 2310 // Put SV in a virtual register to make it available from the new blocks. 2311 ExportFromCurrentBlock(SV); 2312 } 2313 2314 BitTestBlock BTB(lowBound, cmpRange, SV, 2315 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2316 CR.CaseBB, Default, BTC); 2317 2318 if (CR.CaseBB == SwitchBB) 2319 visitBitTestHeader(BTB, SwitchBB); 2320 2321 BitTestCases.push_back(BTB); 2322 2323 return true; 2324} 2325 2326/// Clusterify - Transform simple list of Cases into list of CaseRange's 2327size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2328 const SwitchInst& SI) { 2329 size_t numCmps = 0; 2330 2331 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2332 // Start with "simple" cases 2333 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2334 BasicBlock *SuccBB = SI.getSuccessor(i); 2335 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2336 2337 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0; 2338 2339 Cases.push_back(Case(SI.getSuccessorValue(i), 2340 SI.getSuccessorValue(i), 2341 SMBB, ExtraWeight)); 2342 } 2343 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2344 2345 // Merge case into clusters 2346 if (Cases.size() >= 2) 2347 // Must recompute end() each iteration because it may be 2348 // invalidated by erase if we hold on to it 2349 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2350 J != Cases.end(); ) { 2351 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2352 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2353 MachineBasicBlock* nextBB = J->BB; 2354 MachineBasicBlock* currentBB = I->BB; 2355 2356 // If the two neighboring cases go to the same destination, merge them 2357 // into a single case. 2358 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2359 I->High = J->High; 2360 J = Cases.erase(J); 2361 2362 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) { 2363 uint32_t CurWeight = currentBB->getBasicBlock() ? 2364 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16; 2365 uint32_t NextWeight = nextBB->getBasicBlock() ? 2366 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16; 2367 2368 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(), 2369 CurWeight + NextWeight); 2370 } 2371 } else { 2372 I = J++; 2373 } 2374 } 2375 2376 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2377 if (I->Low != I->High) 2378 // A range counts double, since it requires two compares. 2379 ++numCmps; 2380 } 2381 2382 return numCmps; 2383} 2384 2385void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2386 MachineBasicBlock *Last) { 2387 // Update JTCases. 2388 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2389 if (JTCases[i].first.HeaderBB == First) 2390 JTCases[i].first.HeaderBB = Last; 2391 2392 // Update BitTestCases. 2393 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2394 if (BitTestCases[i].Parent == First) 2395 BitTestCases[i].Parent = Last; 2396} 2397 2398void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2399 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2400 2401 // Figure out which block is immediately after the current one. 2402 MachineBasicBlock *NextBlock = 0; 2403 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2404 2405 // If there is only the default destination, branch to it if it is not the 2406 // next basic block. Otherwise, just fall through. 2407 if (SI.getNumOperands() == 2) { 2408 // Update machine-CFG edges. 2409 2410 // If this is not a fall-through branch, emit the branch. 2411 SwitchMBB->addSuccessor(Default); 2412 if (Default != NextBlock) 2413 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2414 MVT::Other, getControlRoot(), 2415 DAG.getBasicBlock(Default))); 2416 2417 return; 2418 } 2419 2420 // If there are any non-default case statements, create a vector of Cases 2421 // representing each one, and sort the vector so that we can efficiently 2422 // create a binary search tree from them. 2423 CaseVector Cases; 2424 size_t numCmps = Clusterify(Cases, SI); 2425 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2426 << ". Total compares: " << numCmps << '\n'); 2427 numCmps = 0; 2428 2429 // Get the Value to be switched on and default basic blocks, which will be 2430 // inserted into CaseBlock records, representing basic blocks in the binary 2431 // search tree. 2432 const Value *SV = SI.getOperand(0); 2433 2434 // Push the initial CaseRec onto the worklist 2435 CaseRecVector WorkList; 2436 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2437 CaseRange(Cases.begin(),Cases.end()))); 2438 2439 while (!WorkList.empty()) { 2440 // Grab a record representing a case range to process off the worklist 2441 CaseRec CR = WorkList.back(); 2442 WorkList.pop_back(); 2443 2444 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2445 continue; 2446 2447 // If the range has few cases (two or less) emit a series of specific 2448 // tests. 2449 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2450 continue; 2451 2452 // If the switch has more than 5 blocks, and at least 40% dense, and the 2453 // target supports indirect branches, then emit a jump table rather than 2454 // lowering the switch to a binary tree of conditional branches. 2455 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2456 continue; 2457 2458 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2459 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2460 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2461 } 2462} 2463 2464void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2465 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2466 2467 // Update machine-CFG edges with unique successors. 2468 SmallVector<BasicBlock*, 32> succs; 2469 succs.reserve(I.getNumSuccessors()); 2470 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2471 succs.push_back(I.getSuccessor(i)); 2472 array_pod_sort(succs.begin(), succs.end()); 2473 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2474 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2475 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2476 addSuccessorWithWeight(IndirectBrMBB, Succ); 2477 } 2478 2479 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2480 MVT::Other, getControlRoot(), 2481 getValue(I.getAddress()))); 2482} 2483 2484void SelectionDAGBuilder::visitFSub(const User &I) { 2485 // -0.0 - X --> fneg 2486 Type *Ty = I.getType(); 2487 if (isa<Constant>(I.getOperand(0)) && 2488 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2489 SDValue Op2 = getValue(I.getOperand(1)); 2490 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2491 Op2.getValueType(), Op2)); 2492 return; 2493 } 2494 2495 visitBinary(I, ISD::FSUB); 2496} 2497 2498void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2499 SDValue Op1 = getValue(I.getOperand(0)); 2500 SDValue Op2 = getValue(I.getOperand(1)); 2501 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2502 Op1.getValueType(), Op1, Op2)); 2503} 2504 2505void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2506 SDValue Op1 = getValue(I.getOperand(0)); 2507 SDValue Op2 = getValue(I.getOperand(1)); 2508 2509 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2510 2511 // Coerce the shift amount to the right type if we can. 2512 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2513 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2514 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2515 DebugLoc DL = getCurDebugLoc(); 2516 2517 // If the operand is smaller than the shift count type, promote it. 2518 if (ShiftSize > Op2Size) 2519 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2520 2521 // If the operand is larger than the shift count type but the shift 2522 // count type has enough bits to represent any shift value, truncate 2523 // it now. This is a common case and it exposes the truncate to 2524 // optimization early. 2525 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2526 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2527 // Otherwise we'll need to temporarily settle for some other convenient 2528 // type. Type legalization will make adjustments once the shiftee is split. 2529 else 2530 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2531 } 2532 2533 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2534 Op1.getValueType(), Op1, Op2)); 2535} 2536 2537void SelectionDAGBuilder::visitSDiv(const User &I) { 2538 SDValue Op1 = getValue(I.getOperand(0)); 2539 SDValue Op2 = getValue(I.getOperand(1)); 2540 2541 // Turn exact SDivs into multiplications. 2542 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2543 // exact bit. 2544 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2545 !isa<ConstantSDNode>(Op1) && 2546 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2547 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2548 else 2549 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2550 Op1, Op2)); 2551} 2552 2553void SelectionDAGBuilder::visitICmp(const User &I) { 2554 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2555 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2556 predicate = IC->getPredicate(); 2557 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2558 predicate = ICmpInst::Predicate(IC->getPredicate()); 2559 SDValue Op1 = getValue(I.getOperand(0)); 2560 SDValue Op2 = getValue(I.getOperand(1)); 2561 ISD::CondCode Opcode = getICmpCondCode(predicate); 2562 2563 EVT DestVT = TLI.getValueType(I.getType()); 2564 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2565} 2566 2567void SelectionDAGBuilder::visitFCmp(const User &I) { 2568 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2569 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2570 predicate = FC->getPredicate(); 2571 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2572 predicate = FCmpInst::Predicate(FC->getPredicate()); 2573 SDValue Op1 = getValue(I.getOperand(0)); 2574 SDValue Op2 = getValue(I.getOperand(1)); 2575 ISD::CondCode Condition = getFCmpCondCode(predicate); 2576 EVT DestVT = TLI.getValueType(I.getType()); 2577 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2578} 2579 2580void SelectionDAGBuilder::visitSelect(const User &I) { 2581 SmallVector<EVT, 4> ValueVTs; 2582 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2583 unsigned NumValues = ValueVTs.size(); 2584 if (NumValues == 0) return; 2585 2586 SmallVector<SDValue, 4> Values(NumValues); 2587 SDValue Cond = getValue(I.getOperand(0)); 2588 SDValue TrueVal = getValue(I.getOperand(1)); 2589 SDValue FalseVal = getValue(I.getOperand(2)); 2590 2591 for (unsigned i = 0; i != NumValues; ++i) 2592 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2593 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2594 Cond, 2595 SDValue(TrueVal.getNode(), 2596 TrueVal.getResNo() + i), 2597 SDValue(FalseVal.getNode(), 2598 FalseVal.getResNo() + i)); 2599 2600 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2601 DAG.getVTList(&ValueVTs[0], NumValues), 2602 &Values[0], NumValues)); 2603} 2604 2605void SelectionDAGBuilder::visitTrunc(const User &I) { 2606 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2607 SDValue N = getValue(I.getOperand(0)); 2608 EVT DestVT = TLI.getValueType(I.getType()); 2609 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2610} 2611 2612void SelectionDAGBuilder::visitZExt(const User &I) { 2613 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2614 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2615 SDValue N = getValue(I.getOperand(0)); 2616 EVT DestVT = TLI.getValueType(I.getType()); 2617 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2618} 2619 2620void SelectionDAGBuilder::visitSExt(const User &I) { 2621 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2622 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2623 SDValue N = getValue(I.getOperand(0)); 2624 EVT DestVT = TLI.getValueType(I.getType()); 2625 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2626} 2627 2628void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2629 // FPTrunc is never a no-op cast, no need to check 2630 SDValue N = getValue(I.getOperand(0)); 2631 EVT DestVT = TLI.getValueType(I.getType()); 2632 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2633 DestVT, N, DAG.getIntPtrConstant(0))); 2634} 2635 2636void SelectionDAGBuilder::visitFPExt(const User &I){ 2637 // FPTrunc is never a no-op cast, no need to check 2638 SDValue N = getValue(I.getOperand(0)); 2639 EVT DestVT = TLI.getValueType(I.getType()); 2640 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2641} 2642 2643void SelectionDAGBuilder::visitFPToUI(const User &I) { 2644 // FPToUI is never a no-op cast, no need to check 2645 SDValue N = getValue(I.getOperand(0)); 2646 EVT DestVT = TLI.getValueType(I.getType()); 2647 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2648} 2649 2650void SelectionDAGBuilder::visitFPToSI(const User &I) { 2651 // FPToSI is never a no-op cast, no need to check 2652 SDValue N = getValue(I.getOperand(0)); 2653 EVT DestVT = TLI.getValueType(I.getType()); 2654 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2655} 2656 2657void SelectionDAGBuilder::visitUIToFP(const User &I) { 2658 // UIToFP is never a no-op cast, no need to check 2659 SDValue N = getValue(I.getOperand(0)); 2660 EVT DestVT = TLI.getValueType(I.getType()); 2661 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2662} 2663 2664void SelectionDAGBuilder::visitSIToFP(const User &I){ 2665 // SIToFP is never a no-op cast, no need to check 2666 SDValue N = getValue(I.getOperand(0)); 2667 EVT DestVT = TLI.getValueType(I.getType()); 2668 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2669} 2670 2671void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2672 // What to do depends on the size of the integer and the size of the pointer. 2673 // We can either truncate, zero extend, or no-op, accordingly. 2674 SDValue N = getValue(I.getOperand(0)); 2675 EVT DestVT = TLI.getValueType(I.getType()); 2676 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2677} 2678 2679void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2680 // What to do depends on the size of the integer and the size of the pointer. 2681 // We can either truncate, zero extend, or no-op, accordingly. 2682 SDValue N = getValue(I.getOperand(0)); 2683 EVT DestVT = TLI.getValueType(I.getType()); 2684 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2685} 2686 2687void SelectionDAGBuilder::visitBitCast(const User &I) { 2688 SDValue N = getValue(I.getOperand(0)); 2689 EVT DestVT = TLI.getValueType(I.getType()); 2690 2691 // BitCast assures us that source and destination are the same size so this is 2692 // either a BITCAST or a no-op. 2693 if (DestVT != N.getValueType()) 2694 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2695 DestVT, N)); // convert types. 2696 else 2697 setValue(&I, N); // noop cast. 2698} 2699 2700void SelectionDAGBuilder::visitInsertElement(const User &I) { 2701 SDValue InVec = getValue(I.getOperand(0)); 2702 SDValue InVal = getValue(I.getOperand(1)); 2703 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2704 TLI.getPointerTy(), 2705 getValue(I.getOperand(2))); 2706 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2707 TLI.getValueType(I.getType()), 2708 InVec, InVal, InIdx)); 2709} 2710 2711void SelectionDAGBuilder::visitExtractElement(const User &I) { 2712 SDValue InVec = getValue(I.getOperand(0)); 2713 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2714 TLI.getPointerTy(), 2715 getValue(I.getOperand(1))); 2716 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2717 TLI.getValueType(I.getType()), InVec, InIdx)); 2718} 2719 2720// Utility for visitShuffleVector - Returns true if the mask is mask starting 2721// from SIndx and increasing to the element length (undefs are allowed). 2722static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2723 unsigned MaskNumElts = Mask.size(); 2724 for (unsigned i = 0; i != MaskNumElts; ++i) 2725 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2726 return false; 2727 return true; 2728} 2729 2730void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2731 SmallVector<int, 8> Mask; 2732 SDValue Src1 = getValue(I.getOperand(0)); 2733 SDValue Src2 = getValue(I.getOperand(1)); 2734 2735 // Convert the ConstantVector mask operand into an array of ints, with -1 2736 // representing undef values. 2737 SmallVector<Constant*, 8> MaskElts; 2738 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2739 unsigned MaskNumElts = MaskElts.size(); 2740 for (unsigned i = 0; i != MaskNumElts; ++i) { 2741 if (isa<UndefValue>(MaskElts[i])) 2742 Mask.push_back(-1); 2743 else 2744 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2745 } 2746 2747 EVT VT = TLI.getValueType(I.getType()); 2748 EVT SrcVT = Src1.getValueType(); 2749 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2750 2751 if (SrcNumElts == MaskNumElts) { 2752 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2753 &Mask[0])); 2754 return; 2755 } 2756 2757 // Normalize the shuffle vector since mask and vector length don't match. 2758 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2759 // Mask is longer than the source vectors and is a multiple of the source 2760 // vectors. We can use concatenate vector to make the mask and vectors 2761 // lengths match. 2762 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2763 // The shuffle is concatenating two vectors together. 2764 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2765 VT, Src1, Src2)); 2766 return; 2767 } 2768 2769 // Pad both vectors with undefs to make them the same length as the mask. 2770 unsigned NumConcat = MaskNumElts / SrcNumElts; 2771 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2772 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2773 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2774 2775 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2776 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2777 MOps1[0] = Src1; 2778 MOps2[0] = Src2; 2779 2780 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2781 getCurDebugLoc(), VT, 2782 &MOps1[0], NumConcat); 2783 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2784 getCurDebugLoc(), VT, 2785 &MOps2[0], NumConcat); 2786 2787 // Readjust mask for new input vector length. 2788 SmallVector<int, 8> MappedOps; 2789 for (unsigned i = 0; i != MaskNumElts; ++i) { 2790 int Idx = Mask[i]; 2791 if (Idx < (int)SrcNumElts) 2792 MappedOps.push_back(Idx); 2793 else 2794 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2795 } 2796 2797 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2798 &MappedOps[0])); 2799 return; 2800 } 2801 2802 if (SrcNumElts > MaskNumElts) { 2803 // Analyze the access pattern of the vector to see if we can extract 2804 // two subvectors and do the shuffle. The analysis is done by calculating 2805 // the range of elements the mask access on both vectors. 2806 int MinRange[2] = { static_cast<int>(SrcNumElts+1), 2807 static_cast<int>(SrcNumElts+1)}; 2808 int MaxRange[2] = {-1, -1}; 2809 2810 for (unsigned i = 0; i != MaskNumElts; ++i) { 2811 int Idx = Mask[i]; 2812 int Input = 0; 2813 if (Idx < 0) 2814 continue; 2815 2816 if (Idx >= (int)SrcNumElts) { 2817 Input = 1; 2818 Idx -= SrcNumElts; 2819 } 2820 if (Idx > MaxRange[Input]) 2821 MaxRange[Input] = Idx; 2822 if (Idx < MinRange[Input]) 2823 MinRange[Input] = Idx; 2824 } 2825 2826 // Check if the access is smaller than the vector size and can we find 2827 // a reasonable extract index. 2828 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2829 // Extract. 2830 int StartIdx[2]; // StartIdx to extract from 2831 for (int Input=0; Input < 2; ++Input) { 2832 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2833 RangeUse[Input] = 0; // Unused 2834 StartIdx[Input] = 0; 2835 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2836 // Fits within range but we should see if we can find a good 2837 // start index that is a multiple of the mask length. 2838 if (MaxRange[Input] < (int)MaskNumElts) { 2839 RangeUse[Input] = 1; // Extract from beginning of the vector 2840 StartIdx[Input] = 0; 2841 } else { 2842 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2843 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2844 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2845 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2846 } 2847 } 2848 } 2849 2850 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2851 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2852 return; 2853 } 2854 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2855 // Extract appropriate subvector and generate a vector shuffle 2856 for (int Input=0; Input < 2; ++Input) { 2857 SDValue &Src = Input == 0 ? Src1 : Src2; 2858 if (RangeUse[Input] == 0) 2859 Src = DAG.getUNDEF(VT); 2860 else 2861 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2862 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2863 } 2864 2865 // Calculate new mask. 2866 SmallVector<int, 8> MappedOps; 2867 for (unsigned i = 0; i != MaskNumElts; ++i) { 2868 int Idx = Mask[i]; 2869 if (Idx < 0) 2870 MappedOps.push_back(Idx); 2871 else if (Idx < (int)SrcNumElts) 2872 MappedOps.push_back(Idx - StartIdx[0]); 2873 else 2874 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2875 } 2876 2877 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2878 &MappedOps[0])); 2879 return; 2880 } 2881 } 2882 2883 // We can't use either concat vectors or extract subvectors so fall back to 2884 // replacing the shuffle with extract and build vector. 2885 // to insert and build vector. 2886 EVT EltVT = VT.getVectorElementType(); 2887 EVT PtrVT = TLI.getPointerTy(); 2888 SmallVector<SDValue,8> Ops; 2889 for (unsigned i = 0; i != MaskNumElts; ++i) { 2890 if (Mask[i] < 0) { 2891 Ops.push_back(DAG.getUNDEF(EltVT)); 2892 } else { 2893 int Idx = Mask[i]; 2894 SDValue Res; 2895 2896 if (Idx < (int)SrcNumElts) 2897 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2898 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2899 else 2900 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2901 EltVT, Src2, 2902 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2903 2904 Ops.push_back(Res); 2905 } 2906 } 2907 2908 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2909 VT, &Ops[0], Ops.size())); 2910} 2911 2912void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2913 const Value *Op0 = I.getOperand(0); 2914 const Value *Op1 = I.getOperand(1); 2915 Type *AggTy = I.getType(); 2916 Type *ValTy = Op1->getType(); 2917 bool IntoUndef = isa<UndefValue>(Op0); 2918 bool FromUndef = isa<UndefValue>(Op1); 2919 2920 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2921 2922 SmallVector<EVT, 4> AggValueVTs; 2923 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2924 SmallVector<EVT, 4> ValValueVTs; 2925 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2926 2927 unsigned NumAggValues = AggValueVTs.size(); 2928 unsigned NumValValues = ValValueVTs.size(); 2929 SmallVector<SDValue, 4> Values(NumAggValues); 2930 2931 SDValue Agg = getValue(Op0); 2932 unsigned i = 0; 2933 // Copy the beginning value(s) from the original aggregate. 2934 for (; i != LinearIndex; ++i) 2935 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2936 SDValue(Agg.getNode(), Agg.getResNo() + i); 2937 // Copy values from the inserted value(s). 2938 if (NumValValues) { 2939 SDValue Val = getValue(Op1); 2940 for (; i != LinearIndex + NumValValues; ++i) 2941 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2942 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2943 } 2944 // Copy remaining value(s) from the original aggregate. 2945 for (; i != NumAggValues; ++i) 2946 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2947 SDValue(Agg.getNode(), Agg.getResNo() + i); 2948 2949 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2950 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2951 &Values[0], NumAggValues)); 2952} 2953 2954void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2955 const Value *Op0 = I.getOperand(0); 2956 Type *AggTy = Op0->getType(); 2957 Type *ValTy = I.getType(); 2958 bool OutOfUndef = isa<UndefValue>(Op0); 2959 2960 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2961 2962 SmallVector<EVT, 4> ValValueVTs; 2963 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2964 2965 unsigned NumValValues = ValValueVTs.size(); 2966 2967 // Ignore a extractvalue that produces an empty object 2968 if (!NumValValues) { 2969 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 2970 return; 2971 } 2972 2973 SmallVector<SDValue, 4> Values(NumValValues); 2974 2975 SDValue Agg = getValue(Op0); 2976 // Copy out the selected value(s). 2977 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2978 Values[i - LinearIndex] = 2979 OutOfUndef ? 2980 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2981 SDValue(Agg.getNode(), Agg.getResNo() + i); 2982 2983 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2984 DAG.getVTList(&ValValueVTs[0], NumValValues), 2985 &Values[0], NumValValues)); 2986} 2987 2988void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2989 SDValue N = getValue(I.getOperand(0)); 2990 Type *Ty = I.getOperand(0)->getType(); 2991 2992 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2993 OI != E; ++OI) { 2994 const Value *Idx = *OI; 2995 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 2996 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2997 if (Field) { 2998 // N = N + Offset 2999 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3000 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3001 DAG.getIntPtrConstant(Offset)); 3002 } 3003 3004 Ty = StTy->getElementType(Field); 3005 } else { 3006 Ty = cast<SequentialType>(Ty)->getElementType(); 3007 3008 // If this is a constant subscript, handle it quickly. 3009 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3010 if (CI->isZero()) continue; 3011 uint64_t Offs = 3012 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3013 SDValue OffsVal; 3014 EVT PTy = TLI.getPointerTy(); 3015 unsigned PtrBits = PTy.getSizeInBits(); 3016 if (PtrBits < 64) 3017 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3018 TLI.getPointerTy(), 3019 DAG.getConstant(Offs, MVT::i64)); 3020 else 3021 OffsVal = DAG.getIntPtrConstant(Offs); 3022 3023 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3024 OffsVal); 3025 continue; 3026 } 3027 3028 // N = N + Idx * ElementSize; 3029 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3030 TD->getTypeAllocSize(Ty)); 3031 SDValue IdxN = getValue(Idx); 3032 3033 // If the index is smaller or larger than intptr_t, truncate or extend 3034 // it. 3035 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3036 3037 // If this is a multiply by a power of two, turn it into a shl 3038 // immediately. This is a very common case. 3039 if (ElementSize != 1) { 3040 if (ElementSize.isPowerOf2()) { 3041 unsigned Amt = ElementSize.logBase2(); 3042 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3043 N.getValueType(), IdxN, 3044 DAG.getConstant(Amt, TLI.getPointerTy())); 3045 } else { 3046 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3047 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3048 N.getValueType(), IdxN, Scale); 3049 } 3050 } 3051 3052 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3053 N.getValueType(), N, IdxN); 3054 } 3055 } 3056 3057 setValue(&I, N); 3058} 3059 3060void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3061 // If this is a fixed sized alloca in the entry block of the function, 3062 // allocate it statically on the stack. 3063 if (FuncInfo.StaticAllocaMap.count(&I)) 3064 return; // getValue will auto-populate this. 3065 3066 Type *Ty = I.getAllocatedType(); 3067 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3068 unsigned Align = 3069 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3070 I.getAlignment()); 3071 3072 SDValue AllocSize = getValue(I.getArraySize()); 3073 3074 EVT IntPtr = TLI.getPointerTy(); 3075 if (AllocSize.getValueType() != IntPtr) 3076 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3077 3078 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3079 AllocSize, 3080 DAG.getConstant(TySize, IntPtr)); 3081 3082 // Handle alignment. If the requested alignment is less than or equal to 3083 // the stack alignment, ignore it. If the size is greater than or equal to 3084 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3085 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3086 if (Align <= StackAlign) 3087 Align = 0; 3088 3089 // Round the size of the allocation up to the stack alignment size 3090 // by add SA-1 to the size. 3091 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3092 AllocSize.getValueType(), AllocSize, 3093 DAG.getIntPtrConstant(StackAlign-1)); 3094 3095 // Mask out the low bits for alignment purposes. 3096 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3097 AllocSize.getValueType(), AllocSize, 3098 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3099 3100 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3101 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3102 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3103 VTs, Ops, 3); 3104 setValue(&I, DSA); 3105 DAG.setRoot(DSA.getValue(1)); 3106 3107 // Inform the Frame Information that we have just allocated a variable-sized 3108 // object. 3109 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3110} 3111 3112void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3113 const Value *SV = I.getOperand(0); 3114 SDValue Ptr = getValue(SV); 3115 3116 Type *Ty = I.getType(); 3117 3118 bool isVolatile = I.isVolatile(); 3119 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3120 unsigned Alignment = I.getAlignment(); 3121 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3122 3123 SmallVector<EVT, 4> ValueVTs; 3124 SmallVector<uint64_t, 4> Offsets; 3125 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3126 unsigned NumValues = ValueVTs.size(); 3127 if (NumValues == 0) 3128 return; 3129 3130 SDValue Root; 3131 bool ConstantMemory = false; 3132 if (I.isVolatile() || NumValues > MaxParallelChains) 3133 // Serialize volatile loads with other side effects. 3134 Root = getRoot(); 3135 else if (AA->pointsToConstantMemory( 3136 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3137 // Do not serialize (non-volatile) loads of constant memory with anything. 3138 Root = DAG.getEntryNode(); 3139 ConstantMemory = true; 3140 } else { 3141 // Do not serialize non-volatile loads against each other. 3142 Root = DAG.getRoot(); 3143 } 3144 3145 SmallVector<SDValue, 4> Values(NumValues); 3146 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3147 NumValues)); 3148 EVT PtrVT = Ptr.getValueType(); 3149 unsigned ChainI = 0; 3150 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3151 // Serializing loads here may result in excessive register pressure, and 3152 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3153 // could recover a bit by hoisting nodes upward in the chain by recognizing 3154 // they are side-effect free or do not alias. The optimizer should really 3155 // avoid this case by converting large object/array copies to llvm.memcpy 3156 // (MaxParallelChains should always remain as failsafe). 3157 if (ChainI == MaxParallelChains) { 3158 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3159 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3160 MVT::Other, &Chains[0], ChainI); 3161 Root = Chain; 3162 ChainI = 0; 3163 } 3164 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3165 PtrVT, Ptr, 3166 DAG.getConstant(Offsets[i], PtrVT)); 3167 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3168 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3169 isNonTemporal, Alignment, TBAAInfo); 3170 3171 Values[i] = L; 3172 Chains[ChainI] = L.getValue(1); 3173 } 3174 3175 if (!ConstantMemory) { 3176 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3177 MVT::Other, &Chains[0], ChainI); 3178 if (isVolatile) 3179 DAG.setRoot(Chain); 3180 else 3181 PendingLoads.push_back(Chain); 3182 } 3183 3184 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3185 DAG.getVTList(&ValueVTs[0], NumValues), 3186 &Values[0], NumValues)); 3187} 3188 3189void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3190 const Value *SrcV = I.getOperand(0); 3191 const Value *PtrV = I.getOperand(1); 3192 3193 SmallVector<EVT, 4> ValueVTs; 3194 SmallVector<uint64_t, 4> Offsets; 3195 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3196 unsigned NumValues = ValueVTs.size(); 3197 if (NumValues == 0) 3198 return; 3199 3200 // Get the lowered operands. Note that we do this after 3201 // checking if NumResults is zero, because with zero results 3202 // the operands won't have values in the map. 3203 SDValue Src = getValue(SrcV); 3204 SDValue Ptr = getValue(PtrV); 3205 3206 SDValue Root = getRoot(); 3207 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3208 NumValues)); 3209 EVT PtrVT = Ptr.getValueType(); 3210 bool isVolatile = I.isVolatile(); 3211 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3212 unsigned Alignment = I.getAlignment(); 3213 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3214 3215 unsigned ChainI = 0; 3216 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3217 // See visitLoad comments. 3218 if (ChainI == MaxParallelChains) { 3219 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3220 MVT::Other, &Chains[0], ChainI); 3221 Root = Chain; 3222 ChainI = 0; 3223 } 3224 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3225 DAG.getConstant(Offsets[i], PtrVT)); 3226 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3227 SDValue(Src.getNode(), Src.getResNo() + i), 3228 Add, MachinePointerInfo(PtrV, Offsets[i]), 3229 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3230 Chains[ChainI] = St; 3231 } 3232 3233 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3234 MVT::Other, &Chains[0], ChainI); 3235 ++SDNodeOrder; 3236 AssignOrderingToNode(StoreNode.getNode()); 3237 DAG.setRoot(StoreNode); 3238} 3239 3240static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3241 bool Before, DebugLoc dl, 3242 SelectionDAG &DAG, 3243 const TargetLowering &TLI) { 3244 // Fence, if necessary 3245 if (Before) { 3246 if (Order == AcquireRelease) 3247 Order = Release; 3248 else if (Order == Acquire || Order == Monotonic) 3249 return Chain; 3250 } else { 3251 if (Order == AcquireRelease) 3252 Order = Acquire; 3253 else if (Order == Release || Order == Monotonic) 3254 return Chain; 3255 } 3256 SDValue Ops[3]; 3257 Ops[0] = Chain; 3258 Ops[1] = DAG.getConstant(SequentiallyConsistent, TLI.getPointerTy()); 3259 Ops[2] = DAG.getConstant(Order, TLI.getPointerTy()); 3260 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3261} 3262 3263void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3264 DebugLoc dl = getCurDebugLoc(); 3265 AtomicOrdering Order = I.getOrdering(); 3266 3267 SDValue InChain = getRoot(); 3268 3269 if (TLI.getInsertFencesForAtomic()) 3270 InChain = InsertFenceForAtomic(InChain, Order, true, dl, DAG, TLI); 3271 3272 SDValue L = 3273 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3274 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3275 InChain, 3276 getValue(I.getPointerOperand()), 3277 getValue(I.getCompareOperand()), 3278 getValue(I.getNewValOperand()), 3279 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3280 I.getOrdering(), I.getSynchScope()); 3281 3282 SDValue OutChain = L.getValue(1); 3283 3284 if (TLI.getInsertFencesForAtomic()) 3285 OutChain = InsertFenceForAtomic(OutChain, Order, false, dl, DAG, TLI); 3286 3287 setValue(&I, L); 3288 DAG.setRoot(OutChain); 3289} 3290 3291void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3292 DebugLoc dl = getCurDebugLoc(); 3293 ISD::NodeType NT; 3294 switch (I.getOperation()) { 3295 default: llvm_unreachable("Unknown atomicrmw operation"); return; 3296 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3297 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3298 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3299 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3300 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3301 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3302 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3303 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3304 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3305 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3306 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3307 } 3308 AtomicOrdering Order = I.getOrdering(); 3309 3310 SDValue InChain = getRoot(); 3311 3312 if (TLI.getInsertFencesForAtomic()) 3313 InChain = InsertFenceForAtomic(InChain, Order, true, dl, DAG, TLI); 3314 3315 SDValue L = 3316 DAG.getAtomic(NT, dl, 3317 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3318 InChain, 3319 getValue(I.getPointerOperand()), 3320 getValue(I.getValOperand()), 3321 I.getPointerOperand(), 0 /* Alignment */, 3322 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3323 I.getSynchScope()); 3324 3325 SDValue OutChain = L.getValue(1); 3326 3327 if (TLI.getInsertFencesForAtomic()) 3328 OutChain = InsertFenceForAtomic(OutChain, Order, false, dl, DAG, TLI); 3329 3330 setValue(&I, L); 3331 DAG.setRoot(OutChain); 3332} 3333 3334void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3335 DebugLoc dl = getCurDebugLoc(); 3336 SDValue Ops[3]; 3337 Ops[0] = getRoot(); 3338 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3339 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3340 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3341} 3342 3343/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3344/// node. 3345void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3346 unsigned Intrinsic) { 3347 bool HasChain = !I.doesNotAccessMemory(); 3348 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3349 3350 // Build the operand list. 3351 SmallVector<SDValue, 8> Ops; 3352 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3353 if (OnlyLoad) { 3354 // We don't need to serialize loads against other loads. 3355 Ops.push_back(DAG.getRoot()); 3356 } else { 3357 Ops.push_back(getRoot()); 3358 } 3359 } 3360 3361 // Info is set by getTgtMemInstrinsic 3362 TargetLowering::IntrinsicInfo Info; 3363 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3364 3365 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3366 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3367 Info.opc == ISD::INTRINSIC_W_CHAIN) 3368 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3369 3370 // Add all operands of the call to the operand list. 3371 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3372 SDValue Op = getValue(I.getArgOperand(i)); 3373 assert(TLI.isTypeLegal(Op.getValueType()) && 3374 "Intrinsic uses a non-legal type?"); 3375 Ops.push_back(Op); 3376 } 3377 3378 SmallVector<EVT, 4> ValueVTs; 3379 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3380#ifndef NDEBUG 3381 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3382 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3383 "Intrinsic uses a non-legal type?"); 3384 } 3385#endif // NDEBUG 3386 3387 if (HasChain) 3388 ValueVTs.push_back(MVT::Other); 3389 3390 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3391 3392 // Create the node. 3393 SDValue Result; 3394 if (IsTgtIntrinsic) { 3395 // This is target intrinsic that touches memory 3396 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3397 VTs, &Ops[0], Ops.size(), 3398 Info.memVT, 3399 MachinePointerInfo(Info.ptrVal, Info.offset), 3400 Info.align, Info.vol, 3401 Info.readMem, Info.writeMem); 3402 } else if (!HasChain) { 3403 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3404 VTs, &Ops[0], Ops.size()); 3405 } else if (!I.getType()->isVoidTy()) { 3406 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3407 VTs, &Ops[0], Ops.size()); 3408 } else { 3409 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3410 VTs, &Ops[0], Ops.size()); 3411 } 3412 3413 if (HasChain) { 3414 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3415 if (OnlyLoad) 3416 PendingLoads.push_back(Chain); 3417 else 3418 DAG.setRoot(Chain); 3419 } 3420 3421 if (!I.getType()->isVoidTy()) { 3422 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3423 EVT VT = TLI.getValueType(PTy); 3424 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3425 } 3426 3427 setValue(&I, Result); 3428 } 3429} 3430 3431/// GetSignificand - Get the significand and build it into a floating-point 3432/// number with exponent of 1: 3433/// 3434/// Op = (Op & 0x007fffff) | 0x3f800000; 3435/// 3436/// where Op is the hexidecimal representation of floating point value. 3437static SDValue 3438GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3439 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3440 DAG.getConstant(0x007fffff, MVT::i32)); 3441 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3442 DAG.getConstant(0x3f800000, MVT::i32)); 3443 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3444} 3445 3446/// GetExponent - Get the exponent: 3447/// 3448/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3449/// 3450/// where Op is the hexidecimal representation of floating point value. 3451static SDValue 3452GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3453 DebugLoc dl) { 3454 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3455 DAG.getConstant(0x7f800000, MVT::i32)); 3456 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3457 DAG.getConstant(23, TLI.getPointerTy())); 3458 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3459 DAG.getConstant(127, MVT::i32)); 3460 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3461} 3462 3463/// getF32Constant - Get 32-bit floating point constant. 3464static SDValue 3465getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3466 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3467} 3468 3469/// Inlined utility function to implement binary input atomic intrinsics for 3470/// visitIntrinsicCall: I is a call instruction 3471/// Op is the associated NodeType for I 3472const char * 3473SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3474 ISD::NodeType Op) { 3475 SDValue Root = getRoot(); 3476 SDValue L = 3477 DAG.getAtomic(Op, getCurDebugLoc(), 3478 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3479 Root, 3480 getValue(I.getArgOperand(0)), 3481 getValue(I.getArgOperand(1)), 3482 I.getArgOperand(0), 0 /* Alignment */, 3483 Monotonic, CrossThread); 3484 setValue(&I, L); 3485 DAG.setRoot(L.getValue(1)); 3486 return 0; 3487} 3488 3489// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3490const char * 3491SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3492 SDValue Op1 = getValue(I.getArgOperand(0)); 3493 SDValue Op2 = getValue(I.getArgOperand(1)); 3494 3495 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3496 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3497 return 0; 3498} 3499 3500/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3501/// limited-precision mode. 3502void 3503SelectionDAGBuilder::visitExp(const CallInst &I) { 3504 SDValue result; 3505 DebugLoc dl = getCurDebugLoc(); 3506 3507 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3508 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3509 SDValue Op = getValue(I.getArgOperand(0)); 3510 3511 // Put the exponent in the right bit position for later addition to the 3512 // final result: 3513 // 3514 // #define LOG2OFe 1.4426950f 3515 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3516 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3517 getF32Constant(DAG, 0x3fb8aa3b)); 3518 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3519 3520 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3521 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3522 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3523 3524 // IntegerPartOfX <<= 23; 3525 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3526 DAG.getConstant(23, TLI.getPointerTy())); 3527 3528 if (LimitFloatPrecision <= 6) { 3529 // For floating-point precision of 6: 3530 // 3531 // TwoToFractionalPartOfX = 3532 // 0.997535578f + 3533 // (0.735607626f + 0.252464424f * x) * x; 3534 // 3535 // error 0.0144103317, which is 6 bits 3536 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3537 getF32Constant(DAG, 0x3e814304)); 3538 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3539 getF32Constant(DAG, 0x3f3c50c8)); 3540 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3541 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3542 getF32Constant(DAG, 0x3f7f5e7e)); 3543 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3544 3545 // Add the exponent into the result in integer domain. 3546 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3547 TwoToFracPartOfX, IntegerPartOfX); 3548 3549 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3550 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3551 // For floating-point precision of 12: 3552 // 3553 // TwoToFractionalPartOfX = 3554 // 0.999892986f + 3555 // (0.696457318f + 3556 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3557 // 3558 // 0.000107046256 error, which is 13 to 14 bits 3559 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3560 getF32Constant(DAG, 0x3da235e3)); 3561 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3562 getF32Constant(DAG, 0x3e65b8f3)); 3563 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3564 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3565 getF32Constant(DAG, 0x3f324b07)); 3566 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3567 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3568 getF32Constant(DAG, 0x3f7ff8fd)); 3569 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3570 3571 // Add the exponent into the result in integer domain. 3572 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3573 TwoToFracPartOfX, IntegerPartOfX); 3574 3575 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3576 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3577 // For floating-point precision of 18: 3578 // 3579 // TwoToFractionalPartOfX = 3580 // 0.999999982f + 3581 // (0.693148872f + 3582 // (0.240227044f + 3583 // (0.554906021e-1f + 3584 // (0.961591928e-2f + 3585 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3586 // 3587 // error 2.47208000*10^(-7), which is better than 18 bits 3588 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3589 getF32Constant(DAG, 0x3924b03e)); 3590 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3591 getF32Constant(DAG, 0x3ab24b87)); 3592 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3593 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3594 getF32Constant(DAG, 0x3c1d8c17)); 3595 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3596 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3597 getF32Constant(DAG, 0x3d634a1d)); 3598 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3599 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3600 getF32Constant(DAG, 0x3e75fe14)); 3601 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3602 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3603 getF32Constant(DAG, 0x3f317234)); 3604 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3605 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3606 getF32Constant(DAG, 0x3f800000)); 3607 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3608 MVT::i32, t13); 3609 3610 // Add the exponent into the result in integer domain. 3611 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3612 TwoToFracPartOfX, IntegerPartOfX); 3613 3614 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3615 } 3616 } else { 3617 // No special expansion. 3618 result = DAG.getNode(ISD::FEXP, dl, 3619 getValue(I.getArgOperand(0)).getValueType(), 3620 getValue(I.getArgOperand(0))); 3621 } 3622 3623 setValue(&I, result); 3624} 3625 3626/// visitLog - Lower a log intrinsic. Handles the special sequences for 3627/// limited-precision mode. 3628void 3629SelectionDAGBuilder::visitLog(const CallInst &I) { 3630 SDValue result; 3631 DebugLoc dl = getCurDebugLoc(); 3632 3633 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3634 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3635 SDValue Op = getValue(I.getArgOperand(0)); 3636 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3637 3638 // Scale the exponent by log(2) [0.69314718f]. 3639 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3640 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3641 getF32Constant(DAG, 0x3f317218)); 3642 3643 // Get the significand and build it into a floating-point number with 3644 // exponent of 1. 3645 SDValue X = GetSignificand(DAG, Op1, dl); 3646 3647 if (LimitFloatPrecision <= 6) { 3648 // For floating-point precision of 6: 3649 // 3650 // LogofMantissa = 3651 // -1.1609546f + 3652 // (1.4034025f - 0.23903021f * x) * x; 3653 // 3654 // error 0.0034276066, which is better than 8 bits 3655 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3656 getF32Constant(DAG, 0xbe74c456)); 3657 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3658 getF32Constant(DAG, 0x3fb3a2b1)); 3659 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3660 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3661 getF32Constant(DAG, 0x3f949a29)); 3662 3663 result = DAG.getNode(ISD::FADD, dl, 3664 MVT::f32, LogOfExponent, LogOfMantissa); 3665 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3666 // For floating-point precision of 12: 3667 // 3668 // LogOfMantissa = 3669 // -1.7417939f + 3670 // (2.8212026f + 3671 // (-1.4699568f + 3672 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3673 // 3674 // error 0.000061011436, which is 14 bits 3675 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3676 getF32Constant(DAG, 0xbd67b6d6)); 3677 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3678 getF32Constant(DAG, 0x3ee4f4b8)); 3679 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3680 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3681 getF32Constant(DAG, 0x3fbc278b)); 3682 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3683 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3684 getF32Constant(DAG, 0x40348e95)); 3685 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3686 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3687 getF32Constant(DAG, 0x3fdef31a)); 3688 3689 result = DAG.getNode(ISD::FADD, dl, 3690 MVT::f32, LogOfExponent, LogOfMantissa); 3691 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3692 // For floating-point precision of 18: 3693 // 3694 // LogOfMantissa = 3695 // -2.1072184f + 3696 // (4.2372794f + 3697 // (-3.7029485f + 3698 // (2.2781945f + 3699 // (-0.87823314f + 3700 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3701 // 3702 // error 0.0000023660568, which is better than 18 bits 3703 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3704 getF32Constant(DAG, 0xbc91e5ac)); 3705 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3706 getF32Constant(DAG, 0x3e4350aa)); 3707 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3708 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3709 getF32Constant(DAG, 0x3f60d3e3)); 3710 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3711 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3712 getF32Constant(DAG, 0x4011cdf0)); 3713 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3714 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3715 getF32Constant(DAG, 0x406cfd1c)); 3716 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3717 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3718 getF32Constant(DAG, 0x408797cb)); 3719 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3720 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3721 getF32Constant(DAG, 0x4006dcab)); 3722 3723 result = DAG.getNode(ISD::FADD, dl, 3724 MVT::f32, LogOfExponent, LogOfMantissa); 3725 } 3726 } else { 3727 // No special expansion. 3728 result = DAG.getNode(ISD::FLOG, dl, 3729 getValue(I.getArgOperand(0)).getValueType(), 3730 getValue(I.getArgOperand(0))); 3731 } 3732 3733 setValue(&I, result); 3734} 3735 3736/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3737/// limited-precision mode. 3738void 3739SelectionDAGBuilder::visitLog2(const CallInst &I) { 3740 SDValue result; 3741 DebugLoc dl = getCurDebugLoc(); 3742 3743 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3744 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3745 SDValue Op = getValue(I.getArgOperand(0)); 3746 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3747 3748 // Get the exponent. 3749 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3750 3751 // Get the significand and build it into a floating-point number with 3752 // exponent of 1. 3753 SDValue X = GetSignificand(DAG, Op1, dl); 3754 3755 // Different possible minimax approximations of significand in 3756 // floating-point for various degrees of accuracy over [1,2]. 3757 if (LimitFloatPrecision <= 6) { 3758 // For floating-point precision of 6: 3759 // 3760 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3761 // 3762 // error 0.0049451742, which is more than 7 bits 3763 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3764 getF32Constant(DAG, 0xbeb08fe0)); 3765 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3766 getF32Constant(DAG, 0x40019463)); 3767 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3768 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3769 getF32Constant(DAG, 0x3fd6633d)); 3770 3771 result = DAG.getNode(ISD::FADD, dl, 3772 MVT::f32, LogOfExponent, Log2ofMantissa); 3773 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3774 // For floating-point precision of 12: 3775 // 3776 // Log2ofMantissa = 3777 // -2.51285454f + 3778 // (4.07009056f + 3779 // (-2.12067489f + 3780 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3781 // 3782 // error 0.0000876136000, which is better than 13 bits 3783 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3784 getF32Constant(DAG, 0xbda7262e)); 3785 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3786 getF32Constant(DAG, 0x3f25280b)); 3787 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3788 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3789 getF32Constant(DAG, 0x4007b923)); 3790 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3791 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3792 getF32Constant(DAG, 0x40823e2f)); 3793 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3794 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3795 getF32Constant(DAG, 0x4020d29c)); 3796 3797 result = DAG.getNode(ISD::FADD, dl, 3798 MVT::f32, LogOfExponent, Log2ofMantissa); 3799 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3800 // For floating-point precision of 18: 3801 // 3802 // Log2ofMantissa = 3803 // -3.0400495f + 3804 // (6.1129976f + 3805 // (-5.3420409f + 3806 // (3.2865683f + 3807 // (-1.2669343f + 3808 // (0.27515199f - 3809 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3810 // 3811 // error 0.0000018516, which is better than 18 bits 3812 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3813 getF32Constant(DAG, 0xbcd2769e)); 3814 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3815 getF32Constant(DAG, 0x3e8ce0b9)); 3816 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3817 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3818 getF32Constant(DAG, 0x3fa22ae7)); 3819 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3820 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3821 getF32Constant(DAG, 0x40525723)); 3822 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3823 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3824 getF32Constant(DAG, 0x40aaf200)); 3825 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3826 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3827 getF32Constant(DAG, 0x40c39dad)); 3828 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3829 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3830 getF32Constant(DAG, 0x4042902c)); 3831 3832 result = DAG.getNode(ISD::FADD, dl, 3833 MVT::f32, LogOfExponent, Log2ofMantissa); 3834 } 3835 } else { 3836 // No special expansion. 3837 result = DAG.getNode(ISD::FLOG2, dl, 3838 getValue(I.getArgOperand(0)).getValueType(), 3839 getValue(I.getArgOperand(0))); 3840 } 3841 3842 setValue(&I, result); 3843} 3844 3845/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3846/// limited-precision mode. 3847void 3848SelectionDAGBuilder::visitLog10(const CallInst &I) { 3849 SDValue result; 3850 DebugLoc dl = getCurDebugLoc(); 3851 3852 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3853 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3854 SDValue Op = getValue(I.getArgOperand(0)); 3855 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3856 3857 // Scale the exponent by log10(2) [0.30102999f]. 3858 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3859 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3860 getF32Constant(DAG, 0x3e9a209a)); 3861 3862 // Get the significand and build it into a floating-point number with 3863 // exponent of 1. 3864 SDValue X = GetSignificand(DAG, Op1, dl); 3865 3866 if (LimitFloatPrecision <= 6) { 3867 // For floating-point precision of 6: 3868 // 3869 // Log10ofMantissa = 3870 // -0.50419619f + 3871 // (0.60948995f - 0.10380950f * x) * x; 3872 // 3873 // error 0.0014886165, which is 6 bits 3874 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3875 getF32Constant(DAG, 0xbdd49a13)); 3876 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3877 getF32Constant(DAG, 0x3f1c0789)); 3878 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3879 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3880 getF32Constant(DAG, 0x3f011300)); 3881 3882 result = DAG.getNode(ISD::FADD, dl, 3883 MVT::f32, LogOfExponent, Log10ofMantissa); 3884 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3885 // For floating-point precision of 12: 3886 // 3887 // Log10ofMantissa = 3888 // -0.64831180f + 3889 // (0.91751397f + 3890 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3891 // 3892 // error 0.00019228036, which is better than 12 bits 3893 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3894 getF32Constant(DAG, 0x3d431f31)); 3895 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3896 getF32Constant(DAG, 0x3ea21fb2)); 3897 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3898 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3899 getF32Constant(DAG, 0x3f6ae232)); 3900 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3901 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3902 getF32Constant(DAG, 0x3f25f7c3)); 3903 3904 result = DAG.getNode(ISD::FADD, dl, 3905 MVT::f32, LogOfExponent, Log10ofMantissa); 3906 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3907 // For floating-point precision of 18: 3908 // 3909 // Log10ofMantissa = 3910 // -0.84299375f + 3911 // (1.5327582f + 3912 // (-1.0688956f + 3913 // (0.49102474f + 3914 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3915 // 3916 // error 0.0000037995730, which is better than 18 bits 3917 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3918 getF32Constant(DAG, 0x3c5d51ce)); 3919 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3920 getF32Constant(DAG, 0x3e00685a)); 3921 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3922 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3923 getF32Constant(DAG, 0x3efb6798)); 3924 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3925 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3926 getF32Constant(DAG, 0x3f88d192)); 3927 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3928 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3929 getF32Constant(DAG, 0x3fc4316c)); 3930 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3931 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3932 getF32Constant(DAG, 0x3f57ce70)); 3933 3934 result = DAG.getNode(ISD::FADD, dl, 3935 MVT::f32, LogOfExponent, Log10ofMantissa); 3936 } 3937 } else { 3938 // No special expansion. 3939 result = DAG.getNode(ISD::FLOG10, dl, 3940 getValue(I.getArgOperand(0)).getValueType(), 3941 getValue(I.getArgOperand(0))); 3942 } 3943 3944 setValue(&I, result); 3945} 3946 3947/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3948/// limited-precision mode. 3949void 3950SelectionDAGBuilder::visitExp2(const CallInst &I) { 3951 SDValue result; 3952 DebugLoc dl = getCurDebugLoc(); 3953 3954 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3955 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3956 SDValue Op = getValue(I.getArgOperand(0)); 3957 3958 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3959 3960 // FractionalPartOfX = x - (float)IntegerPartOfX; 3961 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3962 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3963 3964 // IntegerPartOfX <<= 23; 3965 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3966 DAG.getConstant(23, TLI.getPointerTy())); 3967 3968 if (LimitFloatPrecision <= 6) { 3969 // For floating-point precision of 6: 3970 // 3971 // TwoToFractionalPartOfX = 3972 // 0.997535578f + 3973 // (0.735607626f + 0.252464424f * x) * x; 3974 // 3975 // error 0.0144103317, which is 6 bits 3976 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3977 getF32Constant(DAG, 0x3e814304)); 3978 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3979 getF32Constant(DAG, 0x3f3c50c8)); 3980 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3981 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3982 getF32Constant(DAG, 0x3f7f5e7e)); 3983 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3984 SDValue TwoToFractionalPartOfX = 3985 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3986 3987 result = DAG.getNode(ISD::BITCAST, dl, 3988 MVT::f32, TwoToFractionalPartOfX); 3989 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3990 // For floating-point precision of 12: 3991 // 3992 // TwoToFractionalPartOfX = 3993 // 0.999892986f + 3994 // (0.696457318f + 3995 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3996 // 3997 // error 0.000107046256, which is 13 to 14 bits 3998 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3999 getF32Constant(DAG, 0x3da235e3)); 4000 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4001 getF32Constant(DAG, 0x3e65b8f3)); 4002 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4003 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4004 getF32Constant(DAG, 0x3f324b07)); 4005 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4006 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4007 getF32Constant(DAG, 0x3f7ff8fd)); 4008 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4009 SDValue TwoToFractionalPartOfX = 4010 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4011 4012 result = DAG.getNode(ISD::BITCAST, dl, 4013 MVT::f32, TwoToFractionalPartOfX); 4014 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4015 // For floating-point precision of 18: 4016 // 4017 // TwoToFractionalPartOfX = 4018 // 0.999999982f + 4019 // (0.693148872f + 4020 // (0.240227044f + 4021 // (0.554906021e-1f + 4022 // (0.961591928e-2f + 4023 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4024 // error 2.47208000*10^(-7), which is better than 18 bits 4025 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4026 getF32Constant(DAG, 0x3924b03e)); 4027 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4028 getF32Constant(DAG, 0x3ab24b87)); 4029 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4030 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4031 getF32Constant(DAG, 0x3c1d8c17)); 4032 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4033 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4034 getF32Constant(DAG, 0x3d634a1d)); 4035 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4036 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4037 getF32Constant(DAG, 0x3e75fe14)); 4038 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4039 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4040 getF32Constant(DAG, 0x3f317234)); 4041 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4042 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4043 getF32Constant(DAG, 0x3f800000)); 4044 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4045 SDValue TwoToFractionalPartOfX = 4046 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4047 4048 result = DAG.getNode(ISD::BITCAST, dl, 4049 MVT::f32, TwoToFractionalPartOfX); 4050 } 4051 } else { 4052 // No special expansion. 4053 result = DAG.getNode(ISD::FEXP2, dl, 4054 getValue(I.getArgOperand(0)).getValueType(), 4055 getValue(I.getArgOperand(0))); 4056 } 4057 4058 setValue(&I, result); 4059} 4060 4061/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4062/// limited-precision mode with x == 10.0f. 4063void 4064SelectionDAGBuilder::visitPow(const CallInst &I) { 4065 SDValue result; 4066 const Value *Val = I.getArgOperand(0); 4067 DebugLoc dl = getCurDebugLoc(); 4068 bool IsExp10 = false; 4069 4070 if (getValue(Val).getValueType() == MVT::f32 && 4071 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4072 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4073 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4074 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4075 APFloat Ten(10.0f); 4076 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4077 } 4078 } 4079 } 4080 4081 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4082 SDValue Op = getValue(I.getArgOperand(1)); 4083 4084 // Put the exponent in the right bit position for later addition to the 4085 // final result: 4086 // 4087 // #define LOG2OF10 3.3219281f 4088 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4089 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4090 getF32Constant(DAG, 0x40549a78)); 4091 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4092 4093 // FractionalPartOfX = x - (float)IntegerPartOfX; 4094 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4095 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4096 4097 // IntegerPartOfX <<= 23; 4098 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4099 DAG.getConstant(23, TLI.getPointerTy())); 4100 4101 if (LimitFloatPrecision <= 6) { 4102 // For floating-point precision of 6: 4103 // 4104 // twoToFractionalPartOfX = 4105 // 0.997535578f + 4106 // (0.735607626f + 0.252464424f * x) * x; 4107 // 4108 // error 0.0144103317, which is 6 bits 4109 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4110 getF32Constant(DAG, 0x3e814304)); 4111 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4112 getF32Constant(DAG, 0x3f3c50c8)); 4113 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4114 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4115 getF32Constant(DAG, 0x3f7f5e7e)); 4116 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4117 SDValue TwoToFractionalPartOfX = 4118 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4119 4120 result = DAG.getNode(ISD::BITCAST, dl, 4121 MVT::f32, TwoToFractionalPartOfX); 4122 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4123 // For floating-point precision of 12: 4124 // 4125 // TwoToFractionalPartOfX = 4126 // 0.999892986f + 4127 // (0.696457318f + 4128 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4129 // 4130 // error 0.000107046256, which is 13 to 14 bits 4131 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4132 getF32Constant(DAG, 0x3da235e3)); 4133 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4134 getF32Constant(DAG, 0x3e65b8f3)); 4135 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4136 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4137 getF32Constant(DAG, 0x3f324b07)); 4138 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4139 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4140 getF32Constant(DAG, 0x3f7ff8fd)); 4141 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4142 SDValue TwoToFractionalPartOfX = 4143 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4144 4145 result = DAG.getNode(ISD::BITCAST, dl, 4146 MVT::f32, TwoToFractionalPartOfX); 4147 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4148 // For floating-point precision of 18: 4149 // 4150 // TwoToFractionalPartOfX = 4151 // 0.999999982f + 4152 // (0.693148872f + 4153 // (0.240227044f + 4154 // (0.554906021e-1f + 4155 // (0.961591928e-2f + 4156 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4157 // error 2.47208000*10^(-7), which is better than 18 bits 4158 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4159 getF32Constant(DAG, 0x3924b03e)); 4160 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4161 getF32Constant(DAG, 0x3ab24b87)); 4162 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4163 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4164 getF32Constant(DAG, 0x3c1d8c17)); 4165 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4166 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4167 getF32Constant(DAG, 0x3d634a1d)); 4168 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4169 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4170 getF32Constant(DAG, 0x3e75fe14)); 4171 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4172 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4173 getF32Constant(DAG, 0x3f317234)); 4174 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4175 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4176 getF32Constant(DAG, 0x3f800000)); 4177 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4178 SDValue TwoToFractionalPartOfX = 4179 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4180 4181 result = DAG.getNode(ISD::BITCAST, dl, 4182 MVT::f32, TwoToFractionalPartOfX); 4183 } 4184 } else { 4185 // No special expansion. 4186 result = DAG.getNode(ISD::FPOW, dl, 4187 getValue(I.getArgOperand(0)).getValueType(), 4188 getValue(I.getArgOperand(0)), 4189 getValue(I.getArgOperand(1))); 4190 } 4191 4192 setValue(&I, result); 4193} 4194 4195 4196/// ExpandPowI - Expand a llvm.powi intrinsic. 4197static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4198 SelectionDAG &DAG) { 4199 // If RHS is a constant, we can expand this out to a multiplication tree, 4200 // otherwise we end up lowering to a call to __powidf2 (for example). When 4201 // optimizing for size, we only want to do this if the expansion would produce 4202 // a small number of multiplies, otherwise we do the full expansion. 4203 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4204 // Get the exponent as a positive value. 4205 unsigned Val = RHSC->getSExtValue(); 4206 if ((int)Val < 0) Val = -Val; 4207 4208 // powi(x, 0) -> 1.0 4209 if (Val == 0) 4210 return DAG.getConstantFP(1.0, LHS.getValueType()); 4211 4212 const Function *F = DAG.getMachineFunction().getFunction(); 4213 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4214 // If optimizing for size, don't insert too many multiplies. This 4215 // inserts up to 5 multiplies. 4216 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4217 // We use the simple binary decomposition method to generate the multiply 4218 // sequence. There are more optimal ways to do this (for example, 4219 // powi(x,15) generates one more multiply than it should), but this has 4220 // the benefit of being both really simple and much better than a libcall. 4221 SDValue Res; // Logically starts equal to 1.0 4222 SDValue CurSquare = LHS; 4223 while (Val) { 4224 if (Val & 1) { 4225 if (Res.getNode()) 4226 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4227 else 4228 Res = CurSquare; // 1.0*CurSquare. 4229 } 4230 4231 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4232 CurSquare, CurSquare); 4233 Val >>= 1; 4234 } 4235 4236 // If the original was negative, invert the result, producing 1/(x*x*x). 4237 if (RHSC->getSExtValue() < 0) 4238 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4239 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4240 return Res; 4241 } 4242 } 4243 4244 // Otherwise, expand to a libcall. 4245 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4246} 4247 4248// getTruncatedArgReg - Find underlying register used for an truncated 4249// argument. 4250static unsigned getTruncatedArgReg(const SDValue &N) { 4251 if (N.getOpcode() != ISD::TRUNCATE) 4252 return 0; 4253 4254 const SDValue &Ext = N.getOperand(0); 4255 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4256 const SDValue &CFR = Ext.getOperand(0); 4257 if (CFR.getOpcode() == ISD::CopyFromReg) 4258 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4259 else 4260 if (CFR.getOpcode() == ISD::TRUNCATE) 4261 return getTruncatedArgReg(CFR); 4262 } 4263 return 0; 4264} 4265 4266/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4267/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4268/// At the end of instruction selection, they will be inserted to the entry BB. 4269bool 4270SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4271 int64_t Offset, 4272 const SDValue &N) { 4273 const Argument *Arg = dyn_cast<Argument>(V); 4274 if (!Arg) 4275 return false; 4276 4277 MachineFunction &MF = DAG.getMachineFunction(); 4278 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4279 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4280 4281 // Ignore inlined function arguments here. 4282 DIVariable DV(Variable); 4283 if (DV.isInlinedFnArgument(MF.getFunction())) 4284 return false; 4285 4286 unsigned Reg = 0; 4287 if (Arg->hasByValAttr()) { 4288 // Byval arguments' frame index is recorded during argument lowering. 4289 // Use this info directly. 4290 Reg = TRI->getFrameRegister(MF); 4291 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 4292 // If byval argument ofset is not recorded then ignore this. 4293 if (!Offset) 4294 Reg = 0; 4295 } 4296 4297 if (N.getNode()) { 4298 if (N.getOpcode() == ISD::CopyFromReg) 4299 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4300 else 4301 Reg = getTruncatedArgReg(N); 4302 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4303 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4304 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4305 if (PR) 4306 Reg = PR; 4307 } 4308 } 4309 4310 if (!Reg) { 4311 // Check if ValueMap has reg number. 4312 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4313 if (VMI != FuncInfo.ValueMap.end()) 4314 Reg = VMI->second; 4315 } 4316 4317 if (!Reg && N.getNode()) { 4318 // Check if frame index is available. 4319 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4320 if (FrameIndexSDNode *FINode = 4321 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4322 Reg = TRI->getFrameRegister(MF); 4323 Offset = FINode->getIndex(); 4324 } 4325 } 4326 4327 if (!Reg) 4328 return false; 4329 4330 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4331 TII->get(TargetOpcode::DBG_VALUE)) 4332 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4333 FuncInfo.ArgDbgValues.push_back(&*MIB); 4334 return true; 4335} 4336 4337// VisualStudio defines setjmp as _setjmp 4338#if defined(_MSC_VER) && defined(setjmp) && \ 4339 !defined(setjmp_undefined_for_msvc) 4340# pragma push_macro("setjmp") 4341# undef setjmp 4342# define setjmp_undefined_for_msvc 4343#endif 4344 4345/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4346/// we want to emit this as a call to a named external function, return the name 4347/// otherwise lower it and return null. 4348const char * 4349SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4350 DebugLoc dl = getCurDebugLoc(); 4351 SDValue Res; 4352 4353 switch (Intrinsic) { 4354 default: 4355 // By default, turn this into a target intrinsic node. 4356 visitTargetIntrinsic(I, Intrinsic); 4357 return 0; 4358 case Intrinsic::vastart: visitVAStart(I); return 0; 4359 case Intrinsic::vaend: visitVAEnd(I); return 0; 4360 case Intrinsic::vacopy: visitVACopy(I); return 0; 4361 case Intrinsic::returnaddress: 4362 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4363 getValue(I.getArgOperand(0)))); 4364 return 0; 4365 case Intrinsic::frameaddress: 4366 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4367 getValue(I.getArgOperand(0)))); 4368 return 0; 4369 case Intrinsic::setjmp: 4370 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4371 case Intrinsic::longjmp: 4372 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4373 case Intrinsic::memcpy: { 4374 // Assert for address < 256 since we support only user defined address 4375 // spaces. 4376 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4377 < 256 && 4378 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4379 < 256 && 4380 "Unknown address space"); 4381 SDValue Op1 = getValue(I.getArgOperand(0)); 4382 SDValue Op2 = getValue(I.getArgOperand(1)); 4383 SDValue Op3 = getValue(I.getArgOperand(2)); 4384 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4385 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4386 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4387 MachinePointerInfo(I.getArgOperand(0)), 4388 MachinePointerInfo(I.getArgOperand(1)))); 4389 return 0; 4390 } 4391 case Intrinsic::memset: { 4392 // Assert for address < 256 since we support only user defined address 4393 // spaces. 4394 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4395 < 256 && 4396 "Unknown address space"); 4397 SDValue Op1 = getValue(I.getArgOperand(0)); 4398 SDValue Op2 = getValue(I.getArgOperand(1)); 4399 SDValue Op3 = getValue(I.getArgOperand(2)); 4400 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4401 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4402 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4403 MachinePointerInfo(I.getArgOperand(0)))); 4404 return 0; 4405 } 4406 case Intrinsic::memmove: { 4407 // Assert for address < 256 since we support only user defined address 4408 // spaces. 4409 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4410 < 256 && 4411 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4412 < 256 && 4413 "Unknown address space"); 4414 SDValue Op1 = getValue(I.getArgOperand(0)); 4415 SDValue Op2 = getValue(I.getArgOperand(1)); 4416 SDValue Op3 = getValue(I.getArgOperand(2)); 4417 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4418 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4419 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4420 MachinePointerInfo(I.getArgOperand(0)), 4421 MachinePointerInfo(I.getArgOperand(1)))); 4422 return 0; 4423 } 4424 case Intrinsic::dbg_declare: { 4425 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4426 MDNode *Variable = DI.getVariable(); 4427 const Value *Address = DI.getAddress(); 4428 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4429 return 0; 4430 4431 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4432 // but do not always have a corresponding SDNode built. The SDNodeOrder 4433 // absolute, but not relative, values are different depending on whether 4434 // debug info exists. 4435 ++SDNodeOrder; 4436 4437 // Check if address has undef value. 4438 if (isa<UndefValue>(Address) || 4439 (Address->use_empty() && !isa<Argument>(Address))) { 4440 DEBUG(dbgs() << "Dropping debug info for " << DI); 4441 return 0; 4442 } 4443 4444 SDValue &N = NodeMap[Address]; 4445 if (!N.getNode() && isa<Argument>(Address)) 4446 // Check unused arguments map. 4447 N = UnusedArgNodeMap[Address]; 4448 SDDbgValue *SDV; 4449 if (N.getNode()) { 4450 // Parameters are handled specially. 4451 bool isParameter = 4452 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4453 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4454 Address = BCI->getOperand(0); 4455 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4456 4457 if (isParameter && !AI) { 4458 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4459 if (FINode) 4460 // Byval parameter. We have a frame index at this point. 4461 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4462 0, dl, SDNodeOrder); 4463 else { 4464 // Address is an argument, so try to emit its dbg value using 4465 // virtual register info from the FuncInfo.ValueMap. 4466 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4467 return 0; 4468 } 4469 } else if (AI) 4470 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4471 0, dl, SDNodeOrder); 4472 else { 4473 // Can't do anything with other non-AI cases yet. 4474 DEBUG(dbgs() << "Dropping debug info for " << DI); 4475 return 0; 4476 } 4477 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4478 } else { 4479 // If Address is an argument then try to emit its dbg value using 4480 // virtual register info from the FuncInfo.ValueMap. 4481 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4482 // If variable is pinned by a alloca in dominating bb then 4483 // use StaticAllocaMap. 4484 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4485 if (AI->getParent() != DI.getParent()) { 4486 DenseMap<const AllocaInst*, int>::iterator SI = 4487 FuncInfo.StaticAllocaMap.find(AI); 4488 if (SI != FuncInfo.StaticAllocaMap.end()) { 4489 SDV = DAG.getDbgValue(Variable, SI->second, 4490 0, dl, SDNodeOrder); 4491 DAG.AddDbgValue(SDV, 0, false); 4492 return 0; 4493 } 4494 } 4495 } 4496 DEBUG(dbgs() << "Dropping debug info for " << DI); 4497 } 4498 } 4499 return 0; 4500 } 4501 case Intrinsic::dbg_value: { 4502 const DbgValueInst &DI = cast<DbgValueInst>(I); 4503 if (!DIVariable(DI.getVariable()).Verify()) 4504 return 0; 4505 4506 MDNode *Variable = DI.getVariable(); 4507 uint64_t Offset = DI.getOffset(); 4508 const Value *V = DI.getValue(); 4509 if (!V) 4510 return 0; 4511 4512 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4513 // but do not always have a corresponding SDNode built. The SDNodeOrder 4514 // absolute, but not relative, values are different depending on whether 4515 // debug info exists. 4516 ++SDNodeOrder; 4517 SDDbgValue *SDV; 4518 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4519 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4520 DAG.AddDbgValue(SDV, 0, false); 4521 } else { 4522 // Do not use getValue() in here; we don't want to generate code at 4523 // this point if it hasn't been done yet. 4524 SDValue N = NodeMap[V]; 4525 if (!N.getNode() && isa<Argument>(V)) 4526 // Check unused arguments map. 4527 N = UnusedArgNodeMap[V]; 4528 if (N.getNode()) { 4529 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4530 SDV = DAG.getDbgValue(Variable, N.getNode(), 4531 N.getResNo(), Offset, dl, SDNodeOrder); 4532 DAG.AddDbgValue(SDV, N.getNode(), false); 4533 } 4534 } else if (!V->use_empty() ) { 4535 // Do not call getValue(V) yet, as we don't want to generate code. 4536 // Remember it for later. 4537 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4538 DanglingDebugInfoMap[V] = DDI; 4539 } else { 4540 // We may expand this to cover more cases. One case where we have no 4541 // data available is an unreferenced parameter. 4542 DEBUG(dbgs() << "Dropping debug info for " << DI); 4543 } 4544 } 4545 4546 // Build a debug info table entry. 4547 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4548 V = BCI->getOperand(0); 4549 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4550 // Don't handle byval struct arguments or VLAs, for example. 4551 if (!AI) 4552 return 0; 4553 DenseMap<const AllocaInst*, int>::iterator SI = 4554 FuncInfo.StaticAllocaMap.find(AI); 4555 if (SI == FuncInfo.StaticAllocaMap.end()) 4556 return 0; // VLAs. 4557 int FI = SI->second; 4558 4559 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4560 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4561 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4562 return 0; 4563 } 4564 case Intrinsic::eh_exception: { 4565 // Insert the EXCEPTIONADDR instruction. 4566 assert(FuncInfo.MBB->isLandingPad() && 4567 "Call to eh.exception not in landing pad!"); 4568 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4569 SDValue Ops[1]; 4570 Ops[0] = DAG.getRoot(); 4571 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4572 setValue(&I, Op); 4573 DAG.setRoot(Op.getValue(1)); 4574 return 0; 4575 } 4576 4577 case Intrinsic::eh_selector: { 4578 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4579 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4580 if (CallMBB->isLandingPad()) 4581 AddCatchInfo(I, &MMI, CallMBB); 4582 else { 4583#ifndef NDEBUG 4584 FuncInfo.CatchInfoLost.insert(&I); 4585#endif 4586 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4587 unsigned Reg = TLI.getExceptionSelectorRegister(); 4588 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4589 } 4590 4591 // Insert the EHSELECTION instruction. 4592 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4593 SDValue Ops[2]; 4594 Ops[0] = getValue(I.getArgOperand(0)); 4595 Ops[1] = getRoot(); 4596 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4597 DAG.setRoot(Op.getValue(1)); 4598 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4599 return 0; 4600 } 4601 4602 case Intrinsic::eh_typeid_for: { 4603 // Find the type id for the given typeinfo. 4604 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4605 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4606 Res = DAG.getConstant(TypeID, MVT::i32); 4607 setValue(&I, Res); 4608 return 0; 4609 } 4610 4611 case Intrinsic::eh_return_i32: 4612 case Intrinsic::eh_return_i64: 4613 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4614 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4615 MVT::Other, 4616 getControlRoot(), 4617 getValue(I.getArgOperand(0)), 4618 getValue(I.getArgOperand(1)))); 4619 return 0; 4620 case Intrinsic::eh_unwind_init: 4621 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4622 return 0; 4623 case Intrinsic::eh_dwarf_cfa: { 4624 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4625 TLI.getPointerTy()); 4626 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4627 TLI.getPointerTy(), 4628 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4629 TLI.getPointerTy()), 4630 CfaArg); 4631 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4632 TLI.getPointerTy(), 4633 DAG.getConstant(0, TLI.getPointerTy())); 4634 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4635 FA, Offset)); 4636 return 0; 4637 } 4638 case Intrinsic::eh_sjlj_callsite: { 4639 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4640 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4641 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4642 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4643 4644 MMI.setCurrentCallSite(CI->getZExtValue()); 4645 return 0; 4646 } 4647 case Intrinsic::eh_sjlj_setjmp: { 4648 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4649 getValue(I.getArgOperand(0)))); 4650 return 0; 4651 } 4652 case Intrinsic::eh_sjlj_longjmp: { 4653 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4654 getRoot(), getValue(I.getArgOperand(0)))); 4655 return 0; 4656 } 4657 case Intrinsic::eh_sjlj_dispatch_setup: { 4658 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4659 getRoot(), getValue(I.getArgOperand(0)))); 4660 return 0; 4661 } 4662 4663 case Intrinsic::x86_mmx_pslli_w: 4664 case Intrinsic::x86_mmx_pslli_d: 4665 case Intrinsic::x86_mmx_pslli_q: 4666 case Intrinsic::x86_mmx_psrli_w: 4667 case Intrinsic::x86_mmx_psrli_d: 4668 case Intrinsic::x86_mmx_psrli_q: 4669 case Intrinsic::x86_mmx_psrai_w: 4670 case Intrinsic::x86_mmx_psrai_d: { 4671 SDValue ShAmt = getValue(I.getArgOperand(1)); 4672 if (isa<ConstantSDNode>(ShAmt)) { 4673 visitTargetIntrinsic(I, Intrinsic); 4674 return 0; 4675 } 4676 unsigned NewIntrinsic = 0; 4677 EVT ShAmtVT = MVT::v2i32; 4678 switch (Intrinsic) { 4679 case Intrinsic::x86_mmx_pslli_w: 4680 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4681 break; 4682 case Intrinsic::x86_mmx_pslli_d: 4683 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4684 break; 4685 case Intrinsic::x86_mmx_pslli_q: 4686 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4687 break; 4688 case Intrinsic::x86_mmx_psrli_w: 4689 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4690 break; 4691 case Intrinsic::x86_mmx_psrli_d: 4692 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4693 break; 4694 case Intrinsic::x86_mmx_psrli_q: 4695 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4696 break; 4697 case Intrinsic::x86_mmx_psrai_w: 4698 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4699 break; 4700 case Intrinsic::x86_mmx_psrai_d: 4701 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4702 break; 4703 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4704 } 4705 4706 // The vector shift intrinsics with scalars uses 32b shift amounts but 4707 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4708 // to be zero. 4709 // We must do this early because v2i32 is not a legal type. 4710 DebugLoc dl = getCurDebugLoc(); 4711 SDValue ShOps[2]; 4712 ShOps[0] = ShAmt; 4713 ShOps[1] = DAG.getConstant(0, MVT::i32); 4714 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4715 EVT DestVT = TLI.getValueType(I.getType()); 4716 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4717 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4718 DAG.getConstant(NewIntrinsic, MVT::i32), 4719 getValue(I.getArgOperand(0)), ShAmt); 4720 setValue(&I, Res); 4721 return 0; 4722 } 4723 case Intrinsic::convertff: 4724 case Intrinsic::convertfsi: 4725 case Intrinsic::convertfui: 4726 case Intrinsic::convertsif: 4727 case Intrinsic::convertuif: 4728 case Intrinsic::convertss: 4729 case Intrinsic::convertsu: 4730 case Intrinsic::convertus: 4731 case Intrinsic::convertuu: { 4732 ISD::CvtCode Code = ISD::CVT_INVALID; 4733 switch (Intrinsic) { 4734 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4735 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4736 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4737 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4738 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4739 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4740 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4741 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4742 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4743 } 4744 EVT DestVT = TLI.getValueType(I.getType()); 4745 const Value *Op1 = I.getArgOperand(0); 4746 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4747 DAG.getValueType(DestVT), 4748 DAG.getValueType(getValue(Op1).getValueType()), 4749 getValue(I.getArgOperand(1)), 4750 getValue(I.getArgOperand(2)), 4751 Code); 4752 setValue(&I, Res); 4753 return 0; 4754 } 4755 case Intrinsic::sqrt: 4756 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4757 getValue(I.getArgOperand(0)).getValueType(), 4758 getValue(I.getArgOperand(0)))); 4759 return 0; 4760 case Intrinsic::powi: 4761 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4762 getValue(I.getArgOperand(1)), DAG)); 4763 return 0; 4764 case Intrinsic::sin: 4765 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4766 getValue(I.getArgOperand(0)).getValueType(), 4767 getValue(I.getArgOperand(0)))); 4768 return 0; 4769 case Intrinsic::cos: 4770 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4771 getValue(I.getArgOperand(0)).getValueType(), 4772 getValue(I.getArgOperand(0)))); 4773 return 0; 4774 case Intrinsic::log: 4775 visitLog(I); 4776 return 0; 4777 case Intrinsic::log2: 4778 visitLog2(I); 4779 return 0; 4780 case Intrinsic::log10: 4781 visitLog10(I); 4782 return 0; 4783 case Intrinsic::exp: 4784 visitExp(I); 4785 return 0; 4786 case Intrinsic::exp2: 4787 visitExp2(I); 4788 return 0; 4789 case Intrinsic::pow: 4790 visitPow(I); 4791 return 0; 4792 case Intrinsic::fma: 4793 setValue(&I, DAG.getNode(ISD::FMA, dl, 4794 getValue(I.getArgOperand(0)).getValueType(), 4795 getValue(I.getArgOperand(0)), 4796 getValue(I.getArgOperand(1)), 4797 getValue(I.getArgOperand(2)))); 4798 return 0; 4799 case Intrinsic::convert_to_fp16: 4800 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4801 MVT::i16, getValue(I.getArgOperand(0)))); 4802 return 0; 4803 case Intrinsic::convert_from_fp16: 4804 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4805 MVT::f32, getValue(I.getArgOperand(0)))); 4806 return 0; 4807 case Intrinsic::pcmarker: { 4808 SDValue Tmp = getValue(I.getArgOperand(0)); 4809 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4810 return 0; 4811 } 4812 case Intrinsic::readcyclecounter: { 4813 SDValue Op = getRoot(); 4814 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4815 DAG.getVTList(MVT::i64, MVT::Other), 4816 &Op, 1); 4817 setValue(&I, Res); 4818 DAG.setRoot(Res.getValue(1)); 4819 return 0; 4820 } 4821 case Intrinsic::bswap: 4822 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4823 getValue(I.getArgOperand(0)).getValueType(), 4824 getValue(I.getArgOperand(0)))); 4825 return 0; 4826 case Intrinsic::cttz: { 4827 SDValue Arg = getValue(I.getArgOperand(0)); 4828 EVT Ty = Arg.getValueType(); 4829 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4830 return 0; 4831 } 4832 case Intrinsic::ctlz: { 4833 SDValue Arg = getValue(I.getArgOperand(0)); 4834 EVT Ty = Arg.getValueType(); 4835 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4836 return 0; 4837 } 4838 case Intrinsic::ctpop: { 4839 SDValue Arg = getValue(I.getArgOperand(0)); 4840 EVT Ty = Arg.getValueType(); 4841 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4842 return 0; 4843 } 4844 case Intrinsic::stacksave: { 4845 SDValue Op = getRoot(); 4846 Res = DAG.getNode(ISD::STACKSAVE, dl, 4847 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4848 setValue(&I, Res); 4849 DAG.setRoot(Res.getValue(1)); 4850 return 0; 4851 } 4852 case Intrinsic::stackrestore: { 4853 Res = getValue(I.getArgOperand(0)); 4854 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4855 return 0; 4856 } 4857 case Intrinsic::stackprotector: { 4858 // Emit code into the DAG to store the stack guard onto the stack. 4859 MachineFunction &MF = DAG.getMachineFunction(); 4860 MachineFrameInfo *MFI = MF.getFrameInfo(); 4861 EVT PtrTy = TLI.getPointerTy(); 4862 4863 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4864 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4865 4866 int FI = FuncInfo.StaticAllocaMap[Slot]; 4867 MFI->setStackProtectorIndex(FI); 4868 4869 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4870 4871 // Store the stack protector onto the stack. 4872 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4873 MachinePointerInfo::getFixedStack(FI), 4874 true, false, 0); 4875 setValue(&I, Res); 4876 DAG.setRoot(Res); 4877 return 0; 4878 } 4879 case Intrinsic::objectsize: { 4880 // If we don't know by now, we're never going to know. 4881 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4882 4883 assert(CI && "Non-constant type in __builtin_object_size?"); 4884 4885 SDValue Arg = getValue(I.getCalledValue()); 4886 EVT Ty = Arg.getValueType(); 4887 4888 if (CI->isZero()) 4889 Res = DAG.getConstant(-1ULL, Ty); 4890 else 4891 Res = DAG.getConstant(0, Ty); 4892 4893 setValue(&I, Res); 4894 return 0; 4895 } 4896 case Intrinsic::var_annotation: 4897 // Discard annotate attributes 4898 return 0; 4899 4900 case Intrinsic::init_trampoline: { 4901 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4902 4903 SDValue Ops[6]; 4904 Ops[0] = getRoot(); 4905 Ops[1] = getValue(I.getArgOperand(0)); 4906 Ops[2] = getValue(I.getArgOperand(1)); 4907 Ops[3] = getValue(I.getArgOperand(2)); 4908 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4909 Ops[5] = DAG.getSrcValue(F); 4910 4911 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4912 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4913 Ops, 6); 4914 4915 setValue(&I, Res); 4916 DAG.setRoot(Res.getValue(1)); 4917 return 0; 4918 } 4919 case Intrinsic::gcroot: 4920 if (GFI) { 4921 const Value *Alloca = I.getArgOperand(0); 4922 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4923 4924 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4925 GFI->addStackRoot(FI->getIndex(), TypeMap); 4926 } 4927 return 0; 4928 case Intrinsic::gcread: 4929 case Intrinsic::gcwrite: 4930 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4931 return 0; 4932 case Intrinsic::flt_rounds: 4933 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4934 return 0; 4935 4936 case Intrinsic::expect: { 4937 // Just replace __builtin_expect(exp, c) with EXP. 4938 setValue(&I, getValue(I.getArgOperand(0))); 4939 return 0; 4940 } 4941 4942 case Intrinsic::trap: { 4943 StringRef TrapFuncName = getTrapFunctionName(); 4944 if (TrapFuncName.empty()) { 4945 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4946 return 0; 4947 } 4948 TargetLowering::ArgListTy Args; 4949 std::pair<SDValue, SDValue> Result = 4950 TLI.LowerCallTo(getRoot(), I.getType(), 4951 false, false, false, false, 0, CallingConv::C, 4952 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 4953 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 4954 Args, DAG, getCurDebugLoc()); 4955 DAG.setRoot(Result.second); 4956 return 0; 4957 } 4958 case Intrinsic::uadd_with_overflow: 4959 return implVisitAluOverflow(I, ISD::UADDO); 4960 case Intrinsic::sadd_with_overflow: 4961 return implVisitAluOverflow(I, ISD::SADDO); 4962 case Intrinsic::usub_with_overflow: 4963 return implVisitAluOverflow(I, ISD::USUBO); 4964 case Intrinsic::ssub_with_overflow: 4965 return implVisitAluOverflow(I, ISD::SSUBO); 4966 case Intrinsic::umul_with_overflow: 4967 return implVisitAluOverflow(I, ISD::UMULO); 4968 case Intrinsic::smul_with_overflow: 4969 return implVisitAluOverflow(I, ISD::SMULO); 4970 4971 case Intrinsic::prefetch: { 4972 SDValue Ops[5]; 4973 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 4974 Ops[0] = getRoot(); 4975 Ops[1] = getValue(I.getArgOperand(0)); 4976 Ops[2] = getValue(I.getArgOperand(1)); 4977 Ops[3] = getValue(I.getArgOperand(2)); 4978 Ops[4] = getValue(I.getArgOperand(3)); 4979 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 4980 DAG.getVTList(MVT::Other), 4981 &Ops[0], 5, 4982 EVT::getIntegerVT(*Context, 8), 4983 MachinePointerInfo(I.getArgOperand(0)), 4984 0, /* align */ 4985 false, /* volatile */ 4986 rw==0, /* read */ 4987 rw==1)); /* write */ 4988 return 0; 4989 } 4990 case Intrinsic::memory_barrier: { 4991 SDValue Ops[6]; 4992 Ops[0] = getRoot(); 4993 for (int x = 1; x < 6; ++x) 4994 Ops[x] = getValue(I.getArgOperand(x - 1)); 4995 4996 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4997 return 0; 4998 } 4999 case Intrinsic::atomic_cmp_swap: { 5000 SDValue Root = getRoot(); 5001 SDValue L = 5002 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 5003 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 5004 Root, 5005 getValue(I.getArgOperand(0)), 5006 getValue(I.getArgOperand(1)), 5007 getValue(I.getArgOperand(2)), 5008 MachinePointerInfo(I.getArgOperand(0)), 0 /* Alignment */, 5009 Monotonic, CrossThread); 5010 setValue(&I, L); 5011 DAG.setRoot(L.getValue(1)); 5012 return 0; 5013 } 5014 case Intrinsic::atomic_load_add: 5015 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 5016 case Intrinsic::atomic_load_sub: 5017 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 5018 case Intrinsic::atomic_load_or: 5019 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 5020 case Intrinsic::atomic_load_xor: 5021 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 5022 case Intrinsic::atomic_load_and: 5023 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 5024 case Intrinsic::atomic_load_nand: 5025 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 5026 case Intrinsic::atomic_load_max: 5027 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 5028 case Intrinsic::atomic_load_min: 5029 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 5030 case Intrinsic::atomic_load_umin: 5031 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 5032 case Intrinsic::atomic_load_umax: 5033 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 5034 case Intrinsic::atomic_swap: 5035 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 5036 5037 case Intrinsic::invariant_start: 5038 case Intrinsic::lifetime_start: 5039 // Discard region information. 5040 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5041 return 0; 5042 case Intrinsic::invariant_end: 5043 case Intrinsic::lifetime_end: 5044 // Discard region information. 5045 return 0; 5046 } 5047} 5048 5049void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5050 bool isTailCall, 5051 MachineBasicBlock *LandingPad) { 5052 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5053 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5054 Type *RetTy = FTy->getReturnType(); 5055 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5056 MCSymbol *BeginLabel = 0; 5057 5058 TargetLowering::ArgListTy Args; 5059 TargetLowering::ArgListEntry Entry; 5060 Args.reserve(CS.arg_size()); 5061 5062 // Check whether the function can return without sret-demotion. 5063 SmallVector<ISD::OutputArg, 4> Outs; 5064 SmallVector<uint64_t, 4> Offsets; 5065 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5066 Outs, TLI, &Offsets); 5067 5068 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5069 DAG.getMachineFunction(), 5070 FTy->isVarArg(), Outs, 5071 FTy->getContext()); 5072 5073 SDValue DemoteStackSlot; 5074 int DemoteStackIdx = -100; 5075 5076 if (!CanLowerReturn) { 5077 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5078 FTy->getReturnType()); 5079 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5080 FTy->getReturnType()); 5081 MachineFunction &MF = DAG.getMachineFunction(); 5082 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5083 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5084 5085 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5086 Entry.Node = DemoteStackSlot; 5087 Entry.Ty = StackSlotPtrType; 5088 Entry.isSExt = false; 5089 Entry.isZExt = false; 5090 Entry.isInReg = false; 5091 Entry.isSRet = true; 5092 Entry.isNest = false; 5093 Entry.isByVal = false; 5094 Entry.Alignment = Align; 5095 Args.push_back(Entry); 5096 RetTy = Type::getVoidTy(FTy->getContext()); 5097 } 5098 5099 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5100 i != e; ++i) { 5101 const Value *V = *i; 5102 5103 // Skip empty types 5104 if (V->getType()->isEmptyTy()) 5105 continue; 5106 5107 SDValue ArgNode = getValue(V); 5108 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5109 5110 unsigned attrInd = i - CS.arg_begin() + 1; 5111 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5112 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5113 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5114 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5115 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5116 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5117 Entry.Alignment = CS.getParamAlignment(attrInd); 5118 Args.push_back(Entry); 5119 } 5120 5121 if (LandingPad) { 5122 // Insert a label before the invoke call to mark the try range. This can be 5123 // used to detect deletion of the invoke via the MachineModuleInfo. 5124 BeginLabel = MMI.getContext().CreateTempSymbol(); 5125 5126 // For SjLj, keep track of which landing pads go with which invokes 5127 // so as to maintain the ordering of pads in the LSDA. 5128 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5129 if (CallSiteIndex) { 5130 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5131 // Now that the call site is handled, stop tracking it. 5132 MMI.setCurrentCallSite(0); 5133 } 5134 5135 // Both PendingLoads and PendingExports must be flushed here; 5136 // this call might not return. 5137 (void)getRoot(); 5138 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5139 } 5140 5141 // Check if target-independent constraints permit a tail call here. 5142 // Target-dependent constraints are checked within TLI.LowerCallTo. 5143 if (isTailCall && 5144 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5145 isTailCall = false; 5146 5147 // If there's a possibility that fast-isel has already selected some amount 5148 // of the current basic block, don't emit a tail call. 5149 if (isTailCall && EnableFastISel) 5150 isTailCall = false; 5151 5152 std::pair<SDValue,SDValue> Result = 5153 TLI.LowerCallTo(getRoot(), RetTy, 5154 CS.paramHasAttr(0, Attribute::SExt), 5155 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5156 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5157 CS.getCallingConv(), 5158 isTailCall, 5159 !CS.getInstruction()->use_empty(), 5160 Callee, Args, DAG, getCurDebugLoc()); 5161 assert((isTailCall || Result.second.getNode()) && 5162 "Non-null chain expected with non-tail call!"); 5163 assert((Result.second.getNode() || !Result.first.getNode()) && 5164 "Null value expected with tail call!"); 5165 if (Result.first.getNode()) { 5166 setValue(CS.getInstruction(), Result.first); 5167 } else if (!CanLowerReturn && Result.second.getNode()) { 5168 // The instruction result is the result of loading from the 5169 // hidden sret parameter. 5170 SmallVector<EVT, 1> PVTs; 5171 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5172 5173 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5174 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5175 EVT PtrVT = PVTs[0]; 5176 unsigned NumValues = Outs.size(); 5177 SmallVector<SDValue, 4> Values(NumValues); 5178 SmallVector<SDValue, 4> Chains(NumValues); 5179 5180 for (unsigned i = 0; i < NumValues; ++i) { 5181 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5182 DemoteStackSlot, 5183 DAG.getConstant(Offsets[i], PtrVT)); 5184 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5185 Add, 5186 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5187 false, false, 1); 5188 Values[i] = L; 5189 Chains[i] = L.getValue(1); 5190 } 5191 5192 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5193 MVT::Other, &Chains[0], NumValues); 5194 PendingLoads.push_back(Chain); 5195 5196 // Collect the legal value parts into potentially illegal values 5197 // that correspond to the original function's return values. 5198 SmallVector<EVT, 4> RetTys; 5199 RetTy = FTy->getReturnType(); 5200 ComputeValueVTs(TLI, RetTy, RetTys); 5201 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5202 SmallVector<SDValue, 4> ReturnValues; 5203 unsigned CurReg = 0; 5204 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5205 EVT VT = RetTys[I]; 5206 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5207 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5208 5209 SDValue ReturnValue = 5210 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5211 RegisterVT, VT, AssertOp); 5212 ReturnValues.push_back(ReturnValue); 5213 CurReg += NumRegs; 5214 } 5215 5216 setValue(CS.getInstruction(), 5217 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5218 DAG.getVTList(&RetTys[0], RetTys.size()), 5219 &ReturnValues[0], ReturnValues.size())); 5220 } 5221 5222 // Assign order to nodes here. If the call does not produce a result, it won't 5223 // be mapped to a SDNode and visit() will not assign it an order number. 5224 if (!Result.second.getNode()) { 5225 // As a special case, a null chain means that a tail call has been emitted and 5226 // the DAG root is already updated. 5227 HasTailCall = true; 5228 ++SDNodeOrder; 5229 AssignOrderingToNode(DAG.getRoot().getNode()); 5230 } else { 5231 DAG.setRoot(Result.second); 5232 ++SDNodeOrder; 5233 AssignOrderingToNode(Result.second.getNode()); 5234 } 5235 5236 if (LandingPad) { 5237 // Insert a label at the end of the invoke call to mark the try range. This 5238 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5239 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5240 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5241 5242 // Inform MachineModuleInfo of range. 5243 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5244 } 5245} 5246 5247/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5248/// value is equal or not-equal to zero. 5249static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5250 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5251 UI != E; ++UI) { 5252 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5253 if (IC->isEquality()) 5254 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5255 if (C->isNullValue()) 5256 continue; 5257 // Unknown instruction. 5258 return false; 5259 } 5260 return true; 5261} 5262 5263static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5264 Type *LoadTy, 5265 SelectionDAGBuilder &Builder) { 5266 5267 // Check to see if this load can be trivially constant folded, e.g. if the 5268 // input is from a string literal. 5269 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5270 // Cast pointer to the type we really want to load. 5271 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5272 PointerType::getUnqual(LoadTy)); 5273 5274 if (const Constant *LoadCst = 5275 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5276 Builder.TD)) 5277 return Builder.getValue(LoadCst); 5278 } 5279 5280 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5281 // still constant memory, the input chain can be the entry node. 5282 SDValue Root; 5283 bool ConstantMemory = false; 5284 5285 // Do not serialize (non-volatile) loads of constant memory with anything. 5286 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5287 Root = Builder.DAG.getEntryNode(); 5288 ConstantMemory = true; 5289 } else { 5290 // Do not serialize non-volatile loads against each other. 5291 Root = Builder.DAG.getRoot(); 5292 } 5293 5294 SDValue Ptr = Builder.getValue(PtrVal); 5295 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5296 Ptr, MachinePointerInfo(PtrVal), 5297 false /*volatile*/, 5298 false /*nontemporal*/, 1 /* align=1 */); 5299 5300 if (!ConstantMemory) 5301 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5302 return LoadVal; 5303} 5304 5305 5306/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5307/// If so, return true and lower it, otherwise return false and it will be 5308/// lowered like a normal call. 5309bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5310 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5311 if (I.getNumArgOperands() != 3) 5312 return false; 5313 5314 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5315 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5316 !I.getArgOperand(2)->getType()->isIntegerTy() || 5317 !I.getType()->isIntegerTy()) 5318 return false; 5319 5320 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5321 5322 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5323 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5324 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5325 bool ActuallyDoIt = true; 5326 MVT LoadVT; 5327 Type *LoadTy; 5328 switch (Size->getZExtValue()) { 5329 default: 5330 LoadVT = MVT::Other; 5331 LoadTy = 0; 5332 ActuallyDoIt = false; 5333 break; 5334 case 2: 5335 LoadVT = MVT::i16; 5336 LoadTy = Type::getInt16Ty(Size->getContext()); 5337 break; 5338 case 4: 5339 LoadVT = MVT::i32; 5340 LoadTy = Type::getInt32Ty(Size->getContext()); 5341 break; 5342 case 8: 5343 LoadVT = MVT::i64; 5344 LoadTy = Type::getInt64Ty(Size->getContext()); 5345 break; 5346 /* 5347 case 16: 5348 LoadVT = MVT::v4i32; 5349 LoadTy = Type::getInt32Ty(Size->getContext()); 5350 LoadTy = VectorType::get(LoadTy, 4); 5351 break; 5352 */ 5353 } 5354 5355 // This turns into unaligned loads. We only do this if the target natively 5356 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5357 // we'll only produce a small number of byte loads. 5358 5359 // Require that we can find a legal MVT, and only do this if the target 5360 // supports unaligned loads of that type. Expanding into byte loads would 5361 // bloat the code. 5362 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5363 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5364 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5365 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5366 ActuallyDoIt = false; 5367 } 5368 5369 if (ActuallyDoIt) { 5370 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5371 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5372 5373 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5374 ISD::SETNE); 5375 EVT CallVT = TLI.getValueType(I.getType(), true); 5376 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5377 return true; 5378 } 5379 } 5380 5381 5382 return false; 5383} 5384 5385 5386void SelectionDAGBuilder::visitCall(const CallInst &I) { 5387 // Handle inline assembly differently. 5388 if (isa<InlineAsm>(I.getCalledValue())) { 5389 visitInlineAsm(&I); 5390 return; 5391 } 5392 5393 // See if any floating point values are being passed to this function. This is 5394 // used to emit an undefined reference to fltused on Windows. 5395 FunctionType *FT = 5396 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5397 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5398 if (FT->isVarArg() && 5399 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5400 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5401 Type* T = I.getArgOperand(i)->getType(); 5402 for (po_iterator<Type*> i = po_begin(T), e = po_end(T); 5403 i != e; ++i) { 5404 if (!i->isFloatingPointTy()) continue; 5405 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5406 break; 5407 } 5408 } 5409 } 5410 5411 const char *RenameFn = 0; 5412 if (Function *F = I.getCalledFunction()) { 5413 if (F->isDeclaration()) { 5414 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5415 if (unsigned IID = II->getIntrinsicID(F)) { 5416 RenameFn = visitIntrinsicCall(I, IID); 5417 if (!RenameFn) 5418 return; 5419 } 5420 } 5421 if (unsigned IID = F->getIntrinsicID()) { 5422 RenameFn = visitIntrinsicCall(I, IID); 5423 if (!RenameFn) 5424 return; 5425 } 5426 } 5427 5428 // Check for well-known libc/libm calls. If the function is internal, it 5429 // can't be a library call. 5430 if (!F->hasLocalLinkage() && F->hasName()) { 5431 StringRef Name = F->getName(); 5432 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5433 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5434 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5435 I.getType() == I.getArgOperand(0)->getType() && 5436 I.getType() == I.getArgOperand(1)->getType()) { 5437 SDValue LHS = getValue(I.getArgOperand(0)); 5438 SDValue RHS = getValue(I.getArgOperand(1)); 5439 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5440 LHS.getValueType(), LHS, RHS)); 5441 return; 5442 } 5443 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5444 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5445 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5446 I.getType() == I.getArgOperand(0)->getType()) { 5447 SDValue Tmp = getValue(I.getArgOperand(0)); 5448 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5449 Tmp.getValueType(), Tmp)); 5450 return; 5451 } 5452 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5453 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5454 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5455 I.getType() == I.getArgOperand(0)->getType() && 5456 I.onlyReadsMemory()) { 5457 SDValue Tmp = getValue(I.getArgOperand(0)); 5458 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5459 Tmp.getValueType(), Tmp)); 5460 return; 5461 } 5462 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5463 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5464 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5465 I.getType() == I.getArgOperand(0)->getType() && 5466 I.onlyReadsMemory()) { 5467 SDValue Tmp = getValue(I.getArgOperand(0)); 5468 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5469 Tmp.getValueType(), Tmp)); 5470 return; 5471 } 5472 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5473 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5474 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5475 I.getType() == I.getArgOperand(0)->getType() && 5476 I.onlyReadsMemory()) { 5477 SDValue Tmp = getValue(I.getArgOperand(0)); 5478 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5479 Tmp.getValueType(), Tmp)); 5480 return; 5481 } 5482 } else if (Name == "memcmp") { 5483 if (visitMemCmpCall(I)) 5484 return; 5485 } 5486 } 5487 } 5488 5489 SDValue Callee; 5490 if (!RenameFn) 5491 Callee = getValue(I.getCalledValue()); 5492 else 5493 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5494 5495 // Check if we can potentially perform a tail call. More detailed checking is 5496 // be done within LowerCallTo, after more information about the call is known. 5497 LowerCallTo(&I, Callee, I.isTailCall()); 5498} 5499 5500namespace { 5501 5502/// AsmOperandInfo - This contains information for each constraint that we are 5503/// lowering. 5504class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5505public: 5506 /// CallOperand - If this is the result output operand or a clobber 5507 /// this is null, otherwise it is the incoming operand to the CallInst. 5508 /// This gets modified as the asm is processed. 5509 SDValue CallOperand; 5510 5511 /// AssignedRegs - If this is a register or register class operand, this 5512 /// contains the set of register corresponding to the operand. 5513 RegsForValue AssignedRegs; 5514 5515 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5516 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5517 } 5518 5519 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5520 /// busy in OutputRegs/InputRegs. 5521 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5522 std::set<unsigned> &OutputRegs, 5523 std::set<unsigned> &InputRegs, 5524 const TargetRegisterInfo &TRI) const { 5525 if (isOutReg) { 5526 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5527 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5528 } 5529 if (isInReg) { 5530 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5531 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5532 } 5533 } 5534 5535 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5536 /// corresponds to. If there is no Value* for this operand, it returns 5537 /// MVT::Other. 5538 EVT getCallOperandValEVT(LLVMContext &Context, 5539 const TargetLowering &TLI, 5540 const TargetData *TD) const { 5541 if (CallOperandVal == 0) return MVT::Other; 5542 5543 if (isa<BasicBlock>(CallOperandVal)) 5544 return TLI.getPointerTy(); 5545 5546 llvm::Type *OpTy = CallOperandVal->getType(); 5547 5548 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5549 // If this is an indirect operand, the operand is a pointer to the 5550 // accessed type. 5551 if (isIndirect) { 5552 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5553 if (!PtrTy) 5554 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5555 OpTy = PtrTy->getElementType(); 5556 } 5557 5558 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5559 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5560 if (STy->getNumElements() == 1) 5561 OpTy = STy->getElementType(0); 5562 5563 // If OpTy is not a single value, it may be a struct/union that we 5564 // can tile with integers. 5565 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5566 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5567 switch (BitSize) { 5568 default: break; 5569 case 1: 5570 case 8: 5571 case 16: 5572 case 32: 5573 case 64: 5574 case 128: 5575 OpTy = IntegerType::get(Context, BitSize); 5576 break; 5577 } 5578 } 5579 5580 return TLI.getValueType(OpTy, true); 5581 } 5582 5583private: 5584 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5585 /// specified set. 5586 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5587 const TargetRegisterInfo &TRI) { 5588 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5589 Regs.insert(Reg); 5590 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5591 for (; *Aliases; ++Aliases) 5592 Regs.insert(*Aliases); 5593 } 5594}; 5595 5596typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5597 5598} // end anonymous namespace 5599 5600/// GetRegistersForValue - Assign registers (virtual or physical) for the 5601/// specified operand. We prefer to assign virtual registers, to allow the 5602/// register allocator to handle the assignment process. However, if the asm 5603/// uses features that we can't model on machineinstrs, we have SDISel do the 5604/// allocation. This produces generally horrible, but correct, code. 5605/// 5606/// OpInfo describes the operand. 5607/// Input and OutputRegs are the set of already allocated physical registers. 5608/// 5609static void GetRegistersForValue(SelectionDAG &DAG, 5610 const TargetLowering &TLI, 5611 DebugLoc DL, 5612 SDISelAsmOperandInfo &OpInfo, 5613 std::set<unsigned> &OutputRegs, 5614 std::set<unsigned> &InputRegs) { 5615 LLVMContext &Context = *DAG.getContext(); 5616 5617 // Compute whether this value requires an input register, an output register, 5618 // or both. 5619 bool isOutReg = false; 5620 bool isInReg = false; 5621 switch (OpInfo.Type) { 5622 case InlineAsm::isOutput: 5623 isOutReg = true; 5624 5625 // If there is an input constraint that matches this, we need to reserve 5626 // the input register so no other inputs allocate to it. 5627 isInReg = OpInfo.hasMatchingInput(); 5628 break; 5629 case InlineAsm::isInput: 5630 isInReg = true; 5631 isOutReg = false; 5632 break; 5633 case InlineAsm::isClobber: 5634 isOutReg = true; 5635 isInReg = true; 5636 break; 5637 } 5638 5639 5640 MachineFunction &MF = DAG.getMachineFunction(); 5641 SmallVector<unsigned, 4> Regs; 5642 5643 // If this is a constraint for a single physreg, or a constraint for a 5644 // register class, find it. 5645 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5646 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5647 OpInfo.ConstraintVT); 5648 5649 unsigned NumRegs = 1; 5650 if (OpInfo.ConstraintVT != MVT::Other) { 5651 // If this is a FP input in an integer register (or visa versa) insert a bit 5652 // cast of the input value. More generally, handle any case where the input 5653 // value disagrees with the register class we plan to stick this in. 5654 if (OpInfo.Type == InlineAsm::isInput && 5655 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5656 // Try to convert to the first EVT that the reg class contains. If the 5657 // types are identical size, use a bitcast to convert (e.g. two differing 5658 // vector types). 5659 EVT RegVT = *PhysReg.second->vt_begin(); 5660 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5661 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5662 RegVT, OpInfo.CallOperand); 5663 OpInfo.ConstraintVT = RegVT; 5664 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5665 // If the input is a FP value and we want it in FP registers, do a 5666 // bitcast to the corresponding integer type. This turns an f64 value 5667 // into i64, which can be passed with two i32 values on a 32-bit 5668 // machine. 5669 RegVT = EVT::getIntegerVT(Context, 5670 OpInfo.ConstraintVT.getSizeInBits()); 5671 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5672 RegVT, OpInfo.CallOperand); 5673 OpInfo.ConstraintVT = RegVT; 5674 } 5675 } 5676 5677 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5678 } 5679 5680 EVT RegVT; 5681 EVT ValueVT = OpInfo.ConstraintVT; 5682 5683 // If this is a constraint for a specific physical register, like {r17}, 5684 // assign it now. 5685 if (unsigned AssignedReg = PhysReg.first) { 5686 const TargetRegisterClass *RC = PhysReg.second; 5687 if (OpInfo.ConstraintVT == MVT::Other) 5688 ValueVT = *RC->vt_begin(); 5689 5690 // Get the actual register value type. This is important, because the user 5691 // may have asked for (e.g.) the AX register in i32 type. We need to 5692 // remember that AX is actually i16 to get the right extension. 5693 RegVT = *RC->vt_begin(); 5694 5695 // This is a explicit reference to a physical register. 5696 Regs.push_back(AssignedReg); 5697 5698 // If this is an expanded reference, add the rest of the regs to Regs. 5699 if (NumRegs != 1) { 5700 TargetRegisterClass::iterator I = RC->begin(); 5701 for (; *I != AssignedReg; ++I) 5702 assert(I != RC->end() && "Didn't find reg!"); 5703 5704 // Already added the first reg. 5705 --NumRegs; ++I; 5706 for (; NumRegs; --NumRegs, ++I) { 5707 assert(I != RC->end() && "Ran out of registers to allocate!"); 5708 Regs.push_back(*I); 5709 } 5710 } 5711 5712 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5713 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5714 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5715 return; 5716 } 5717 5718 // Otherwise, if this was a reference to an LLVM register class, create vregs 5719 // for this reference. 5720 if (const TargetRegisterClass *RC = PhysReg.second) { 5721 RegVT = *RC->vt_begin(); 5722 if (OpInfo.ConstraintVT == MVT::Other) 5723 ValueVT = RegVT; 5724 5725 // Create the appropriate number of virtual registers. 5726 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5727 for (; NumRegs; --NumRegs) 5728 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5729 5730 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5731 return; 5732 } 5733 5734 // Otherwise, we couldn't allocate enough registers for this. 5735} 5736 5737/// visitInlineAsm - Handle a call to an InlineAsm object. 5738/// 5739void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5740 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5741 5742 /// ConstraintOperands - Information about all of the constraints. 5743 SDISelAsmOperandInfoVector ConstraintOperands; 5744 5745 std::set<unsigned> OutputRegs, InputRegs; 5746 5747 TargetLowering::AsmOperandInfoVector 5748 TargetConstraints = TLI.ParseConstraints(CS); 5749 5750 bool hasMemory = false; 5751 5752 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5753 unsigned ResNo = 0; // ResNo - The result number of the next output. 5754 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5755 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5756 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5757 5758 EVT OpVT = MVT::Other; 5759 5760 // Compute the value type for each operand. 5761 switch (OpInfo.Type) { 5762 case InlineAsm::isOutput: 5763 // Indirect outputs just consume an argument. 5764 if (OpInfo.isIndirect) { 5765 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5766 break; 5767 } 5768 5769 // The return value of the call is this value. As such, there is no 5770 // corresponding argument. 5771 assert(!CS.getType()->isVoidTy() && 5772 "Bad inline asm!"); 5773 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5774 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5775 } else { 5776 assert(ResNo == 0 && "Asm only has one result!"); 5777 OpVT = TLI.getValueType(CS.getType()); 5778 } 5779 ++ResNo; 5780 break; 5781 case InlineAsm::isInput: 5782 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5783 break; 5784 case InlineAsm::isClobber: 5785 // Nothing to do. 5786 break; 5787 } 5788 5789 // If this is an input or an indirect output, process the call argument. 5790 // BasicBlocks are labels, currently appearing only in asm's. 5791 if (OpInfo.CallOperandVal) { 5792 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5793 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5794 } else { 5795 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5796 } 5797 5798 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5799 } 5800 5801 OpInfo.ConstraintVT = OpVT; 5802 5803 // Indirect operand accesses access memory. 5804 if (OpInfo.isIndirect) 5805 hasMemory = true; 5806 else { 5807 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5808 TargetLowering::ConstraintType 5809 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5810 if (CType == TargetLowering::C_Memory) { 5811 hasMemory = true; 5812 break; 5813 } 5814 } 5815 } 5816 } 5817 5818 SDValue Chain, Flag; 5819 5820 // We won't need to flush pending loads if this asm doesn't touch 5821 // memory and is nonvolatile. 5822 if (hasMemory || IA->hasSideEffects()) 5823 Chain = getRoot(); 5824 else 5825 Chain = DAG.getRoot(); 5826 5827 // Second pass over the constraints: compute which constraint option to use 5828 // and assign registers to constraints that want a specific physreg. 5829 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5830 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5831 5832 // If this is an output operand with a matching input operand, look up the 5833 // matching input. If their types mismatch, e.g. one is an integer, the 5834 // other is floating point, or their sizes are different, flag it as an 5835 // error. 5836 if (OpInfo.hasMatchingInput()) { 5837 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5838 5839 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5840 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5841 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); 5842 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5843 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT); 5844 if ((OpInfo.ConstraintVT.isInteger() != 5845 Input.ConstraintVT.isInteger()) || 5846 (MatchRC.second != InputRC.second)) { 5847 report_fatal_error("Unsupported asm: input constraint" 5848 " with a matching output constraint of" 5849 " incompatible type!"); 5850 } 5851 Input.ConstraintVT = OpInfo.ConstraintVT; 5852 } 5853 } 5854 5855 // Compute the constraint code and ConstraintType to use. 5856 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5857 5858 // If this is a memory input, and if the operand is not indirect, do what we 5859 // need to to provide an address for the memory input. 5860 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5861 !OpInfo.isIndirect) { 5862 assert((OpInfo.isMultipleAlternative || 5863 (OpInfo.Type == InlineAsm::isInput)) && 5864 "Can only indirectify direct input operands!"); 5865 5866 // Memory operands really want the address of the value. If we don't have 5867 // an indirect input, put it in the constpool if we can, otherwise spill 5868 // it to a stack slot. 5869 // TODO: This isn't quite right. We need to handle these according to 5870 // the addressing mode that the constraint wants. Also, this may take 5871 // an additional register for the computation and we don't want that 5872 // either. 5873 5874 // If the operand is a float, integer, or vector constant, spill to a 5875 // constant pool entry to get its address. 5876 const Value *OpVal = OpInfo.CallOperandVal; 5877 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5878 isa<ConstantVector>(OpVal)) { 5879 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5880 TLI.getPointerTy()); 5881 } else { 5882 // Otherwise, create a stack slot and emit a store to it before the 5883 // asm. 5884 Type *Ty = OpVal->getType(); 5885 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5886 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5887 MachineFunction &MF = DAG.getMachineFunction(); 5888 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5889 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5890 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5891 OpInfo.CallOperand, StackSlot, 5892 MachinePointerInfo::getFixedStack(SSFI), 5893 false, false, 0); 5894 OpInfo.CallOperand = StackSlot; 5895 } 5896 5897 // There is no longer a Value* corresponding to this operand. 5898 OpInfo.CallOperandVal = 0; 5899 5900 // It is now an indirect operand. 5901 OpInfo.isIndirect = true; 5902 } 5903 5904 // If this constraint is for a specific register, allocate it before 5905 // anything else. 5906 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5907 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5908 InputRegs); 5909 } 5910 5911 // Second pass - Loop over all of the operands, assigning virtual or physregs 5912 // to register class operands. 5913 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5914 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5915 5916 // C_Register operands have already been allocated, Other/Memory don't need 5917 // to be. 5918 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5919 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5920 InputRegs); 5921 } 5922 5923 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5924 std::vector<SDValue> AsmNodeOperands; 5925 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5926 AsmNodeOperands.push_back( 5927 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5928 TLI.getPointerTy())); 5929 5930 // If we have a !srcloc metadata node associated with it, we want to attach 5931 // this to the ultimately generated inline asm machineinstr. To do this, we 5932 // pass in the third operand as this (potentially null) inline asm MDNode. 5933 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5934 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5935 5936 // Remember the HasSideEffect and AlignStack bits as operand 3. 5937 unsigned ExtraInfo = 0; 5938 if (IA->hasSideEffects()) 5939 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 5940 if (IA->isAlignStack()) 5941 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 5942 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 5943 TLI.getPointerTy())); 5944 5945 // Loop over all of the inputs, copying the operand values into the 5946 // appropriate registers and processing the output regs. 5947 RegsForValue RetValRegs; 5948 5949 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5950 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5951 5952 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5953 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5954 5955 switch (OpInfo.Type) { 5956 case InlineAsm::isOutput: { 5957 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5958 OpInfo.ConstraintType != TargetLowering::C_Register) { 5959 // Memory output, or 'other' output (e.g. 'X' constraint). 5960 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5961 5962 // Add information to the INLINEASM node to know about this output. 5963 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5964 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5965 TLI.getPointerTy())); 5966 AsmNodeOperands.push_back(OpInfo.CallOperand); 5967 break; 5968 } 5969 5970 // Otherwise, this is a register or register class output. 5971 5972 // Copy the output from the appropriate register. Find a register that 5973 // we can use. 5974 if (OpInfo.AssignedRegs.Regs.empty()) 5975 report_fatal_error("Couldn't allocate output reg for constraint '" + 5976 Twine(OpInfo.ConstraintCode) + "'!"); 5977 5978 // If this is an indirect operand, store through the pointer after the 5979 // asm. 5980 if (OpInfo.isIndirect) { 5981 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5982 OpInfo.CallOperandVal)); 5983 } else { 5984 // This is the result value of the call. 5985 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5986 // Concatenate this output onto the outputs list. 5987 RetValRegs.append(OpInfo.AssignedRegs); 5988 } 5989 5990 // Add information to the INLINEASM node to know that this register is 5991 // set. 5992 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5993 InlineAsm::Kind_RegDefEarlyClobber : 5994 InlineAsm::Kind_RegDef, 5995 false, 5996 0, 5997 DAG, 5998 AsmNodeOperands); 5999 break; 6000 } 6001 case InlineAsm::isInput: { 6002 SDValue InOperandVal = OpInfo.CallOperand; 6003 6004 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6005 // If this is required to match an output register we have already set, 6006 // just use its register. 6007 unsigned OperandNo = OpInfo.getMatchedOperand(); 6008 6009 // Scan until we find the definition we already emitted of this operand. 6010 // When we find it, create a RegsForValue operand. 6011 unsigned CurOp = InlineAsm::Op_FirstOperand; 6012 for (; OperandNo; --OperandNo) { 6013 // Advance to the next operand. 6014 unsigned OpFlag = 6015 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6016 assert((InlineAsm::isRegDefKind(OpFlag) || 6017 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6018 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6019 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6020 } 6021 6022 unsigned OpFlag = 6023 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6024 if (InlineAsm::isRegDefKind(OpFlag) || 6025 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6026 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6027 if (OpInfo.isIndirect) { 6028 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6029 LLVMContext &Ctx = *DAG.getContext(); 6030 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6031 " don't know how to handle tied " 6032 "indirect register inputs"); 6033 } 6034 6035 RegsForValue MatchedRegs; 6036 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6037 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6038 MatchedRegs.RegVTs.push_back(RegVT); 6039 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6040 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6041 i != e; ++i) 6042 MatchedRegs.Regs.push_back 6043 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6044 6045 // Use the produced MatchedRegs object to 6046 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6047 Chain, &Flag); 6048 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6049 true, OpInfo.getMatchedOperand(), 6050 DAG, AsmNodeOperands); 6051 break; 6052 } 6053 6054 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6055 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6056 "Unexpected number of operands"); 6057 // Add information to the INLINEASM node to know about this input. 6058 // See InlineAsm.h isUseOperandTiedToDef. 6059 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6060 OpInfo.getMatchedOperand()); 6061 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6062 TLI.getPointerTy())); 6063 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6064 break; 6065 } 6066 6067 // Treat indirect 'X' constraint as memory. 6068 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6069 OpInfo.isIndirect) 6070 OpInfo.ConstraintType = TargetLowering::C_Memory; 6071 6072 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6073 std::vector<SDValue> Ops; 6074 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6075 Ops, DAG); 6076 if (Ops.empty()) 6077 report_fatal_error("Invalid operand for inline asm constraint '" + 6078 Twine(OpInfo.ConstraintCode) + "'!"); 6079 6080 // Add information to the INLINEASM node to know about this input. 6081 unsigned ResOpType = 6082 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6083 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6084 TLI.getPointerTy())); 6085 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6086 break; 6087 } 6088 6089 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6090 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6091 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6092 "Memory operands expect pointer values"); 6093 6094 // Add information to the INLINEASM node to know about this input. 6095 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6096 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6097 TLI.getPointerTy())); 6098 AsmNodeOperands.push_back(InOperandVal); 6099 break; 6100 } 6101 6102 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6103 OpInfo.ConstraintType == TargetLowering::C_Register) && 6104 "Unknown constraint type!"); 6105 assert(!OpInfo.isIndirect && 6106 "Don't know how to handle indirect register inputs yet!"); 6107 6108 // Copy the input into the appropriate registers. 6109 if (OpInfo.AssignedRegs.Regs.empty()) 6110 report_fatal_error("Couldn't allocate input reg for constraint '" + 6111 Twine(OpInfo.ConstraintCode) + "'!"); 6112 6113 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6114 Chain, &Flag); 6115 6116 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6117 DAG, AsmNodeOperands); 6118 break; 6119 } 6120 case InlineAsm::isClobber: { 6121 // Add the clobbered value to the operand list, so that the register 6122 // allocator is aware that the physreg got clobbered. 6123 if (!OpInfo.AssignedRegs.Regs.empty()) 6124 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6125 false, 0, DAG, 6126 AsmNodeOperands); 6127 break; 6128 } 6129 } 6130 } 6131 6132 // Finish up input operands. Set the input chain and add the flag last. 6133 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6134 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6135 6136 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6137 DAG.getVTList(MVT::Other, MVT::Glue), 6138 &AsmNodeOperands[0], AsmNodeOperands.size()); 6139 Flag = Chain.getValue(1); 6140 6141 // If this asm returns a register value, copy the result from that register 6142 // and set it as the value of the call. 6143 if (!RetValRegs.Regs.empty()) { 6144 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6145 Chain, &Flag); 6146 6147 // FIXME: Why don't we do this for inline asms with MRVs? 6148 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6149 EVT ResultType = TLI.getValueType(CS.getType()); 6150 6151 // If any of the results of the inline asm is a vector, it may have the 6152 // wrong width/num elts. This can happen for register classes that can 6153 // contain multiple different value types. The preg or vreg allocated may 6154 // not have the same VT as was expected. Convert it to the right type 6155 // with bit_convert. 6156 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6157 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6158 ResultType, Val); 6159 6160 } else if (ResultType != Val.getValueType() && 6161 ResultType.isInteger() && Val.getValueType().isInteger()) { 6162 // If a result value was tied to an input value, the computed result may 6163 // have a wider width than the expected result. Extract the relevant 6164 // portion. 6165 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6166 } 6167 6168 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6169 } 6170 6171 setValue(CS.getInstruction(), Val); 6172 // Don't need to use this as a chain in this case. 6173 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6174 return; 6175 } 6176 6177 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6178 6179 // Process indirect outputs, first output all of the flagged copies out of 6180 // physregs. 6181 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6182 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6183 const Value *Ptr = IndirectStoresToEmit[i].second; 6184 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6185 Chain, &Flag); 6186 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6187 } 6188 6189 // Emit the non-flagged stores from the physregs. 6190 SmallVector<SDValue, 8> OutChains; 6191 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6192 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6193 StoresToEmit[i].first, 6194 getValue(StoresToEmit[i].second), 6195 MachinePointerInfo(StoresToEmit[i].second), 6196 false, false, 0); 6197 OutChains.push_back(Val); 6198 } 6199 6200 if (!OutChains.empty()) 6201 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6202 &OutChains[0], OutChains.size()); 6203 6204 DAG.setRoot(Chain); 6205} 6206 6207void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6208 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6209 MVT::Other, getRoot(), 6210 getValue(I.getArgOperand(0)), 6211 DAG.getSrcValue(I.getArgOperand(0)))); 6212} 6213 6214void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6215 const TargetData &TD = *TLI.getTargetData(); 6216 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6217 getRoot(), getValue(I.getOperand(0)), 6218 DAG.getSrcValue(I.getOperand(0)), 6219 TD.getABITypeAlignment(I.getType())); 6220 setValue(&I, V); 6221 DAG.setRoot(V.getValue(1)); 6222} 6223 6224void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6225 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6226 MVT::Other, getRoot(), 6227 getValue(I.getArgOperand(0)), 6228 DAG.getSrcValue(I.getArgOperand(0)))); 6229} 6230 6231void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6232 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6233 MVT::Other, getRoot(), 6234 getValue(I.getArgOperand(0)), 6235 getValue(I.getArgOperand(1)), 6236 DAG.getSrcValue(I.getArgOperand(0)), 6237 DAG.getSrcValue(I.getArgOperand(1)))); 6238} 6239 6240/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6241/// implementation, which just calls LowerCall. 6242/// FIXME: When all targets are 6243/// migrated to using LowerCall, this hook should be integrated into SDISel. 6244std::pair<SDValue, SDValue> 6245TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6246 bool RetSExt, bool RetZExt, bool isVarArg, 6247 bool isInreg, unsigned NumFixedArgs, 6248 CallingConv::ID CallConv, bool isTailCall, 6249 bool isReturnValueUsed, 6250 SDValue Callee, 6251 ArgListTy &Args, SelectionDAG &DAG, 6252 DebugLoc dl) const { 6253 // Handle all of the outgoing arguments. 6254 SmallVector<ISD::OutputArg, 32> Outs; 6255 SmallVector<SDValue, 32> OutVals; 6256 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6257 SmallVector<EVT, 4> ValueVTs; 6258 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6259 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6260 Value != NumValues; ++Value) { 6261 EVT VT = ValueVTs[Value]; 6262 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6263 SDValue Op = SDValue(Args[i].Node.getNode(), 6264 Args[i].Node.getResNo() + Value); 6265 ISD::ArgFlagsTy Flags; 6266 unsigned OriginalAlignment = 6267 getTargetData()->getABITypeAlignment(ArgTy); 6268 6269 if (Args[i].isZExt) 6270 Flags.setZExt(); 6271 if (Args[i].isSExt) 6272 Flags.setSExt(); 6273 if (Args[i].isInReg) 6274 Flags.setInReg(); 6275 if (Args[i].isSRet) 6276 Flags.setSRet(); 6277 if (Args[i].isByVal) { 6278 Flags.setByVal(); 6279 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6280 Type *ElementTy = Ty->getElementType(); 6281 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6282 // For ByVal, alignment should come from FE. BE will guess if this 6283 // info is not there but there are cases it cannot get right. 6284 unsigned FrameAlign; 6285 if (Args[i].Alignment) 6286 FrameAlign = Args[i].Alignment; 6287 else 6288 FrameAlign = getByValTypeAlignment(ElementTy); 6289 Flags.setByValAlign(FrameAlign); 6290 } 6291 if (Args[i].isNest) 6292 Flags.setNest(); 6293 Flags.setOrigAlign(OriginalAlignment); 6294 6295 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6296 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6297 SmallVector<SDValue, 4> Parts(NumParts); 6298 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6299 6300 if (Args[i].isSExt) 6301 ExtendKind = ISD::SIGN_EXTEND; 6302 else if (Args[i].isZExt) 6303 ExtendKind = ISD::ZERO_EXTEND; 6304 6305 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6306 PartVT, ExtendKind); 6307 6308 for (unsigned j = 0; j != NumParts; ++j) { 6309 // if it isn't first piece, alignment must be 1 6310 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6311 i < NumFixedArgs); 6312 if (NumParts > 1 && j == 0) 6313 MyFlags.Flags.setSplit(); 6314 else if (j != 0) 6315 MyFlags.Flags.setOrigAlign(1); 6316 6317 Outs.push_back(MyFlags); 6318 OutVals.push_back(Parts[j]); 6319 } 6320 } 6321 } 6322 6323 // Handle the incoming return values from the call. 6324 SmallVector<ISD::InputArg, 32> Ins; 6325 SmallVector<EVT, 4> RetTys; 6326 ComputeValueVTs(*this, RetTy, RetTys); 6327 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6328 EVT VT = RetTys[I]; 6329 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6330 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6331 for (unsigned i = 0; i != NumRegs; ++i) { 6332 ISD::InputArg MyFlags; 6333 MyFlags.VT = RegisterVT.getSimpleVT(); 6334 MyFlags.Used = isReturnValueUsed; 6335 if (RetSExt) 6336 MyFlags.Flags.setSExt(); 6337 if (RetZExt) 6338 MyFlags.Flags.setZExt(); 6339 if (isInreg) 6340 MyFlags.Flags.setInReg(); 6341 Ins.push_back(MyFlags); 6342 } 6343 } 6344 6345 SmallVector<SDValue, 4> InVals; 6346 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6347 Outs, OutVals, Ins, dl, DAG, InVals); 6348 6349 // Verify that the target's LowerCall behaved as expected. 6350 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6351 "LowerCall didn't return a valid chain!"); 6352 assert((!isTailCall || InVals.empty()) && 6353 "LowerCall emitted a return value for a tail call!"); 6354 assert((isTailCall || InVals.size() == Ins.size()) && 6355 "LowerCall didn't emit the correct number of values!"); 6356 6357 // For a tail call, the return value is merely live-out and there aren't 6358 // any nodes in the DAG representing it. Return a special value to 6359 // indicate that a tail call has been emitted and no more Instructions 6360 // should be processed in the current block. 6361 if (isTailCall) { 6362 DAG.setRoot(Chain); 6363 return std::make_pair(SDValue(), SDValue()); 6364 } 6365 6366 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6367 assert(InVals[i].getNode() && 6368 "LowerCall emitted a null value!"); 6369 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6370 "LowerCall emitted a value with the wrong type!"); 6371 }); 6372 6373 // Collect the legal value parts into potentially illegal values 6374 // that correspond to the original function's return values. 6375 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6376 if (RetSExt) 6377 AssertOp = ISD::AssertSext; 6378 else if (RetZExt) 6379 AssertOp = ISD::AssertZext; 6380 SmallVector<SDValue, 4> ReturnValues; 6381 unsigned CurReg = 0; 6382 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6383 EVT VT = RetTys[I]; 6384 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6385 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6386 6387 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6388 NumRegs, RegisterVT, VT, 6389 AssertOp)); 6390 CurReg += NumRegs; 6391 } 6392 6393 // For a function returning void, there is no return value. We can't create 6394 // such a node, so we just return a null return value in that case. In 6395 // that case, nothing will actually look at the value. 6396 if (ReturnValues.empty()) 6397 return std::make_pair(SDValue(), Chain); 6398 6399 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6400 DAG.getVTList(&RetTys[0], RetTys.size()), 6401 &ReturnValues[0], ReturnValues.size()); 6402 return std::make_pair(Res, Chain); 6403} 6404 6405void TargetLowering::LowerOperationWrapper(SDNode *N, 6406 SmallVectorImpl<SDValue> &Results, 6407 SelectionDAG &DAG) const { 6408 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6409 if (Res.getNode()) 6410 Results.push_back(Res); 6411} 6412 6413SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6414 llvm_unreachable("LowerOperation not implemented for this target!"); 6415 return SDValue(); 6416} 6417 6418void 6419SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6420 SDValue Op = getNonRegisterValue(V); 6421 assert((Op.getOpcode() != ISD::CopyFromReg || 6422 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6423 "Copy from a reg to the same reg!"); 6424 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6425 6426 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6427 SDValue Chain = DAG.getEntryNode(); 6428 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6429 PendingExports.push_back(Chain); 6430} 6431 6432#include "llvm/CodeGen/SelectionDAGISel.h" 6433 6434/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6435/// entry block, return true. This includes arguments used by switches, since 6436/// the switch may expand into multiple basic blocks. 6437static bool isOnlyUsedInEntryBlock(const Argument *A) { 6438 // With FastISel active, we may be splitting blocks, so force creation 6439 // of virtual registers for all non-dead arguments. 6440 if (EnableFastISel) 6441 return A->use_empty(); 6442 6443 const BasicBlock *Entry = A->getParent()->begin(); 6444 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6445 UI != E; ++UI) { 6446 const User *U = *UI; 6447 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6448 return false; // Use not in entry block. 6449 } 6450 return true; 6451} 6452 6453void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6454 // If this is the entry block, emit arguments. 6455 const Function &F = *LLVMBB->getParent(); 6456 SelectionDAG &DAG = SDB->DAG; 6457 DebugLoc dl = SDB->getCurDebugLoc(); 6458 const TargetData *TD = TLI.getTargetData(); 6459 SmallVector<ISD::InputArg, 16> Ins; 6460 6461 // Check whether the function can return without sret-demotion. 6462 SmallVector<ISD::OutputArg, 4> Outs; 6463 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6464 Outs, TLI); 6465 6466 if (!FuncInfo->CanLowerReturn) { 6467 // Put in an sret pointer parameter before all the other parameters. 6468 SmallVector<EVT, 1> ValueVTs; 6469 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6470 6471 // NOTE: Assuming that a pointer will never break down to more than one VT 6472 // or one register. 6473 ISD::ArgFlagsTy Flags; 6474 Flags.setSRet(); 6475 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6476 ISD::InputArg RetArg(Flags, RegisterVT, true); 6477 Ins.push_back(RetArg); 6478 } 6479 6480 // Set up the incoming argument description vector. 6481 unsigned Idx = 1; 6482 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6483 I != E; ++I, ++Idx) { 6484 SmallVector<EVT, 4> ValueVTs; 6485 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6486 bool isArgValueUsed = !I->use_empty(); 6487 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6488 Value != NumValues; ++Value) { 6489 EVT VT = ValueVTs[Value]; 6490 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6491 ISD::ArgFlagsTy Flags; 6492 unsigned OriginalAlignment = 6493 TD->getABITypeAlignment(ArgTy); 6494 6495 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6496 Flags.setZExt(); 6497 if (F.paramHasAttr(Idx, Attribute::SExt)) 6498 Flags.setSExt(); 6499 if (F.paramHasAttr(Idx, Attribute::InReg)) 6500 Flags.setInReg(); 6501 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6502 Flags.setSRet(); 6503 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6504 Flags.setByVal(); 6505 PointerType *Ty = cast<PointerType>(I->getType()); 6506 Type *ElementTy = Ty->getElementType(); 6507 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6508 // For ByVal, alignment should be passed from FE. BE will guess if 6509 // this info is not there but there are cases it cannot get right. 6510 unsigned FrameAlign; 6511 if (F.getParamAlignment(Idx)) 6512 FrameAlign = F.getParamAlignment(Idx); 6513 else 6514 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6515 Flags.setByValAlign(FrameAlign); 6516 } 6517 if (F.paramHasAttr(Idx, Attribute::Nest)) 6518 Flags.setNest(); 6519 Flags.setOrigAlign(OriginalAlignment); 6520 6521 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6522 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6523 for (unsigned i = 0; i != NumRegs; ++i) { 6524 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6525 if (NumRegs > 1 && i == 0) 6526 MyFlags.Flags.setSplit(); 6527 // if it isn't first piece, alignment must be 1 6528 else if (i > 0) 6529 MyFlags.Flags.setOrigAlign(1); 6530 Ins.push_back(MyFlags); 6531 } 6532 } 6533 } 6534 6535 // Call the target to set up the argument values. 6536 SmallVector<SDValue, 8> InVals; 6537 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6538 F.isVarArg(), Ins, 6539 dl, DAG, InVals); 6540 6541 // Verify that the target's LowerFormalArguments behaved as expected. 6542 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6543 "LowerFormalArguments didn't return a valid chain!"); 6544 assert(InVals.size() == Ins.size() && 6545 "LowerFormalArguments didn't emit the correct number of values!"); 6546 DEBUG({ 6547 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6548 assert(InVals[i].getNode() && 6549 "LowerFormalArguments emitted a null value!"); 6550 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6551 "LowerFormalArguments emitted a value with the wrong type!"); 6552 } 6553 }); 6554 6555 // Update the DAG with the new chain value resulting from argument lowering. 6556 DAG.setRoot(NewRoot); 6557 6558 // Set up the argument values. 6559 unsigned i = 0; 6560 Idx = 1; 6561 if (!FuncInfo->CanLowerReturn) { 6562 // Create a virtual register for the sret pointer, and put in a copy 6563 // from the sret argument into it. 6564 SmallVector<EVT, 1> ValueVTs; 6565 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6566 EVT VT = ValueVTs[0]; 6567 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6568 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6569 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6570 RegVT, VT, AssertOp); 6571 6572 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6573 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6574 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6575 FuncInfo->DemoteRegister = SRetReg; 6576 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6577 SRetReg, ArgValue); 6578 DAG.setRoot(NewRoot); 6579 6580 // i indexes lowered arguments. Bump it past the hidden sret argument. 6581 // Idx indexes LLVM arguments. Don't touch it. 6582 ++i; 6583 } 6584 6585 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6586 ++I, ++Idx) { 6587 SmallVector<SDValue, 4> ArgValues; 6588 SmallVector<EVT, 4> ValueVTs; 6589 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6590 unsigned NumValues = ValueVTs.size(); 6591 6592 // If this argument is unused then remember its value. It is used to generate 6593 // debugging information. 6594 if (I->use_empty() && NumValues) 6595 SDB->setUnusedArgValue(I, InVals[i]); 6596 6597 for (unsigned Val = 0; Val != NumValues; ++Val) { 6598 EVT VT = ValueVTs[Val]; 6599 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6600 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6601 6602 if (!I->use_empty()) { 6603 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6604 if (F.paramHasAttr(Idx, Attribute::SExt)) 6605 AssertOp = ISD::AssertSext; 6606 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6607 AssertOp = ISD::AssertZext; 6608 6609 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6610 NumParts, PartVT, VT, 6611 AssertOp)); 6612 } 6613 6614 i += NumParts; 6615 } 6616 6617 // We don't need to do anything else for unused arguments. 6618 if (ArgValues.empty()) 6619 continue; 6620 6621 // Note down frame index for byval arguments. 6622 if (I->hasByValAttr()) 6623 if (FrameIndexSDNode *FI = 6624 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6625 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6626 6627 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6628 SDB->getCurDebugLoc()); 6629 SDB->setValue(I, Res); 6630 6631 // If this argument is live outside of the entry block, insert a copy from 6632 // wherever we got it to the vreg that other BB's will reference it as. 6633 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6634 // If we can, though, try to skip creating an unnecessary vreg. 6635 // FIXME: This isn't very clean... it would be nice to make this more 6636 // general. It's also subtly incompatible with the hacks FastISel 6637 // uses with vregs. 6638 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6639 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6640 FuncInfo->ValueMap[I] = Reg; 6641 continue; 6642 } 6643 } 6644 if (!isOnlyUsedInEntryBlock(I)) { 6645 FuncInfo->InitializeRegForValue(I); 6646 SDB->CopyToExportRegsIfNeeded(I); 6647 } 6648 } 6649 6650 assert(i == InVals.size() && "Argument register count mismatch!"); 6651 6652 // Finally, if the target has anything special to do, allow it to do so. 6653 // FIXME: this should insert code into the DAG! 6654 EmitFunctionEntryCode(); 6655} 6656 6657/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6658/// ensure constants are generated when needed. Remember the virtual registers 6659/// that need to be added to the Machine PHI nodes as input. We cannot just 6660/// directly add them, because expansion might result in multiple MBB's for one 6661/// BB. As such, the start of the BB might correspond to a different MBB than 6662/// the end. 6663/// 6664void 6665SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6666 const TerminatorInst *TI = LLVMBB->getTerminator(); 6667 6668 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6669 6670 // Check successor nodes' PHI nodes that expect a constant to be available 6671 // from this block. 6672 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6673 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6674 if (!isa<PHINode>(SuccBB->begin())) continue; 6675 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6676 6677 // If this terminator has multiple identical successors (common for 6678 // switches), only handle each succ once. 6679 if (!SuccsHandled.insert(SuccMBB)) continue; 6680 6681 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6682 6683 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6684 // nodes and Machine PHI nodes, but the incoming operands have not been 6685 // emitted yet. 6686 for (BasicBlock::const_iterator I = SuccBB->begin(); 6687 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6688 // Ignore dead phi's. 6689 if (PN->use_empty()) continue; 6690 6691 // Skip empty types 6692 if (PN->getType()->isEmptyTy()) 6693 continue; 6694 6695 unsigned Reg; 6696 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6697 6698 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6699 unsigned &RegOut = ConstantsOut[C]; 6700 if (RegOut == 0) { 6701 RegOut = FuncInfo.CreateRegs(C->getType()); 6702 CopyValueToVirtualRegister(C, RegOut); 6703 } 6704 Reg = RegOut; 6705 } else { 6706 DenseMap<const Value *, unsigned>::iterator I = 6707 FuncInfo.ValueMap.find(PHIOp); 6708 if (I != FuncInfo.ValueMap.end()) 6709 Reg = I->second; 6710 else { 6711 assert(isa<AllocaInst>(PHIOp) && 6712 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6713 "Didn't codegen value into a register!??"); 6714 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6715 CopyValueToVirtualRegister(PHIOp, Reg); 6716 } 6717 } 6718 6719 // Remember that this register needs to added to the machine PHI node as 6720 // the input for this MBB. 6721 SmallVector<EVT, 4> ValueVTs; 6722 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6723 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6724 EVT VT = ValueVTs[vti]; 6725 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6726 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6727 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6728 Reg += NumRegisters; 6729 } 6730 } 6731 } 6732 ConstantsOut.clear(); 6733} 6734