SelectionDAGBuilder.cpp revision c3ab388ba9574eb93c44ed57ea46acd4f623b5dc
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getIntPtrConstant(1)); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209 return SDValue(); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert(PartVT.isInteger() && ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 } 361 } else if (PartBits == ValueVT.getSizeInBits()) { 362 // Different types of the same size. 363 assert(NumParts == 1 && PartVT != ValueVT); 364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 366 // If the parts cover less bits than value has, truncate the value. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Unknown mismatch!"); 369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 371 } 372 373 // The value may have changed - recompute ValueVT. 374 ValueVT = Val.getValueType(); 375 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 376 "Failed to tile the value with PartVT!"); 377 378 if (NumParts == 1) { 379 assert(PartVT == ValueVT && "Type conversion failed!"); 380 Parts[0] = Val; 381 return; 382 } 383 384 // Expand the value into multiple parts. 385 if (NumParts & (NumParts - 1)) { 386 // The number of parts is not a power of 2. Split off and copy the tail. 387 assert(PartVT.isInteger() && ValueVT.isInteger() && 388 "Do not know what to expand to!"); 389 unsigned RoundParts = 1 << Log2_32(NumParts); 390 unsigned RoundBits = RoundParts * PartBits; 391 unsigned OddParts = NumParts - RoundParts; 392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 393 DAG.getIntPtrConstant(RoundBits)); 394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 395 396 if (TLI.isBigEndian()) 397 // The odd parts were reversed by getCopyToParts - unreverse them. 398 std::reverse(Parts + RoundParts, Parts + NumParts); 399 400 NumParts = RoundParts; 401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 403 } 404 405 // The number of parts is a power of 2. Repeatedly bisect the value using 406 // EXTRACT_ELEMENT. 407 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 408 EVT::getIntegerVT(*DAG.getContext(), 409 ValueVT.getSizeInBits()), 410 Val); 411 412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 413 for (unsigned i = 0; i < NumParts; i += StepSize) { 414 unsigned ThisBits = StepSize * PartBits / 2; 415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 416 SDValue &Part0 = Parts[i]; 417 SDValue &Part1 = Parts[i+StepSize/2]; 418 419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 420 ThisVT, Part0, DAG.getIntPtrConstant(1)); 421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 422 ThisVT, Part0, DAG.getIntPtrConstant(0)); 423 424 if (ThisBits == PartBits && ThisVT != PartVT) { 425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 427 } 428 } 429 } 430 431 if (TLI.isBigEndian()) 432 std::reverse(Parts, Parts + OrigNumParts); 433} 434 435 436/// getCopyToPartsVector - Create a series of nodes that contain the specified 437/// value split into legal parts. 438static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 439 SDValue Val, SDValue *Parts, unsigned NumParts, 440 EVT PartVT) { 441 EVT ValueVT = Val.getValueType(); 442 assert(ValueVT.isVector() && "Not a vector"); 443 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 444 445 if (NumParts == 1) { 446 if (PartVT == ValueVT) { 447 // Nothing to do. 448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 449 // Bitconvert vector->vector case. 450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 451 } else if (PartVT.isVector() && 452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 454 EVT ElementVT = PartVT.getVectorElementType(); 455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 456 // undef elements. 457 SmallVector<SDValue, 16> Ops; 458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 460 ElementVT, Val, DAG.getIntPtrConstant(i))); 461 462 for (unsigned i = ValueVT.getVectorNumElements(), 463 e = PartVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getUNDEF(ElementVT)); 465 466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 467 468 // FIXME: Use CONCAT for 2x -> 4x. 469 470 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 472 } else if (PartVT.isVector() && 473 PartVT.getVectorElementType().bitsGE( 474 ValueVT.getVectorElementType()) && 475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 476 477 // Promoted vector extract 478 bool Smaller = PartVT.bitsLE(ValueVT); 479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 480 DL, PartVT, Val); 481 } else{ 482 // Vector -> scalar conversion. 483 assert(ValueVT.getVectorNumElements() == 1 && 484 "Only trivial vector-to-scalar conversions should get here!"); 485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 PartVT, Val, DAG.getIntPtrConstant(0)); 487 488 bool Smaller = ValueVT.bitsLE(PartVT); 489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 490 DL, PartVT, Val); 491 } 492 493 Parts[0] = Val; 494 return; 495 } 496 497 // Handle a multi-element vector. 498 EVT IntermediateVT, RegisterVT; 499 unsigned NumIntermediates; 500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 501 IntermediateVT, 502 NumIntermediates, RegisterVT); 503 unsigned NumElements = ValueVT.getVectorNumElements(); 504 505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 506 NumParts = NumRegs; // Silence a compiler warning. 507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 508 509 // Split the vector into intermediate operands. 510 SmallVector<SDValue, 8> Ops(NumIntermediates); 511 for (unsigned i = 0; i != NumIntermediates; ++i) { 512 if (IntermediateVT.isVector()) 513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 514 IntermediateVT, Val, 515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 516 else 517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 519 } 520 521 // Split the intermediate operands into legal parts. 522 if (NumParts == NumIntermediates) { 523 // If the register was not expanded, promote or copy the value, 524 // as appropriate. 525 for (unsigned i = 0; i != NumParts; ++i) 526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 527 } else if (NumParts > 0) { 528 // If the intermediate type was expanded, split each the value into 529 // legal parts. 530 assert(NumParts % NumIntermediates == 0 && 531 "Must expand into a divisible number of parts!"); 532 unsigned Factor = NumParts / NumIntermediates; 533 for (unsigned i = 0; i != NumIntermediates; ++i) 534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 535 } 536} 537 538 539 540 541namespace { 542 /// RegsForValue - This struct represents the registers (physical or virtual) 543 /// that a particular set of values is assigned, and the type information 544 /// about the value. The most common situation is to represent one value at a 545 /// time, but struct or array values are handled element-wise as multiple 546 /// values. The splitting of aggregates is performed recursively, so that we 547 /// never have aggregate-typed registers. The values at this point do not 548 /// necessarily have legal types, so each value may require one or more 549 /// registers of some legal type. 550 /// 551 struct RegsForValue { 552 /// ValueVTs - The value types of the values, which may not be legal, and 553 /// may need be promoted or synthesized from one or more registers. 554 /// 555 SmallVector<EVT, 4> ValueVTs; 556 557 /// RegVTs - The value types of the registers. This is the same size as 558 /// ValueVTs and it records, for each value, what the type of the assigned 559 /// register or registers are. (Individual values are never synthesized 560 /// from more than one type of register.) 561 /// 562 /// With virtual registers, the contents of RegVTs is redundant with TLI's 563 /// getRegisterType member function, however when with physical registers 564 /// it is necessary to have a separate record of the types. 565 /// 566 SmallVector<EVT, 4> RegVTs; 567 568 /// Regs - This list holds the registers assigned to the values. 569 /// Each legal or promoted value requires one register, and each 570 /// expanded value requires multiple registers. 571 /// 572 SmallVector<unsigned, 4> Regs; 573 574 RegsForValue() {} 575 576 RegsForValue(const SmallVector<unsigned, 4> ®s, 577 EVT regvt, EVT valuevt) 578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 579 580 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 581 unsigned Reg, Type *Ty) { 582 ComputeValueVTs(tli, Ty, ValueVTs); 583 584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 585 EVT ValueVT = ValueVTs[Value]; 586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 588 for (unsigned i = 0; i != NumRegs; ++i) 589 Regs.push_back(Reg + i); 590 RegVTs.push_back(RegisterVT); 591 Reg += NumRegs; 592 } 593 } 594 595 /// areValueTypesLegal - Return true if types of all the values are legal. 596 bool areValueTypesLegal(const TargetLowering &TLI) { 597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 598 EVT RegisterVT = RegVTs[Value]; 599 if (!TLI.isTypeLegal(RegisterVT)) 600 return false; 601 } 602 return true; 603 } 604 605 /// append - Add the specified values to this one. 606 void append(const RegsForValue &RHS) { 607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 609 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 610 } 611 612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 613 /// this value and returns the result as a ValueVTs value. This uses 614 /// Chain/Flag as the input and updates them for the output Chain/Flag. 615 /// If the Flag pointer is NULL, no flag is used. 616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 617 DebugLoc dl, 618 SDValue &Chain, SDValue *Flag) const; 619 620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 621 /// specified value into the registers specified by this object. This uses 622 /// Chain/Flag as the input and updates them for the output Chain/Flag. 623 /// If the Flag pointer is NULL, no flag is used. 624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 625 SDValue &Chain, SDValue *Flag) const; 626 627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 628 /// operand list. This adds the code marker, matching input operand index 629 /// (if applicable), and includes the number of values added into it. 630 void AddInlineAsmOperands(unsigned Kind, 631 bool HasMatching, unsigned MatchingIdx, 632 SelectionDAG &DAG, 633 std::vector<SDValue> &Ops) const; 634 }; 635} 636 637/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 638/// this value and returns the result as a ValueVT value. This uses 639/// Chain/Flag as the input and updates them for the output Chain/Flag. 640/// If the Flag pointer is NULL, no flag is used. 641SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 642 FunctionLoweringInfo &FuncInfo, 643 DebugLoc dl, 644 SDValue &Chain, SDValue *Flag) const { 645 // A Value with type {} or [0 x %t] needs no registers. 646 if (ValueVTs.empty()) 647 return SDValue(); 648 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 650 651 // Assemble the legal parts into the final values. 652 SmallVector<SDValue, 4> Values(ValueVTs.size()); 653 SmallVector<SDValue, 8> Parts; 654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 655 // Copy the legal parts from the registers. 656 EVT ValueVT = ValueVTs[Value]; 657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 658 EVT RegisterVT = RegVTs[Value]; 659 660 Parts.resize(NumRegs); 661 for (unsigned i = 0; i != NumRegs; ++i) { 662 SDValue P; 663 if (Flag == 0) { 664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 665 } else { 666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 667 *Flag = P.getValue(2); 668 } 669 670 Chain = P.getValue(1); 671 Parts[i] = P; 672 673 // If the source register was virtual and if we know something about it, 674 // add an assert node. 675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 676 !RegisterVT.isInteger() || RegisterVT.isVector()) 677 continue; 678 679 const FunctionLoweringInfo::LiveOutInfo *LOI = 680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 681 if (!LOI) 682 continue; 683 684 unsigned RegSize = RegisterVT.getSizeInBits(); 685 unsigned NumSignBits = LOI->NumSignBits; 686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 687 688 // FIXME: We capture more information than the dag can represent. For 689 // now, just use the tightest assertzext/assertsext possible. 690 bool isSExt = true; 691 EVT FromVT(MVT::Other); 692 if (NumSignBits == RegSize) 693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 694 else if (NumZeroBits >= RegSize-1) 695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 696 else if (NumSignBits > RegSize-8) 697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 698 else if (NumZeroBits >= RegSize-8) 699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 700 else if (NumSignBits > RegSize-16) 701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 702 else if (NumZeroBits >= RegSize-16) 703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 704 else if (NumSignBits > RegSize-32) 705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 706 else if (NumZeroBits >= RegSize-32) 707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 708 else 709 continue; 710 711 // Add an assertion node. 712 assert(FromVT != MVT::Other); 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 714 RegisterVT, P, DAG.getValueType(FromVT)); 715 } 716 717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 718 NumRegs, RegisterVT, ValueVT); 719 Part += NumRegs; 720 Parts.clear(); 721 } 722 723 return DAG.getNode(ISD::MERGE_VALUES, dl, 724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 725 &Values[0], ValueVTs.size()); 726} 727 728/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 729/// specified value into the registers specified by this object. This uses 730/// Chain/Flag as the input and updates them for the output Chain/Flag. 731/// If the Flag pointer is NULL, no flag is used. 732void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 733 SDValue &Chain, SDValue *Flag) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 // Get the list of the values's legal parts. 737 unsigned NumRegs = Regs.size(); 738 SmallVector<SDValue, 8> Parts(NumRegs); 739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 740 EVT ValueVT = ValueVTs[Value]; 741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 742 EVT RegisterVT = RegVTs[Value]; 743 744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 745 &Parts[Part], NumParts, RegisterVT); 746 Part += NumParts; 747 } 748 749 // Copy the parts into the registers. 750 SmallVector<SDValue, 8> Chains(NumRegs); 751 for (unsigned i = 0; i != NumRegs; ++i) { 752 SDValue Part; 753 if (Flag == 0) { 754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 755 } else { 756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 757 *Flag = Part.getValue(1); 758 } 759 760 Chains[i] = Part.getValue(0); 761 } 762 763 if (NumRegs == 1 || Flag) 764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 765 // flagged to it. That is the CopyToReg nodes and the user are considered 766 // a single scheduling unit. If we create a TokenFactor and return it as 767 // chain, then the TokenFactor is both a predecessor (operand) of the 768 // user as well as a successor (the TF operands are flagged to the user). 769 // c1, f1 = CopyToReg 770 // c2, f2 = CopyToReg 771 // c3 = TokenFactor c1, c2 772 // ... 773 // = op c3, ..., f2 774 Chain = Chains[NumRegs-1]; 775 else 776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 777} 778 779/// AddInlineAsmOperands - Add this value to the specified inlineasm node 780/// operand list. This adds the code marker and includes the number of 781/// values added into it. 782void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 783 unsigned MatchingIdx, 784 SelectionDAG &DAG, 785 std::vector<SDValue> &Ops) const { 786 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 787 788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 789 if (HasMatching) 790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 792 Ops.push_back(Res); 793 794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 796 EVT RegisterVT = RegVTs[Value]; 797 for (unsigned i = 0; i != NumRegs; ++i) { 798 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 800 } 801 } 802} 803 804void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 805 AA = &aa; 806 GFI = gfi; 807 TD = DAG.getTarget().getTargetData(); 808} 809 810/// clear - Clear out the current SelectionDAG and the associated 811/// state and prepare this SelectionDAGBuilder object to be used 812/// for a new block. This doesn't clear out information about 813/// additional blocks that are needed to complete switch lowering 814/// or PHI node updating; that information is cleared out as it is 815/// consumed. 816void SelectionDAGBuilder::clear() { 817 NodeMap.clear(); 818 UnusedArgNodeMap.clear(); 819 PendingLoads.clear(); 820 PendingExports.clear(); 821 CurDebugLoc = DebugLoc(); 822 HasTailCall = false; 823} 824 825/// clearDanglingDebugInfo - Clear the dangling debug information 826/// map. This function is seperated from the clear so that debug 827/// information that is dangling in a basic block can be properly 828/// resolved in a different basic block. This allows the 829/// SelectionDAG to resolve dangling debug information attached 830/// to PHI nodes. 831void SelectionDAGBuilder::clearDanglingDebugInfo() { 832 DanglingDebugInfoMap.clear(); 833} 834 835/// getRoot - Return the current virtual root of the Selection DAG, 836/// flushing any PendingLoad items. This must be done before emitting 837/// a store or any other node that may need to be ordered after any 838/// prior load instructions. 839/// 840SDValue SelectionDAGBuilder::getRoot() { 841 if (PendingLoads.empty()) 842 return DAG.getRoot(); 843 844 if (PendingLoads.size() == 1) { 845 SDValue Root = PendingLoads[0]; 846 DAG.setRoot(Root); 847 PendingLoads.clear(); 848 return Root; 849 } 850 851 // Otherwise, we have to make a token factor node. 852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 853 &PendingLoads[0], PendingLoads.size()); 854 PendingLoads.clear(); 855 DAG.setRoot(Root); 856 return Root; 857} 858 859/// getControlRoot - Similar to getRoot, but instead of flushing all the 860/// PendingLoad items, flush all the PendingExports items. It is necessary 861/// to do this before emitting a terminator instruction. 862/// 863SDValue SelectionDAGBuilder::getControlRoot() { 864 SDValue Root = DAG.getRoot(); 865 866 if (PendingExports.empty()) 867 return Root; 868 869 // Turn all of the CopyToReg chains into one factored node. 870 if (Root.getOpcode() != ISD::EntryToken) { 871 unsigned i = 0, e = PendingExports.size(); 872 for (; i != e; ++i) { 873 assert(PendingExports[i].getNode()->getNumOperands() > 1); 874 if (PendingExports[i].getNode()->getOperand(0) == Root) 875 break; // Don't add the root if we already indirectly depend on it. 876 } 877 878 if (i == e) 879 PendingExports.push_back(Root); 880 } 881 882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 883 &PendingExports[0], 884 PendingExports.size()); 885 PendingExports.clear(); 886 DAG.setRoot(Root); 887 return Root; 888} 889 890void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 892 DAG.AssignOrdering(Node, SDNodeOrder); 893 894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 895 AssignOrderingToNode(Node->getOperand(I).getNode()); 896} 897 898void SelectionDAGBuilder::visit(const Instruction &I) { 899 // Set up outgoing PHI node register values before emitting the terminator. 900 if (isa<TerminatorInst>(&I)) 901 HandlePHINodesInSuccessorBlocks(I.getParent()); 902 903 CurDebugLoc = I.getDebugLoc(); 904 905 visit(I.getOpcode(), I); 906 907 if (!isa<TerminatorInst>(&I) && !HasTailCall) 908 CopyToExportRegsIfNeeded(&I); 909 910 CurDebugLoc = DebugLoc(); 911} 912 913void SelectionDAGBuilder::visitPHI(const PHINode &) { 914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 915} 916 917void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 918 // Note: this doesn't use InstVisitor, because it has to work with 919 // ConstantExpr's in addition to instructions. 920 switch (Opcode) { 921 default: llvm_unreachable("Unknown instruction type encountered!"); 922 // Build the switch statement using the Instruction.def file. 923#define HANDLE_INST(NUM, OPCODE, CLASS) \ 924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 925#include "llvm/Instruction.def" 926 } 927 928 // Assign the ordering to the freshly created DAG nodes. 929 if (NodeMap.count(&I)) { 930 ++SDNodeOrder; 931 AssignOrderingToNode(getValue(&I).getNode()); 932 } 933} 934 935// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 936// generate the debug data structures now that we've seen its definition. 937void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 938 SDValue Val) { 939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 940 if (DDI.getDI()) { 941 const DbgValueInst *DI = DDI.getDI(); 942 DebugLoc dl = DDI.getdl(); 943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 944 MDNode *Variable = DI->getVariable(); 945 uint64_t Offset = DI->getOffset(); 946 SDDbgValue *SDV; 947 if (Val.getNode()) { 948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 949 SDV = DAG.getDbgValue(Variable, Val.getNode(), 950 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 951 DAG.AddDbgValue(SDV, Val.getNode(), false); 952 } 953 } else 954 DEBUG(dbgs() << "Dropping debug info for " << DI); 955 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 956 } 957} 958 959// getValue - Return an SDValue for the given Value. 960SDValue SelectionDAGBuilder::getValue(const Value *V) { 961 // If we already have an SDValue for this value, use it. It's important 962 // to do this first, so that we don't create a CopyFromReg if we already 963 // have a regular SDValue. 964 SDValue &N = NodeMap[V]; 965 if (N.getNode()) return N; 966 967 // If there's a virtual register allocated and initialized for this 968 // value, use it. 969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 970 if (It != FuncInfo.ValueMap.end()) { 971 unsigned InReg = It->second; 972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 973 SDValue Chain = DAG.getEntryNode(); 974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 975 resolveDanglingDebugInfo(V, N); 976 return N; 977 } 978 979 // Otherwise create a new SDValue and remember it. 980 SDValue Val = getValueImpl(V); 981 NodeMap[V] = Val; 982 resolveDanglingDebugInfo(V, Val); 983 return Val; 984} 985 986/// getNonRegisterValue - Return an SDValue for the given Value, but 987/// don't look in FuncInfo.ValueMap for a virtual register. 988SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 989 // If we already have an SDValue for this value, use it. 990 SDValue &N = NodeMap[V]; 991 if (N.getNode()) return N; 992 993 // Otherwise create a new SDValue and remember it. 994 SDValue Val = getValueImpl(V); 995 NodeMap[V] = Val; 996 resolveDanglingDebugInfo(V, Val); 997 return Val; 998} 999 1000/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1001/// Create an SDValue for the given value. 1002SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1003 if (const Constant *C = dyn_cast<Constant>(V)) { 1004 EVT VT = TLI.getValueType(V->getType(), true); 1005 1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1007 return DAG.getConstant(*CI, VT); 1008 1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1011 1012 if (isa<ConstantPointerNull>(C)) 1013 return DAG.getConstant(0, TLI.getPointerTy()); 1014 1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1016 return DAG.getConstantFP(*CFP, VT); 1017 1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1019 return DAG.getUNDEF(VT); 1020 1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1022 visit(CE->getOpcode(), *CE); 1023 SDValue N1 = NodeMap[V]; 1024 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1025 return N1; 1026 } 1027 1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1029 SmallVector<SDValue, 4> Constants; 1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1031 OI != OE; ++OI) { 1032 SDNode *Val = getValue(*OI).getNode(); 1033 // If the operand is an empty aggregate, there are no values. 1034 if (!Val) continue; 1035 // Add each leaf value from the operand to the Constants list 1036 // to form a flattened list of all the values. 1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1038 Constants.push_back(SDValue(Val, i)); 1039 } 1040 1041 return DAG.getMergeValues(&Constants[0], Constants.size(), 1042 getCurDebugLoc()); 1043 } 1044 1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1047 "Unknown struct or array constant!"); 1048 1049 SmallVector<EVT, 4> ValueVTs; 1050 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1051 unsigned NumElts = ValueVTs.size(); 1052 if (NumElts == 0) 1053 return SDValue(); // empty struct 1054 SmallVector<SDValue, 4> Constants(NumElts); 1055 for (unsigned i = 0; i != NumElts; ++i) { 1056 EVT EltVT = ValueVTs[i]; 1057 if (isa<UndefValue>(C)) 1058 Constants[i] = DAG.getUNDEF(EltVT); 1059 else if (EltVT.isFloatingPoint()) 1060 Constants[i] = DAG.getConstantFP(0, EltVT); 1061 else 1062 Constants[i] = DAG.getConstant(0, EltVT); 1063 } 1064 1065 return DAG.getMergeValues(&Constants[0], NumElts, 1066 getCurDebugLoc()); 1067 } 1068 1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1070 return DAG.getBlockAddress(BA, VT); 1071 1072 VectorType *VecTy = cast<VectorType>(V->getType()); 1073 unsigned NumElements = VecTy->getNumElements(); 1074 1075 // Now that we know the number and type of the elements, get that number of 1076 // elements into the Ops array based on what kind of constant it is. 1077 SmallVector<SDValue, 16> Ops; 1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1079 for (unsigned i = 0; i != NumElements; ++i) 1080 Ops.push_back(getValue(CP->getOperand(i))); 1081 } else { 1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1083 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1084 1085 SDValue Op; 1086 if (EltVT.isFloatingPoint()) 1087 Op = DAG.getConstantFP(0, EltVT); 1088 else 1089 Op = DAG.getConstant(0, EltVT); 1090 Ops.assign(NumElements, Op); 1091 } 1092 1093 // Create a BUILD_VECTOR node. 1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1095 VT, &Ops[0], Ops.size()); 1096 } 1097 1098 // If this is a static alloca, generate it as the frameindex instead of 1099 // computation. 1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1101 DenseMap<const AllocaInst*, int>::iterator SI = 1102 FuncInfo.StaticAllocaMap.find(AI); 1103 if (SI != FuncInfo.StaticAllocaMap.end()) 1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1105 } 1106 1107 // If this is an instruction which fast-isel has deferred, select it now. 1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1111 SDValue Chain = DAG.getEntryNode(); 1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1113 } 1114 1115 llvm_unreachable("Can't get register for value!"); 1116 return SDValue(); 1117} 1118 1119void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1120 SDValue Chain = getControlRoot(); 1121 SmallVector<ISD::OutputArg, 8> Outs; 1122 SmallVector<SDValue, 8> OutVals; 1123 1124 if (!FuncInfo.CanLowerReturn) { 1125 unsigned DemoteReg = FuncInfo.DemoteRegister; 1126 const Function *F = I.getParent()->getParent(); 1127 1128 // Emit a store of the return value through the virtual register. 1129 // Leave Outs empty so that LowerReturn won't try to load return 1130 // registers the usual way. 1131 SmallVector<EVT, 1> PtrValueVTs; 1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1133 PtrValueVTs); 1134 1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1136 SDValue RetOp = getValue(I.getOperand(0)); 1137 1138 SmallVector<EVT, 4> ValueVTs; 1139 SmallVector<uint64_t, 4> Offsets; 1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1141 unsigned NumValues = ValueVTs.size(); 1142 1143 SmallVector<SDValue, 4> Chains(NumValues); 1144 for (unsigned i = 0; i != NumValues; ++i) { 1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1146 RetPtr.getValueType(), RetPtr, 1147 DAG.getIntPtrConstant(Offsets[i])); 1148 Chains[i] = 1149 DAG.getStore(Chain, getCurDebugLoc(), 1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1151 // FIXME: better loc info would be nice. 1152 Add, MachinePointerInfo(), false, false, 0); 1153 } 1154 1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1156 MVT::Other, &Chains[0], NumValues); 1157 } else if (I.getNumOperands() != 0) { 1158 SmallVector<EVT, 4> ValueVTs; 1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1160 unsigned NumValues = ValueVTs.size(); 1161 if (NumValues) { 1162 SDValue RetOp = getValue(I.getOperand(0)); 1163 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1164 EVT VT = ValueVTs[j]; 1165 1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1167 1168 const Function *F = I.getParent()->getParent(); 1169 if (F->paramHasAttr(0, Attribute::SExt)) 1170 ExtendKind = ISD::SIGN_EXTEND; 1171 else if (F->paramHasAttr(0, Attribute::ZExt)) 1172 ExtendKind = ISD::ZERO_EXTEND; 1173 1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1176 1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1179 SmallVector<SDValue, 4> Parts(NumParts); 1180 getCopyToParts(DAG, getCurDebugLoc(), 1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1182 &Parts[0], NumParts, PartVT, ExtendKind); 1183 1184 // 'inreg' on function refers to return value 1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1186 if (F->paramHasAttr(0, Attribute::InReg)) 1187 Flags.setInReg(); 1188 1189 // Propagate extension type if any 1190 if (ExtendKind == ISD::SIGN_EXTEND) 1191 Flags.setSExt(); 1192 else if (ExtendKind == ISD::ZERO_EXTEND) 1193 Flags.setZExt(); 1194 1195 for (unsigned i = 0; i < NumParts; ++i) { 1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1197 /*isfixed=*/true)); 1198 OutVals.push_back(Parts[i]); 1199 } 1200 } 1201 } 1202 } 1203 1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1205 CallingConv::ID CallConv = 1206 DAG.getMachineFunction().getFunction()->getCallingConv(); 1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1208 Outs, OutVals, getCurDebugLoc(), DAG); 1209 1210 // Verify that the target's LowerReturn behaved as expected. 1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1212 "LowerReturn didn't return a valid chain!"); 1213 1214 // Update the DAG with the new chain value resulting from return lowering. 1215 DAG.setRoot(Chain); 1216} 1217 1218/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1219/// created for it, emit nodes to copy the value into the virtual 1220/// registers. 1221void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1222 // Skip empty types 1223 if (V->getType()->isEmptyTy()) 1224 return; 1225 1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1227 if (VMI != FuncInfo.ValueMap.end()) { 1228 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1229 CopyValueToVirtualRegister(V, VMI->second); 1230 } 1231} 1232 1233/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1234/// the current basic block, add it to ValueMap now so that we'll get a 1235/// CopyTo/FromReg. 1236void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1237 // No need to export constants. 1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1239 1240 // Already exported? 1241 if (FuncInfo.isExportedInst(V)) return; 1242 1243 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1244 CopyValueToVirtualRegister(V, Reg); 1245} 1246 1247bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1248 const BasicBlock *FromBB) { 1249 // The operands of the setcc have to be in this block. We don't know 1250 // how to export them from some other block. 1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1252 // Can export from current BB. 1253 if (VI->getParent() == FromBB) 1254 return true; 1255 1256 // Is already exported, noop. 1257 return FuncInfo.isExportedInst(V); 1258 } 1259 1260 // If this is an argument, we can export it if the BB is the entry block or 1261 // if it is already exported. 1262 if (isa<Argument>(V)) { 1263 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1264 return true; 1265 1266 // Otherwise, can only export this if it is already exported. 1267 return FuncInfo.isExportedInst(V); 1268 } 1269 1270 // Otherwise, constants can always be exported. 1271 return true; 1272} 1273 1274/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1275uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src, 1276 MachineBasicBlock *Dst) { 1277 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1278 if (!BPI) 1279 return 0; 1280 const BasicBlock *SrcBB = Src->getBasicBlock(); 1281 const BasicBlock *DstBB = Dst->getBasicBlock(); 1282 return BPI->getEdgeWeight(SrcBB, DstBB); 1283} 1284 1285void SelectionDAGBuilder:: 1286addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1287 uint32_t Weight /* = 0 */) { 1288 if (!Weight) 1289 Weight = getEdgeWeight(Src, Dst); 1290 Src->addSuccessor(Dst, Weight); 1291} 1292 1293 1294static bool InBlock(const Value *V, const BasicBlock *BB) { 1295 if (const Instruction *I = dyn_cast<Instruction>(V)) 1296 return I->getParent() == BB; 1297 return true; 1298} 1299 1300/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1301/// This function emits a branch and is used at the leaves of an OR or an 1302/// AND operator tree. 1303/// 1304void 1305SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1306 MachineBasicBlock *TBB, 1307 MachineBasicBlock *FBB, 1308 MachineBasicBlock *CurBB, 1309 MachineBasicBlock *SwitchBB) { 1310 const BasicBlock *BB = CurBB->getBasicBlock(); 1311 1312 // If the leaf of the tree is a comparison, merge the condition into 1313 // the caseblock. 1314 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1315 // The operands of the cmp have to be in this block. We don't know 1316 // how to export them from some other block. If this is the first block 1317 // of the sequence, no exporting is needed. 1318 if (CurBB == SwitchBB || 1319 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1320 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1321 ISD::CondCode Condition; 1322 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1323 Condition = getICmpCondCode(IC->getPredicate()); 1324 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1325 Condition = getFCmpCondCode(FC->getPredicate()); 1326 } else { 1327 Condition = ISD::SETEQ; // silence warning. 1328 llvm_unreachable("Unknown compare instruction"); 1329 } 1330 1331 CaseBlock CB(Condition, BOp->getOperand(0), 1332 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1333 SwitchCases.push_back(CB); 1334 return; 1335 } 1336 } 1337 1338 // Create a CaseBlock record representing this branch. 1339 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1340 NULL, TBB, FBB, CurBB); 1341 SwitchCases.push_back(CB); 1342} 1343 1344/// FindMergedConditions - If Cond is an expression like 1345void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1346 MachineBasicBlock *TBB, 1347 MachineBasicBlock *FBB, 1348 MachineBasicBlock *CurBB, 1349 MachineBasicBlock *SwitchBB, 1350 unsigned Opc) { 1351 // If this node is not part of the or/and tree, emit it as a branch. 1352 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1353 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1354 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1355 BOp->getParent() != CurBB->getBasicBlock() || 1356 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1357 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1358 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1359 return; 1360 } 1361 1362 // Create TmpBB after CurBB. 1363 MachineFunction::iterator BBI = CurBB; 1364 MachineFunction &MF = DAG.getMachineFunction(); 1365 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1366 CurBB->getParent()->insert(++BBI, TmpBB); 1367 1368 if (Opc == Instruction::Or) { 1369 // Codegen X | Y as: 1370 // jmp_if_X TBB 1371 // jmp TmpBB 1372 // TmpBB: 1373 // jmp_if_Y TBB 1374 // jmp FBB 1375 // 1376 1377 // Emit the LHS condition. 1378 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1379 1380 // Emit the RHS condition into TmpBB. 1381 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1382 } else { 1383 assert(Opc == Instruction::And && "Unknown merge op!"); 1384 // Codegen X & Y as: 1385 // jmp_if_X TmpBB 1386 // jmp FBB 1387 // TmpBB: 1388 // jmp_if_Y TBB 1389 // jmp FBB 1390 // 1391 // This requires creation of TmpBB after CurBB. 1392 1393 // Emit the LHS condition. 1394 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1395 1396 // Emit the RHS condition into TmpBB. 1397 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1398 } 1399} 1400 1401/// If the set of cases should be emitted as a series of branches, return true. 1402/// If we should emit this as a bunch of and/or'd together conditions, return 1403/// false. 1404bool 1405SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1406 if (Cases.size() != 2) return true; 1407 1408 // If this is two comparisons of the same values or'd or and'd together, they 1409 // will get folded into a single comparison, so don't emit two blocks. 1410 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1411 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1412 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1413 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1414 return false; 1415 } 1416 1417 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1418 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1419 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1420 Cases[0].CC == Cases[1].CC && 1421 isa<Constant>(Cases[0].CmpRHS) && 1422 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1423 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1424 return false; 1425 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1426 return false; 1427 } 1428 1429 return true; 1430} 1431 1432void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1433 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1434 1435 // Update machine-CFG edges. 1436 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1437 1438 // Figure out which block is immediately after the current one. 1439 MachineBasicBlock *NextBlock = 0; 1440 MachineFunction::iterator BBI = BrMBB; 1441 if (++BBI != FuncInfo.MF->end()) 1442 NextBlock = BBI; 1443 1444 if (I.isUnconditional()) { 1445 // Update machine-CFG edges. 1446 BrMBB->addSuccessor(Succ0MBB); 1447 1448 // If this is not a fall-through branch, emit the branch. 1449 if (Succ0MBB != NextBlock) 1450 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1451 MVT::Other, getControlRoot(), 1452 DAG.getBasicBlock(Succ0MBB))); 1453 1454 return; 1455 } 1456 1457 // If this condition is one of the special cases we handle, do special stuff 1458 // now. 1459 const Value *CondVal = I.getCondition(); 1460 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1461 1462 // If this is a series of conditions that are or'd or and'd together, emit 1463 // this as a sequence of branches instead of setcc's with and/or operations. 1464 // As long as jumps are not expensive, this should improve performance. 1465 // For example, instead of something like: 1466 // cmp A, B 1467 // C = seteq 1468 // cmp D, E 1469 // F = setle 1470 // or C, F 1471 // jnz foo 1472 // Emit: 1473 // cmp A, B 1474 // je foo 1475 // cmp D, E 1476 // jle foo 1477 // 1478 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1479 if (!TLI.isJumpExpensive() && 1480 BOp->hasOneUse() && 1481 (BOp->getOpcode() == Instruction::And || 1482 BOp->getOpcode() == Instruction::Or)) { 1483 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1484 BOp->getOpcode()); 1485 // If the compares in later blocks need to use values not currently 1486 // exported from this block, export them now. This block should always 1487 // be the first entry. 1488 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1489 1490 // Allow some cases to be rejected. 1491 if (ShouldEmitAsBranches(SwitchCases)) { 1492 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1493 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1494 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1495 } 1496 1497 // Emit the branch for this block. 1498 visitSwitchCase(SwitchCases[0], BrMBB); 1499 SwitchCases.erase(SwitchCases.begin()); 1500 return; 1501 } 1502 1503 // Okay, we decided not to do this, remove any inserted MBB's and clear 1504 // SwitchCases. 1505 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1506 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1507 1508 SwitchCases.clear(); 1509 } 1510 } 1511 1512 // Create a CaseBlock record representing this branch. 1513 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1514 NULL, Succ0MBB, Succ1MBB, BrMBB); 1515 1516 // Use visitSwitchCase to actually insert the fast branch sequence for this 1517 // cond branch. 1518 visitSwitchCase(CB, BrMBB); 1519} 1520 1521/// visitSwitchCase - Emits the necessary code to represent a single node in 1522/// the binary search tree resulting from lowering a switch instruction. 1523void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1524 MachineBasicBlock *SwitchBB) { 1525 SDValue Cond; 1526 SDValue CondLHS = getValue(CB.CmpLHS); 1527 DebugLoc dl = getCurDebugLoc(); 1528 1529 // Build the setcc now. 1530 if (CB.CmpMHS == NULL) { 1531 // Fold "(X == true)" to X and "(X == false)" to !X to 1532 // handle common cases produced by branch lowering. 1533 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1534 CB.CC == ISD::SETEQ) 1535 Cond = CondLHS; 1536 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1537 CB.CC == ISD::SETEQ) { 1538 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1539 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1540 } else 1541 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1542 } else { 1543 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1544 1545 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1546 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1547 1548 SDValue CmpOp = getValue(CB.CmpMHS); 1549 EVT VT = CmpOp.getValueType(); 1550 1551 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1552 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1553 ISD::SETLE); 1554 } else { 1555 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1556 VT, CmpOp, DAG.getConstant(Low, VT)); 1557 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1558 DAG.getConstant(High-Low, VT), ISD::SETULE); 1559 } 1560 } 1561 1562 // Update successor info 1563 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1564 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1565 1566 // Set NextBlock to be the MBB immediately after the current one, if any. 1567 // This is used to avoid emitting unnecessary branches to the next block. 1568 MachineBasicBlock *NextBlock = 0; 1569 MachineFunction::iterator BBI = SwitchBB; 1570 if (++BBI != FuncInfo.MF->end()) 1571 NextBlock = BBI; 1572 1573 // If the lhs block is the next block, invert the condition so that we can 1574 // fall through to the lhs instead of the rhs block. 1575 if (CB.TrueBB == NextBlock) { 1576 std::swap(CB.TrueBB, CB.FalseBB); 1577 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1578 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1579 } 1580 1581 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1582 MVT::Other, getControlRoot(), Cond, 1583 DAG.getBasicBlock(CB.TrueBB)); 1584 1585 // Insert the false branch. Do this even if it's a fall through branch, 1586 // this makes it easier to do DAG optimizations which require inverting 1587 // the branch condition. 1588 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1589 DAG.getBasicBlock(CB.FalseBB)); 1590 1591 DAG.setRoot(BrCond); 1592} 1593 1594/// visitJumpTable - Emit JumpTable node in the current MBB 1595void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1596 // Emit the code for the jump table 1597 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1598 EVT PTy = TLI.getPointerTy(); 1599 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1600 JT.Reg, PTy); 1601 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1602 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1603 MVT::Other, Index.getValue(1), 1604 Table, Index); 1605 DAG.setRoot(BrJumpTable); 1606} 1607 1608/// visitJumpTableHeader - This function emits necessary code to produce index 1609/// in the JumpTable from switch case. 1610void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1611 JumpTableHeader &JTH, 1612 MachineBasicBlock *SwitchBB) { 1613 // Subtract the lowest switch case value from the value being switched on and 1614 // conditional branch to default mbb if the result is greater than the 1615 // difference between smallest and largest cases. 1616 SDValue SwitchOp = getValue(JTH.SValue); 1617 EVT VT = SwitchOp.getValueType(); 1618 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1619 DAG.getConstant(JTH.First, VT)); 1620 1621 // The SDNode we just created, which holds the value being switched on minus 1622 // the smallest case value, needs to be copied to a virtual register so it 1623 // can be used as an index into the jump table in a subsequent basic block. 1624 // This value may be smaller or larger than the target's pointer type, and 1625 // therefore require extension or truncating. 1626 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1627 1628 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1629 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1630 JumpTableReg, SwitchOp); 1631 JT.Reg = JumpTableReg; 1632 1633 // Emit the range check for the jump table, and branch to the default block 1634 // for the switch statement if the value being switched on exceeds the largest 1635 // case in the switch. 1636 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1637 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1638 DAG.getConstant(JTH.Last-JTH.First,VT), 1639 ISD::SETUGT); 1640 1641 // Set NextBlock to be the MBB immediately after the current one, if any. 1642 // This is used to avoid emitting unnecessary branches to the next block. 1643 MachineBasicBlock *NextBlock = 0; 1644 MachineFunction::iterator BBI = SwitchBB; 1645 1646 if (++BBI != FuncInfo.MF->end()) 1647 NextBlock = BBI; 1648 1649 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1650 MVT::Other, CopyTo, CMP, 1651 DAG.getBasicBlock(JT.Default)); 1652 1653 if (JT.MBB != NextBlock) 1654 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1655 DAG.getBasicBlock(JT.MBB)); 1656 1657 DAG.setRoot(BrCond); 1658} 1659 1660/// visitBitTestHeader - This function emits necessary code to produce value 1661/// suitable for "bit tests" 1662void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1663 MachineBasicBlock *SwitchBB) { 1664 // Subtract the minimum value 1665 SDValue SwitchOp = getValue(B.SValue); 1666 EVT VT = SwitchOp.getValueType(); 1667 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1668 DAG.getConstant(B.First, VT)); 1669 1670 // Check range 1671 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1672 TLI.getSetCCResultType(Sub.getValueType()), 1673 Sub, DAG.getConstant(B.Range, VT), 1674 ISD::SETUGT); 1675 1676 // Determine the type of the test operands. 1677 bool UsePtrType = false; 1678 if (!TLI.isTypeLegal(VT)) 1679 UsePtrType = true; 1680 else { 1681 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1682 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1683 // Switch table case range are encoded into series of masks. 1684 // Just use pointer type, it's guaranteed to fit. 1685 UsePtrType = true; 1686 break; 1687 } 1688 } 1689 if (UsePtrType) { 1690 VT = TLI.getPointerTy(); 1691 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1692 } 1693 1694 B.RegVT = VT; 1695 B.Reg = FuncInfo.CreateReg(VT); 1696 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1697 B.Reg, Sub); 1698 1699 // Set NextBlock to be the MBB immediately after the current one, if any. 1700 // This is used to avoid emitting unnecessary branches to the next block. 1701 MachineBasicBlock *NextBlock = 0; 1702 MachineFunction::iterator BBI = SwitchBB; 1703 if (++BBI != FuncInfo.MF->end()) 1704 NextBlock = BBI; 1705 1706 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1707 1708 addSuccessorWithWeight(SwitchBB, B.Default); 1709 addSuccessorWithWeight(SwitchBB, MBB); 1710 1711 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1712 MVT::Other, CopyTo, RangeCmp, 1713 DAG.getBasicBlock(B.Default)); 1714 1715 if (MBB != NextBlock) 1716 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1717 DAG.getBasicBlock(MBB)); 1718 1719 DAG.setRoot(BrRange); 1720} 1721 1722/// visitBitTestCase - this function produces one "bit test" 1723void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1724 MachineBasicBlock* NextMBB, 1725 unsigned Reg, 1726 BitTestCase &B, 1727 MachineBasicBlock *SwitchBB) { 1728 EVT VT = BB.RegVT; 1729 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1730 Reg, VT); 1731 SDValue Cmp; 1732 unsigned PopCount = CountPopulation_64(B.Mask); 1733 if (PopCount == 1) { 1734 // Testing for a single bit; just compare the shift count with what it 1735 // would need to be to shift a 1 bit in that position. 1736 Cmp = DAG.getSetCC(getCurDebugLoc(), 1737 TLI.getSetCCResultType(VT), 1738 ShiftOp, 1739 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1740 ISD::SETEQ); 1741 } else if (PopCount == BB.Range) { 1742 // There is only one zero bit in the range, test for it directly. 1743 Cmp = DAG.getSetCC(getCurDebugLoc(), 1744 TLI.getSetCCResultType(VT), 1745 ShiftOp, 1746 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1747 ISD::SETNE); 1748 } else { 1749 // Make desired shift 1750 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1751 DAG.getConstant(1, VT), ShiftOp); 1752 1753 // Emit bit tests and jumps 1754 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1755 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1756 Cmp = DAG.getSetCC(getCurDebugLoc(), 1757 TLI.getSetCCResultType(VT), 1758 AndOp, DAG.getConstant(0, VT), 1759 ISD::SETNE); 1760 } 1761 1762 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1763 addSuccessorWithWeight(SwitchBB, NextMBB); 1764 1765 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1766 MVT::Other, getControlRoot(), 1767 Cmp, DAG.getBasicBlock(B.TargetBB)); 1768 1769 // Set NextBlock to be the MBB immediately after the current one, if any. 1770 // This is used to avoid emitting unnecessary branches to the next block. 1771 MachineBasicBlock *NextBlock = 0; 1772 MachineFunction::iterator BBI = SwitchBB; 1773 if (++BBI != FuncInfo.MF->end()) 1774 NextBlock = BBI; 1775 1776 if (NextMBB != NextBlock) 1777 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1778 DAG.getBasicBlock(NextMBB)); 1779 1780 DAG.setRoot(BrAnd); 1781} 1782 1783void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1784 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1785 1786 // Retrieve successors. 1787 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1788 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1789 1790 const Value *Callee(I.getCalledValue()); 1791 if (isa<InlineAsm>(Callee)) 1792 visitInlineAsm(&I); 1793 else 1794 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1795 1796 // If the value of the invoke is used outside of its defining block, make it 1797 // available as a virtual register. 1798 CopyToExportRegsIfNeeded(&I); 1799 1800 // Update successor info 1801 InvokeMBB->addSuccessor(Return); 1802 InvokeMBB->addSuccessor(LandingPad); 1803 1804 // Drop into normal successor. 1805 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1806 MVT::Other, getControlRoot(), 1807 DAG.getBasicBlock(Return))); 1808} 1809 1810void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1811} 1812 1813void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1814 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1815} 1816 1817void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1818 assert(FuncInfo.MBB->isLandingPad() && 1819 "Call to landingpad not in landing pad!"); 1820 1821 MachineBasicBlock *MBB = FuncInfo.MBB; 1822 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1823 AddLandingPadInfo(LP, MMI, MBB); 1824 1825 SmallVector<EVT, 2> ValueVTs; 1826 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1827 1828 // Insert the EXCEPTIONADDR instruction. 1829 assert(FuncInfo.MBB->isLandingPad() && 1830 "Call to eh.exception not in landing pad!"); 1831 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1832 SDValue Ops[2]; 1833 Ops[0] = DAG.getRoot(); 1834 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1835 SDValue Chain = Op1.getValue(1); 1836 1837 // Insert the EHSELECTION instruction. 1838 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1839 Ops[0] = Op1; 1840 Ops[1] = Chain; 1841 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1842 Chain = Op2.getValue(1); 1843 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1844 1845 Ops[0] = Op1; 1846 Ops[1] = Op2; 1847 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1848 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1849 &Ops[0], 2); 1850 1851 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1852 setValue(&LP, RetPair.first); 1853 DAG.setRoot(RetPair.second); 1854} 1855 1856/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1857/// small case ranges). 1858bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1859 CaseRecVector& WorkList, 1860 const Value* SV, 1861 MachineBasicBlock *Default, 1862 MachineBasicBlock *SwitchBB) { 1863 Case& BackCase = *(CR.Range.second-1); 1864 1865 // Size is the number of Cases represented by this range. 1866 size_t Size = CR.Range.second - CR.Range.first; 1867 if (Size > 3) 1868 return false; 1869 1870 // Get the MachineFunction which holds the current MBB. This is used when 1871 // inserting any additional MBBs necessary to represent the switch. 1872 MachineFunction *CurMF = FuncInfo.MF; 1873 1874 // Figure out which block is immediately after the current one. 1875 MachineBasicBlock *NextBlock = 0; 1876 MachineFunction::iterator BBI = CR.CaseBB; 1877 1878 if (++BBI != FuncInfo.MF->end()) 1879 NextBlock = BBI; 1880 1881 // If any two of the cases has the same destination, and if one value 1882 // is the same as the other, but has one bit unset that the other has set, 1883 // use bit manipulation to do two compares at once. For example: 1884 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1885 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1886 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1887 if (Size == 2 && CR.CaseBB == SwitchBB) { 1888 Case &Small = *CR.Range.first; 1889 Case &Big = *(CR.Range.second-1); 1890 1891 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1892 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1893 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1894 1895 // Check that there is only one bit different. 1896 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1897 (SmallValue | BigValue) == BigValue) { 1898 // Isolate the common bit. 1899 APInt CommonBit = BigValue & ~SmallValue; 1900 assert((SmallValue | CommonBit) == BigValue && 1901 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1902 1903 SDValue CondLHS = getValue(SV); 1904 EVT VT = CondLHS.getValueType(); 1905 DebugLoc DL = getCurDebugLoc(); 1906 1907 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1908 DAG.getConstant(CommonBit, VT)); 1909 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1910 Or, DAG.getConstant(BigValue, VT), 1911 ISD::SETEQ); 1912 1913 // Update successor info. 1914 addSuccessorWithWeight(SwitchBB, Small.BB); 1915 addSuccessorWithWeight(SwitchBB, Default); 1916 1917 // Insert the true branch. 1918 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1919 getControlRoot(), Cond, 1920 DAG.getBasicBlock(Small.BB)); 1921 1922 // Insert the false branch. 1923 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1924 DAG.getBasicBlock(Default)); 1925 1926 DAG.setRoot(BrCond); 1927 return true; 1928 } 1929 } 1930 } 1931 1932 // Rearrange the case blocks so that the last one falls through if possible. 1933 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1934 // The last case block won't fall through into 'NextBlock' if we emit the 1935 // branches in this order. See if rearranging a case value would help. 1936 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1937 if (I->BB == NextBlock) { 1938 std::swap(*I, BackCase); 1939 break; 1940 } 1941 } 1942 } 1943 1944 // Create a CaseBlock record representing a conditional branch to 1945 // the Case's target mbb if the value being switched on SV is equal 1946 // to C. 1947 MachineBasicBlock *CurBlock = CR.CaseBB; 1948 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1949 MachineBasicBlock *FallThrough; 1950 if (I != E-1) { 1951 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1952 CurMF->insert(BBI, FallThrough); 1953 1954 // Put SV in a virtual register to make it available from the new blocks. 1955 ExportFromCurrentBlock(SV); 1956 } else { 1957 // If the last case doesn't match, go to the default block. 1958 FallThrough = Default; 1959 } 1960 1961 const Value *RHS, *LHS, *MHS; 1962 ISD::CondCode CC; 1963 if (I->High == I->Low) { 1964 // This is just small small case range :) containing exactly 1 case 1965 CC = ISD::SETEQ; 1966 LHS = SV; RHS = I->High; MHS = NULL; 1967 } else { 1968 CC = ISD::SETLE; 1969 LHS = I->Low; MHS = SV; RHS = I->High; 1970 } 1971 1972 uint32_t ExtraWeight = I->ExtraWeight; 1973 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 1974 /* me */ CurBlock, 1975 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 1976 1977 // If emitting the first comparison, just call visitSwitchCase to emit the 1978 // code into the current block. Otherwise, push the CaseBlock onto the 1979 // vector to be later processed by SDISel, and insert the node's MBB 1980 // before the next MBB. 1981 if (CurBlock == SwitchBB) 1982 visitSwitchCase(CB, SwitchBB); 1983 else 1984 SwitchCases.push_back(CB); 1985 1986 CurBlock = FallThrough; 1987 } 1988 1989 return true; 1990} 1991 1992static inline bool areJTsAllowed(const TargetLowering &TLI) { 1993 return !DisableJumpTables && 1994 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1995 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1996} 1997 1998static APInt ComputeRange(const APInt &First, const APInt &Last) { 1999 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2000 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 2001 return (LastExt - FirstExt + 1ULL); 2002} 2003 2004/// handleJTSwitchCase - Emit jumptable for current switch case range 2005bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2006 CaseRecVector &WorkList, 2007 const Value *SV, 2008 MachineBasicBlock *Default, 2009 MachineBasicBlock *SwitchBB) { 2010 Case& FrontCase = *CR.Range.first; 2011 Case& BackCase = *(CR.Range.second-1); 2012 2013 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2014 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2015 2016 APInt TSize(First.getBitWidth(), 0); 2017 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2018 TSize += I->size(); 2019 2020 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2021 return false; 2022 2023 APInt Range = ComputeRange(First, Last); 2024 double Density = TSize.roundToDouble() / Range.roundToDouble(); 2025 if (Density < 0.4) 2026 return false; 2027 2028 DEBUG(dbgs() << "Lowering jump table\n" 2029 << "First entry: " << First << ". Last entry: " << Last << '\n' 2030 << "Range: " << Range 2031 << ". Size: " << TSize << ". Density: " << Density << "\n\n"); 2032 2033 // Get the MachineFunction which holds the current MBB. This is used when 2034 // inserting any additional MBBs necessary to represent the switch. 2035 MachineFunction *CurMF = FuncInfo.MF; 2036 2037 // Figure out which block is immediately after the current one. 2038 MachineFunction::iterator BBI = CR.CaseBB; 2039 ++BBI; 2040 2041 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2042 2043 // Create a new basic block to hold the code for loading the address 2044 // of the jump table, and jumping to it. Update successor information; 2045 // we will either branch to the default case for the switch, or the jump 2046 // table. 2047 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2048 CurMF->insert(BBI, JumpTableBB); 2049 2050 addSuccessorWithWeight(CR.CaseBB, Default); 2051 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2052 2053 // Build a vector of destination BBs, corresponding to each target 2054 // of the jump table. If the value of the jump table slot corresponds to 2055 // a case statement, push the case's BB onto the vector, otherwise, push 2056 // the default BB. 2057 std::vector<MachineBasicBlock*> DestBBs; 2058 APInt TEI = First; 2059 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2060 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2061 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2062 2063 if (Low.sle(TEI) && TEI.sle(High)) { 2064 DestBBs.push_back(I->BB); 2065 if (TEI==High) 2066 ++I; 2067 } else { 2068 DestBBs.push_back(Default); 2069 } 2070 } 2071 2072 // Update successor info. Add one edge to each unique successor. 2073 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2074 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2075 E = DestBBs.end(); I != E; ++I) { 2076 if (!SuccsHandled[(*I)->getNumber()]) { 2077 SuccsHandled[(*I)->getNumber()] = true; 2078 addSuccessorWithWeight(JumpTableBB, *I); 2079 } 2080 } 2081 2082 // Create a jump table index for this jump table. 2083 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2084 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2085 ->createJumpTableIndex(DestBBs); 2086 2087 // Set the jump table information so that we can codegen it as a second 2088 // MachineBasicBlock 2089 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2090 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2091 if (CR.CaseBB == SwitchBB) 2092 visitJumpTableHeader(JT, JTH, SwitchBB); 2093 2094 JTCases.push_back(JumpTableBlock(JTH, JT)); 2095 return true; 2096} 2097 2098/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2099/// 2 subtrees. 2100bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2101 CaseRecVector& WorkList, 2102 const Value* SV, 2103 MachineBasicBlock *Default, 2104 MachineBasicBlock *SwitchBB) { 2105 // Get the MachineFunction which holds the current MBB. This is used when 2106 // inserting any additional MBBs necessary to represent the switch. 2107 MachineFunction *CurMF = FuncInfo.MF; 2108 2109 // Figure out which block is immediately after the current one. 2110 MachineFunction::iterator BBI = CR.CaseBB; 2111 ++BBI; 2112 2113 Case& FrontCase = *CR.Range.first; 2114 Case& BackCase = *(CR.Range.second-1); 2115 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2116 2117 // Size is the number of Cases represented by this range. 2118 unsigned Size = CR.Range.second - CR.Range.first; 2119 2120 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2121 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2122 double FMetric = 0; 2123 CaseItr Pivot = CR.Range.first + Size/2; 2124 2125 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2126 // (heuristically) allow us to emit JumpTable's later. 2127 APInt TSize(First.getBitWidth(), 0); 2128 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2129 I!=E; ++I) 2130 TSize += I->size(); 2131 2132 APInt LSize = FrontCase.size(); 2133 APInt RSize = TSize-LSize; 2134 DEBUG(dbgs() << "Selecting best pivot: \n" 2135 << "First: " << First << ", Last: " << Last <<'\n' 2136 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2137 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2138 J!=E; ++I, ++J) { 2139 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2140 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2141 APInt Range = ComputeRange(LEnd, RBegin); 2142 assert((Range - 2ULL).isNonNegative() && 2143 "Invalid case distance"); 2144 // Use volatile double here to avoid excess precision issues on some hosts, 2145 // e.g. that use 80-bit X87 registers. 2146 volatile double LDensity = 2147 (double)LSize.roundToDouble() / 2148 (LEnd - First + 1ULL).roundToDouble(); 2149 volatile double RDensity = 2150 (double)RSize.roundToDouble() / 2151 (Last - RBegin + 1ULL).roundToDouble(); 2152 double Metric = Range.logBase2()*(LDensity+RDensity); 2153 // Should always split in some non-trivial place 2154 DEBUG(dbgs() <<"=>Step\n" 2155 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2156 << "LDensity: " << LDensity 2157 << ", RDensity: " << RDensity << '\n' 2158 << "Metric: " << Metric << '\n'); 2159 if (FMetric < Metric) { 2160 Pivot = J; 2161 FMetric = Metric; 2162 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2163 } 2164 2165 LSize += J->size(); 2166 RSize -= J->size(); 2167 } 2168 if (areJTsAllowed(TLI)) { 2169 // If our case is dense we *really* should handle it earlier! 2170 assert((FMetric > 0) && "Should handle dense range earlier!"); 2171 } else { 2172 Pivot = CR.Range.first + Size/2; 2173 } 2174 2175 CaseRange LHSR(CR.Range.first, Pivot); 2176 CaseRange RHSR(Pivot, CR.Range.second); 2177 Constant *C = Pivot->Low; 2178 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2179 2180 // We know that we branch to the LHS if the Value being switched on is 2181 // less than the Pivot value, C. We use this to optimize our binary 2182 // tree a bit, by recognizing that if SV is greater than or equal to the 2183 // LHS's Case Value, and that Case Value is exactly one less than the 2184 // Pivot's Value, then we can branch directly to the LHS's Target, 2185 // rather than creating a leaf node for it. 2186 if ((LHSR.second - LHSR.first) == 1 && 2187 LHSR.first->High == CR.GE && 2188 cast<ConstantInt>(C)->getValue() == 2189 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2190 TrueBB = LHSR.first->BB; 2191 } else { 2192 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2193 CurMF->insert(BBI, TrueBB); 2194 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2195 2196 // Put SV in a virtual register to make it available from the new blocks. 2197 ExportFromCurrentBlock(SV); 2198 } 2199 2200 // Similar to the optimization above, if the Value being switched on is 2201 // known to be less than the Constant CR.LT, and the current Case Value 2202 // is CR.LT - 1, then we can branch directly to the target block for 2203 // the current Case Value, rather than emitting a RHS leaf node for it. 2204 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2205 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2206 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2207 FalseBB = RHSR.first->BB; 2208 } else { 2209 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2210 CurMF->insert(BBI, FalseBB); 2211 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2212 2213 // Put SV in a virtual register to make it available from the new blocks. 2214 ExportFromCurrentBlock(SV); 2215 } 2216 2217 // Create a CaseBlock record representing a conditional branch to 2218 // the LHS node if the value being switched on SV is less than C. 2219 // Otherwise, branch to LHS. 2220 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2221 2222 if (CR.CaseBB == SwitchBB) 2223 visitSwitchCase(CB, SwitchBB); 2224 else 2225 SwitchCases.push_back(CB); 2226 2227 return true; 2228} 2229 2230/// handleBitTestsSwitchCase - if current case range has few destination and 2231/// range span less, than machine word bitwidth, encode case range into series 2232/// of masks and emit bit tests with these masks. 2233bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2234 CaseRecVector& WorkList, 2235 const Value* SV, 2236 MachineBasicBlock* Default, 2237 MachineBasicBlock *SwitchBB){ 2238 EVT PTy = TLI.getPointerTy(); 2239 unsigned IntPtrBits = PTy.getSizeInBits(); 2240 2241 Case& FrontCase = *CR.Range.first; 2242 Case& BackCase = *(CR.Range.second-1); 2243 2244 // Get the MachineFunction which holds the current MBB. This is used when 2245 // inserting any additional MBBs necessary to represent the switch. 2246 MachineFunction *CurMF = FuncInfo.MF; 2247 2248 // If target does not have legal shift left, do not emit bit tests at all. 2249 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2250 return false; 2251 2252 size_t numCmps = 0; 2253 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2254 I!=E; ++I) { 2255 // Single case counts one, case range - two. 2256 numCmps += (I->Low == I->High ? 1 : 2); 2257 } 2258 2259 // Count unique destinations 2260 SmallSet<MachineBasicBlock*, 4> Dests; 2261 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2262 Dests.insert(I->BB); 2263 if (Dests.size() > 3) 2264 // Don't bother the code below, if there are too much unique destinations 2265 return false; 2266 } 2267 DEBUG(dbgs() << "Total number of unique destinations: " 2268 << Dests.size() << '\n' 2269 << "Total number of comparisons: " << numCmps << '\n'); 2270 2271 // Compute span of values. 2272 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2273 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2274 APInt cmpRange = maxValue - minValue; 2275 2276 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2277 << "Low bound: " << minValue << '\n' 2278 << "High bound: " << maxValue << '\n'); 2279 2280 if (cmpRange.uge(IntPtrBits) || 2281 (!(Dests.size() == 1 && numCmps >= 3) && 2282 !(Dests.size() == 2 && numCmps >= 5) && 2283 !(Dests.size() >= 3 && numCmps >= 6))) 2284 return false; 2285 2286 DEBUG(dbgs() << "Emitting bit tests\n"); 2287 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2288 2289 // Optimize the case where all the case values fit in a 2290 // word without having to subtract minValue. In this case, 2291 // we can optimize away the subtraction. 2292 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2293 cmpRange = maxValue; 2294 } else { 2295 lowBound = minValue; 2296 } 2297 2298 CaseBitsVector CasesBits; 2299 unsigned i, count = 0; 2300 2301 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2302 MachineBasicBlock* Dest = I->BB; 2303 for (i = 0; i < count; ++i) 2304 if (Dest == CasesBits[i].BB) 2305 break; 2306 2307 if (i == count) { 2308 assert((count < 3) && "Too much destinations to test!"); 2309 CasesBits.push_back(CaseBits(0, Dest, 0)); 2310 count++; 2311 } 2312 2313 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2314 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2315 2316 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2317 uint64_t hi = (highValue - lowBound).getZExtValue(); 2318 2319 for (uint64_t j = lo; j <= hi; j++) { 2320 CasesBits[i].Mask |= 1ULL << j; 2321 CasesBits[i].Bits++; 2322 } 2323 2324 } 2325 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2326 2327 BitTestInfo BTC; 2328 2329 // Figure out which block is immediately after the current one. 2330 MachineFunction::iterator BBI = CR.CaseBB; 2331 ++BBI; 2332 2333 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2334 2335 DEBUG(dbgs() << "Cases:\n"); 2336 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2337 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2338 << ", Bits: " << CasesBits[i].Bits 2339 << ", BB: " << CasesBits[i].BB << '\n'); 2340 2341 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2342 CurMF->insert(BBI, CaseBB); 2343 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2344 CaseBB, 2345 CasesBits[i].BB)); 2346 2347 // Put SV in a virtual register to make it available from the new blocks. 2348 ExportFromCurrentBlock(SV); 2349 } 2350 2351 BitTestBlock BTB(lowBound, cmpRange, SV, 2352 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2353 CR.CaseBB, Default, BTC); 2354 2355 if (CR.CaseBB == SwitchBB) 2356 visitBitTestHeader(BTB, SwitchBB); 2357 2358 BitTestCases.push_back(BTB); 2359 2360 return true; 2361} 2362 2363/// Clusterify - Transform simple list of Cases into list of CaseRange's 2364size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2365 const SwitchInst& SI) { 2366 size_t numCmps = 0; 2367 2368 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2369 // Start with "simple" cases 2370 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2371 BasicBlock *SuccBB = SI.getSuccessor(i); 2372 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2373 2374 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0; 2375 2376 Cases.push_back(Case(SI.getSuccessorValue(i), 2377 SI.getSuccessorValue(i), 2378 SMBB, ExtraWeight)); 2379 } 2380 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2381 2382 // Merge case into clusters 2383 if (Cases.size() >= 2) 2384 // Must recompute end() each iteration because it may be 2385 // invalidated by erase if we hold on to it 2386 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2387 J != Cases.end(); ) { 2388 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2389 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2390 MachineBasicBlock* nextBB = J->BB; 2391 MachineBasicBlock* currentBB = I->BB; 2392 2393 // If the two neighboring cases go to the same destination, merge them 2394 // into a single case. 2395 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2396 I->High = J->High; 2397 J = Cases.erase(J); 2398 2399 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) { 2400 uint32_t CurWeight = currentBB->getBasicBlock() ? 2401 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16; 2402 uint32_t NextWeight = nextBB->getBasicBlock() ? 2403 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16; 2404 2405 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(), 2406 CurWeight + NextWeight); 2407 } 2408 } else { 2409 I = J++; 2410 } 2411 } 2412 2413 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2414 if (I->Low != I->High) 2415 // A range counts double, since it requires two compares. 2416 ++numCmps; 2417 } 2418 2419 return numCmps; 2420} 2421 2422void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2423 MachineBasicBlock *Last) { 2424 // Update JTCases. 2425 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2426 if (JTCases[i].first.HeaderBB == First) 2427 JTCases[i].first.HeaderBB = Last; 2428 2429 // Update BitTestCases. 2430 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2431 if (BitTestCases[i].Parent == First) 2432 BitTestCases[i].Parent = Last; 2433} 2434 2435void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2436 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2437 2438 // Figure out which block is immediately after the current one. 2439 MachineBasicBlock *NextBlock = 0; 2440 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2441 2442 // If there is only the default destination, branch to it if it is not the 2443 // next basic block. Otherwise, just fall through. 2444 if (SI.getNumOperands() == 2) { 2445 // Update machine-CFG edges. 2446 2447 // If this is not a fall-through branch, emit the branch. 2448 SwitchMBB->addSuccessor(Default); 2449 if (Default != NextBlock) 2450 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2451 MVT::Other, getControlRoot(), 2452 DAG.getBasicBlock(Default))); 2453 2454 return; 2455 } 2456 2457 // If there are any non-default case statements, create a vector of Cases 2458 // representing each one, and sort the vector so that we can efficiently 2459 // create a binary search tree from them. 2460 CaseVector Cases; 2461 size_t numCmps = Clusterify(Cases, SI); 2462 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2463 << ". Total compares: " << numCmps << '\n'); 2464 numCmps = 0; 2465 2466 // Get the Value to be switched on and default basic blocks, which will be 2467 // inserted into CaseBlock records, representing basic blocks in the binary 2468 // search tree. 2469 const Value *SV = SI.getOperand(0); 2470 2471 // Push the initial CaseRec onto the worklist 2472 CaseRecVector WorkList; 2473 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2474 CaseRange(Cases.begin(),Cases.end()))); 2475 2476 while (!WorkList.empty()) { 2477 // Grab a record representing a case range to process off the worklist 2478 CaseRec CR = WorkList.back(); 2479 WorkList.pop_back(); 2480 2481 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2482 continue; 2483 2484 // If the range has few cases (two or less) emit a series of specific 2485 // tests. 2486 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2487 continue; 2488 2489 // If the switch has more than 5 blocks, and at least 40% dense, and the 2490 // target supports indirect branches, then emit a jump table rather than 2491 // lowering the switch to a binary tree of conditional branches. 2492 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2493 continue; 2494 2495 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2496 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2497 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2498 } 2499} 2500 2501void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2502 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2503 2504 // Update machine-CFG edges with unique successors. 2505 SmallVector<BasicBlock*, 32> succs; 2506 succs.reserve(I.getNumSuccessors()); 2507 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2508 succs.push_back(I.getSuccessor(i)); 2509 array_pod_sort(succs.begin(), succs.end()); 2510 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2511 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2512 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2513 addSuccessorWithWeight(IndirectBrMBB, Succ); 2514 } 2515 2516 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2517 MVT::Other, getControlRoot(), 2518 getValue(I.getAddress()))); 2519} 2520 2521void SelectionDAGBuilder::visitFSub(const User &I) { 2522 // -0.0 - X --> fneg 2523 Type *Ty = I.getType(); 2524 if (isa<Constant>(I.getOperand(0)) && 2525 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2526 SDValue Op2 = getValue(I.getOperand(1)); 2527 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2528 Op2.getValueType(), Op2)); 2529 return; 2530 } 2531 2532 visitBinary(I, ISD::FSUB); 2533} 2534 2535void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2536 SDValue Op1 = getValue(I.getOperand(0)); 2537 SDValue Op2 = getValue(I.getOperand(1)); 2538 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2539 Op1.getValueType(), Op1, Op2)); 2540} 2541 2542void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2543 SDValue Op1 = getValue(I.getOperand(0)); 2544 SDValue Op2 = getValue(I.getOperand(1)); 2545 2546 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2547 2548 // Coerce the shift amount to the right type if we can. 2549 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2550 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2551 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2552 DebugLoc DL = getCurDebugLoc(); 2553 2554 // If the operand is smaller than the shift count type, promote it. 2555 if (ShiftSize > Op2Size) 2556 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2557 2558 // If the operand is larger than the shift count type but the shift 2559 // count type has enough bits to represent any shift value, truncate 2560 // it now. This is a common case and it exposes the truncate to 2561 // optimization early. 2562 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2563 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2564 // Otherwise we'll need to temporarily settle for some other convenient 2565 // type. Type legalization will make adjustments once the shiftee is split. 2566 else 2567 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2568 } 2569 2570 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2571 Op1.getValueType(), Op1, Op2)); 2572} 2573 2574void SelectionDAGBuilder::visitSDiv(const User &I) { 2575 SDValue Op1 = getValue(I.getOperand(0)); 2576 SDValue Op2 = getValue(I.getOperand(1)); 2577 2578 // Turn exact SDivs into multiplications. 2579 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2580 // exact bit. 2581 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2582 !isa<ConstantSDNode>(Op1) && 2583 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2584 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2585 else 2586 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2587 Op1, Op2)); 2588} 2589 2590void SelectionDAGBuilder::visitICmp(const User &I) { 2591 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2592 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2593 predicate = IC->getPredicate(); 2594 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2595 predicate = ICmpInst::Predicate(IC->getPredicate()); 2596 SDValue Op1 = getValue(I.getOperand(0)); 2597 SDValue Op2 = getValue(I.getOperand(1)); 2598 ISD::CondCode Opcode = getICmpCondCode(predicate); 2599 2600 EVT DestVT = TLI.getValueType(I.getType()); 2601 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2602} 2603 2604void SelectionDAGBuilder::visitFCmp(const User &I) { 2605 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2606 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2607 predicate = FC->getPredicate(); 2608 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2609 predicate = FCmpInst::Predicate(FC->getPredicate()); 2610 SDValue Op1 = getValue(I.getOperand(0)); 2611 SDValue Op2 = getValue(I.getOperand(1)); 2612 ISD::CondCode Condition = getFCmpCondCode(predicate); 2613 EVT DestVT = TLI.getValueType(I.getType()); 2614 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2615} 2616 2617void SelectionDAGBuilder::visitSelect(const User &I) { 2618 SmallVector<EVT, 4> ValueVTs; 2619 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2620 unsigned NumValues = ValueVTs.size(); 2621 if (NumValues == 0) return; 2622 2623 SmallVector<SDValue, 4> Values(NumValues); 2624 SDValue Cond = getValue(I.getOperand(0)); 2625 SDValue TrueVal = getValue(I.getOperand(1)); 2626 SDValue FalseVal = getValue(I.getOperand(2)); 2627 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2628 ISD::VSELECT : ISD::SELECT; 2629 2630 for (unsigned i = 0; i != NumValues; ++i) 2631 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2632 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2633 Cond, 2634 SDValue(TrueVal.getNode(), 2635 TrueVal.getResNo() + i), 2636 SDValue(FalseVal.getNode(), 2637 FalseVal.getResNo() + i)); 2638 2639 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2640 DAG.getVTList(&ValueVTs[0], NumValues), 2641 &Values[0], NumValues)); 2642} 2643 2644void SelectionDAGBuilder::visitTrunc(const User &I) { 2645 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2646 SDValue N = getValue(I.getOperand(0)); 2647 EVT DestVT = TLI.getValueType(I.getType()); 2648 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2649} 2650 2651void SelectionDAGBuilder::visitZExt(const User &I) { 2652 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2653 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2654 SDValue N = getValue(I.getOperand(0)); 2655 EVT DestVT = TLI.getValueType(I.getType()); 2656 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2657} 2658 2659void SelectionDAGBuilder::visitSExt(const User &I) { 2660 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2661 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2662 SDValue N = getValue(I.getOperand(0)); 2663 EVT DestVT = TLI.getValueType(I.getType()); 2664 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2665} 2666 2667void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2668 // FPTrunc is never a no-op cast, no need to check 2669 SDValue N = getValue(I.getOperand(0)); 2670 EVT DestVT = TLI.getValueType(I.getType()); 2671 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2672 DestVT, N, DAG.getIntPtrConstant(0))); 2673} 2674 2675void SelectionDAGBuilder::visitFPExt(const User &I){ 2676 // FPTrunc is never a no-op cast, no need to check 2677 SDValue N = getValue(I.getOperand(0)); 2678 EVT DestVT = TLI.getValueType(I.getType()); 2679 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2680} 2681 2682void SelectionDAGBuilder::visitFPToUI(const User &I) { 2683 // FPToUI is never a no-op cast, no need to check 2684 SDValue N = getValue(I.getOperand(0)); 2685 EVT DestVT = TLI.getValueType(I.getType()); 2686 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2687} 2688 2689void SelectionDAGBuilder::visitFPToSI(const User &I) { 2690 // FPToSI is never a no-op cast, no need to check 2691 SDValue N = getValue(I.getOperand(0)); 2692 EVT DestVT = TLI.getValueType(I.getType()); 2693 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2694} 2695 2696void SelectionDAGBuilder::visitUIToFP(const User &I) { 2697 // UIToFP is never a no-op cast, no need to check 2698 SDValue N = getValue(I.getOperand(0)); 2699 EVT DestVT = TLI.getValueType(I.getType()); 2700 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2701} 2702 2703void SelectionDAGBuilder::visitSIToFP(const User &I){ 2704 // SIToFP is never a no-op cast, no need to check 2705 SDValue N = getValue(I.getOperand(0)); 2706 EVT DestVT = TLI.getValueType(I.getType()); 2707 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2708} 2709 2710void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2711 // What to do depends on the size of the integer and the size of the pointer. 2712 // We can either truncate, zero extend, or no-op, accordingly. 2713 SDValue N = getValue(I.getOperand(0)); 2714 EVT DestVT = TLI.getValueType(I.getType()); 2715 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2716} 2717 2718void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2719 // What to do depends on the size of the integer and the size of the pointer. 2720 // We can either truncate, zero extend, or no-op, accordingly. 2721 SDValue N = getValue(I.getOperand(0)); 2722 EVT DestVT = TLI.getValueType(I.getType()); 2723 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2724} 2725 2726void SelectionDAGBuilder::visitBitCast(const User &I) { 2727 SDValue N = getValue(I.getOperand(0)); 2728 EVT DestVT = TLI.getValueType(I.getType()); 2729 2730 // BitCast assures us that source and destination are the same size so this is 2731 // either a BITCAST or a no-op. 2732 if (DestVT != N.getValueType()) 2733 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2734 DestVT, N)); // convert types. 2735 else 2736 setValue(&I, N); // noop cast. 2737} 2738 2739void SelectionDAGBuilder::visitInsertElement(const User &I) { 2740 SDValue InVec = getValue(I.getOperand(0)); 2741 SDValue InVal = getValue(I.getOperand(1)); 2742 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2743 TLI.getPointerTy(), 2744 getValue(I.getOperand(2))); 2745 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2746 TLI.getValueType(I.getType()), 2747 InVec, InVal, InIdx)); 2748} 2749 2750void SelectionDAGBuilder::visitExtractElement(const User &I) { 2751 SDValue InVec = getValue(I.getOperand(0)); 2752 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2753 TLI.getPointerTy(), 2754 getValue(I.getOperand(1))); 2755 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2756 TLI.getValueType(I.getType()), InVec, InIdx)); 2757} 2758 2759// Utility for visitShuffleVector - Returns true if the mask is mask starting 2760// from SIndx and increasing to the element length (undefs are allowed). 2761static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2762 unsigned MaskNumElts = Mask.size(); 2763 for (unsigned i = 0; i != MaskNumElts; ++i) 2764 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2765 return false; 2766 return true; 2767} 2768 2769void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2770 SmallVector<int, 8> Mask; 2771 SDValue Src1 = getValue(I.getOperand(0)); 2772 SDValue Src2 = getValue(I.getOperand(1)); 2773 2774 // Convert the ConstantVector mask operand into an array of ints, with -1 2775 // representing undef values. 2776 SmallVector<Constant*, 8> MaskElts; 2777 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2778 unsigned MaskNumElts = MaskElts.size(); 2779 for (unsigned i = 0; i != MaskNumElts; ++i) { 2780 if (isa<UndefValue>(MaskElts[i])) 2781 Mask.push_back(-1); 2782 else 2783 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2784 } 2785 2786 EVT VT = TLI.getValueType(I.getType()); 2787 EVT SrcVT = Src1.getValueType(); 2788 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2789 2790 if (SrcNumElts == MaskNumElts) { 2791 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2792 &Mask[0])); 2793 return; 2794 } 2795 2796 // Normalize the shuffle vector since mask and vector length don't match. 2797 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2798 // Mask is longer than the source vectors and is a multiple of the source 2799 // vectors. We can use concatenate vector to make the mask and vectors 2800 // lengths match. 2801 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2802 // The shuffle is concatenating two vectors together. 2803 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2804 VT, Src1, Src2)); 2805 return; 2806 } 2807 2808 // Pad both vectors with undefs to make them the same length as the mask. 2809 unsigned NumConcat = MaskNumElts / SrcNumElts; 2810 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2811 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2812 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2813 2814 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2815 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2816 MOps1[0] = Src1; 2817 MOps2[0] = Src2; 2818 2819 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2820 getCurDebugLoc(), VT, 2821 &MOps1[0], NumConcat); 2822 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2823 getCurDebugLoc(), VT, 2824 &MOps2[0], NumConcat); 2825 2826 // Readjust mask for new input vector length. 2827 SmallVector<int, 8> MappedOps; 2828 for (unsigned i = 0; i != MaskNumElts; ++i) { 2829 int Idx = Mask[i]; 2830 if (Idx < (int)SrcNumElts) 2831 MappedOps.push_back(Idx); 2832 else 2833 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2834 } 2835 2836 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2837 &MappedOps[0])); 2838 return; 2839 } 2840 2841 if (SrcNumElts > MaskNumElts) { 2842 // Analyze the access pattern of the vector to see if we can extract 2843 // two subvectors and do the shuffle. The analysis is done by calculating 2844 // the range of elements the mask access on both vectors. 2845 int MinRange[2] = { static_cast<int>(SrcNumElts+1), 2846 static_cast<int>(SrcNumElts+1)}; 2847 int MaxRange[2] = {-1, -1}; 2848 2849 for (unsigned i = 0; i != MaskNumElts; ++i) { 2850 int Idx = Mask[i]; 2851 int Input = 0; 2852 if (Idx < 0) 2853 continue; 2854 2855 if (Idx >= (int)SrcNumElts) { 2856 Input = 1; 2857 Idx -= SrcNumElts; 2858 } 2859 if (Idx > MaxRange[Input]) 2860 MaxRange[Input] = Idx; 2861 if (Idx < MinRange[Input]) 2862 MinRange[Input] = Idx; 2863 } 2864 2865 // Check if the access is smaller than the vector size and can we find 2866 // a reasonable extract index. 2867 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2868 // Extract. 2869 int StartIdx[2]; // StartIdx to extract from 2870 for (int Input=0; Input < 2; ++Input) { 2871 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2872 RangeUse[Input] = 0; // Unused 2873 StartIdx[Input] = 0; 2874 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2875 // Fits within range but we should see if we can find a good 2876 // start index that is a multiple of the mask length. 2877 if (MaxRange[Input] < (int)MaskNumElts) { 2878 RangeUse[Input] = 1; // Extract from beginning of the vector 2879 StartIdx[Input] = 0; 2880 } else { 2881 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2882 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2883 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2884 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2885 } 2886 } 2887 } 2888 2889 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2890 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2891 return; 2892 } 2893 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2894 // Extract appropriate subvector and generate a vector shuffle 2895 for (int Input=0; Input < 2; ++Input) { 2896 SDValue &Src = Input == 0 ? Src1 : Src2; 2897 if (RangeUse[Input] == 0) 2898 Src = DAG.getUNDEF(VT); 2899 else 2900 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2901 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2902 } 2903 2904 // Calculate new mask. 2905 SmallVector<int, 8> MappedOps; 2906 for (unsigned i = 0; i != MaskNumElts; ++i) { 2907 int Idx = Mask[i]; 2908 if (Idx < 0) 2909 MappedOps.push_back(Idx); 2910 else if (Idx < (int)SrcNumElts) 2911 MappedOps.push_back(Idx - StartIdx[0]); 2912 else 2913 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2914 } 2915 2916 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2917 &MappedOps[0])); 2918 return; 2919 } 2920 } 2921 2922 // We can't use either concat vectors or extract subvectors so fall back to 2923 // replacing the shuffle with extract and build vector. 2924 // to insert and build vector. 2925 EVT EltVT = VT.getVectorElementType(); 2926 EVT PtrVT = TLI.getPointerTy(); 2927 SmallVector<SDValue,8> Ops; 2928 for (unsigned i = 0; i != MaskNumElts; ++i) { 2929 if (Mask[i] < 0) { 2930 Ops.push_back(DAG.getUNDEF(EltVT)); 2931 } else { 2932 int Idx = Mask[i]; 2933 SDValue Res; 2934 2935 if (Idx < (int)SrcNumElts) 2936 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2937 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2938 else 2939 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2940 EltVT, Src2, 2941 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2942 2943 Ops.push_back(Res); 2944 } 2945 } 2946 2947 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2948 VT, &Ops[0], Ops.size())); 2949} 2950 2951void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2952 const Value *Op0 = I.getOperand(0); 2953 const Value *Op1 = I.getOperand(1); 2954 Type *AggTy = I.getType(); 2955 Type *ValTy = Op1->getType(); 2956 bool IntoUndef = isa<UndefValue>(Op0); 2957 bool FromUndef = isa<UndefValue>(Op1); 2958 2959 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2960 2961 SmallVector<EVT, 4> AggValueVTs; 2962 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2963 SmallVector<EVT, 4> ValValueVTs; 2964 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2965 2966 unsigned NumAggValues = AggValueVTs.size(); 2967 unsigned NumValValues = ValValueVTs.size(); 2968 SmallVector<SDValue, 4> Values(NumAggValues); 2969 2970 SDValue Agg = getValue(Op0); 2971 unsigned i = 0; 2972 // Copy the beginning value(s) from the original aggregate. 2973 for (; i != LinearIndex; ++i) 2974 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2975 SDValue(Agg.getNode(), Agg.getResNo() + i); 2976 // Copy values from the inserted value(s). 2977 if (NumValValues) { 2978 SDValue Val = getValue(Op1); 2979 for (; i != LinearIndex + NumValValues; ++i) 2980 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2981 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2982 } 2983 // Copy remaining value(s) from the original aggregate. 2984 for (; i != NumAggValues; ++i) 2985 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2986 SDValue(Agg.getNode(), Agg.getResNo() + i); 2987 2988 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2989 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2990 &Values[0], NumAggValues)); 2991} 2992 2993void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2994 const Value *Op0 = I.getOperand(0); 2995 Type *AggTy = Op0->getType(); 2996 Type *ValTy = I.getType(); 2997 bool OutOfUndef = isa<UndefValue>(Op0); 2998 2999 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3000 3001 SmallVector<EVT, 4> ValValueVTs; 3002 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3003 3004 unsigned NumValValues = ValValueVTs.size(); 3005 3006 // Ignore a extractvalue that produces an empty object 3007 if (!NumValValues) { 3008 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3009 return; 3010 } 3011 3012 SmallVector<SDValue, 4> Values(NumValValues); 3013 3014 SDValue Agg = getValue(Op0); 3015 // Copy out the selected value(s). 3016 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3017 Values[i - LinearIndex] = 3018 OutOfUndef ? 3019 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3020 SDValue(Agg.getNode(), Agg.getResNo() + i); 3021 3022 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3023 DAG.getVTList(&ValValueVTs[0], NumValValues), 3024 &Values[0], NumValValues)); 3025} 3026 3027void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3028 SDValue N = getValue(I.getOperand(0)); 3029 Type *Ty = I.getOperand(0)->getType(); 3030 3031 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3032 OI != E; ++OI) { 3033 const Value *Idx = *OI; 3034 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3035 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3036 if (Field) { 3037 // N = N + Offset 3038 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3039 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3040 DAG.getIntPtrConstant(Offset)); 3041 } 3042 3043 Ty = StTy->getElementType(Field); 3044 } else { 3045 Ty = cast<SequentialType>(Ty)->getElementType(); 3046 3047 // If this is a constant subscript, handle it quickly. 3048 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3049 if (CI->isZero()) continue; 3050 uint64_t Offs = 3051 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3052 SDValue OffsVal; 3053 EVT PTy = TLI.getPointerTy(); 3054 unsigned PtrBits = PTy.getSizeInBits(); 3055 if (PtrBits < 64) 3056 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3057 TLI.getPointerTy(), 3058 DAG.getConstant(Offs, MVT::i64)); 3059 else 3060 OffsVal = DAG.getIntPtrConstant(Offs); 3061 3062 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3063 OffsVal); 3064 continue; 3065 } 3066 3067 // N = N + Idx * ElementSize; 3068 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3069 TD->getTypeAllocSize(Ty)); 3070 SDValue IdxN = getValue(Idx); 3071 3072 // If the index is smaller or larger than intptr_t, truncate or extend 3073 // it. 3074 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3075 3076 // If this is a multiply by a power of two, turn it into a shl 3077 // immediately. This is a very common case. 3078 if (ElementSize != 1) { 3079 if (ElementSize.isPowerOf2()) { 3080 unsigned Amt = ElementSize.logBase2(); 3081 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3082 N.getValueType(), IdxN, 3083 DAG.getConstant(Amt, TLI.getPointerTy())); 3084 } else { 3085 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3086 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3087 N.getValueType(), IdxN, Scale); 3088 } 3089 } 3090 3091 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3092 N.getValueType(), N, IdxN); 3093 } 3094 } 3095 3096 setValue(&I, N); 3097} 3098 3099void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3100 // If this is a fixed sized alloca in the entry block of the function, 3101 // allocate it statically on the stack. 3102 if (FuncInfo.StaticAllocaMap.count(&I)) 3103 return; // getValue will auto-populate this. 3104 3105 Type *Ty = I.getAllocatedType(); 3106 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3107 unsigned Align = 3108 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3109 I.getAlignment()); 3110 3111 SDValue AllocSize = getValue(I.getArraySize()); 3112 3113 EVT IntPtr = TLI.getPointerTy(); 3114 if (AllocSize.getValueType() != IntPtr) 3115 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3116 3117 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3118 AllocSize, 3119 DAG.getConstant(TySize, IntPtr)); 3120 3121 // Handle alignment. If the requested alignment is less than or equal to 3122 // the stack alignment, ignore it. If the size is greater than or equal to 3123 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3124 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3125 if (Align <= StackAlign) 3126 Align = 0; 3127 3128 // Round the size of the allocation up to the stack alignment size 3129 // by add SA-1 to the size. 3130 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3131 AllocSize.getValueType(), AllocSize, 3132 DAG.getIntPtrConstant(StackAlign-1)); 3133 3134 // Mask out the low bits for alignment purposes. 3135 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3136 AllocSize.getValueType(), AllocSize, 3137 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3138 3139 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3140 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3141 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3142 VTs, Ops, 3); 3143 setValue(&I, DSA); 3144 DAG.setRoot(DSA.getValue(1)); 3145 3146 // Inform the Frame Information that we have just allocated a variable-sized 3147 // object. 3148 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3149} 3150 3151void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3152 if (I.isAtomic()) 3153 return visitAtomicLoad(I); 3154 3155 const Value *SV = I.getOperand(0); 3156 SDValue Ptr = getValue(SV); 3157 3158 Type *Ty = I.getType(); 3159 3160 bool isVolatile = I.isVolatile(); 3161 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3162 unsigned Alignment = I.getAlignment(); 3163 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3164 3165 SmallVector<EVT, 4> ValueVTs; 3166 SmallVector<uint64_t, 4> Offsets; 3167 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3168 unsigned NumValues = ValueVTs.size(); 3169 if (NumValues == 0) 3170 return; 3171 3172 SDValue Root; 3173 bool ConstantMemory = false; 3174 if (I.isVolatile() || NumValues > MaxParallelChains) 3175 // Serialize volatile loads with other side effects. 3176 Root = getRoot(); 3177 else if (AA->pointsToConstantMemory( 3178 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3179 // Do not serialize (non-volatile) loads of constant memory with anything. 3180 Root = DAG.getEntryNode(); 3181 ConstantMemory = true; 3182 } else { 3183 // Do not serialize non-volatile loads against each other. 3184 Root = DAG.getRoot(); 3185 } 3186 3187 SmallVector<SDValue, 4> Values(NumValues); 3188 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3189 NumValues)); 3190 EVT PtrVT = Ptr.getValueType(); 3191 unsigned ChainI = 0; 3192 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3193 // Serializing loads here may result in excessive register pressure, and 3194 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3195 // could recover a bit by hoisting nodes upward in the chain by recognizing 3196 // they are side-effect free or do not alias. The optimizer should really 3197 // avoid this case by converting large object/array copies to llvm.memcpy 3198 // (MaxParallelChains should always remain as failsafe). 3199 if (ChainI == MaxParallelChains) { 3200 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3201 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3202 MVT::Other, &Chains[0], ChainI); 3203 Root = Chain; 3204 ChainI = 0; 3205 } 3206 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3207 PtrVT, Ptr, 3208 DAG.getConstant(Offsets[i], PtrVT)); 3209 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3210 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3211 isNonTemporal, Alignment, TBAAInfo); 3212 3213 Values[i] = L; 3214 Chains[ChainI] = L.getValue(1); 3215 } 3216 3217 if (!ConstantMemory) { 3218 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3219 MVT::Other, &Chains[0], ChainI); 3220 if (isVolatile) 3221 DAG.setRoot(Chain); 3222 else 3223 PendingLoads.push_back(Chain); 3224 } 3225 3226 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3227 DAG.getVTList(&ValueVTs[0], NumValues), 3228 &Values[0], NumValues)); 3229} 3230 3231void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3232 if (I.isAtomic()) 3233 return visitAtomicStore(I); 3234 3235 const Value *SrcV = I.getOperand(0); 3236 const Value *PtrV = I.getOperand(1); 3237 3238 SmallVector<EVT, 4> ValueVTs; 3239 SmallVector<uint64_t, 4> Offsets; 3240 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3241 unsigned NumValues = ValueVTs.size(); 3242 if (NumValues == 0) 3243 return; 3244 3245 // Get the lowered operands. Note that we do this after 3246 // checking if NumResults is zero, because with zero results 3247 // the operands won't have values in the map. 3248 SDValue Src = getValue(SrcV); 3249 SDValue Ptr = getValue(PtrV); 3250 3251 SDValue Root = getRoot(); 3252 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3253 NumValues)); 3254 EVT PtrVT = Ptr.getValueType(); 3255 bool isVolatile = I.isVolatile(); 3256 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3257 unsigned Alignment = I.getAlignment(); 3258 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3259 3260 unsigned ChainI = 0; 3261 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3262 // See visitLoad comments. 3263 if (ChainI == MaxParallelChains) { 3264 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3265 MVT::Other, &Chains[0], ChainI); 3266 Root = Chain; 3267 ChainI = 0; 3268 } 3269 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3270 DAG.getConstant(Offsets[i], PtrVT)); 3271 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3272 SDValue(Src.getNode(), Src.getResNo() + i), 3273 Add, MachinePointerInfo(PtrV, Offsets[i]), 3274 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3275 Chains[ChainI] = St; 3276 } 3277 3278 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3279 MVT::Other, &Chains[0], ChainI); 3280 ++SDNodeOrder; 3281 AssignOrderingToNode(StoreNode.getNode()); 3282 DAG.setRoot(StoreNode); 3283} 3284 3285static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3286 SynchronizationScope Scope, 3287 bool Before, DebugLoc dl, 3288 SelectionDAG &DAG, 3289 const TargetLowering &TLI) { 3290 // Fence, if necessary 3291 if (Before) { 3292 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3293 Order = Release; 3294 else if (Order == Acquire || Order == Monotonic) 3295 return Chain; 3296 } else { 3297 if (Order == AcquireRelease) 3298 Order = Acquire; 3299 else if (Order == Release || Order == Monotonic) 3300 return Chain; 3301 } 3302 SDValue Ops[3]; 3303 Ops[0] = Chain; 3304 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3305 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3306 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3307} 3308 3309void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3310 DebugLoc dl = getCurDebugLoc(); 3311 AtomicOrdering Order = I.getOrdering(); 3312 SynchronizationScope Scope = I.getSynchScope(); 3313 3314 SDValue InChain = getRoot(); 3315 3316 if (TLI.getInsertFencesForAtomic()) 3317 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3318 DAG, TLI); 3319 3320 SDValue L = 3321 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3322 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3323 InChain, 3324 getValue(I.getPointerOperand()), 3325 getValue(I.getCompareOperand()), 3326 getValue(I.getNewValOperand()), 3327 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3328 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3329 Scope); 3330 3331 SDValue OutChain = L.getValue(1); 3332 3333 if (TLI.getInsertFencesForAtomic()) 3334 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3335 DAG, TLI); 3336 3337 setValue(&I, L); 3338 DAG.setRoot(OutChain); 3339} 3340 3341void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3342 DebugLoc dl = getCurDebugLoc(); 3343 ISD::NodeType NT; 3344 switch (I.getOperation()) { 3345 default: llvm_unreachable("Unknown atomicrmw operation"); return; 3346 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3347 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3348 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3349 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3350 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3351 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3352 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3353 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3354 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3355 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3356 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3357 } 3358 AtomicOrdering Order = I.getOrdering(); 3359 SynchronizationScope Scope = I.getSynchScope(); 3360 3361 SDValue InChain = getRoot(); 3362 3363 if (TLI.getInsertFencesForAtomic()) 3364 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3365 DAG, TLI); 3366 3367 SDValue L = 3368 DAG.getAtomic(NT, dl, 3369 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3370 InChain, 3371 getValue(I.getPointerOperand()), 3372 getValue(I.getValOperand()), 3373 I.getPointerOperand(), 0 /* Alignment */, 3374 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3375 Scope); 3376 3377 SDValue OutChain = L.getValue(1); 3378 3379 if (TLI.getInsertFencesForAtomic()) 3380 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3381 DAG, TLI); 3382 3383 setValue(&I, L); 3384 DAG.setRoot(OutChain); 3385} 3386 3387void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3388 DebugLoc dl = getCurDebugLoc(); 3389 SDValue Ops[3]; 3390 Ops[0] = getRoot(); 3391 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3392 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3393 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3394} 3395 3396void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3397 DebugLoc dl = getCurDebugLoc(); 3398 AtomicOrdering Order = I.getOrdering(); 3399 SynchronizationScope Scope = I.getSynchScope(); 3400 3401 SDValue InChain = getRoot(); 3402 3403 EVT VT = EVT::getEVT(I.getType()); 3404 3405 SDValue L = 3406 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3407 getValue(I.getPointerOperand()), 3408 I.getPointerOperand(), I.getAlignment(), 3409 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3410 Scope); 3411 3412 SDValue OutChain = L.getValue(1); 3413 3414 if (TLI.getInsertFencesForAtomic()) 3415 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3416 DAG, TLI); 3417 3418 setValue(&I, L); 3419 DAG.setRoot(OutChain); 3420} 3421 3422void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3423 DebugLoc dl = getCurDebugLoc(); 3424 3425 AtomicOrdering Order = I.getOrdering(); 3426 SynchronizationScope Scope = I.getSynchScope(); 3427 3428 SDValue InChain = getRoot(); 3429 3430 if (TLI.getInsertFencesForAtomic()) 3431 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3432 DAG, TLI); 3433 3434 SDValue OutChain = 3435 DAG.getAtomic(ISD::ATOMIC_STORE, dl, 3436 getValue(I.getValueOperand()).getValueType().getSimpleVT(), 3437 InChain, 3438 getValue(I.getPointerOperand()), 3439 getValue(I.getValueOperand()), 3440 I.getPointerOperand(), I.getAlignment(), 3441 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3442 Scope); 3443 3444 if (TLI.getInsertFencesForAtomic()) 3445 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3446 DAG, TLI); 3447 3448 DAG.setRoot(OutChain); 3449} 3450 3451/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3452/// node. 3453void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3454 unsigned Intrinsic) { 3455 bool HasChain = !I.doesNotAccessMemory(); 3456 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3457 3458 // Build the operand list. 3459 SmallVector<SDValue, 8> Ops; 3460 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3461 if (OnlyLoad) { 3462 // We don't need to serialize loads against other loads. 3463 Ops.push_back(DAG.getRoot()); 3464 } else { 3465 Ops.push_back(getRoot()); 3466 } 3467 } 3468 3469 // Info is set by getTgtMemInstrinsic 3470 TargetLowering::IntrinsicInfo Info; 3471 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3472 3473 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3474 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3475 Info.opc == ISD::INTRINSIC_W_CHAIN) 3476 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3477 3478 // Add all operands of the call to the operand list. 3479 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3480 SDValue Op = getValue(I.getArgOperand(i)); 3481 assert(TLI.isTypeLegal(Op.getValueType()) && 3482 "Intrinsic uses a non-legal type?"); 3483 Ops.push_back(Op); 3484 } 3485 3486 SmallVector<EVT, 4> ValueVTs; 3487 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3488#ifndef NDEBUG 3489 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3490 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3491 "Intrinsic uses a non-legal type?"); 3492 } 3493#endif // NDEBUG 3494 3495 if (HasChain) 3496 ValueVTs.push_back(MVT::Other); 3497 3498 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3499 3500 // Create the node. 3501 SDValue Result; 3502 if (IsTgtIntrinsic) { 3503 // This is target intrinsic that touches memory 3504 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3505 VTs, &Ops[0], Ops.size(), 3506 Info.memVT, 3507 MachinePointerInfo(Info.ptrVal, Info.offset), 3508 Info.align, Info.vol, 3509 Info.readMem, Info.writeMem); 3510 } else if (!HasChain) { 3511 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3512 VTs, &Ops[0], Ops.size()); 3513 } else if (!I.getType()->isVoidTy()) { 3514 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3515 VTs, &Ops[0], Ops.size()); 3516 } else { 3517 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3518 VTs, &Ops[0], Ops.size()); 3519 } 3520 3521 if (HasChain) { 3522 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3523 if (OnlyLoad) 3524 PendingLoads.push_back(Chain); 3525 else 3526 DAG.setRoot(Chain); 3527 } 3528 3529 if (!I.getType()->isVoidTy()) { 3530 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3531 EVT VT = TLI.getValueType(PTy); 3532 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3533 } 3534 3535 setValue(&I, Result); 3536 } 3537} 3538 3539/// GetSignificand - Get the significand and build it into a floating-point 3540/// number with exponent of 1: 3541/// 3542/// Op = (Op & 0x007fffff) | 0x3f800000; 3543/// 3544/// where Op is the hexidecimal representation of floating point value. 3545static SDValue 3546GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3547 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3548 DAG.getConstant(0x007fffff, MVT::i32)); 3549 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3550 DAG.getConstant(0x3f800000, MVT::i32)); 3551 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3552} 3553 3554/// GetExponent - Get the exponent: 3555/// 3556/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3557/// 3558/// where Op is the hexidecimal representation of floating point value. 3559static SDValue 3560GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3561 DebugLoc dl) { 3562 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3563 DAG.getConstant(0x7f800000, MVT::i32)); 3564 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3565 DAG.getConstant(23, TLI.getPointerTy())); 3566 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3567 DAG.getConstant(127, MVT::i32)); 3568 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3569} 3570 3571/// getF32Constant - Get 32-bit floating point constant. 3572static SDValue 3573getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3574 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3575} 3576 3577/// Inlined utility function to implement binary input atomic intrinsics for 3578/// visitIntrinsicCall: I is a call instruction 3579/// Op is the associated NodeType for I 3580const char * 3581SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3582 ISD::NodeType Op) { 3583 SDValue Root = getRoot(); 3584 SDValue L = 3585 DAG.getAtomic(Op, getCurDebugLoc(), 3586 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3587 Root, 3588 getValue(I.getArgOperand(0)), 3589 getValue(I.getArgOperand(1)), 3590 I.getArgOperand(0), 0 /* Alignment */, 3591 Monotonic, CrossThread); 3592 setValue(&I, L); 3593 DAG.setRoot(L.getValue(1)); 3594 return 0; 3595} 3596 3597// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3598const char * 3599SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3600 SDValue Op1 = getValue(I.getArgOperand(0)); 3601 SDValue Op2 = getValue(I.getArgOperand(1)); 3602 3603 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3604 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3605 return 0; 3606} 3607 3608/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3609/// limited-precision mode. 3610void 3611SelectionDAGBuilder::visitExp(const CallInst &I) { 3612 SDValue result; 3613 DebugLoc dl = getCurDebugLoc(); 3614 3615 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3616 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3617 SDValue Op = getValue(I.getArgOperand(0)); 3618 3619 // Put the exponent in the right bit position for later addition to the 3620 // final result: 3621 // 3622 // #define LOG2OFe 1.4426950f 3623 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3624 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3625 getF32Constant(DAG, 0x3fb8aa3b)); 3626 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3627 3628 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3629 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3630 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3631 3632 // IntegerPartOfX <<= 23; 3633 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3634 DAG.getConstant(23, TLI.getPointerTy())); 3635 3636 if (LimitFloatPrecision <= 6) { 3637 // For floating-point precision of 6: 3638 // 3639 // TwoToFractionalPartOfX = 3640 // 0.997535578f + 3641 // (0.735607626f + 0.252464424f * x) * x; 3642 // 3643 // error 0.0144103317, which is 6 bits 3644 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3645 getF32Constant(DAG, 0x3e814304)); 3646 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3647 getF32Constant(DAG, 0x3f3c50c8)); 3648 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3649 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3650 getF32Constant(DAG, 0x3f7f5e7e)); 3651 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3652 3653 // Add the exponent into the result in integer domain. 3654 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3655 TwoToFracPartOfX, IntegerPartOfX); 3656 3657 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3658 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3659 // For floating-point precision of 12: 3660 // 3661 // TwoToFractionalPartOfX = 3662 // 0.999892986f + 3663 // (0.696457318f + 3664 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3665 // 3666 // 0.000107046256 error, which is 13 to 14 bits 3667 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3668 getF32Constant(DAG, 0x3da235e3)); 3669 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3670 getF32Constant(DAG, 0x3e65b8f3)); 3671 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3672 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3673 getF32Constant(DAG, 0x3f324b07)); 3674 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3675 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3676 getF32Constant(DAG, 0x3f7ff8fd)); 3677 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3678 3679 // Add the exponent into the result in integer domain. 3680 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3681 TwoToFracPartOfX, IntegerPartOfX); 3682 3683 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3684 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3685 // For floating-point precision of 18: 3686 // 3687 // TwoToFractionalPartOfX = 3688 // 0.999999982f + 3689 // (0.693148872f + 3690 // (0.240227044f + 3691 // (0.554906021e-1f + 3692 // (0.961591928e-2f + 3693 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3694 // 3695 // error 2.47208000*10^(-7), which is better than 18 bits 3696 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3697 getF32Constant(DAG, 0x3924b03e)); 3698 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3699 getF32Constant(DAG, 0x3ab24b87)); 3700 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3701 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3702 getF32Constant(DAG, 0x3c1d8c17)); 3703 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3704 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3705 getF32Constant(DAG, 0x3d634a1d)); 3706 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3707 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3708 getF32Constant(DAG, 0x3e75fe14)); 3709 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3710 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3711 getF32Constant(DAG, 0x3f317234)); 3712 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3713 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3714 getF32Constant(DAG, 0x3f800000)); 3715 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3716 MVT::i32, t13); 3717 3718 // Add the exponent into the result in integer domain. 3719 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3720 TwoToFracPartOfX, IntegerPartOfX); 3721 3722 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3723 } 3724 } else { 3725 // No special expansion. 3726 result = DAG.getNode(ISD::FEXP, dl, 3727 getValue(I.getArgOperand(0)).getValueType(), 3728 getValue(I.getArgOperand(0))); 3729 } 3730 3731 setValue(&I, result); 3732} 3733 3734/// visitLog - Lower a log intrinsic. Handles the special sequences for 3735/// limited-precision mode. 3736void 3737SelectionDAGBuilder::visitLog(const CallInst &I) { 3738 SDValue result; 3739 DebugLoc dl = getCurDebugLoc(); 3740 3741 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3742 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3743 SDValue Op = getValue(I.getArgOperand(0)); 3744 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3745 3746 // Scale the exponent by log(2) [0.69314718f]. 3747 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3748 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3749 getF32Constant(DAG, 0x3f317218)); 3750 3751 // Get the significand and build it into a floating-point number with 3752 // exponent of 1. 3753 SDValue X = GetSignificand(DAG, Op1, dl); 3754 3755 if (LimitFloatPrecision <= 6) { 3756 // For floating-point precision of 6: 3757 // 3758 // LogofMantissa = 3759 // -1.1609546f + 3760 // (1.4034025f - 0.23903021f * x) * x; 3761 // 3762 // error 0.0034276066, which is better than 8 bits 3763 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3764 getF32Constant(DAG, 0xbe74c456)); 3765 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3766 getF32Constant(DAG, 0x3fb3a2b1)); 3767 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3768 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3769 getF32Constant(DAG, 0x3f949a29)); 3770 3771 result = DAG.getNode(ISD::FADD, dl, 3772 MVT::f32, LogOfExponent, LogOfMantissa); 3773 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3774 // For floating-point precision of 12: 3775 // 3776 // LogOfMantissa = 3777 // -1.7417939f + 3778 // (2.8212026f + 3779 // (-1.4699568f + 3780 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3781 // 3782 // error 0.000061011436, which is 14 bits 3783 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3784 getF32Constant(DAG, 0xbd67b6d6)); 3785 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3786 getF32Constant(DAG, 0x3ee4f4b8)); 3787 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3788 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3789 getF32Constant(DAG, 0x3fbc278b)); 3790 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3791 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3792 getF32Constant(DAG, 0x40348e95)); 3793 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3794 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3795 getF32Constant(DAG, 0x3fdef31a)); 3796 3797 result = DAG.getNode(ISD::FADD, dl, 3798 MVT::f32, LogOfExponent, LogOfMantissa); 3799 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3800 // For floating-point precision of 18: 3801 // 3802 // LogOfMantissa = 3803 // -2.1072184f + 3804 // (4.2372794f + 3805 // (-3.7029485f + 3806 // (2.2781945f + 3807 // (-0.87823314f + 3808 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3809 // 3810 // error 0.0000023660568, which is better than 18 bits 3811 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3812 getF32Constant(DAG, 0xbc91e5ac)); 3813 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3814 getF32Constant(DAG, 0x3e4350aa)); 3815 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3816 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3817 getF32Constant(DAG, 0x3f60d3e3)); 3818 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3819 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3820 getF32Constant(DAG, 0x4011cdf0)); 3821 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3822 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3823 getF32Constant(DAG, 0x406cfd1c)); 3824 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3825 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3826 getF32Constant(DAG, 0x408797cb)); 3827 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3828 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3829 getF32Constant(DAG, 0x4006dcab)); 3830 3831 result = DAG.getNode(ISD::FADD, dl, 3832 MVT::f32, LogOfExponent, LogOfMantissa); 3833 } 3834 } else { 3835 // No special expansion. 3836 result = DAG.getNode(ISD::FLOG, dl, 3837 getValue(I.getArgOperand(0)).getValueType(), 3838 getValue(I.getArgOperand(0))); 3839 } 3840 3841 setValue(&I, result); 3842} 3843 3844/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3845/// limited-precision mode. 3846void 3847SelectionDAGBuilder::visitLog2(const CallInst &I) { 3848 SDValue result; 3849 DebugLoc dl = getCurDebugLoc(); 3850 3851 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3852 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3853 SDValue Op = getValue(I.getArgOperand(0)); 3854 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3855 3856 // Get the exponent. 3857 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3858 3859 // Get the significand and build it into a floating-point number with 3860 // exponent of 1. 3861 SDValue X = GetSignificand(DAG, Op1, dl); 3862 3863 // Different possible minimax approximations of significand in 3864 // floating-point for various degrees of accuracy over [1,2]. 3865 if (LimitFloatPrecision <= 6) { 3866 // For floating-point precision of 6: 3867 // 3868 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3869 // 3870 // error 0.0049451742, which is more than 7 bits 3871 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3872 getF32Constant(DAG, 0xbeb08fe0)); 3873 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3874 getF32Constant(DAG, 0x40019463)); 3875 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3876 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3877 getF32Constant(DAG, 0x3fd6633d)); 3878 3879 result = DAG.getNode(ISD::FADD, dl, 3880 MVT::f32, LogOfExponent, Log2ofMantissa); 3881 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3882 // For floating-point precision of 12: 3883 // 3884 // Log2ofMantissa = 3885 // -2.51285454f + 3886 // (4.07009056f + 3887 // (-2.12067489f + 3888 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3889 // 3890 // error 0.0000876136000, which is better than 13 bits 3891 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3892 getF32Constant(DAG, 0xbda7262e)); 3893 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3894 getF32Constant(DAG, 0x3f25280b)); 3895 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3896 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3897 getF32Constant(DAG, 0x4007b923)); 3898 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3899 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3900 getF32Constant(DAG, 0x40823e2f)); 3901 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3902 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3903 getF32Constant(DAG, 0x4020d29c)); 3904 3905 result = DAG.getNode(ISD::FADD, dl, 3906 MVT::f32, LogOfExponent, Log2ofMantissa); 3907 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3908 // For floating-point precision of 18: 3909 // 3910 // Log2ofMantissa = 3911 // -3.0400495f + 3912 // (6.1129976f + 3913 // (-5.3420409f + 3914 // (3.2865683f + 3915 // (-1.2669343f + 3916 // (0.27515199f - 3917 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3918 // 3919 // error 0.0000018516, which is better than 18 bits 3920 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3921 getF32Constant(DAG, 0xbcd2769e)); 3922 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3923 getF32Constant(DAG, 0x3e8ce0b9)); 3924 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3925 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3926 getF32Constant(DAG, 0x3fa22ae7)); 3927 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3928 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3929 getF32Constant(DAG, 0x40525723)); 3930 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3931 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3932 getF32Constant(DAG, 0x40aaf200)); 3933 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3934 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3935 getF32Constant(DAG, 0x40c39dad)); 3936 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3937 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3938 getF32Constant(DAG, 0x4042902c)); 3939 3940 result = DAG.getNode(ISD::FADD, dl, 3941 MVT::f32, LogOfExponent, Log2ofMantissa); 3942 } 3943 } else { 3944 // No special expansion. 3945 result = DAG.getNode(ISD::FLOG2, dl, 3946 getValue(I.getArgOperand(0)).getValueType(), 3947 getValue(I.getArgOperand(0))); 3948 } 3949 3950 setValue(&I, result); 3951} 3952 3953/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3954/// limited-precision mode. 3955void 3956SelectionDAGBuilder::visitLog10(const CallInst &I) { 3957 SDValue result; 3958 DebugLoc dl = getCurDebugLoc(); 3959 3960 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3961 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3962 SDValue Op = getValue(I.getArgOperand(0)); 3963 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3964 3965 // Scale the exponent by log10(2) [0.30102999f]. 3966 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3967 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3968 getF32Constant(DAG, 0x3e9a209a)); 3969 3970 // Get the significand and build it into a floating-point number with 3971 // exponent of 1. 3972 SDValue X = GetSignificand(DAG, Op1, dl); 3973 3974 if (LimitFloatPrecision <= 6) { 3975 // For floating-point precision of 6: 3976 // 3977 // Log10ofMantissa = 3978 // -0.50419619f + 3979 // (0.60948995f - 0.10380950f * x) * x; 3980 // 3981 // error 0.0014886165, which is 6 bits 3982 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3983 getF32Constant(DAG, 0xbdd49a13)); 3984 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3985 getF32Constant(DAG, 0x3f1c0789)); 3986 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3987 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3988 getF32Constant(DAG, 0x3f011300)); 3989 3990 result = DAG.getNode(ISD::FADD, dl, 3991 MVT::f32, LogOfExponent, Log10ofMantissa); 3992 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3993 // For floating-point precision of 12: 3994 // 3995 // Log10ofMantissa = 3996 // -0.64831180f + 3997 // (0.91751397f + 3998 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3999 // 4000 // error 0.00019228036, which is better than 12 bits 4001 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4002 getF32Constant(DAG, 0x3d431f31)); 4003 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4004 getF32Constant(DAG, 0x3ea21fb2)); 4005 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4006 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4007 getF32Constant(DAG, 0x3f6ae232)); 4008 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4009 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4010 getF32Constant(DAG, 0x3f25f7c3)); 4011 4012 result = DAG.getNode(ISD::FADD, dl, 4013 MVT::f32, LogOfExponent, Log10ofMantissa); 4014 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4015 // For floating-point precision of 18: 4016 // 4017 // Log10ofMantissa = 4018 // -0.84299375f + 4019 // (1.5327582f + 4020 // (-1.0688956f + 4021 // (0.49102474f + 4022 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4023 // 4024 // error 0.0000037995730, which is better than 18 bits 4025 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4026 getF32Constant(DAG, 0x3c5d51ce)); 4027 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4028 getF32Constant(DAG, 0x3e00685a)); 4029 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4030 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4031 getF32Constant(DAG, 0x3efb6798)); 4032 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4033 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4034 getF32Constant(DAG, 0x3f88d192)); 4035 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4036 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4037 getF32Constant(DAG, 0x3fc4316c)); 4038 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4039 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4040 getF32Constant(DAG, 0x3f57ce70)); 4041 4042 result = DAG.getNode(ISD::FADD, dl, 4043 MVT::f32, LogOfExponent, Log10ofMantissa); 4044 } 4045 } else { 4046 // No special expansion. 4047 result = DAG.getNode(ISD::FLOG10, dl, 4048 getValue(I.getArgOperand(0)).getValueType(), 4049 getValue(I.getArgOperand(0))); 4050 } 4051 4052 setValue(&I, result); 4053} 4054 4055/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4056/// limited-precision mode. 4057void 4058SelectionDAGBuilder::visitExp2(const CallInst &I) { 4059 SDValue result; 4060 DebugLoc dl = getCurDebugLoc(); 4061 4062 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4063 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4064 SDValue Op = getValue(I.getArgOperand(0)); 4065 4066 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4067 4068 // FractionalPartOfX = x - (float)IntegerPartOfX; 4069 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4070 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4071 4072 // IntegerPartOfX <<= 23; 4073 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4074 DAG.getConstant(23, TLI.getPointerTy())); 4075 4076 if (LimitFloatPrecision <= 6) { 4077 // For floating-point precision of 6: 4078 // 4079 // TwoToFractionalPartOfX = 4080 // 0.997535578f + 4081 // (0.735607626f + 0.252464424f * x) * x; 4082 // 4083 // error 0.0144103317, which is 6 bits 4084 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4085 getF32Constant(DAG, 0x3e814304)); 4086 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4087 getF32Constant(DAG, 0x3f3c50c8)); 4088 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4089 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4090 getF32Constant(DAG, 0x3f7f5e7e)); 4091 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4092 SDValue TwoToFractionalPartOfX = 4093 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4094 4095 result = DAG.getNode(ISD::BITCAST, dl, 4096 MVT::f32, TwoToFractionalPartOfX); 4097 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4098 // For floating-point precision of 12: 4099 // 4100 // TwoToFractionalPartOfX = 4101 // 0.999892986f + 4102 // (0.696457318f + 4103 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4104 // 4105 // error 0.000107046256, which is 13 to 14 bits 4106 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4107 getF32Constant(DAG, 0x3da235e3)); 4108 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4109 getF32Constant(DAG, 0x3e65b8f3)); 4110 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4111 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4112 getF32Constant(DAG, 0x3f324b07)); 4113 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4114 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4115 getF32Constant(DAG, 0x3f7ff8fd)); 4116 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4117 SDValue TwoToFractionalPartOfX = 4118 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4119 4120 result = DAG.getNode(ISD::BITCAST, dl, 4121 MVT::f32, TwoToFractionalPartOfX); 4122 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4123 // For floating-point precision of 18: 4124 // 4125 // TwoToFractionalPartOfX = 4126 // 0.999999982f + 4127 // (0.693148872f + 4128 // (0.240227044f + 4129 // (0.554906021e-1f + 4130 // (0.961591928e-2f + 4131 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4132 // error 2.47208000*10^(-7), which is better than 18 bits 4133 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4134 getF32Constant(DAG, 0x3924b03e)); 4135 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4136 getF32Constant(DAG, 0x3ab24b87)); 4137 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4138 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4139 getF32Constant(DAG, 0x3c1d8c17)); 4140 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4141 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4142 getF32Constant(DAG, 0x3d634a1d)); 4143 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4144 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4145 getF32Constant(DAG, 0x3e75fe14)); 4146 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4147 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4148 getF32Constant(DAG, 0x3f317234)); 4149 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4150 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4151 getF32Constant(DAG, 0x3f800000)); 4152 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4153 SDValue TwoToFractionalPartOfX = 4154 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4155 4156 result = DAG.getNode(ISD::BITCAST, dl, 4157 MVT::f32, TwoToFractionalPartOfX); 4158 } 4159 } else { 4160 // No special expansion. 4161 result = DAG.getNode(ISD::FEXP2, dl, 4162 getValue(I.getArgOperand(0)).getValueType(), 4163 getValue(I.getArgOperand(0))); 4164 } 4165 4166 setValue(&I, result); 4167} 4168 4169/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4170/// limited-precision mode with x == 10.0f. 4171void 4172SelectionDAGBuilder::visitPow(const CallInst &I) { 4173 SDValue result; 4174 const Value *Val = I.getArgOperand(0); 4175 DebugLoc dl = getCurDebugLoc(); 4176 bool IsExp10 = false; 4177 4178 if (getValue(Val).getValueType() == MVT::f32 && 4179 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4180 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4181 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4182 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4183 APFloat Ten(10.0f); 4184 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4185 } 4186 } 4187 } 4188 4189 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4190 SDValue Op = getValue(I.getArgOperand(1)); 4191 4192 // Put the exponent in the right bit position for later addition to the 4193 // final result: 4194 // 4195 // #define LOG2OF10 3.3219281f 4196 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4197 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4198 getF32Constant(DAG, 0x40549a78)); 4199 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4200 4201 // FractionalPartOfX = x - (float)IntegerPartOfX; 4202 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4203 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4204 4205 // IntegerPartOfX <<= 23; 4206 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4207 DAG.getConstant(23, TLI.getPointerTy())); 4208 4209 if (LimitFloatPrecision <= 6) { 4210 // For floating-point precision of 6: 4211 // 4212 // twoToFractionalPartOfX = 4213 // 0.997535578f + 4214 // (0.735607626f + 0.252464424f * x) * x; 4215 // 4216 // error 0.0144103317, which is 6 bits 4217 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4218 getF32Constant(DAG, 0x3e814304)); 4219 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4220 getF32Constant(DAG, 0x3f3c50c8)); 4221 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4222 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4223 getF32Constant(DAG, 0x3f7f5e7e)); 4224 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4225 SDValue TwoToFractionalPartOfX = 4226 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4227 4228 result = DAG.getNode(ISD::BITCAST, dl, 4229 MVT::f32, TwoToFractionalPartOfX); 4230 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4231 // For floating-point precision of 12: 4232 // 4233 // TwoToFractionalPartOfX = 4234 // 0.999892986f + 4235 // (0.696457318f + 4236 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4237 // 4238 // error 0.000107046256, which is 13 to 14 bits 4239 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4240 getF32Constant(DAG, 0x3da235e3)); 4241 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4242 getF32Constant(DAG, 0x3e65b8f3)); 4243 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4244 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4245 getF32Constant(DAG, 0x3f324b07)); 4246 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4247 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4248 getF32Constant(DAG, 0x3f7ff8fd)); 4249 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4250 SDValue TwoToFractionalPartOfX = 4251 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4252 4253 result = DAG.getNode(ISD::BITCAST, dl, 4254 MVT::f32, TwoToFractionalPartOfX); 4255 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4256 // For floating-point precision of 18: 4257 // 4258 // TwoToFractionalPartOfX = 4259 // 0.999999982f + 4260 // (0.693148872f + 4261 // (0.240227044f + 4262 // (0.554906021e-1f + 4263 // (0.961591928e-2f + 4264 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4265 // error 2.47208000*10^(-7), which is better than 18 bits 4266 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4267 getF32Constant(DAG, 0x3924b03e)); 4268 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4269 getF32Constant(DAG, 0x3ab24b87)); 4270 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4271 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4272 getF32Constant(DAG, 0x3c1d8c17)); 4273 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4274 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4275 getF32Constant(DAG, 0x3d634a1d)); 4276 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4277 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4278 getF32Constant(DAG, 0x3e75fe14)); 4279 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4280 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4281 getF32Constant(DAG, 0x3f317234)); 4282 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4283 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4284 getF32Constant(DAG, 0x3f800000)); 4285 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4286 SDValue TwoToFractionalPartOfX = 4287 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4288 4289 result = DAG.getNode(ISD::BITCAST, dl, 4290 MVT::f32, TwoToFractionalPartOfX); 4291 } 4292 } else { 4293 // No special expansion. 4294 result = DAG.getNode(ISD::FPOW, dl, 4295 getValue(I.getArgOperand(0)).getValueType(), 4296 getValue(I.getArgOperand(0)), 4297 getValue(I.getArgOperand(1))); 4298 } 4299 4300 setValue(&I, result); 4301} 4302 4303 4304/// ExpandPowI - Expand a llvm.powi intrinsic. 4305static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4306 SelectionDAG &DAG) { 4307 // If RHS is a constant, we can expand this out to a multiplication tree, 4308 // otherwise we end up lowering to a call to __powidf2 (for example). When 4309 // optimizing for size, we only want to do this if the expansion would produce 4310 // a small number of multiplies, otherwise we do the full expansion. 4311 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4312 // Get the exponent as a positive value. 4313 unsigned Val = RHSC->getSExtValue(); 4314 if ((int)Val < 0) Val = -Val; 4315 4316 // powi(x, 0) -> 1.0 4317 if (Val == 0) 4318 return DAG.getConstantFP(1.0, LHS.getValueType()); 4319 4320 const Function *F = DAG.getMachineFunction().getFunction(); 4321 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4322 // If optimizing for size, don't insert too many multiplies. This 4323 // inserts up to 5 multiplies. 4324 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4325 // We use the simple binary decomposition method to generate the multiply 4326 // sequence. There are more optimal ways to do this (for example, 4327 // powi(x,15) generates one more multiply than it should), but this has 4328 // the benefit of being both really simple and much better than a libcall. 4329 SDValue Res; // Logically starts equal to 1.0 4330 SDValue CurSquare = LHS; 4331 while (Val) { 4332 if (Val & 1) { 4333 if (Res.getNode()) 4334 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4335 else 4336 Res = CurSquare; // 1.0*CurSquare. 4337 } 4338 4339 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4340 CurSquare, CurSquare); 4341 Val >>= 1; 4342 } 4343 4344 // If the original was negative, invert the result, producing 1/(x*x*x). 4345 if (RHSC->getSExtValue() < 0) 4346 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4347 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4348 return Res; 4349 } 4350 } 4351 4352 // Otherwise, expand to a libcall. 4353 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4354} 4355 4356// getTruncatedArgReg - Find underlying register used for an truncated 4357// argument. 4358static unsigned getTruncatedArgReg(const SDValue &N) { 4359 if (N.getOpcode() != ISD::TRUNCATE) 4360 return 0; 4361 4362 const SDValue &Ext = N.getOperand(0); 4363 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4364 const SDValue &CFR = Ext.getOperand(0); 4365 if (CFR.getOpcode() == ISD::CopyFromReg) 4366 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4367 else 4368 if (CFR.getOpcode() == ISD::TRUNCATE) 4369 return getTruncatedArgReg(CFR); 4370 } 4371 return 0; 4372} 4373 4374/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4375/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4376/// At the end of instruction selection, they will be inserted to the entry BB. 4377bool 4378SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4379 int64_t Offset, 4380 const SDValue &N) { 4381 const Argument *Arg = dyn_cast<Argument>(V); 4382 if (!Arg) 4383 return false; 4384 4385 MachineFunction &MF = DAG.getMachineFunction(); 4386 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4387 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4388 4389 // Ignore inlined function arguments here. 4390 DIVariable DV(Variable); 4391 if (DV.isInlinedFnArgument(MF.getFunction())) 4392 return false; 4393 4394 unsigned Reg = 0; 4395 // Some arguments' frame index is recorded during argument lowering. 4396 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4397 if (Offset) 4398 Reg = TRI->getFrameRegister(MF); 4399 4400 if (!Reg && N.getNode()) { 4401 if (N.getOpcode() == ISD::CopyFromReg) 4402 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4403 else 4404 Reg = getTruncatedArgReg(N); 4405 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4406 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4407 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4408 if (PR) 4409 Reg = PR; 4410 } 4411 } 4412 4413 if (!Reg) { 4414 // Check if ValueMap has reg number. 4415 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4416 if (VMI != FuncInfo.ValueMap.end()) 4417 Reg = VMI->second; 4418 } 4419 4420 if (!Reg && N.getNode()) { 4421 // Check if frame index is available. 4422 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4423 if (FrameIndexSDNode *FINode = 4424 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4425 Reg = TRI->getFrameRegister(MF); 4426 Offset = FINode->getIndex(); 4427 } 4428 } 4429 4430 if (!Reg) 4431 return false; 4432 4433 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4434 TII->get(TargetOpcode::DBG_VALUE)) 4435 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4436 FuncInfo.ArgDbgValues.push_back(&*MIB); 4437 return true; 4438} 4439 4440// VisualStudio defines setjmp as _setjmp 4441#if defined(_MSC_VER) && defined(setjmp) && \ 4442 !defined(setjmp_undefined_for_msvc) 4443# pragma push_macro("setjmp") 4444# undef setjmp 4445# define setjmp_undefined_for_msvc 4446#endif 4447 4448/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4449/// we want to emit this as a call to a named external function, return the name 4450/// otherwise lower it and return null. 4451const char * 4452SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4453 DebugLoc dl = getCurDebugLoc(); 4454 SDValue Res; 4455 4456 switch (Intrinsic) { 4457 default: 4458 // By default, turn this into a target intrinsic node. 4459 visitTargetIntrinsic(I, Intrinsic); 4460 return 0; 4461 case Intrinsic::vastart: visitVAStart(I); return 0; 4462 case Intrinsic::vaend: visitVAEnd(I); return 0; 4463 case Intrinsic::vacopy: visitVACopy(I); return 0; 4464 case Intrinsic::returnaddress: 4465 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4466 getValue(I.getArgOperand(0)))); 4467 return 0; 4468 case Intrinsic::frameaddress: 4469 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4470 getValue(I.getArgOperand(0)))); 4471 return 0; 4472 case Intrinsic::setjmp: 4473 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4474 case Intrinsic::longjmp: 4475 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4476 case Intrinsic::memcpy: { 4477 // Assert for address < 256 since we support only user defined address 4478 // spaces. 4479 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4480 < 256 && 4481 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4482 < 256 && 4483 "Unknown address space"); 4484 SDValue Op1 = getValue(I.getArgOperand(0)); 4485 SDValue Op2 = getValue(I.getArgOperand(1)); 4486 SDValue Op3 = getValue(I.getArgOperand(2)); 4487 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4488 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4489 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4490 MachinePointerInfo(I.getArgOperand(0)), 4491 MachinePointerInfo(I.getArgOperand(1)))); 4492 return 0; 4493 } 4494 case Intrinsic::memset: { 4495 // Assert for address < 256 since we support only user defined address 4496 // spaces. 4497 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4498 < 256 && 4499 "Unknown address space"); 4500 SDValue Op1 = getValue(I.getArgOperand(0)); 4501 SDValue Op2 = getValue(I.getArgOperand(1)); 4502 SDValue Op3 = getValue(I.getArgOperand(2)); 4503 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4504 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4505 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4506 MachinePointerInfo(I.getArgOperand(0)))); 4507 return 0; 4508 } 4509 case Intrinsic::memmove: { 4510 // Assert for address < 256 since we support only user defined address 4511 // spaces. 4512 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4513 < 256 && 4514 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4515 < 256 && 4516 "Unknown address space"); 4517 SDValue Op1 = getValue(I.getArgOperand(0)); 4518 SDValue Op2 = getValue(I.getArgOperand(1)); 4519 SDValue Op3 = getValue(I.getArgOperand(2)); 4520 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4521 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4522 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4523 MachinePointerInfo(I.getArgOperand(0)), 4524 MachinePointerInfo(I.getArgOperand(1)))); 4525 return 0; 4526 } 4527 case Intrinsic::dbg_declare: { 4528 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4529 MDNode *Variable = DI.getVariable(); 4530 const Value *Address = DI.getAddress(); 4531 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4532 return 0; 4533 4534 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4535 // but do not always have a corresponding SDNode built. The SDNodeOrder 4536 // absolute, but not relative, values are different depending on whether 4537 // debug info exists. 4538 ++SDNodeOrder; 4539 4540 // Check if address has undef value. 4541 if (isa<UndefValue>(Address) || 4542 (Address->use_empty() && !isa<Argument>(Address))) { 4543 DEBUG(dbgs() << "Dropping debug info for " << DI); 4544 return 0; 4545 } 4546 4547 SDValue &N = NodeMap[Address]; 4548 if (!N.getNode() && isa<Argument>(Address)) 4549 // Check unused arguments map. 4550 N = UnusedArgNodeMap[Address]; 4551 SDDbgValue *SDV; 4552 if (N.getNode()) { 4553 // Parameters are handled specially. 4554 bool isParameter = 4555 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4556 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4557 Address = BCI->getOperand(0); 4558 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4559 4560 if (isParameter && !AI) { 4561 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4562 if (FINode) 4563 // Byval parameter. We have a frame index at this point. 4564 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4565 0, dl, SDNodeOrder); 4566 else { 4567 // Address is an argument, so try to emit its dbg value using 4568 // virtual register info from the FuncInfo.ValueMap. 4569 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4570 return 0; 4571 } 4572 } else if (AI) 4573 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4574 0, dl, SDNodeOrder); 4575 else { 4576 // Can't do anything with other non-AI cases yet. 4577 DEBUG(dbgs() << "Dropping debug info for " << DI); 4578 return 0; 4579 } 4580 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4581 } else { 4582 // If Address is an argument then try to emit its dbg value using 4583 // virtual register info from the FuncInfo.ValueMap. 4584 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4585 // If variable is pinned by a alloca in dominating bb then 4586 // use StaticAllocaMap. 4587 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4588 if (AI->getParent() != DI.getParent()) { 4589 DenseMap<const AllocaInst*, int>::iterator SI = 4590 FuncInfo.StaticAllocaMap.find(AI); 4591 if (SI != FuncInfo.StaticAllocaMap.end()) { 4592 SDV = DAG.getDbgValue(Variable, SI->second, 4593 0, dl, SDNodeOrder); 4594 DAG.AddDbgValue(SDV, 0, false); 4595 return 0; 4596 } 4597 } 4598 } 4599 DEBUG(dbgs() << "Dropping debug info for " << DI); 4600 } 4601 } 4602 return 0; 4603 } 4604 case Intrinsic::dbg_value: { 4605 const DbgValueInst &DI = cast<DbgValueInst>(I); 4606 if (!DIVariable(DI.getVariable()).Verify()) 4607 return 0; 4608 4609 MDNode *Variable = DI.getVariable(); 4610 uint64_t Offset = DI.getOffset(); 4611 const Value *V = DI.getValue(); 4612 if (!V) 4613 return 0; 4614 4615 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4616 // but do not always have a corresponding SDNode built. The SDNodeOrder 4617 // absolute, but not relative, values are different depending on whether 4618 // debug info exists. 4619 ++SDNodeOrder; 4620 SDDbgValue *SDV; 4621 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4622 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4623 DAG.AddDbgValue(SDV, 0, false); 4624 } else { 4625 // Do not use getValue() in here; we don't want to generate code at 4626 // this point if it hasn't been done yet. 4627 SDValue N = NodeMap[V]; 4628 if (!N.getNode() && isa<Argument>(V)) 4629 // Check unused arguments map. 4630 N = UnusedArgNodeMap[V]; 4631 if (N.getNode()) { 4632 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4633 SDV = DAG.getDbgValue(Variable, N.getNode(), 4634 N.getResNo(), Offset, dl, SDNodeOrder); 4635 DAG.AddDbgValue(SDV, N.getNode(), false); 4636 } 4637 } else if (!V->use_empty() ) { 4638 // Do not call getValue(V) yet, as we don't want to generate code. 4639 // Remember it for later. 4640 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4641 DanglingDebugInfoMap[V] = DDI; 4642 } else { 4643 // We may expand this to cover more cases. One case where we have no 4644 // data available is an unreferenced parameter. 4645 DEBUG(dbgs() << "Dropping debug info for " << DI); 4646 } 4647 } 4648 4649 // Build a debug info table entry. 4650 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4651 V = BCI->getOperand(0); 4652 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4653 // Don't handle byval struct arguments or VLAs, for example. 4654 if (!AI) 4655 return 0; 4656 DenseMap<const AllocaInst*, int>::iterator SI = 4657 FuncInfo.StaticAllocaMap.find(AI); 4658 if (SI == FuncInfo.StaticAllocaMap.end()) 4659 return 0; // VLAs. 4660 int FI = SI->second; 4661 4662 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4663 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4664 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4665 return 0; 4666 } 4667 case Intrinsic::eh_exception: { 4668 // Insert the EXCEPTIONADDR instruction. 4669 assert(FuncInfo.MBB->isLandingPad() && 4670 "Call to eh.exception not in landing pad!"); 4671 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4672 SDValue Ops[1]; 4673 Ops[0] = DAG.getRoot(); 4674 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4675 setValue(&I, Op); 4676 DAG.setRoot(Op.getValue(1)); 4677 return 0; 4678 } 4679 4680 case Intrinsic::eh_selector: { 4681 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4682 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4683 if (CallMBB->isLandingPad()) 4684 AddCatchInfo(I, &MMI, CallMBB); 4685 else { 4686#ifndef NDEBUG 4687 FuncInfo.CatchInfoLost.insert(&I); 4688#endif 4689 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4690 unsigned Reg = TLI.getExceptionSelectorRegister(); 4691 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4692 } 4693 4694 // Insert the EHSELECTION instruction. 4695 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4696 SDValue Ops[2]; 4697 Ops[0] = getValue(I.getArgOperand(0)); 4698 Ops[1] = getRoot(); 4699 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4700 DAG.setRoot(Op.getValue(1)); 4701 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4702 return 0; 4703 } 4704 4705 case Intrinsic::eh_typeid_for: { 4706 // Find the type id for the given typeinfo. 4707 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4708 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4709 Res = DAG.getConstant(TypeID, MVT::i32); 4710 setValue(&I, Res); 4711 return 0; 4712 } 4713 4714 case Intrinsic::eh_return_i32: 4715 case Intrinsic::eh_return_i64: 4716 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4717 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4718 MVT::Other, 4719 getControlRoot(), 4720 getValue(I.getArgOperand(0)), 4721 getValue(I.getArgOperand(1)))); 4722 return 0; 4723 case Intrinsic::eh_unwind_init: 4724 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4725 return 0; 4726 case Intrinsic::eh_dwarf_cfa: { 4727 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4728 TLI.getPointerTy()); 4729 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4730 TLI.getPointerTy(), 4731 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4732 TLI.getPointerTy()), 4733 CfaArg); 4734 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4735 TLI.getPointerTy(), 4736 DAG.getConstant(0, TLI.getPointerTy())); 4737 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4738 FA, Offset)); 4739 return 0; 4740 } 4741 case Intrinsic::eh_sjlj_callsite: { 4742 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4743 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4744 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4745 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4746 4747 MMI.setCurrentCallSite(CI->getZExtValue()); 4748 return 0; 4749 } 4750 case Intrinsic::eh_sjlj_setjmp: { 4751 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4752 getValue(I.getArgOperand(0)))); 4753 return 0; 4754 } 4755 case Intrinsic::eh_sjlj_longjmp: { 4756 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4757 getRoot(), getValue(I.getArgOperand(0)))); 4758 return 0; 4759 } 4760 case Intrinsic::eh_sjlj_dispatch_setup: { 4761 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4762 getRoot(), getValue(I.getArgOperand(0)))); 4763 return 0; 4764 } 4765 4766 case Intrinsic::x86_mmx_pslli_w: 4767 case Intrinsic::x86_mmx_pslli_d: 4768 case Intrinsic::x86_mmx_pslli_q: 4769 case Intrinsic::x86_mmx_psrli_w: 4770 case Intrinsic::x86_mmx_psrli_d: 4771 case Intrinsic::x86_mmx_psrli_q: 4772 case Intrinsic::x86_mmx_psrai_w: 4773 case Intrinsic::x86_mmx_psrai_d: { 4774 SDValue ShAmt = getValue(I.getArgOperand(1)); 4775 if (isa<ConstantSDNode>(ShAmt)) { 4776 visitTargetIntrinsic(I, Intrinsic); 4777 return 0; 4778 } 4779 unsigned NewIntrinsic = 0; 4780 EVT ShAmtVT = MVT::v2i32; 4781 switch (Intrinsic) { 4782 case Intrinsic::x86_mmx_pslli_w: 4783 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4784 break; 4785 case Intrinsic::x86_mmx_pslli_d: 4786 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4787 break; 4788 case Intrinsic::x86_mmx_pslli_q: 4789 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4790 break; 4791 case Intrinsic::x86_mmx_psrli_w: 4792 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4793 break; 4794 case Intrinsic::x86_mmx_psrli_d: 4795 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4796 break; 4797 case Intrinsic::x86_mmx_psrli_q: 4798 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4799 break; 4800 case Intrinsic::x86_mmx_psrai_w: 4801 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4802 break; 4803 case Intrinsic::x86_mmx_psrai_d: 4804 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4805 break; 4806 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4807 } 4808 4809 // The vector shift intrinsics with scalars uses 32b shift amounts but 4810 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4811 // to be zero. 4812 // We must do this early because v2i32 is not a legal type. 4813 DebugLoc dl = getCurDebugLoc(); 4814 SDValue ShOps[2]; 4815 ShOps[0] = ShAmt; 4816 ShOps[1] = DAG.getConstant(0, MVT::i32); 4817 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4818 EVT DestVT = TLI.getValueType(I.getType()); 4819 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4820 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4821 DAG.getConstant(NewIntrinsic, MVT::i32), 4822 getValue(I.getArgOperand(0)), ShAmt); 4823 setValue(&I, Res); 4824 return 0; 4825 } 4826 case Intrinsic::convertff: 4827 case Intrinsic::convertfsi: 4828 case Intrinsic::convertfui: 4829 case Intrinsic::convertsif: 4830 case Intrinsic::convertuif: 4831 case Intrinsic::convertss: 4832 case Intrinsic::convertsu: 4833 case Intrinsic::convertus: 4834 case Intrinsic::convertuu: { 4835 ISD::CvtCode Code = ISD::CVT_INVALID; 4836 switch (Intrinsic) { 4837 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4838 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4839 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4840 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4841 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4842 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4843 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4844 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4845 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4846 } 4847 EVT DestVT = TLI.getValueType(I.getType()); 4848 const Value *Op1 = I.getArgOperand(0); 4849 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4850 DAG.getValueType(DestVT), 4851 DAG.getValueType(getValue(Op1).getValueType()), 4852 getValue(I.getArgOperand(1)), 4853 getValue(I.getArgOperand(2)), 4854 Code); 4855 setValue(&I, Res); 4856 return 0; 4857 } 4858 case Intrinsic::sqrt: 4859 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4860 getValue(I.getArgOperand(0)).getValueType(), 4861 getValue(I.getArgOperand(0)))); 4862 return 0; 4863 case Intrinsic::powi: 4864 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4865 getValue(I.getArgOperand(1)), DAG)); 4866 return 0; 4867 case Intrinsic::sin: 4868 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4869 getValue(I.getArgOperand(0)).getValueType(), 4870 getValue(I.getArgOperand(0)))); 4871 return 0; 4872 case Intrinsic::cos: 4873 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4874 getValue(I.getArgOperand(0)).getValueType(), 4875 getValue(I.getArgOperand(0)))); 4876 return 0; 4877 case Intrinsic::log: 4878 visitLog(I); 4879 return 0; 4880 case Intrinsic::log2: 4881 visitLog2(I); 4882 return 0; 4883 case Intrinsic::log10: 4884 visitLog10(I); 4885 return 0; 4886 case Intrinsic::exp: 4887 visitExp(I); 4888 return 0; 4889 case Intrinsic::exp2: 4890 visitExp2(I); 4891 return 0; 4892 case Intrinsic::pow: 4893 visitPow(I); 4894 return 0; 4895 case Intrinsic::fma: 4896 setValue(&I, DAG.getNode(ISD::FMA, dl, 4897 getValue(I.getArgOperand(0)).getValueType(), 4898 getValue(I.getArgOperand(0)), 4899 getValue(I.getArgOperand(1)), 4900 getValue(I.getArgOperand(2)))); 4901 return 0; 4902 case Intrinsic::convert_to_fp16: 4903 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4904 MVT::i16, getValue(I.getArgOperand(0)))); 4905 return 0; 4906 case Intrinsic::convert_from_fp16: 4907 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4908 MVT::f32, getValue(I.getArgOperand(0)))); 4909 return 0; 4910 case Intrinsic::pcmarker: { 4911 SDValue Tmp = getValue(I.getArgOperand(0)); 4912 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4913 return 0; 4914 } 4915 case Intrinsic::readcyclecounter: { 4916 SDValue Op = getRoot(); 4917 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4918 DAG.getVTList(MVT::i64, MVT::Other), 4919 &Op, 1); 4920 setValue(&I, Res); 4921 DAG.setRoot(Res.getValue(1)); 4922 return 0; 4923 } 4924 case Intrinsic::bswap: 4925 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4926 getValue(I.getArgOperand(0)).getValueType(), 4927 getValue(I.getArgOperand(0)))); 4928 return 0; 4929 case Intrinsic::cttz: { 4930 SDValue Arg = getValue(I.getArgOperand(0)); 4931 EVT Ty = Arg.getValueType(); 4932 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4933 return 0; 4934 } 4935 case Intrinsic::ctlz: { 4936 SDValue Arg = getValue(I.getArgOperand(0)); 4937 EVT Ty = Arg.getValueType(); 4938 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4939 return 0; 4940 } 4941 case Intrinsic::ctpop: { 4942 SDValue Arg = getValue(I.getArgOperand(0)); 4943 EVT Ty = Arg.getValueType(); 4944 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4945 return 0; 4946 } 4947 case Intrinsic::stacksave: { 4948 SDValue Op = getRoot(); 4949 Res = DAG.getNode(ISD::STACKSAVE, dl, 4950 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4951 setValue(&I, Res); 4952 DAG.setRoot(Res.getValue(1)); 4953 return 0; 4954 } 4955 case Intrinsic::stackrestore: { 4956 Res = getValue(I.getArgOperand(0)); 4957 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4958 return 0; 4959 } 4960 case Intrinsic::stackprotector: { 4961 // Emit code into the DAG to store the stack guard onto the stack. 4962 MachineFunction &MF = DAG.getMachineFunction(); 4963 MachineFrameInfo *MFI = MF.getFrameInfo(); 4964 EVT PtrTy = TLI.getPointerTy(); 4965 4966 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4967 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4968 4969 int FI = FuncInfo.StaticAllocaMap[Slot]; 4970 MFI->setStackProtectorIndex(FI); 4971 4972 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4973 4974 // Store the stack protector onto the stack. 4975 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4976 MachinePointerInfo::getFixedStack(FI), 4977 true, false, 0); 4978 setValue(&I, Res); 4979 DAG.setRoot(Res); 4980 return 0; 4981 } 4982 case Intrinsic::objectsize: { 4983 // If we don't know by now, we're never going to know. 4984 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4985 4986 assert(CI && "Non-constant type in __builtin_object_size?"); 4987 4988 SDValue Arg = getValue(I.getCalledValue()); 4989 EVT Ty = Arg.getValueType(); 4990 4991 if (CI->isZero()) 4992 Res = DAG.getConstant(-1ULL, Ty); 4993 else 4994 Res = DAG.getConstant(0, Ty); 4995 4996 setValue(&I, Res); 4997 return 0; 4998 } 4999 case Intrinsic::var_annotation: 5000 // Discard annotate attributes 5001 return 0; 5002 5003 case Intrinsic::init_trampoline: { 5004 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5005 5006 SDValue Ops[6]; 5007 Ops[0] = getRoot(); 5008 Ops[1] = getValue(I.getArgOperand(0)); 5009 Ops[2] = getValue(I.getArgOperand(1)); 5010 Ops[3] = getValue(I.getArgOperand(2)); 5011 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5012 Ops[5] = DAG.getSrcValue(F); 5013 5014 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5015 5016 DAG.setRoot(Res); 5017 return 0; 5018 } 5019 case Intrinsic::adjust_trampoline: { 5020 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5021 TLI.getPointerTy(), 5022 getValue(I.getArgOperand(0)))); 5023 return 0; 5024 } 5025 case Intrinsic::gcroot: 5026 if (GFI) { 5027 const Value *Alloca = I.getArgOperand(0); 5028 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5029 5030 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5031 GFI->addStackRoot(FI->getIndex(), TypeMap); 5032 } 5033 return 0; 5034 case Intrinsic::gcread: 5035 case Intrinsic::gcwrite: 5036 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5037 return 0; 5038 case Intrinsic::flt_rounds: 5039 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5040 return 0; 5041 5042 case Intrinsic::expect: { 5043 // Just replace __builtin_expect(exp, c) with EXP. 5044 setValue(&I, getValue(I.getArgOperand(0))); 5045 return 0; 5046 } 5047 5048 case Intrinsic::trap: { 5049 StringRef TrapFuncName = getTrapFunctionName(); 5050 if (TrapFuncName.empty()) { 5051 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5052 return 0; 5053 } 5054 TargetLowering::ArgListTy Args; 5055 std::pair<SDValue, SDValue> Result = 5056 TLI.LowerCallTo(getRoot(), I.getType(), 5057 false, false, false, false, 0, CallingConv::C, 5058 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 5059 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5060 Args, DAG, getCurDebugLoc()); 5061 DAG.setRoot(Result.second); 5062 return 0; 5063 } 5064 case Intrinsic::uadd_with_overflow: 5065 return implVisitAluOverflow(I, ISD::UADDO); 5066 case Intrinsic::sadd_with_overflow: 5067 return implVisitAluOverflow(I, ISD::SADDO); 5068 case Intrinsic::usub_with_overflow: 5069 return implVisitAluOverflow(I, ISD::USUBO); 5070 case Intrinsic::ssub_with_overflow: 5071 return implVisitAluOverflow(I, ISD::SSUBO); 5072 case Intrinsic::umul_with_overflow: 5073 return implVisitAluOverflow(I, ISD::UMULO); 5074 case Intrinsic::smul_with_overflow: 5075 return implVisitAluOverflow(I, ISD::SMULO); 5076 5077 case Intrinsic::prefetch: { 5078 SDValue Ops[5]; 5079 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5080 Ops[0] = getRoot(); 5081 Ops[1] = getValue(I.getArgOperand(0)); 5082 Ops[2] = getValue(I.getArgOperand(1)); 5083 Ops[3] = getValue(I.getArgOperand(2)); 5084 Ops[4] = getValue(I.getArgOperand(3)); 5085 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5086 DAG.getVTList(MVT::Other), 5087 &Ops[0], 5, 5088 EVT::getIntegerVT(*Context, 8), 5089 MachinePointerInfo(I.getArgOperand(0)), 5090 0, /* align */ 5091 false, /* volatile */ 5092 rw==0, /* read */ 5093 rw==1)); /* write */ 5094 return 0; 5095 } 5096 case Intrinsic::memory_barrier: { 5097 SDValue Ops[6]; 5098 Ops[0] = getRoot(); 5099 for (int x = 1; x < 6; ++x) 5100 Ops[x] = getValue(I.getArgOperand(x - 1)); 5101 5102 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 5103 return 0; 5104 } 5105 case Intrinsic::atomic_cmp_swap: { 5106 SDValue Root = getRoot(); 5107 SDValue L = 5108 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 5109 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 5110 Root, 5111 getValue(I.getArgOperand(0)), 5112 getValue(I.getArgOperand(1)), 5113 getValue(I.getArgOperand(2)), 5114 MachinePointerInfo(I.getArgOperand(0)), 0 /* Alignment */, 5115 Monotonic, CrossThread); 5116 setValue(&I, L); 5117 DAG.setRoot(L.getValue(1)); 5118 return 0; 5119 } 5120 case Intrinsic::atomic_load_add: 5121 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 5122 case Intrinsic::atomic_load_sub: 5123 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 5124 case Intrinsic::atomic_load_or: 5125 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 5126 case Intrinsic::atomic_load_xor: 5127 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 5128 case Intrinsic::atomic_load_and: 5129 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 5130 case Intrinsic::atomic_load_nand: 5131 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 5132 case Intrinsic::atomic_load_max: 5133 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 5134 case Intrinsic::atomic_load_min: 5135 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 5136 case Intrinsic::atomic_load_umin: 5137 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 5138 case Intrinsic::atomic_load_umax: 5139 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 5140 case Intrinsic::atomic_swap: 5141 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 5142 5143 case Intrinsic::invariant_start: 5144 case Intrinsic::lifetime_start: 5145 // Discard region information. 5146 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5147 return 0; 5148 case Intrinsic::invariant_end: 5149 case Intrinsic::lifetime_end: 5150 // Discard region information. 5151 return 0; 5152 } 5153} 5154 5155void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5156 bool isTailCall, 5157 MachineBasicBlock *LandingPad) { 5158 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5159 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5160 Type *RetTy = FTy->getReturnType(); 5161 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5162 MCSymbol *BeginLabel = 0; 5163 5164 TargetLowering::ArgListTy Args; 5165 TargetLowering::ArgListEntry Entry; 5166 Args.reserve(CS.arg_size()); 5167 5168 // Check whether the function can return without sret-demotion. 5169 SmallVector<ISD::OutputArg, 4> Outs; 5170 SmallVector<uint64_t, 4> Offsets; 5171 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5172 Outs, TLI, &Offsets); 5173 5174 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5175 DAG.getMachineFunction(), 5176 FTy->isVarArg(), Outs, 5177 FTy->getContext()); 5178 5179 SDValue DemoteStackSlot; 5180 int DemoteStackIdx = -100; 5181 5182 if (!CanLowerReturn) { 5183 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5184 FTy->getReturnType()); 5185 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5186 FTy->getReturnType()); 5187 MachineFunction &MF = DAG.getMachineFunction(); 5188 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5189 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5190 5191 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5192 Entry.Node = DemoteStackSlot; 5193 Entry.Ty = StackSlotPtrType; 5194 Entry.isSExt = false; 5195 Entry.isZExt = false; 5196 Entry.isInReg = false; 5197 Entry.isSRet = true; 5198 Entry.isNest = false; 5199 Entry.isByVal = false; 5200 Entry.Alignment = Align; 5201 Args.push_back(Entry); 5202 RetTy = Type::getVoidTy(FTy->getContext()); 5203 } 5204 5205 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5206 i != e; ++i) { 5207 const Value *V = *i; 5208 5209 // Skip empty types 5210 if (V->getType()->isEmptyTy()) 5211 continue; 5212 5213 SDValue ArgNode = getValue(V); 5214 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5215 5216 unsigned attrInd = i - CS.arg_begin() + 1; 5217 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5218 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5219 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5220 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5221 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5222 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5223 Entry.Alignment = CS.getParamAlignment(attrInd); 5224 Args.push_back(Entry); 5225 } 5226 5227 if (LandingPad) { 5228 // Insert a label before the invoke call to mark the try range. This can be 5229 // used to detect deletion of the invoke via the MachineModuleInfo. 5230 BeginLabel = MMI.getContext().CreateTempSymbol(); 5231 5232 // For SjLj, keep track of which landing pads go with which invokes 5233 // so as to maintain the ordering of pads in the LSDA. 5234 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5235 if (CallSiteIndex) { 5236 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5237 // Now that the call site is handled, stop tracking it. 5238 MMI.setCurrentCallSite(0); 5239 } 5240 5241 // Both PendingLoads and PendingExports must be flushed here; 5242 // this call might not return. 5243 (void)getRoot(); 5244 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5245 } 5246 5247 // Check if target-independent constraints permit a tail call here. 5248 // Target-dependent constraints are checked within TLI.LowerCallTo. 5249 if (isTailCall && 5250 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5251 isTailCall = false; 5252 5253 // If there's a possibility that fast-isel has already selected some amount 5254 // of the current basic block, don't emit a tail call. 5255 if (isTailCall && EnableFastISel) 5256 isTailCall = false; 5257 5258 std::pair<SDValue,SDValue> Result = 5259 TLI.LowerCallTo(getRoot(), RetTy, 5260 CS.paramHasAttr(0, Attribute::SExt), 5261 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5262 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5263 CS.getCallingConv(), 5264 isTailCall, 5265 !CS.getInstruction()->use_empty(), 5266 Callee, Args, DAG, getCurDebugLoc()); 5267 assert((isTailCall || Result.second.getNode()) && 5268 "Non-null chain expected with non-tail call!"); 5269 assert((Result.second.getNode() || !Result.first.getNode()) && 5270 "Null value expected with tail call!"); 5271 if (Result.first.getNode()) { 5272 setValue(CS.getInstruction(), Result.first); 5273 } else if (!CanLowerReturn && Result.second.getNode()) { 5274 // The instruction result is the result of loading from the 5275 // hidden sret parameter. 5276 SmallVector<EVT, 1> PVTs; 5277 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5278 5279 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5280 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5281 EVT PtrVT = PVTs[0]; 5282 unsigned NumValues = Outs.size(); 5283 SmallVector<SDValue, 4> Values(NumValues); 5284 SmallVector<SDValue, 4> Chains(NumValues); 5285 5286 for (unsigned i = 0; i < NumValues; ++i) { 5287 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5288 DemoteStackSlot, 5289 DAG.getConstant(Offsets[i], PtrVT)); 5290 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5291 Add, 5292 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5293 false, false, 1); 5294 Values[i] = L; 5295 Chains[i] = L.getValue(1); 5296 } 5297 5298 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5299 MVT::Other, &Chains[0], NumValues); 5300 PendingLoads.push_back(Chain); 5301 5302 // Collect the legal value parts into potentially illegal values 5303 // that correspond to the original function's return values. 5304 SmallVector<EVT, 4> RetTys; 5305 RetTy = FTy->getReturnType(); 5306 ComputeValueVTs(TLI, RetTy, RetTys); 5307 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5308 SmallVector<SDValue, 4> ReturnValues; 5309 unsigned CurReg = 0; 5310 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5311 EVT VT = RetTys[I]; 5312 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5313 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5314 5315 SDValue ReturnValue = 5316 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5317 RegisterVT, VT, AssertOp); 5318 ReturnValues.push_back(ReturnValue); 5319 CurReg += NumRegs; 5320 } 5321 5322 setValue(CS.getInstruction(), 5323 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5324 DAG.getVTList(&RetTys[0], RetTys.size()), 5325 &ReturnValues[0], ReturnValues.size())); 5326 } 5327 5328 // Assign order to nodes here. If the call does not produce a result, it won't 5329 // be mapped to a SDNode and visit() will not assign it an order number. 5330 if (!Result.second.getNode()) { 5331 // As a special case, a null chain means that a tail call has been emitted and 5332 // the DAG root is already updated. 5333 HasTailCall = true; 5334 ++SDNodeOrder; 5335 AssignOrderingToNode(DAG.getRoot().getNode()); 5336 } else { 5337 DAG.setRoot(Result.second); 5338 ++SDNodeOrder; 5339 AssignOrderingToNode(Result.second.getNode()); 5340 } 5341 5342 if (LandingPad) { 5343 // Insert a label at the end of the invoke call to mark the try range. This 5344 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5345 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5346 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5347 5348 // Inform MachineModuleInfo of range. 5349 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5350 } 5351} 5352 5353/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5354/// value is equal or not-equal to zero. 5355static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5356 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5357 UI != E; ++UI) { 5358 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5359 if (IC->isEquality()) 5360 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5361 if (C->isNullValue()) 5362 continue; 5363 // Unknown instruction. 5364 return false; 5365 } 5366 return true; 5367} 5368 5369static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5370 Type *LoadTy, 5371 SelectionDAGBuilder &Builder) { 5372 5373 // Check to see if this load can be trivially constant folded, e.g. if the 5374 // input is from a string literal. 5375 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5376 // Cast pointer to the type we really want to load. 5377 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5378 PointerType::getUnqual(LoadTy)); 5379 5380 if (const Constant *LoadCst = 5381 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5382 Builder.TD)) 5383 return Builder.getValue(LoadCst); 5384 } 5385 5386 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5387 // still constant memory, the input chain can be the entry node. 5388 SDValue Root; 5389 bool ConstantMemory = false; 5390 5391 // Do not serialize (non-volatile) loads of constant memory with anything. 5392 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5393 Root = Builder.DAG.getEntryNode(); 5394 ConstantMemory = true; 5395 } else { 5396 // Do not serialize non-volatile loads against each other. 5397 Root = Builder.DAG.getRoot(); 5398 } 5399 5400 SDValue Ptr = Builder.getValue(PtrVal); 5401 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5402 Ptr, MachinePointerInfo(PtrVal), 5403 false /*volatile*/, 5404 false /*nontemporal*/, 1 /* align=1 */); 5405 5406 if (!ConstantMemory) 5407 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5408 return LoadVal; 5409} 5410 5411 5412/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5413/// If so, return true and lower it, otherwise return false and it will be 5414/// lowered like a normal call. 5415bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5416 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5417 if (I.getNumArgOperands() != 3) 5418 return false; 5419 5420 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5421 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5422 !I.getArgOperand(2)->getType()->isIntegerTy() || 5423 !I.getType()->isIntegerTy()) 5424 return false; 5425 5426 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5427 5428 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5429 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5430 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5431 bool ActuallyDoIt = true; 5432 MVT LoadVT; 5433 Type *LoadTy; 5434 switch (Size->getZExtValue()) { 5435 default: 5436 LoadVT = MVT::Other; 5437 LoadTy = 0; 5438 ActuallyDoIt = false; 5439 break; 5440 case 2: 5441 LoadVT = MVT::i16; 5442 LoadTy = Type::getInt16Ty(Size->getContext()); 5443 break; 5444 case 4: 5445 LoadVT = MVT::i32; 5446 LoadTy = Type::getInt32Ty(Size->getContext()); 5447 break; 5448 case 8: 5449 LoadVT = MVT::i64; 5450 LoadTy = Type::getInt64Ty(Size->getContext()); 5451 break; 5452 /* 5453 case 16: 5454 LoadVT = MVT::v4i32; 5455 LoadTy = Type::getInt32Ty(Size->getContext()); 5456 LoadTy = VectorType::get(LoadTy, 4); 5457 break; 5458 */ 5459 } 5460 5461 // This turns into unaligned loads. We only do this if the target natively 5462 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5463 // we'll only produce a small number of byte loads. 5464 5465 // Require that we can find a legal MVT, and only do this if the target 5466 // supports unaligned loads of that type. Expanding into byte loads would 5467 // bloat the code. 5468 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5469 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5470 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5471 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5472 ActuallyDoIt = false; 5473 } 5474 5475 if (ActuallyDoIt) { 5476 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5477 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5478 5479 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5480 ISD::SETNE); 5481 EVT CallVT = TLI.getValueType(I.getType(), true); 5482 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5483 return true; 5484 } 5485 } 5486 5487 5488 return false; 5489} 5490 5491 5492void SelectionDAGBuilder::visitCall(const CallInst &I) { 5493 // Handle inline assembly differently. 5494 if (isa<InlineAsm>(I.getCalledValue())) { 5495 visitInlineAsm(&I); 5496 return; 5497 } 5498 5499 // See if any floating point values are being passed to this function. This is 5500 // used to emit an undefined reference to fltused on Windows. 5501 FunctionType *FT = 5502 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5503 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5504 if (FT->isVarArg() && 5505 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5506 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5507 Type* T = I.getArgOperand(i)->getType(); 5508 for (po_iterator<Type*> i = po_begin(T), e = po_end(T); 5509 i != e; ++i) { 5510 if (!i->isFloatingPointTy()) continue; 5511 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5512 break; 5513 } 5514 } 5515 } 5516 5517 const char *RenameFn = 0; 5518 if (Function *F = I.getCalledFunction()) { 5519 if (F->isDeclaration()) { 5520 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5521 if (unsigned IID = II->getIntrinsicID(F)) { 5522 RenameFn = visitIntrinsicCall(I, IID); 5523 if (!RenameFn) 5524 return; 5525 } 5526 } 5527 if (unsigned IID = F->getIntrinsicID()) { 5528 RenameFn = visitIntrinsicCall(I, IID); 5529 if (!RenameFn) 5530 return; 5531 } 5532 } 5533 5534 // Check for well-known libc/libm calls. If the function is internal, it 5535 // can't be a library call. 5536 if (!F->hasLocalLinkage() && F->hasName()) { 5537 StringRef Name = F->getName(); 5538 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5539 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5540 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5541 I.getType() == I.getArgOperand(0)->getType() && 5542 I.getType() == I.getArgOperand(1)->getType()) { 5543 SDValue LHS = getValue(I.getArgOperand(0)); 5544 SDValue RHS = getValue(I.getArgOperand(1)); 5545 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5546 LHS.getValueType(), LHS, RHS)); 5547 return; 5548 } 5549 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5550 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5551 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5552 I.getType() == I.getArgOperand(0)->getType()) { 5553 SDValue Tmp = getValue(I.getArgOperand(0)); 5554 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5555 Tmp.getValueType(), Tmp)); 5556 return; 5557 } 5558 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5559 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5560 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5561 I.getType() == I.getArgOperand(0)->getType() && 5562 I.onlyReadsMemory()) { 5563 SDValue Tmp = getValue(I.getArgOperand(0)); 5564 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5565 Tmp.getValueType(), Tmp)); 5566 return; 5567 } 5568 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5569 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5570 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5571 I.getType() == I.getArgOperand(0)->getType() && 5572 I.onlyReadsMemory()) { 5573 SDValue Tmp = getValue(I.getArgOperand(0)); 5574 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5575 Tmp.getValueType(), Tmp)); 5576 return; 5577 } 5578 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5579 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5580 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5581 I.getType() == I.getArgOperand(0)->getType() && 5582 I.onlyReadsMemory()) { 5583 SDValue Tmp = getValue(I.getArgOperand(0)); 5584 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5585 Tmp.getValueType(), Tmp)); 5586 return; 5587 } 5588 } else if (Name == "memcmp") { 5589 if (visitMemCmpCall(I)) 5590 return; 5591 } 5592 } 5593 } 5594 5595 SDValue Callee; 5596 if (!RenameFn) 5597 Callee = getValue(I.getCalledValue()); 5598 else 5599 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5600 5601 // Check if we can potentially perform a tail call. More detailed checking is 5602 // be done within LowerCallTo, after more information about the call is known. 5603 LowerCallTo(&I, Callee, I.isTailCall()); 5604} 5605 5606namespace { 5607 5608/// AsmOperandInfo - This contains information for each constraint that we are 5609/// lowering. 5610class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5611public: 5612 /// CallOperand - If this is the result output operand or a clobber 5613 /// this is null, otherwise it is the incoming operand to the CallInst. 5614 /// This gets modified as the asm is processed. 5615 SDValue CallOperand; 5616 5617 /// AssignedRegs - If this is a register or register class operand, this 5618 /// contains the set of register corresponding to the operand. 5619 RegsForValue AssignedRegs; 5620 5621 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5622 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5623 } 5624 5625 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5626 /// busy in OutputRegs/InputRegs. 5627 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5628 std::set<unsigned> &OutputRegs, 5629 std::set<unsigned> &InputRegs, 5630 const TargetRegisterInfo &TRI) const { 5631 if (isOutReg) { 5632 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5633 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5634 } 5635 if (isInReg) { 5636 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5637 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5638 } 5639 } 5640 5641 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5642 /// corresponds to. If there is no Value* for this operand, it returns 5643 /// MVT::Other. 5644 EVT getCallOperandValEVT(LLVMContext &Context, 5645 const TargetLowering &TLI, 5646 const TargetData *TD) const { 5647 if (CallOperandVal == 0) return MVT::Other; 5648 5649 if (isa<BasicBlock>(CallOperandVal)) 5650 return TLI.getPointerTy(); 5651 5652 llvm::Type *OpTy = CallOperandVal->getType(); 5653 5654 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5655 // If this is an indirect operand, the operand is a pointer to the 5656 // accessed type. 5657 if (isIndirect) { 5658 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5659 if (!PtrTy) 5660 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5661 OpTy = PtrTy->getElementType(); 5662 } 5663 5664 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5665 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5666 if (STy->getNumElements() == 1) 5667 OpTy = STy->getElementType(0); 5668 5669 // If OpTy is not a single value, it may be a struct/union that we 5670 // can tile with integers. 5671 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5672 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5673 switch (BitSize) { 5674 default: break; 5675 case 1: 5676 case 8: 5677 case 16: 5678 case 32: 5679 case 64: 5680 case 128: 5681 OpTy = IntegerType::get(Context, BitSize); 5682 break; 5683 } 5684 } 5685 5686 return TLI.getValueType(OpTy, true); 5687 } 5688 5689private: 5690 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5691 /// specified set. 5692 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5693 const TargetRegisterInfo &TRI) { 5694 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5695 Regs.insert(Reg); 5696 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5697 for (; *Aliases; ++Aliases) 5698 Regs.insert(*Aliases); 5699 } 5700}; 5701 5702typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5703 5704} // end anonymous namespace 5705 5706/// GetRegistersForValue - Assign registers (virtual or physical) for the 5707/// specified operand. We prefer to assign virtual registers, to allow the 5708/// register allocator to handle the assignment process. However, if the asm 5709/// uses features that we can't model on machineinstrs, we have SDISel do the 5710/// allocation. This produces generally horrible, but correct, code. 5711/// 5712/// OpInfo describes the operand. 5713/// Input and OutputRegs are the set of already allocated physical registers. 5714/// 5715static void GetRegistersForValue(SelectionDAG &DAG, 5716 const TargetLowering &TLI, 5717 DebugLoc DL, 5718 SDISelAsmOperandInfo &OpInfo, 5719 std::set<unsigned> &OutputRegs, 5720 std::set<unsigned> &InputRegs) { 5721 LLVMContext &Context = *DAG.getContext(); 5722 5723 // Compute whether this value requires an input register, an output register, 5724 // or both. 5725 bool isOutReg = false; 5726 bool isInReg = false; 5727 switch (OpInfo.Type) { 5728 case InlineAsm::isOutput: 5729 isOutReg = true; 5730 5731 // If there is an input constraint that matches this, we need to reserve 5732 // the input register so no other inputs allocate to it. 5733 isInReg = OpInfo.hasMatchingInput(); 5734 break; 5735 case InlineAsm::isInput: 5736 isInReg = true; 5737 isOutReg = false; 5738 break; 5739 case InlineAsm::isClobber: 5740 isOutReg = true; 5741 isInReg = true; 5742 break; 5743 } 5744 5745 5746 MachineFunction &MF = DAG.getMachineFunction(); 5747 SmallVector<unsigned, 4> Regs; 5748 5749 // If this is a constraint for a single physreg, or a constraint for a 5750 // register class, find it. 5751 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5752 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5753 OpInfo.ConstraintVT); 5754 5755 unsigned NumRegs = 1; 5756 if (OpInfo.ConstraintVT != MVT::Other) { 5757 // If this is a FP input in an integer register (or visa versa) insert a bit 5758 // cast of the input value. More generally, handle any case where the input 5759 // value disagrees with the register class we plan to stick this in. 5760 if (OpInfo.Type == InlineAsm::isInput && 5761 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5762 // Try to convert to the first EVT that the reg class contains. If the 5763 // types are identical size, use a bitcast to convert (e.g. two differing 5764 // vector types). 5765 EVT RegVT = *PhysReg.second->vt_begin(); 5766 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5767 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5768 RegVT, OpInfo.CallOperand); 5769 OpInfo.ConstraintVT = RegVT; 5770 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5771 // If the input is a FP value and we want it in FP registers, do a 5772 // bitcast to the corresponding integer type. This turns an f64 value 5773 // into i64, which can be passed with two i32 values on a 32-bit 5774 // machine. 5775 RegVT = EVT::getIntegerVT(Context, 5776 OpInfo.ConstraintVT.getSizeInBits()); 5777 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5778 RegVT, OpInfo.CallOperand); 5779 OpInfo.ConstraintVT = RegVT; 5780 } 5781 } 5782 5783 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5784 } 5785 5786 EVT RegVT; 5787 EVT ValueVT = OpInfo.ConstraintVT; 5788 5789 // If this is a constraint for a specific physical register, like {r17}, 5790 // assign it now. 5791 if (unsigned AssignedReg = PhysReg.first) { 5792 const TargetRegisterClass *RC = PhysReg.second; 5793 if (OpInfo.ConstraintVT == MVT::Other) 5794 ValueVT = *RC->vt_begin(); 5795 5796 // Get the actual register value type. This is important, because the user 5797 // may have asked for (e.g.) the AX register in i32 type. We need to 5798 // remember that AX is actually i16 to get the right extension. 5799 RegVT = *RC->vt_begin(); 5800 5801 // This is a explicit reference to a physical register. 5802 Regs.push_back(AssignedReg); 5803 5804 // If this is an expanded reference, add the rest of the regs to Regs. 5805 if (NumRegs != 1) { 5806 TargetRegisterClass::iterator I = RC->begin(); 5807 for (; *I != AssignedReg; ++I) 5808 assert(I != RC->end() && "Didn't find reg!"); 5809 5810 // Already added the first reg. 5811 --NumRegs; ++I; 5812 for (; NumRegs; --NumRegs, ++I) { 5813 assert(I != RC->end() && "Ran out of registers to allocate!"); 5814 Regs.push_back(*I); 5815 } 5816 } 5817 5818 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5819 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5820 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5821 return; 5822 } 5823 5824 // Otherwise, if this was a reference to an LLVM register class, create vregs 5825 // for this reference. 5826 if (const TargetRegisterClass *RC = PhysReg.second) { 5827 RegVT = *RC->vt_begin(); 5828 if (OpInfo.ConstraintVT == MVT::Other) 5829 ValueVT = RegVT; 5830 5831 // Create the appropriate number of virtual registers. 5832 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5833 for (; NumRegs; --NumRegs) 5834 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5835 5836 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5837 return; 5838 } 5839 5840 // Otherwise, we couldn't allocate enough registers for this. 5841} 5842 5843/// visitInlineAsm - Handle a call to an InlineAsm object. 5844/// 5845void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5846 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5847 5848 /// ConstraintOperands - Information about all of the constraints. 5849 SDISelAsmOperandInfoVector ConstraintOperands; 5850 5851 std::set<unsigned> OutputRegs, InputRegs; 5852 5853 TargetLowering::AsmOperandInfoVector 5854 TargetConstraints = TLI.ParseConstraints(CS); 5855 5856 bool hasMemory = false; 5857 5858 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5859 unsigned ResNo = 0; // ResNo - The result number of the next output. 5860 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5861 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5862 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5863 5864 EVT OpVT = MVT::Other; 5865 5866 // Compute the value type for each operand. 5867 switch (OpInfo.Type) { 5868 case InlineAsm::isOutput: 5869 // Indirect outputs just consume an argument. 5870 if (OpInfo.isIndirect) { 5871 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5872 break; 5873 } 5874 5875 // The return value of the call is this value. As such, there is no 5876 // corresponding argument. 5877 assert(!CS.getType()->isVoidTy() && 5878 "Bad inline asm!"); 5879 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5880 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5881 } else { 5882 assert(ResNo == 0 && "Asm only has one result!"); 5883 OpVT = TLI.getValueType(CS.getType()); 5884 } 5885 ++ResNo; 5886 break; 5887 case InlineAsm::isInput: 5888 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5889 break; 5890 case InlineAsm::isClobber: 5891 // Nothing to do. 5892 break; 5893 } 5894 5895 // If this is an input or an indirect output, process the call argument. 5896 // BasicBlocks are labels, currently appearing only in asm's. 5897 if (OpInfo.CallOperandVal) { 5898 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5899 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5900 } else { 5901 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5902 } 5903 5904 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5905 } 5906 5907 OpInfo.ConstraintVT = OpVT; 5908 5909 // Indirect operand accesses access memory. 5910 if (OpInfo.isIndirect) 5911 hasMemory = true; 5912 else { 5913 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5914 TargetLowering::ConstraintType 5915 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5916 if (CType == TargetLowering::C_Memory) { 5917 hasMemory = true; 5918 break; 5919 } 5920 } 5921 } 5922 } 5923 5924 SDValue Chain, Flag; 5925 5926 // We won't need to flush pending loads if this asm doesn't touch 5927 // memory and is nonvolatile. 5928 if (hasMemory || IA->hasSideEffects()) 5929 Chain = getRoot(); 5930 else 5931 Chain = DAG.getRoot(); 5932 5933 // Second pass over the constraints: compute which constraint option to use 5934 // and assign registers to constraints that want a specific physreg. 5935 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5936 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5937 5938 // If this is an output operand with a matching input operand, look up the 5939 // matching input. If their types mismatch, e.g. one is an integer, the 5940 // other is floating point, or their sizes are different, flag it as an 5941 // error. 5942 if (OpInfo.hasMatchingInput()) { 5943 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5944 5945 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5946 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5947 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5948 OpInfo.ConstraintVT); 5949 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5950 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5951 Input.ConstraintVT); 5952 if ((OpInfo.ConstraintVT.isInteger() != 5953 Input.ConstraintVT.isInteger()) || 5954 (MatchRC.second != InputRC.second)) { 5955 report_fatal_error("Unsupported asm: input constraint" 5956 " with a matching output constraint of" 5957 " incompatible type!"); 5958 } 5959 Input.ConstraintVT = OpInfo.ConstraintVT; 5960 } 5961 } 5962 5963 // Compute the constraint code and ConstraintType to use. 5964 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5965 5966 // If this is a memory input, and if the operand is not indirect, do what we 5967 // need to to provide an address for the memory input. 5968 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5969 !OpInfo.isIndirect) { 5970 assert((OpInfo.isMultipleAlternative || 5971 (OpInfo.Type == InlineAsm::isInput)) && 5972 "Can only indirectify direct input operands!"); 5973 5974 // Memory operands really want the address of the value. If we don't have 5975 // an indirect input, put it in the constpool if we can, otherwise spill 5976 // it to a stack slot. 5977 // TODO: This isn't quite right. We need to handle these according to 5978 // the addressing mode that the constraint wants. Also, this may take 5979 // an additional register for the computation and we don't want that 5980 // either. 5981 5982 // If the operand is a float, integer, or vector constant, spill to a 5983 // constant pool entry to get its address. 5984 const Value *OpVal = OpInfo.CallOperandVal; 5985 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5986 isa<ConstantVector>(OpVal)) { 5987 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5988 TLI.getPointerTy()); 5989 } else { 5990 // Otherwise, create a stack slot and emit a store to it before the 5991 // asm. 5992 Type *Ty = OpVal->getType(); 5993 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5994 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5995 MachineFunction &MF = DAG.getMachineFunction(); 5996 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5997 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5998 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5999 OpInfo.CallOperand, StackSlot, 6000 MachinePointerInfo::getFixedStack(SSFI), 6001 false, false, 0); 6002 OpInfo.CallOperand = StackSlot; 6003 } 6004 6005 // There is no longer a Value* corresponding to this operand. 6006 OpInfo.CallOperandVal = 0; 6007 6008 // It is now an indirect operand. 6009 OpInfo.isIndirect = true; 6010 } 6011 6012 // If this constraint is for a specific register, allocate it before 6013 // anything else. 6014 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6015 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 6016 InputRegs); 6017 } 6018 6019 // Second pass - Loop over all of the operands, assigning virtual or physregs 6020 // to register class operands. 6021 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6022 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6023 6024 // C_Register operands have already been allocated, Other/Memory don't need 6025 // to be. 6026 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6027 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 6028 InputRegs); 6029 } 6030 6031 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6032 std::vector<SDValue> AsmNodeOperands; 6033 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6034 AsmNodeOperands.push_back( 6035 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6036 TLI.getPointerTy())); 6037 6038 // If we have a !srcloc metadata node associated with it, we want to attach 6039 // this to the ultimately generated inline asm machineinstr. To do this, we 6040 // pass in the third operand as this (potentially null) inline asm MDNode. 6041 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6042 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6043 6044 // Remember the HasSideEffect and AlignStack bits as operand 3. 6045 unsigned ExtraInfo = 0; 6046 if (IA->hasSideEffects()) 6047 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6048 if (IA->isAlignStack()) 6049 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6050 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6051 TLI.getPointerTy())); 6052 6053 // Loop over all of the inputs, copying the operand values into the 6054 // appropriate registers and processing the output regs. 6055 RegsForValue RetValRegs; 6056 6057 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6058 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6059 6060 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6061 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6062 6063 switch (OpInfo.Type) { 6064 case InlineAsm::isOutput: { 6065 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6066 OpInfo.ConstraintType != TargetLowering::C_Register) { 6067 // Memory output, or 'other' output (e.g. 'X' constraint). 6068 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6069 6070 // Add information to the INLINEASM node to know about this output. 6071 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6072 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6073 TLI.getPointerTy())); 6074 AsmNodeOperands.push_back(OpInfo.CallOperand); 6075 break; 6076 } 6077 6078 // Otherwise, this is a register or register class output. 6079 6080 // Copy the output from the appropriate register. Find a register that 6081 // we can use. 6082 if (OpInfo.AssignedRegs.Regs.empty()) 6083 report_fatal_error("Couldn't allocate output reg for constraint '" + 6084 Twine(OpInfo.ConstraintCode) + "'!"); 6085 6086 // If this is an indirect operand, store through the pointer after the 6087 // asm. 6088 if (OpInfo.isIndirect) { 6089 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6090 OpInfo.CallOperandVal)); 6091 } else { 6092 // This is the result value of the call. 6093 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6094 // Concatenate this output onto the outputs list. 6095 RetValRegs.append(OpInfo.AssignedRegs); 6096 } 6097 6098 // Add information to the INLINEASM node to know that this register is 6099 // set. 6100 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6101 InlineAsm::Kind_RegDefEarlyClobber : 6102 InlineAsm::Kind_RegDef, 6103 false, 6104 0, 6105 DAG, 6106 AsmNodeOperands); 6107 break; 6108 } 6109 case InlineAsm::isInput: { 6110 SDValue InOperandVal = OpInfo.CallOperand; 6111 6112 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6113 // If this is required to match an output register we have already set, 6114 // just use its register. 6115 unsigned OperandNo = OpInfo.getMatchedOperand(); 6116 6117 // Scan until we find the definition we already emitted of this operand. 6118 // When we find it, create a RegsForValue operand. 6119 unsigned CurOp = InlineAsm::Op_FirstOperand; 6120 for (; OperandNo; --OperandNo) { 6121 // Advance to the next operand. 6122 unsigned OpFlag = 6123 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6124 assert((InlineAsm::isRegDefKind(OpFlag) || 6125 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6126 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6127 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6128 } 6129 6130 unsigned OpFlag = 6131 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6132 if (InlineAsm::isRegDefKind(OpFlag) || 6133 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6134 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6135 if (OpInfo.isIndirect) { 6136 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6137 LLVMContext &Ctx = *DAG.getContext(); 6138 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6139 " don't know how to handle tied " 6140 "indirect register inputs"); 6141 } 6142 6143 RegsForValue MatchedRegs; 6144 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6145 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6146 MatchedRegs.RegVTs.push_back(RegVT); 6147 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6148 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6149 i != e; ++i) 6150 MatchedRegs.Regs.push_back 6151 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6152 6153 // Use the produced MatchedRegs object to 6154 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6155 Chain, &Flag); 6156 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6157 true, OpInfo.getMatchedOperand(), 6158 DAG, AsmNodeOperands); 6159 break; 6160 } 6161 6162 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6163 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6164 "Unexpected number of operands"); 6165 // Add information to the INLINEASM node to know about this input. 6166 // See InlineAsm.h isUseOperandTiedToDef. 6167 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6168 OpInfo.getMatchedOperand()); 6169 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6170 TLI.getPointerTy())); 6171 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6172 break; 6173 } 6174 6175 // Treat indirect 'X' constraint as memory. 6176 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6177 OpInfo.isIndirect) 6178 OpInfo.ConstraintType = TargetLowering::C_Memory; 6179 6180 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6181 std::vector<SDValue> Ops; 6182 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6183 Ops, DAG); 6184 if (Ops.empty()) 6185 report_fatal_error("Invalid operand for inline asm constraint '" + 6186 Twine(OpInfo.ConstraintCode) + "'!"); 6187 6188 // Add information to the INLINEASM node to know about this input. 6189 unsigned ResOpType = 6190 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6191 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6192 TLI.getPointerTy())); 6193 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6194 break; 6195 } 6196 6197 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6198 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6199 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6200 "Memory operands expect pointer values"); 6201 6202 // Add information to the INLINEASM node to know about this input. 6203 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6204 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6205 TLI.getPointerTy())); 6206 AsmNodeOperands.push_back(InOperandVal); 6207 break; 6208 } 6209 6210 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6211 OpInfo.ConstraintType == TargetLowering::C_Register) && 6212 "Unknown constraint type!"); 6213 assert(!OpInfo.isIndirect && 6214 "Don't know how to handle indirect register inputs yet!"); 6215 6216 // Copy the input into the appropriate registers. 6217 if (OpInfo.AssignedRegs.Regs.empty()) 6218 report_fatal_error("Couldn't allocate input reg for constraint '" + 6219 Twine(OpInfo.ConstraintCode) + "'!"); 6220 6221 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6222 Chain, &Flag); 6223 6224 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6225 DAG, AsmNodeOperands); 6226 break; 6227 } 6228 case InlineAsm::isClobber: { 6229 // Add the clobbered value to the operand list, so that the register 6230 // allocator is aware that the physreg got clobbered. 6231 if (!OpInfo.AssignedRegs.Regs.empty()) 6232 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6233 false, 0, DAG, 6234 AsmNodeOperands); 6235 break; 6236 } 6237 } 6238 } 6239 6240 // Finish up input operands. Set the input chain and add the flag last. 6241 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6242 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6243 6244 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6245 DAG.getVTList(MVT::Other, MVT::Glue), 6246 &AsmNodeOperands[0], AsmNodeOperands.size()); 6247 Flag = Chain.getValue(1); 6248 6249 // If this asm returns a register value, copy the result from that register 6250 // and set it as the value of the call. 6251 if (!RetValRegs.Regs.empty()) { 6252 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6253 Chain, &Flag); 6254 6255 // FIXME: Why don't we do this for inline asms with MRVs? 6256 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6257 EVT ResultType = TLI.getValueType(CS.getType()); 6258 6259 // If any of the results of the inline asm is a vector, it may have the 6260 // wrong width/num elts. This can happen for register classes that can 6261 // contain multiple different value types. The preg or vreg allocated may 6262 // not have the same VT as was expected. Convert it to the right type 6263 // with bit_convert. 6264 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6265 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6266 ResultType, Val); 6267 6268 } else if (ResultType != Val.getValueType() && 6269 ResultType.isInteger() && Val.getValueType().isInteger()) { 6270 // If a result value was tied to an input value, the computed result may 6271 // have a wider width than the expected result. Extract the relevant 6272 // portion. 6273 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6274 } 6275 6276 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6277 } 6278 6279 setValue(CS.getInstruction(), Val); 6280 // Don't need to use this as a chain in this case. 6281 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6282 return; 6283 } 6284 6285 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6286 6287 // Process indirect outputs, first output all of the flagged copies out of 6288 // physregs. 6289 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6290 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6291 const Value *Ptr = IndirectStoresToEmit[i].second; 6292 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6293 Chain, &Flag); 6294 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6295 } 6296 6297 // Emit the non-flagged stores from the physregs. 6298 SmallVector<SDValue, 8> OutChains; 6299 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6300 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6301 StoresToEmit[i].first, 6302 getValue(StoresToEmit[i].second), 6303 MachinePointerInfo(StoresToEmit[i].second), 6304 false, false, 0); 6305 OutChains.push_back(Val); 6306 } 6307 6308 if (!OutChains.empty()) 6309 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6310 &OutChains[0], OutChains.size()); 6311 6312 DAG.setRoot(Chain); 6313} 6314 6315void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6316 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6317 MVT::Other, getRoot(), 6318 getValue(I.getArgOperand(0)), 6319 DAG.getSrcValue(I.getArgOperand(0)))); 6320} 6321 6322void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6323 const TargetData &TD = *TLI.getTargetData(); 6324 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6325 getRoot(), getValue(I.getOperand(0)), 6326 DAG.getSrcValue(I.getOperand(0)), 6327 TD.getABITypeAlignment(I.getType())); 6328 setValue(&I, V); 6329 DAG.setRoot(V.getValue(1)); 6330} 6331 6332void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6333 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6334 MVT::Other, getRoot(), 6335 getValue(I.getArgOperand(0)), 6336 DAG.getSrcValue(I.getArgOperand(0)))); 6337} 6338 6339void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6340 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6341 MVT::Other, getRoot(), 6342 getValue(I.getArgOperand(0)), 6343 getValue(I.getArgOperand(1)), 6344 DAG.getSrcValue(I.getArgOperand(0)), 6345 DAG.getSrcValue(I.getArgOperand(1)))); 6346} 6347 6348/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6349/// implementation, which just calls LowerCall. 6350/// FIXME: When all targets are 6351/// migrated to using LowerCall, this hook should be integrated into SDISel. 6352std::pair<SDValue, SDValue> 6353TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6354 bool RetSExt, bool RetZExt, bool isVarArg, 6355 bool isInreg, unsigned NumFixedArgs, 6356 CallingConv::ID CallConv, bool isTailCall, 6357 bool isReturnValueUsed, 6358 SDValue Callee, 6359 ArgListTy &Args, SelectionDAG &DAG, 6360 DebugLoc dl) const { 6361 // Handle all of the outgoing arguments. 6362 SmallVector<ISD::OutputArg, 32> Outs; 6363 SmallVector<SDValue, 32> OutVals; 6364 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6365 SmallVector<EVT, 4> ValueVTs; 6366 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6367 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6368 Value != NumValues; ++Value) { 6369 EVT VT = ValueVTs[Value]; 6370 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6371 SDValue Op = SDValue(Args[i].Node.getNode(), 6372 Args[i].Node.getResNo() + Value); 6373 ISD::ArgFlagsTy Flags; 6374 unsigned OriginalAlignment = 6375 getTargetData()->getABITypeAlignment(ArgTy); 6376 6377 if (Args[i].isZExt) 6378 Flags.setZExt(); 6379 if (Args[i].isSExt) 6380 Flags.setSExt(); 6381 if (Args[i].isInReg) 6382 Flags.setInReg(); 6383 if (Args[i].isSRet) 6384 Flags.setSRet(); 6385 if (Args[i].isByVal) { 6386 Flags.setByVal(); 6387 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6388 Type *ElementTy = Ty->getElementType(); 6389 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6390 // For ByVal, alignment should come from FE. BE will guess if this 6391 // info is not there but there are cases it cannot get right. 6392 unsigned FrameAlign; 6393 if (Args[i].Alignment) 6394 FrameAlign = Args[i].Alignment; 6395 else 6396 FrameAlign = getByValTypeAlignment(ElementTy); 6397 Flags.setByValAlign(FrameAlign); 6398 } 6399 if (Args[i].isNest) 6400 Flags.setNest(); 6401 Flags.setOrigAlign(OriginalAlignment); 6402 6403 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6404 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6405 SmallVector<SDValue, 4> Parts(NumParts); 6406 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6407 6408 if (Args[i].isSExt) 6409 ExtendKind = ISD::SIGN_EXTEND; 6410 else if (Args[i].isZExt) 6411 ExtendKind = ISD::ZERO_EXTEND; 6412 6413 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6414 PartVT, ExtendKind); 6415 6416 for (unsigned j = 0; j != NumParts; ++j) { 6417 // if it isn't first piece, alignment must be 1 6418 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6419 i < NumFixedArgs); 6420 if (NumParts > 1 && j == 0) 6421 MyFlags.Flags.setSplit(); 6422 else if (j != 0) 6423 MyFlags.Flags.setOrigAlign(1); 6424 6425 Outs.push_back(MyFlags); 6426 OutVals.push_back(Parts[j]); 6427 } 6428 } 6429 } 6430 6431 // Handle the incoming return values from the call. 6432 SmallVector<ISD::InputArg, 32> Ins; 6433 SmallVector<EVT, 4> RetTys; 6434 ComputeValueVTs(*this, RetTy, RetTys); 6435 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6436 EVT VT = RetTys[I]; 6437 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6438 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6439 for (unsigned i = 0; i != NumRegs; ++i) { 6440 ISD::InputArg MyFlags; 6441 MyFlags.VT = RegisterVT.getSimpleVT(); 6442 MyFlags.Used = isReturnValueUsed; 6443 if (RetSExt) 6444 MyFlags.Flags.setSExt(); 6445 if (RetZExt) 6446 MyFlags.Flags.setZExt(); 6447 if (isInreg) 6448 MyFlags.Flags.setInReg(); 6449 Ins.push_back(MyFlags); 6450 } 6451 } 6452 6453 SmallVector<SDValue, 4> InVals; 6454 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6455 Outs, OutVals, Ins, dl, DAG, InVals); 6456 6457 // Verify that the target's LowerCall behaved as expected. 6458 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6459 "LowerCall didn't return a valid chain!"); 6460 assert((!isTailCall || InVals.empty()) && 6461 "LowerCall emitted a return value for a tail call!"); 6462 assert((isTailCall || InVals.size() == Ins.size()) && 6463 "LowerCall didn't emit the correct number of values!"); 6464 6465 // For a tail call, the return value is merely live-out and there aren't 6466 // any nodes in the DAG representing it. Return a special value to 6467 // indicate that a tail call has been emitted and no more Instructions 6468 // should be processed in the current block. 6469 if (isTailCall) { 6470 DAG.setRoot(Chain); 6471 return std::make_pair(SDValue(), SDValue()); 6472 } 6473 6474 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6475 assert(InVals[i].getNode() && 6476 "LowerCall emitted a null value!"); 6477 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6478 "LowerCall emitted a value with the wrong type!"); 6479 }); 6480 6481 // Collect the legal value parts into potentially illegal values 6482 // that correspond to the original function's return values. 6483 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6484 if (RetSExt) 6485 AssertOp = ISD::AssertSext; 6486 else if (RetZExt) 6487 AssertOp = ISD::AssertZext; 6488 SmallVector<SDValue, 4> ReturnValues; 6489 unsigned CurReg = 0; 6490 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6491 EVT VT = RetTys[I]; 6492 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6493 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6494 6495 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6496 NumRegs, RegisterVT, VT, 6497 AssertOp)); 6498 CurReg += NumRegs; 6499 } 6500 6501 // For a function returning void, there is no return value. We can't create 6502 // such a node, so we just return a null return value in that case. In 6503 // that case, nothing will actually look at the value. 6504 if (ReturnValues.empty()) 6505 return std::make_pair(SDValue(), Chain); 6506 6507 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6508 DAG.getVTList(&RetTys[0], RetTys.size()), 6509 &ReturnValues[0], ReturnValues.size()); 6510 return std::make_pair(Res, Chain); 6511} 6512 6513void TargetLowering::LowerOperationWrapper(SDNode *N, 6514 SmallVectorImpl<SDValue> &Results, 6515 SelectionDAG &DAG) const { 6516 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6517 if (Res.getNode()) 6518 Results.push_back(Res); 6519} 6520 6521SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6522 llvm_unreachable("LowerOperation not implemented for this target!"); 6523 return SDValue(); 6524} 6525 6526void 6527SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6528 SDValue Op = getNonRegisterValue(V); 6529 assert((Op.getOpcode() != ISD::CopyFromReg || 6530 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6531 "Copy from a reg to the same reg!"); 6532 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6533 6534 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6535 SDValue Chain = DAG.getEntryNode(); 6536 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6537 PendingExports.push_back(Chain); 6538} 6539 6540#include "llvm/CodeGen/SelectionDAGISel.h" 6541 6542/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6543/// entry block, return true. This includes arguments used by switches, since 6544/// the switch may expand into multiple basic blocks. 6545static bool isOnlyUsedInEntryBlock(const Argument *A) { 6546 // With FastISel active, we may be splitting blocks, so force creation 6547 // of virtual registers for all non-dead arguments. 6548 if (EnableFastISel) 6549 return A->use_empty(); 6550 6551 const BasicBlock *Entry = A->getParent()->begin(); 6552 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6553 UI != E; ++UI) { 6554 const User *U = *UI; 6555 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6556 return false; // Use not in entry block. 6557 } 6558 return true; 6559} 6560 6561void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6562 // If this is the entry block, emit arguments. 6563 const Function &F = *LLVMBB->getParent(); 6564 SelectionDAG &DAG = SDB->DAG; 6565 DebugLoc dl = SDB->getCurDebugLoc(); 6566 const TargetData *TD = TLI.getTargetData(); 6567 SmallVector<ISD::InputArg, 16> Ins; 6568 6569 // Check whether the function can return without sret-demotion. 6570 SmallVector<ISD::OutputArg, 4> Outs; 6571 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6572 Outs, TLI); 6573 6574 if (!FuncInfo->CanLowerReturn) { 6575 // Put in an sret pointer parameter before all the other parameters. 6576 SmallVector<EVT, 1> ValueVTs; 6577 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6578 6579 // NOTE: Assuming that a pointer will never break down to more than one VT 6580 // or one register. 6581 ISD::ArgFlagsTy Flags; 6582 Flags.setSRet(); 6583 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6584 ISD::InputArg RetArg(Flags, RegisterVT, true); 6585 Ins.push_back(RetArg); 6586 } 6587 6588 // Set up the incoming argument description vector. 6589 unsigned Idx = 1; 6590 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6591 I != E; ++I, ++Idx) { 6592 SmallVector<EVT, 4> ValueVTs; 6593 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6594 bool isArgValueUsed = !I->use_empty(); 6595 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6596 Value != NumValues; ++Value) { 6597 EVT VT = ValueVTs[Value]; 6598 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6599 ISD::ArgFlagsTy Flags; 6600 unsigned OriginalAlignment = 6601 TD->getABITypeAlignment(ArgTy); 6602 6603 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6604 Flags.setZExt(); 6605 if (F.paramHasAttr(Idx, Attribute::SExt)) 6606 Flags.setSExt(); 6607 if (F.paramHasAttr(Idx, Attribute::InReg)) 6608 Flags.setInReg(); 6609 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6610 Flags.setSRet(); 6611 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6612 Flags.setByVal(); 6613 PointerType *Ty = cast<PointerType>(I->getType()); 6614 Type *ElementTy = Ty->getElementType(); 6615 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6616 // For ByVal, alignment should be passed from FE. BE will guess if 6617 // this info is not there but there are cases it cannot get right. 6618 unsigned FrameAlign; 6619 if (F.getParamAlignment(Idx)) 6620 FrameAlign = F.getParamAlignment(Idx); 6621 else 6622 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6623 Flags.setByValAlign(FrameAlign); 6624 } 6625 if (F.paramHasAttr(Idx, Attribute::Nest)) 6626 Flags.setNest(); 6627 Flags.setOrigAlign(OriginalAlignment); 6628 6629 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6630 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6631 for (unsigned i = 0; i != NumRegs; ++i) { 6632 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6633 if (NumRegs > 1 && i == 0) 6634 MyFlags.Flags.setSplit(); 6635 // if it isn't first piece, alignment must be 1 6636 else if (i > 0) 6637 MyFlags.Flags.setOrigAlign(1); 6638 Ins.push_back(MyFlags); 6639 } 6640 } 6641 } 6642 6643 // Call the target to set up the argument values. 6644 SmallVector<SDValue, 8> InVals; 6645 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6646 F.isVarArg(), Ins, 6647 dl, DAG, InVals); 6648 6649 // Verify that the target's LowerFormalArguments behaved as expected. 6650 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6651 "LowerFormalArguments didn't return a valid chain!"); 6652 assert(InVals.size() == Ins.size() && 6653 "LowerFormalArguments didn't emit the correct number of values!"); 6654 DEBUG({ 6655 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6656 assert(InVals[i].getNode() && 6657 "LowerFormalArguments emitted a null value!"); 6658 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6659 "LowerFormalArguments emitted a value with the wrong type!"); 6660 } 6661 }); 6662 6663 // Update the DAG with the new chain value resulting from argument lowering. 6664 DAG.setRoot(NewRoot); 6665 6666 // Set up the argument values. 6667 unsigned i = 0; 6668 Idx = 1; 6669 if (!FuncInfo->CanLowerReturn) { 6670 // Create a virtual register for the sret pointer, and put in a copy 6671 // from the sret argument into it. 6672 SmallVector<EVT, 1> ValueVTs; 6673 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6674 EVT VT = ValueVTs[0]; 6675 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6676 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6677 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6678 RegVT, VT, AssertOp); 6679 6680 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6681 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6682 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6683 FuncInfo->DemoteRegister = SRetReg; 6684 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6685 SRetReg, ArgValue); 6686 DAG.setRoot(NewRoot); 6687 6688 // i indexes lowered arguments. Bump it past the hidden sret argument. 6689 // Idx indexes LLVM arguments. Don't touch it. 6690 ++i; 6691 } 6692 6693 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6694 ++I, ++Idx) { 6695 SmallVector<SDValue, 4> ArgValues; 6696 SmallVector<EVT, 4> ValueVTs; 6697 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6698 unsigned NumValues = ValueVTs.size(); 6699 6700 // If this argument is unused then remember its value. It is used to generate 6701 // debugging information. 6702 if (I->use_empty() && NumValues) 6703 SDB->setUnusedArgValue(I, InVals[i]); 6704 6705 for (unsigned Val = 0; Val != NumValues; ++Val) { 6706 EVT VT = ValueVTs[Val]; 6707 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6708 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6709 6710 if (!I->use_empty()) { 6711 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6712 if (F.paramHasAttr(Idx, Attribute::SExt)) 6713 AssertOp = ISD::AssertSext; 6714 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6715 AssertOp = ISD::AssertZext; 6716 6717 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6718 NumParts, PartVT, VT, 6719 AssertOp)); 6720 } 6721 6722 i += NumParts; 6723 } 6724 6725 // We don't need to do anything else for unused arguments. 6726 if (ArgValues.empty()) 6727 continue; 6728 6729 // Note down frame index. 6730 if (FrameIndexSDNode *FI = 6731 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6732 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6733 6734 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6735 SDB->getCurDebugLoc()); 6736 6737 SDB->setValue(I, Res); 6738 if (!EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6739 if (LoadSDNode *LNode = 6740 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6741 if (FrameIndexSDNode *FI = 6742 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6743 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6744 } 6745 6746 // If this argument is live outside of the entry block, insert a copy from 6747 // wherever we got it to the vreg that other BB's will reference it as. 6748 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6749 // If we can, though, try to skip creating an unnecessary vreg. 6750 // FIXME: This isn't very clean... it would be nice to make this more 6751 // general. It's also subtly incompatible with the hacks FastISel 6752 // uses with vregs. 6753 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6754 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6755 FuncInfo->ValueMap[I] = Reg; 6756 continue; 6757 } 6758 } 6759 if (!isOnlyUsedInEntryBlock(I)) { 6760 FuncInfo->InitializeRegForValue(I); 6761 SDB->CopyToExportRegsIfNeeded(I); 6762 } 6763 } 6764 6765 assert(i == InVals.size() && "Argument register count mismatch!"); 6766 6767 // Finally, if the target has anything special to do, allow it to do so. 6768 // FIXME: this should insert code into the DAG! 6769 EmitFunctionEntryCode(); 6770} 6771 6772/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6773/// ensure constants are generated when needed. Remember the virtual registers 6774/// that need to be added to the Machine PHI nodes as input. We cannot just 6775/// directly add them, because expansion might result in multiple MBB's for one 6776/// BB. As such, the start of the BB might correspond to a different MBB than 6777/// the end. 6778/// 6779void 6780SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6781 const TerminatorInst *TI = LLVMBB->getTerminator(); 6782 6783 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6784 6785 // Check successor nodes' PHI nodes that expect a constant to be available 6786 // from this block. 6787 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6788 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6789 if (!isa<PHINode>(SuccBB->begin())) continue; 6790 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6791 6792 // If this terminator has multiple identical successors (common for 6793 // switches), only handle each succ once. 6794 if (!SuccsHandled.insert(SuccMBB)) continue; 6795 6796 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6797 6798 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6799 // nodes and Machine PHI nodes, but the incoming operands have not been 6800 // emitted yet. 6801 for (BasicBlock::const_iterator I = SuccBB->begin(); 6802 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6803 // Ignore dead phi's. 6804 if (PN->use_empty()) continue; 6805 6806 // Skip empty types 6807 if (PN->getType()->isEmptyTy()) 6808 continue; 6809 6810 unsigned Reg; 6811 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6812 6813 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6814 unsigned &RegOut = ConstantsOut[C]; 6815 if (RegOut == 0) { 6816 RegOut = FuncInfo.CreateRegs(C->getType()); 6817 CopyValueToVirtualRegister(C, RegOut); 6818 } 6819 Reg = RegOut; 6820 } else { 6821 DenseMap<const Value *, unsigned>::iterator I = 6822 FuncInfo.ValueMap.find(PHIOp); 6823 if (I != FuncInfo.ValueMap.end()) 6824 Reg = I->second; 6825 else { 6826 assert(isa<AllocaInst>(PHIOp) && 6827 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6828 "Didn't codegen value into a register!??"); 6829 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6830 CopyValueToVirtualRegister(PHIOp, Reg); 6831 } 6832 } 6833 6834 // Remember that this register needs to added to the machine PHI node as 6835 // the input for this MBB. 6836 SmallVector<EVT, 4> ValueVTs; 6837 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6838 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6839 EVT VT = ValueVTs[vti]; 6840 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6841 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6842 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6843 Reg += NumRegisters; 6844 } 6845 } 6846 } 6847 ConstantsOut.clear(); 6848} 6849