SelectionDAGBuilder.cpp revision c8f34de5d615b858319f33d4e19c24622d971416
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetData.h" 48#include "llvm/Target/TargetFrameLowering.h" 49#include "llvm/Target/TargetInstrInfo.h" 50#include "llvm/Target/TargetIntrinsicInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getIntPtrConstant(1)); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209 return SDValue(); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert(PartVT.isInteger() && ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 } 361 } else if (PartBits == ValueVT.getSizeInBits()) { 362 // Different types of the same size. 363 assert(NumParts == 1 && PartVT != ValueVT); 364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 366 // If the parts cover less bits than value has, truncate the value. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Unknown mismatch!"); 369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 371 } 372 373 // The value may have changed - recompute ValueVT. 374 ValueVT = Val.getValueType(); 375 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 376 "Failed to tile the value with PartVT!"); 377 378 if (NumParts == 1) { 379 assert(PartVT == ValueVT && "Type conversion failed!"); 380 Parts[0] = Val; 381 return; 382 } 383 384 // Expand the value into multiple parts. 385 if (NumParts & (NumParts - 1)) { 386 // The number of parts is not a power of 2. Split off and copy the tail. 387 assert(PartVT.isInteger() && ValueVT.isInteger() && 388 "Do not know what to expand to!"); 389 unsigned RoundParts = 1 << Log2_32(NumParts); 390 unsigned RoundBits = RoundParts * PartBits; 391 unsigned OddParts = NumParts - RoundParts; 392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 393 DAG.getIntPtrConstant(RoundBits)); 394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 395 396 if (TLI.isBigEndian()) 397 // The odd parts were reversed by getCopyToParts - unreverse them. 398 std::reverse(Parts + RoundParts, Parts + NumParts); 399 400 NumParts = RoundParts; 401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 403 } 404 405 // The number of parts is a power of 2. Repeatedly bisect the value using 406 // EXTRACT_ELEMENT. 407 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 408 EVT::getIntegerVT(*DAG.getContext(), 409 ValueVT.getSizeInBits()), 410 Val); 411 412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 413 for (unsigned i = 0; i < NumParts; i += StepSize) { 414 unsigned ThisBits = StepSize * PartBits / 2; 415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 416 SDValue &Part0 = Parts[i]; 417 SDValue &Part1 = Parts[i+StepSize/2]; 418 419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 420 ThisVT, Part0, DAG.getIntPtrConstant(1)); 421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 422 ThisVT, Part0, DAG.getIntPtrConstant(0)); 423 424 if (ThisBits == PartBits && ThisVT != PartVT) { 425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 427 } 428 } 429 } 430 431 if (TLI.isBigEndian()) 432 std::reverse(Parts, Parts + OrigNumParts); 433} 434 435 436/// getCopyToPartsVector - Create a series of nodes that contain the specified 437/// value split into legal parts. 438static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 439 SDValue Val, SDValue *Parts, unsigned NumParts, 440 EVT PartVT) { 441 EVT ValueVT = Val.getValueType(); 442 assert(ValueVT.isVector() && "Not a vector"); 443 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 444 445 if (NumParts == 1) { 446 if (PartVT == ValueVT) { 447 // Nothing to do. 448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 449 // Bitconvert vector->vector case. 450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 451 } else if (PartVT.isVector() && 452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 454 EVT ElementVT = PartVT.getVectorElementType(); 455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 456 // undef elements. 457 SmallVector<SDValue, 16> Ops; 458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 460 ElementVT, Val, DAG.getIntPtrConstant(i))); 461 462 for (unsigned i = ValueVT.getVectorNumElements(), 463 e = PartVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getUNDEF(ElementVT)); 465 466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 467 468 // FIXME: Use CONCAT for 2x -> 4x. 469 470 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 472 } else if (PartVT.isVector() && 473 PartVT.getVectorElementType().bitsGE( 474 ValueVT.getVectorElementType()) && 475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 476 477 // Promoted vector extract 478 bool Smaller = PartVT.bitsLE(ValueVT); 479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 480 DL, PartVT, Val); 481 } else{ 482 // Vector -> scalar conversion. 483 assert(ValueVT.getVectorNumElements() == 1 && 484 "Only trivial vector-to-scalar conversions should get here!"); 485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 PartVT, Val, DAG.getIntPtrConstant(0)); 487 488 bool Smaller = ValueVT.bitsLE(PartVT); 489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 490 DL, PartVT, Val); 491 } 492 493 Parts[0] = Val; 494 return; 495 } 496 497 // Handle a multi-element vector. 498 EVT IntermediateVT, RegisterVT; 499 unsigned NumIntermediates; 500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 501 IntermediateVT, 502 NumIntermediates, RegisterVT); 503 unsigned NumElements = ValueVT.getVectorNumElements(); 504 505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 506 NumParts = NumRegs; // Silence a compiler warning. 507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 508 509 // Split the vector into intermediate operands. 510 SmallVector<SDValue, 8> Ops(NumIntermediates); 511 for (unsigned i = 0; i != NumIntermediates; ++i) { 512 if (IntermediateVT.isVector()) 513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 514 IntermediateVT, Val, 515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 516 else 517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 519 } 520 521 // Split the intermediate operands into legal parts. 522 if (NumParts == NumIntermediates) { 523 // If the register was not expanded, promote or copy the value, 524 // as appropriate. 525 for (unsigned i = 0; i != NumParts; ++i) 526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 527 } else if (NumParts > 0) { 528 // If the intermediate type was expanded, split each the value into 529 // legal parts. 530 assert(NumParts % NumIntermediates == 0 && 531 "Must expand into a divisible number of parts!"); 532 unsigned Factor = NumParts / NumIntermediates; 533 for (unsigned i = 0; i != NumIntermediates; ++i) 534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 535 } 536} 537 538 539 540 541namespace { 542 /// RegsForValue - This struct represents the registers (physical or virtual) 543 /// that a particular set of values is assigned, and the type information 544 /// about the value. The most common situation is to represent one value at a 545 /// time, but struct or array values are handled element-wise as multiple 546 /// values. The splitting of aggregates is performed recursively, so that we 547 /// never have aggregate-typed registers. The values at this point do not 548 /// necessarily have legal types, so each value may require one or more 549 /// registers of some legal type. 550 /// 551 struct RegsForValue { 552 /// ValueVTs - The value types of the values, which may not be legal, and 553 /// may need be promoted or synthesized from one or more registers. 554 /// 555 SmallVector<EVT, 4> ValueVTs; 556 557 /// RegVTs - The value types of the registers. This is the same size as 558 /// ValueVTs and it records, for each value, what the type of the assigned 559 /// register or registers are. (Individual values are never synthesized 560 /// from more than one type of register.) 561 /// 562 /// With virtual registers, the contents of RegVTs is redundant with TLI's 563 /// getRegisterType member function, however when with physical registers 564 /// it is necessary to have a separate record of the types. 565 /// 566 SmallVector<EVT, 4> RegVTs; 567 568 /// Regs - This list holds the registers assigned to the values. 569 /// Each legal or promoted value requires one register, and each 570 /// expanded value requires multiple registers. 571 /// 572 SmallVector<unsigned, 4> Regs; 573 574 RegsForValue() {} 575 576 RegsForValue(const SmallVector<unsigned, 4> ®s, 577 EVT regvt, EVT valuevt) 578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 579 580 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 581 unsigned Reg, Type *Ty) { 582 ComputeValueVTs(tli, Ty, ValueVTs); 583 584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 585 EVT ValueVT = ValueVTs[Value]; 586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 588 for (unsigned i = 0; i != NumRegs; ++i) 589 Regs.push_back(Reg + i); 590 RegVTs.push_back(RegisterVT); 591 Reg += NumRegs; 592 } 593 } 594 595 /// areValueTypesLegal - Return true if types of all the values are legal. 596 bool areValueTypesLegal(const TargetLowering &TLI) { 597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 598 EVT RegisterVT = RegVTs[Value]; 599 if (!TLI.isTypeLegal(RegisterVT)) 600 return false; 601 } 602 return true; 603 } 604 605 /// append - Add the specified values to this one. 606 void append(const RegsForValue &RHS) { 607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 609 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 610 } 611 612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 613 /// this value and returns the result as a ValueVTs value. This uses 614 /// Chain/Flag as the input and updates them for the output Chain/Flag. 615 /// If the Flag pointer is NULL, no flag is used. 616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 617 DebugLoc dl, 618 SDValue &Chain, SDValue *Flag) const; 619 620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 621 /// specified value into the registers specified by this object. This uses 622 /// Chain/Flag as the input and updates them for the output Chain/Flag. 623 /// If the Flag pointer is NULL, no flag is used. 624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 625 SDValue &Chain, SDValue *Flag) const; 626 627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 628 /// operand list. This adds the code marker, matching input operand index 629 /// (if applicable), and includes the number of values added into it. 630 void AddInlineAsmOperands(unsigned Kind, 631 bool HasMatching, unsigned MatchingIdx, 632 SelectionDAG &DAG, 633 std::vector<SDValue> &Ops) const; 634 }; 635} 636 637/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 638/// this value and returns the result as a ValueVT value. This uses 639/// Chain/Flag as the input and updates them for the output Chain/Flag. 640/// If the Flag pointer is NULL, no flag is used. 641SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 642 FunctionLoweringInfo &FuncInfo, 643 DebugLoc dl, 644 SDValue &Chain, SDValue *Flag) const { 645 // A Value with type {} or [0 x %t] needs no registers. 646 if (ValueVTs.empty()) 647 return SDValue(); 648 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 650 651 // Assemble the legal parts into the final values. 652 SmallVector<SDValue, 4> Values(ValueVTs.size()); 653 SmallVector<SDValue, 8> Parts; 654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 655 // Copy the legal parts from the registers. 656 EVT ValueVT = ValueVTs[Value]; 657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 658 EVT RegisterVT = RegVTs[Value]; 659 660 Parts.resize(NumRegs); 661 for (unsigned i = 0; i != NumRegs; ++i) { 662 SDValue P; 663 if (Flag == 0) { 664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 665 } else { 666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 667 *Flag = P.getValue(2); 668 } 669 670 Chain = P.getValue(1); 671 Parts[i] = P; 672 673 // If the source register was virtual and if we know something about it, 674 // add an assert node. 675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 676 !RegisterVT.isInteger() || RegisterVT.isVector()) 677 continue; 678 679 const FunctionLoweringInfo::LiveOutInfo *LOI = 680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 681 if (!LOI) 682 continue; 683 684 unsigned RegSize = RegisterVT.getSizeInBits(); 685 unsigned NumSignBits = LOI->NumSignBits; 686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 687 688 // FIXME: We capture more information than the dag can represent. For 689 // now, just use the tightest assertzext/assertsext possible. 690 bool isSExt = true; 691 EVT FromVT(MVT::Other); 692 if (NumSignBits == RegSize) 693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 694 else if (NumZeroBits >= RegSize-1) 695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 696 else if (NumSignBits > RegSize-8) 697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 698 else if (NumZeroBits >= RegSize-8) 699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 700 else if (NumSignBits > RegSize-16) 701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 702 else if (NumZeroBits >= RegSize-16) 703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 704 else if (NumSignBits > RegSize-32) 705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 706 else if (NumZeroBits >= RegSize-32) 707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 708 else 709 continue; 710 711 // Add an assertion node. 712 assert(FromVT != MVT::Other); 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 714 RegisterVT, P, DAG.getValueType(FromVT)); 715 } 716 717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 718 NumRegs, RegisterVT, ValueVT); 719 Part += NumRegs; 720 Parts.clear(); 721 } 722 723 return DAG.getNode(ISD::MERGE_VALUES, dl, 724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 725 &Values[0], ValueVTs.size()); 726} 727 728/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 729/// specified value into the registers specified by this object. This uses 730/// Chain/Flag as the input and updates them for the output Chain/Flag. 731/// If the Flag pointer is NULL, no flag is used. 732void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 733 SDValue &Chain, SDValue *Flag) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 // Get the list of the values's legal parts. 737 unsigned NumRegs = Regs.size(); 738 SmallVector<SDValue, 8> Parts(NumRegs); 739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 740 EVT ValueVT = ValueVTs[Value]; 741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 742 EVT RegisterVT = RegVTs[Value]; 743 744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 745 &Parts[Part], NumParts, RegisterVT); 746 Part += NumParts; 747 } 748 749 // Copy the parts into the registers. 750 SmallVector<SDValue, 8> Chains(NumRegs); 751 for (unsigned i = 0; i != NumRegs; ++i) { 752 SDValue Part; 753 if (Flag == 0) { 754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 755 } else { 756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 757 *Flag = Part.getValue(1); 758 } 759 760 Chains[i] = Part.getValue(0); 761 } 762 763 if (NumRegs == 1 || Flag) 764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 765 // flagged to it. That is the CopyToReg nodes and the user are considered 766 // a single scheduling unit. If we create a TokenFactor and return it as 767 // chain, then the TokenFactor is both a predecessor (operand) of the 768 // user as well as a successor (the TF operands are flagged to the user). 769 // c1, f1 = CopyToReg 770 // c2, f2 = CopyToReg 771 // c3 = TokenFactor c1, c2 772 // ... 773 // = op c3, ..., f2 774 Chain = Chains[NumRegs-1]; 775 else 776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 777} 778 779/// AddInlineAsmOperands - Add this value to the specified inlineasm node 780/// operand list. This adds the code marker and includes the number of 781/// values added into it. 782void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 783 unsigned MatchingIdx, 784 SelectionDAG &DAG, 785 std::vector<SDValue> &Ops) const { 786 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 787 788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 789 if (HasMatching) 790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 791 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 792 Ops.push_back(Res); 793 794 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 795 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 796 EVT RegisterVT = RegVTs[Value]; 797 for (unsigned i = 0; i != NumRegs; ++i) { 798 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 799 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 800 } 801 } 802} 803 804void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 805 AA = &aa; 806 GFI = gfi; 807 TD = DAG.getTarget().getTargetData(); 808} 809 810/// clear - Clear out the current SelectionDAG and the associated 811/// state and prepare this SelectionDAGBuilder object to be used 812/// for a new block. This doesn't clear out information about 813/// additional blocks that are needed to complete switch lowering 814/// or PHI node updating; that information is cleared out as it is 815/// consumed. 816void SelectionDAGBuilder::clear() { 817 NodeMap.clear(); 818 UnusedArgNodeMap.clear(); 819 PendingLoads.clear(); 820 PendingExports.clear(); 821 CurDebugLoc = DebugLoc(); 822 HasTailCall = false; 823} 824 825/// clearDanglingDebugInfo - Clear the dangling debug information 826/// map. This function is seperated from the clear so that debug 827/// information that is dangling in a basic block can be properly 828/// resolved in a different basic block. This allows the 829/// SelectionDAG to resolve dangling debug information attached 830/// to PHI nodes. 831void SelectionDAGBuilder::clearDanglingDebugInfo() { 832 DanglingDebugInfoMap.clear(); 833} 834 835/// getRoot - Return the current virtual root of the Selection DAG, 836/// flushing any PendingLoad items. This must be done before emitting 837/// a store or any other node that may need to be ordered after any 838/// prior load instructions. 839/// 840SDValue SelectionDAGBuilder::getRoot() { 841 if (PendingLoads.empty()) 842 return DAG.getRoot(); 843 844 if (PendingLoads.size() == 1) { 845 SDValue Root = PendingLoads[0]; 846 DAG.setRoot(Root); 847 PendingLoads.clear(); 848 return Root; 849 } 850 851 // Otherwise, we have to make a token factor node. 852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 853 &PendingLoads[0], PendingLoads.size()); 854 PendingLoads.clear(); 855 DAG.setRoot(Root); 856 return Root; 857} 858 859/// getControlRoot - Similar to getRoot, but instead of flushing all the 860/// PendingLoad items, flush all the PendingExports items. It is necessary 861/// to do this before emitting a terminator instruction. 862/// 863SDValue SelectionDAGBuilder::getControlRoot() { 864 SDValue Root = DAG.getRoot(); 865 866 if (PendingExports.empty()) 867 return Root; 868 869 // Turn all of the CopyToReg chains into one factored node. 870 if (Root.getOpcode() != ISD::EntryToken) { 871 unsigned i = 0, e = PendingExports.size(); 872 for (; i != e; ++i) { 873 assert(PendingExports[i].getNode()->getNumOperands() > 1); 874 if (PendingExports[i].getNode()->getOperand(0) == Root) 875 break; // Don't add the root if we already indirectly depend on it. 876 } 877 878 if (i == e) 879 PendingExports.push_back(Root); 880 } 881 882 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 883 &PendingExports[0], 884 PendingExports.size()); 885 PendingExports.clear(); 886 DAG.setRoot(Root); 887 return Root; 888} 889 890void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 891 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 892 DAG.AssignOrdering(Node, SDNodeOrder); 893 894 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 895 AssignOrderingToNode(Node->getOperand(I).getNode()); 896} 897 898void SelectionDAGBuilder::visit(const Instruction &I) { 899 // Set up outgoing PHI node register values before emitting the terminator. 900 if (isa<TerminatorInst>(&I)) 901 HandlePHINodesInSuccessorBlocks(I.getParent()); 902 903 CurDebugLoc = I.getDebugLoc(); 904 905 visit(I.getOpcode(), I); 906 907 if (!isa<TerminatorInst>(&I) && !HasTailCall) 908 CopyToExportRegsIfNeeded(&I); 909 910 CurDebugLoc = DebugLoc(); 911} 912 913void SelectionDAGBuilder::visitPHI(const PHINode &) { 914 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 915} 916 917void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 918 // Note: this doesn't use InstVisitor, because it has to work with 919 // ConstantExpr's in addition to instructions. 920 switch (Opcode) { 921 default: llvm_unreachable("Unknown instruction type encountered!"); 922 // Build the switch statement using the Instruction.def file. 923#define HANDLE_INST(NUM, OPCODE, CLASS) \ 924 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 925#include "llvm/Instruction.def" 926 } 927 928 // Assign the ordering to the freshly created DAG nodes. 929 if (NodeMap.count(&I)) { 930 ++SDNodeOrder; 931 AssignOrderingToNode(getValue(&I).getNode()); 932 } 933} 934 935// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 936// generate the debug data structures now that we've seen its definition. 937void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 938 SDValue Val) { 939 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 940 if (DDI.getDI()) { 941 const DbgValueInst *DI = DDI.getDI(); 942 DebugLoc dl = DDI.getdl(); 943 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 944 MDNode *Variable = DI->getVariable(); 945 uint64_t Offset = DI->getOffset(); 946 SDDbgValue *SDV; 947 if (Val.getNode()) { 948 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 949 SDV = DAG.getDbgValue(Variable, Val.getNode(), 950 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 951 DAG.AddDbgValue(SDV, Val.getNode(), false); 952 } 953 } else 954 DEBUG(dbgs() << "Dropping debug info for " << DI); 955 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 956 } 957} 958 959// getValue - Return an SDValue for the given Value. 960SDValue SelectionDAGBuilder::getValue(const Value *V) { 961 // If we already have an SDValue for this value, use it. It's important 962 // to do this first, so that we don't create a CopyFromReg if we already 963 // have a regular SDValue. 964 SDValue &N = NodeMap[V]; 965 if (N.getNode()) return N; 966 967 // If there's a virtual register allocated and initialized for this 968 // value, use it. 969 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 970 if (It != FuncInfo.ValueMap.end()) { 971 unsigned InReg = It->second; 972 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 973 SDValue Chain = DAG.getEntryNode(); 974 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 975 resolveDanglingDebugInfo(V, N); 976 return N; 977 } 978 979 // Otherwise create a new SDValue and remember it. 980 SDValue Val = getValueImpl(V); 981 NodeMap[V] = Val; 982 resolveDanglingDebugInfo(V, Val); 983 return Val; 984} 985 986/// getNonRegisterValue - Return an SDValue for the given Value, but 987/// don't look in FuncInfo.ValueMap for a virtual register. 988SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 989 // If we already have an SDValue for this value, use it. 990 SDValue &N = NodeMap[V]; 991 if (N.getNode()) return N; 992 993 // Otherwise create a new SDValue and remember it. 994 SDValue Val = getValueImpl(V); 995 NodeMap[V] = Val; 996 resolveDanglingDebugInfo(V, Val); 997 return Val; 998} 999 1000/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1001/// Create an SDValue for the given value. 1002SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1003 if (const Constant *C = dyn_cast<Constant>(V)) { 1004 EVT VT = TLI.getValueType(V->getType(), true); 1005 1006 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1007 return DAG.getConstant(*CI, VT); 1008 1009 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1010 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1011 1012 if (isa<ConstantPointerNull>(C)) 1013 return DAG.getConstant(0, TLI.getPointerTy()); 1014 1015 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1016 return DAG.getConstantFP(*CFP, VT); 1017 1018 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1019 return DAG.getUNDEF(VT); 1020 1021 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1022 visit(CE->getOpcode(), *CE); 1023 SDValue N1 = NodeMap[V]; 1024 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1025 return N1; 1026 } 1027 1028 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1029 SmallVector<SDValue, 4> Constants; 1030 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1031 OI != OE; ++OI) { 1032 SDNode *Val = getValue(*OI).getNode(); 1033 // If the operand is an empty aggregate, there are no values. 1034 if (!Val) continue; 1035 // Add each leaf value from the operand to the Constants list 1036 // to form a flattened list of all the values. 1037 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1038 Constants.push_back(SDValue(Val, i)); 1039 } 1040 1041 return DAG.getMergeValues(&Constants[0], Constants.size(), 1042 getCurDebugLoc()); 1043 } 1044 1045 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1046 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1047 "Unknown struct or array constant!"); 1048 1049 SmallVector<EVT, 4> ValueVTs; 1050 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1051 unsigned NumElts = ValueVTs.size(); 1052 if (NumElts == 0) 1053 return SDValue(); // empty struct 1054 SmallVector<SDValue, 4> Constants(NumElts); 1055 for (unsigned i = 0; i != NumElts; ++i) { 1056 EVT EltVT = ValueVTs[i]; 1057 if (isa<UndefValue>(C)) 1058 Constants[i] = DAG.getUNDEF(EltVT); 1059 else if (EltVT.isFloatingPoint()) 1060 Constants[i] = DAG.getConstantFP(0, EltVT); 1061 else 1062 Constants[i] = DAG.getConstant(0, EltVT); 1063 } 1064 1065 return DAG.getMergeValues(&Constants[0], NumElts, 1066 getCurDebugLoc()); 1067 } 1068 1069 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1070 return DAG.getBlockAddress(BA, VT); 1071 1072 VectorType *VecTy = cast<VectorType>(V->getType()); 1073 unsigned NumElements = VecTy->getNumElements(); 1074 1075 // Now that we know the number and type of the elements, get that number of 1076 // elements into the Ops array based on what kind of constant it is. 1077 SmallVector<SDValue, 16> Ops; 1078 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1079 for (unsigned i = 0; i != NumElements; ++i) 1080 Ops.push_back(getValue(CP->getOperand(i))); 1081 } else { 1082 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1083 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1084 1085 SDValue Op; 1086 if (EltVT.isFloatingPoint()) 1087 Op = DAG.getConstantFP(0, EltVT); 1088 else 1089 Op = DAG.getConstant(0, EltVT); 1090 Ops.assign(NumElements, Op); 1091 } 1092 1093 // Create a BUILD_VECTOR node. 1094 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1095 VT, &Ops[0], Ops.size()); 1096 } 1097 1098 // If this is a static alloca, generate it as the frameindex instead of 1099 // computation. 1100 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1101 DenseMap<const AllocaInst*, int>::iterator SI = 1102 FuncInfo.StaticAllocaMap.find(AI); 1103 if (SI != FuncInfo.StaticAllocaMap.end()) 1104 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1105 } 1106 1107 // If this is an instruction which fast-isel has deferred, select it now. 1108 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1109 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1110 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1111 SDValue Chain = DAG.getEntryNode(); 1112 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1113 } 1114 1115 llvm_unreachable("Can't get register for value!"); 1116 return SDValue(); 1117} 1118 1119void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1120 SDValue Chain = getControlRoot(); 1121 SmallVector<ISD::OutputArg, 8> Outs; 1122 SmallVector<SDValue, 8> OutVals; 1123 1124 if (!FuncInfo.CanLowerReturn) { 1125 unsigned DemoteReg = FuncInfo.DemoteRegister; 1126 const Function *F = I.getParent()->getParent(); 1127 1128 // Emit a store of the return value through the virtual register. 1129 // Leave Outs empty so that LowerReturn won't try to load return 1130 // registers the usual way. 1131 SmallVector<EVT, 1> PtrValueVTs; 1132 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1133 PtrValueVTs); 1134 1135 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1136 SDValue RetOp = getValue(I.getOperand(0)); 1137 1138 SmallVector<EVT, 4> ValueVTs; 1139 SmallVector<uint64_t, 4> Offsets; 1140 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1141 unsigned NumValues = ValueVTs.size(); 1142 1143 SmallVector<SDValue, 4> Chains(NumValues); 1144 for (unsigned i = 0; i != NumValues; ++i) { 1145 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1146 RetPtr.getValueType(), RetPtr, 1147 DAG.getIntPtrConstant(Offsets[i])); 1148 Chains[i] = 1149 DAG.getStore(Chain, getCurDebugLoc(), 1150 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1151 // FIXME: better loc info would be nice. 1152 Add, MachinePointerInfo(), false, false, 0); 1153 } 1154 1155 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1156 MVT::Other, &Chains[0], NumValues); 1157 } else if (I.getNumOperands() != 0) { 1158 SmallVector<EVT, 4> ValueVTs; 1159 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1160 unsigned NumValues = ValueVTs.size(); 1161 if (NumValues) { 1162 SDValue RetOp = getValue(I.getOperand(0)); 1163 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1164 EVT VT = ValueVTs[j]; 1165 1166 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1167 1168 const Function *F = I.getParent()->getParent(); 1169 if (F->paramHasAttr(0, Attribute::SExt)) 1170 ExtendKind = ISD::SIGN_EXTEND; 1171 else if (F->paramHasAttr(0, Attribute::ZExt)) 1172 ExtendKind = ISD::ZERO_EXTEND; 1173 1174 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1175 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1176 1177 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1178 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1179 SmallVector<SDValue, 4> Parts(NumParts); 1180 getCopyToParts(DAG, getCurDebugLoc(), 1181 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1182 &Parts[0], NumParts, PartVT, ExtendKind); 1183 1184 // 'inreg' on function refers to return value 1185 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1186 if (F->paramHasAttr(0, Attribute::InReg)) 1187 Flags.setInReg(); 1188 1189 // Propagate extension type if any 1190 if (ExtendKind == ISD::SIGN_EXTEND) 1191 Flags.setSExt(); 1192 else if (ExtendKind == ISD::ZERO_EXTEND) 1193 Flags.setZExt(); 1194 1195 for (unsigned i = 0; i < NumParts; ++i) { 1196 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1197 /*isfixed=*/true)); 1198 OutVals.push_back(Parts[i]); 1199 } 1200 } 1201 } 1202 } 1203 1204 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1205 CallingConv::ID CallConv = 1206 DAG.getMachineFunction().getFunction()->getCallingConv(); 1207 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1208 Outs, OutVals, getCurDebugLoc(), DAG); 1209 1210 // Verify that the target's LowerReturn behaved as expected. 1211 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1212 "LowerReturn didn't return a valid chain!"); 1213 1214 // Update the DAG with the new chain value resulting from return lowering. 1215 DAG.setRoot(Chain); 1216} 1217 1218/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1219/// created for it, emit nodes to copy the value into the virtual 1220/// registers. 1221void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1222 // Skip empty types 1223 if (V->getType()->isEmptyTy()) 1224 return; 1225 1226 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1227 if (VMI != FuncInfo.ValueMap.end()) { 1228 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1229 CopyValueToVirtualRegister(V, VMI->second); 1230 } 1231} 1232 1233/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1234/// the current basic block, add it to ValueMap now so that we'll get a 1235/// CopyTo/FromReg. 1236void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1237 // No need to export constants. 1238 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1239 1240 // Already exported? 1241 if (FuncInfo.isExportedInst(V)) return; 1242 1243 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1244 CopyValueToVirtualRegister(V, Reg); 1245} 1246 1247bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1248 const BasicBlock *FromBB) { 1249 // The operands of the setcc have to be in this block. We don't know 1250 // how to export them from some other block. 1251 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1252 // Can export from current BB. 1253 if (VI->getParent() == FromBB) 1254 return true; 1255 1256 // Is already exported, noop. 1257 return FuncInfo.isExportedInst(V); 1258 } 1259 1260 // If this is an argument, we can export it if the BB is the entry block or 1261 // if it is already exported. 1262 if (isa<Argument>(V)) { 1263 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1264 return true; 1265 1266 // Otherwise, can only export this if it is already exported. 1267 return FuncInfo.isExportedInst(V); 1268 } 1269 1270 // Otherwise, constants can always be exported. 1271 return true; 1272} 1273 1274/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1275uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src, 1276 MachineBasicBlock *Dst) { 1277 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1278 if (!BPI) 1279 return 0; 1280 const BasicBlock *SrcBB = Src->getBasicBlock(); 1281 const BasicBlock *DstBB = Dst->getBasicBlock(); 1282 return BPI->getEdgeWeight(SrcBB, DstBB); 1283} 1284 1285void SelectionDAGBuilder:: 1286addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1287 uint32_t Weight /* = 0 */) { 1288 if (!Weight) 1289 Weight = getEdgeWeight(Src, Dst); 1290 Src->addSuccessor(Dst, Weight); 1291} 1292 1293 1294static bool InBlock(const Value *V, const BasicBlock *BB) { 1295 if (const Instruction *I = dyn_cast<Instruction>(V)) 1296 return I->getParent() == BB; 1297 return true; 1298} 1299 1300/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1301/// This function emits a branch and is used at the leaves of an OR or an 1302/// AND operator tree. 1303/// 1304void 1305SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1306 MachineBasicBlock *TBB, 1307 MachineBasicBlock *FBB, 1308 MachineBasicBlock *CurBB, 1309 MachineBasicBlock *SwitchBB) { 1310 const BasicBlock *BB = CurBB->getBasicBlock(); 1311 1312 // If the leaf of the tree is a comparison, merge the condition into 1313 // the caseblock. 1314 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1315 // The operands of the cmp have to be in this block. We don't know 1316 // how to export them from some other block. If this is the first block 1317 // of the sequence, no exporting is needed. 1318 if (CurBB == SwitchBB || 1319 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1320 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1321 ISD::CondCode Condition; 1322 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1323 Condition = getICmpCondCode(IC->getPredicate()); 1324 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1325 Condition = getFCmpCondCode(FC->getPredicate()); 1326 } else { 1327 Condition = ISD::SETEQ; // silence warning. 1328 llvm_unreachable("Unknown compare instruction"); 1329 } 1330 1331 CaseBlock CB(Condition, BOp->getOperand(0), 1332 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1333 SwitchCases.push_back(CB); 1334 return; 1335 } 1336 } 1337 1338 // Create a CaseBlock record representing this branch. 1339 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1340 NULL, TBB, FBB, CurBB); 1341 SwitchCases.push_back(CB); 1342} 1343 1344/// FindMergedConditions - If Cond is an expression like 1345void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1346 MachineBasicBlock *TBB, 1347 MachineBasicBlock *FBB, 1348 MachineBasicBlock *CurBB, 1349 MachineBasicBlock *SwitchBB, 1350 unsigned Opc) { 1351 // If this node is not part of the or/and tree, emit it as a branch. 1352 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1353 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1354 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1355 BOp->getParent() != CurBB->getBasicBlock() || 1356 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1357 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1358 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1359 return; 1360 } 1361 1362 // Create TmpBB after CurBB. 1363 MachineFunction::iterator BBI = CurBB; 1364 MachineFunction &MF = DAG.getMachineFunction(); 1365 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1366 CurBB->getParent()->insert(++BBI, TmpBB); 1367 1368 if (Opc == Instruction::Or) { 1369 // Codegen X | Y as: 1370 // jmp_if_X TBB 1371 // jmp TmpBB 1372 // TmpBB: 1373 // jmp_if_Y TBB 1374 // jmp FBB 1375 // 1376 1377 // Emit the LHS condition. 1378 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1379 1380 // Emit the RHS condition into TmpBB. 1381 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1382 } else { 1383 assert(Opc == Instruction::And && "Unknown merge op!"); 1384 // Codegen X & Y as: 1385 // jmp_if_X TmpBB 1386 // jmp FBB 1387 // TmpBB: 1388 // jmp_if_Y TBB 1389 // jmp FBB 1390 // 1391 // This requires creation of TmpBB after CurBB. 1392 1393 // Emit the LHS condition. 1394 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1395 1396 // Emit the RHS condition into TmpBB. 1397 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1398 } 1399} 1400 1401/// If the set of cases should be emitted as a series of branches, return true. 1402/// If we should emit this as a bunch of and/or'd together conditions, return 1403/// false. 1404bool 1405SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1406 if (Cases.size() != 2) return true; 1407 1408 // If this is two comparisons of the same values or'd or and'd together, they 1409 // will get folded into a single comparison, so don't emit two blocks. 1410 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1411 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1412 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1413 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1414 return false; 1415 } 1416 1417 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1418 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1419 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1420 Cases[0].CC == Cases[1].CC && 1421 isa<Constant>(Cases[0].CmpRHS) && 1422 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1423 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1424 return false; 1425 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1426 return false; 1427 } 1428 1429 return true; 1430} 1431 1432void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1433 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1434 1435 // Update machine-CFG edges. 1436 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1437 1438 // Figure out which block is immediately after the current one. 1439 MachineBasicBlock *NextBlock = 0; 1440 MachineFunction::iterator BBI = BrMBB; 1441 if (++BBI != FuncInfo.MF->end()) 1442 NextBlock = BBI; 1443 1444 if (I.isUnconditional()) { 1445 // Update machine-CFG edges. 1446 BrMBB->addSuccessor(Succ0MBB); 1447 1448 // If this is not a fall-through branch, emit the branch. 1449 if (Succ0MBB != NextBlock) 1450 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1451 MVT::Other, getControlRoot(), 1452 DAG.getBasicBlock(Succ0MBB))); 1453 1454 return; 1455 } 1456 1457 // If this condition is one of the special cases we handle, do special stuff 1458 // now. 1459 const Value *CondVal = I.getCondition(); 1460 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1461 1462 // If this is a series of conditions that are or'd or and'd together, emit 1463 // this as a sequence of branches instead of setcc's with and/or operations. 1464 // As long as jumps are not expensive, this should improve performance. 1465 // For example, instead of something like: 1466 // cmp A, B 1467 // C = seteq 1468 // cmp D, E 1469 // F = setle 1470 // or C, F 1471 // jnz foo 1472 // Emit: 1473 // cmp A, B 1474 // je foo 1475 // cmp D, E 1476 // jle foo 1477 // 1478 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1479 if (!TLI.isJumpExpensive() && 1480 BOp->hasOneUse() && 1481 (BOp->getOpcode() == Instruction::And || 1482 BOp->getOpcode() == Instruction::Or)) { 1483 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1484 BOp->getOpcode()); 1485 // If the compares in later blocks need to use values not currently 1486 // exported from this block, export them now. This block should always 1487 // be the first entry. 1488 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1489 1490 // Allow some cases to be rejected. 1491 if (ShouldEmitAsBranches(SwitchCases)) { 1492 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1493 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1494 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1495 } 1496 1497 // Emit the branch for this block. 1498 visitSwitchCase(SwitchCases[0], BrMBB); 1499 SwitchCases.erase(SwitchCases.begin()); 1500 return; 1501 } 1502 1503 // Okay, we decided not to do this, remove any inserted MBB's and clear 1504 // SwitchCases. 1505 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1506 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1507 1508 SwitchCases.clear(); 1509 } 1510 } 1511 1512 // Create a CaseBlock record representing this branch. 1513 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1514 NULL, Succ0MBB, Succ1MBB, BrMBB); 1515 1516 // Use visitSwitchCase to actually insert the fast branch sequence for this 1517 // cond branch. 1518 visitSwitchCase(CB, BrMBB); 1519} 1520 1521/// visitSwitchCase - Emits the necessary code to represent a single node in 1522/// the binary search tree resulting from lowering a switch instruction. 1523void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1524 MachineBasicBlock *SwitchBB) { 1525 SDValue Cond; 1526 SDValue CondLHS = getValue(CB.CmpLHS); 1527 DebugLoc dl = getCurDebugLoc(); 1528 1529 // Build the setcc now. 1530 if (CB.CmpMHS == NULL) { 1531 // Fold "(X == true)" to X and "(X == false)" to !X to 1532 // handle common cases produced by branch lowering. 1533 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1534 CB.CC == ISD::SETEQ) 1535 Cond = CondLHS; 1536 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1537 CB.CC == ISD::SETEQ) { 1538 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1539 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1540 } else 1541 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1542 } else { 1543 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1544 1545 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1546 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1547 1548 SDValue CmpOp = getValue(CB.CmpMHS); 1549 EVT VT = CmpOp.getValueType(); 1550 1551 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1552 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1553 ISD::SETLE); 1554 } else { 1555 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1556 VT, CmpOp, DAG.getConstant(Low, VT)); 1557 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1558 DAG.getConstant(High-Low, VT), ISD::SETULE); 1559 } 1560 } 1561 1562 // Update successor info 1563 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1564 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1565 1566 // Set NextBlock to be the MBB immediately after the current one, if any. 1567 // This is used to avoid emitting unnecessary branches to the next block. 1568 MachineBasicBlock *NextBlock = 0; 1569 MachineFunction::iterator BBI = SwitchBB; 1570 if (++BBI != FuncInfo.MF->end()) 1571 NextBlock = BBI; 1572 1573 // If the lhs block is the next block, invert the condition so that we can 1574 // fall through to the lhs instead of the rhs block. 1575 if (CB.TrueBB == NextBlock) { 1576 std::swap(CB.TrueBB, CB.FalseBB); 1577 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1578 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1579 } 1580 1581 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1582 MVT::Other, getControlRoot(), Cond, 1583 DAG.getBasicBlock(CB.TrueBB)); 1584 1585 // Insert the false branch. Do this even if it's a fall through branch, 1586 // this makes it easier to do DAG optimizations which require inverting 1587 // the branch condition. 1588 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1589 DAG.getBasicBlock(CB.FalseBB)); 1590 1591 DAG.setRoot(BrCond); 1592} 1593 1594/// visitJumpTable - Emit JumpTable node in the current MBB 1595void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1596 // Emit the code for the jump table 1597 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1598 EVT PTy = TLI.getPointerTy(); 1599 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1600 JT.Reg, PTy); 1601 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1602 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1603 MVT::Other, Index.getValue(1), 1604 Table, Index); 1605 DAG.setRoot(BrJumpTable); 1606} 1607 1608/// visitJumpTableHeader - This function emits necessary code to produce index 1609/// in the JumpTable from switch case. 1610void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1611 JumpTableHeader &JTH, 1612 MachineBasicBlock *SwitchBB) { 1613 // Subtract the lowest switch case value from the value being switched on and 1614 // conditional branch to default mbb if the result is greater than the 1615 // difference between smallest and largest cases. 1616 SDValue SwitchOp = getValue(JTH.SValue); 1617 EVT VT = SwitchOp.getValueType(); 1618 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1619 DAG.getConstant(JTH.First, VT)); 1620 1621 // The SDNode we just created, which holds the value being switched on minus 1622 // the smallest case value, needs to be copied to a virtual register so it 1623 // can be used as an index into the jump table in a subsequent basic block. 1624 // This value may be smaller or larger than the target's pointer type, and 1625 // therefore require extension or truncating. 1626 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1627 1628 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1629 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1630 JumpTableReg, SwitchOp); 1631 JT.Reg = JumpTableReg; 1632 1633 // Emit the range check for the jump table, and branch to the default block 1634 // for the switch statement if the value being switched on exceeds the largest 1635 // case in the switch. 1636 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1637 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1638 DAG.getConstant(JTH.Last-JTH.First,VT), 1639 ISD::SETUGT); 1640 1641 // Set NextBlock to be the MBB immediately after the current one, if any. 1642 // This is used to avoid emitting unnecessary branches to the next block. 1643 MachineBasicBlock *NextBlock = 0; 1644 MachineFunction::iterator BBI = SwitchBB; 1645 1646 if (++BBI != FuncInfo.MF->end()) 1647 NextBlock = BBI; 1648 1649 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1650 MVT::Other, CopyTo, CMP, 1651 DAG.getBasicBlock(JT.Default)); 1652 1653 if (JT.MBB != NextBlock) 1654 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1655 DAG.getBasicBlock(JT.MBB)); 1656 1657 DAG.setRoot(BrCond); 1658} 1659 1660/// visitBitTestHeader - This function emits necessary code to produce value 1661/// suitable for "bit tests" 1662void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1663 MachineBasicBlock *SwitchBB) { 1664 // Subtract the minimum value 1665 SDValue SwitchOp = getValue(B.SValue); 1666 EVT VT = SwitchOp.getValueType(); 1667 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1668 DAG.getConstant(B.First, VT)); 1669 1670 // Check range 1671 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1672 TLI.getSetCCResultType(Sub.getValueType()), 1673 Sub, DAG.getConstant(B.Range, VT), 1674 ISD::SETUGT); 1675 1676 // Determine the type of the test operands. 1677 bool UsePtrType = false; 1678 if (!TLI.isTypeLegal(VT)) 1679 UsePtrType = true; 1680 else { 1681 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1682 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) { 1683 // Switch table case range are encoded into series of masks. 1684 // Just use pointer type, it's guaranteed to fit. 1685 UsePtrType = true; 1686 break; 1687 } 1688 } 1689 if (UsePtrType) { 1690 VT = TLI.getPointerTy(); 1691 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1692 } 1693 1694 B.RegVT = VT; 1695 B.Reg = FuncInfo.CreateReg(VT); 1696 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1697 B.Reg, Sub); 1698 1699 // Set NextBlock to be the MBB immediately after the current one, if any. 1700 // This is used to avoid emitting unnecessary branches to the next block. 1701 MachineBasicBlock *NextBlock = 0; 1702 MachineFunction::iterator BBI = SwitchBB; 1703 if (++BBI != FuncInfo.MF->end()) 1704 NextBlock = BBI; 1705 1706 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1707 1708 addSuccessorWithWeight(SwitchBB, B.Default); 1709 addSuccessorWithWeight(SwitchBB, MBB); 1710 1711 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1712 MVT::Other, CopyTo, RangeCmp, 1713 DAG.getBasicBlock(B.Default)); 1714 1715 if (MBB != NextBlock) 1716 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1717 DAG.getBasicBlock(MBB)); 1718 1719 DAG.setRoot(BrRange); 1720} 1721 1722/// visitBitTestCase - this function produces one "bit test" 1723void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1724 MachineBasicBlock* NextMBB, 1725 unsigned Reg, 1726 BitTestCase &B, 1727 MachineBasicBlock *SwitchBB) { 1728 EVT VT = BB.RegVT; 1729 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1730 Reg, VT); 1731 SDValue Cmp; 1732 unsigned PopCount = CountPopulation_64(B.Mask); 1733 if (PopCount == 1) { 1734 // Testing for a single bit; just compare the shift count with what it 1735 // would need to be to shift a 1 bit in that position. 1736 Cmp = DAG.getSetCC(getCurDebugLoc(), 1737 TLI.getSetCCResultType(VT), 1738 ShiftOp, 1739 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1740 ISD::SETEQ); 1741 } else if (PopCount == BB.Range) { 1742 // There is only one zero bit in the range, test for it directly. 1743 Cmp = DAG.getSetCC(getCurDebugLoc(), 1744 TLI.getSetCCResultType(VT), 1745 ShiftOp, 1746 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1747 ISD::SETNE); 1748 } else { 1749 // Make desired shift 1750 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1751 DAG.getConstant(1, VT), ShiftOp); 1752 1753 // Emit bit tests and jumps 1754 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1755 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1756 Cmp = DAG.getSetCC(getCurDebugLoc(), 1757 TLI.getSetCCResultType(VT), 1758 AndOp, DAG.getConstant(0, VT), 1759 ISD::SETNE); 1760 } 1761 1762 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1763 addSuccessorWithWeight(SwitchBB, NextMBB); 1764 1765 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1766 MVT::Other, getControlRoot(), 1767 Cmp, DAG.getBasicBlock(B.TargetBB)); 1768 1769 // Set NextBlock to be the MBB immediately after the current one, if any. 1770 // This is used to avoid emitting unnecessary branches to the next block. 1771 MachineBasicBlock *NextBlock = 0; 1772 MachineFunction::iterator BBI = SwitchBB; 1773 if (++BBI != FuncInfo.MF->end()) 1774 NextBlock = BBI; 1775 1776 if (NextMBB != NextBlock) 1777 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1778 DAG.getBasicBlock(NextMBB)); 1779 1780 DAG.setRoot(BrAnd); 1781} 1782 1783void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1784 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1785 1786 // Retrieve successors. 1787 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1788 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1789 1790 const Value *Callee(I.getCalledValue()); 1791 if (isa<InlineAsm>(Callee)) 1792 visitInlineAsm(&I); 1793 else 1794 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1795 1796 // If the value of the invoke is used outside of its defining block, make it 1797 // available as a virtual register. 1798 CopyToExportRegsIfNeeded(&I); 1799 1800 // Update successor info 1801 InvokeMBB->addSuccessor(Return); 1802 InvokeMBB->addSuccessor(LandingPad); 1803 1804 // Drop into normal successor. 1805 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1806 MVT::Other, getControlRoot(), 1807 DAG.getBasicBlock(Return))); 1808} 1809 1810void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1811} 1812 1813void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1814 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1815} 1816 1817void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1818 // FIXME: Handle this 1819 assert(FuncInfo.MBB->isLandingPad() && 1820 "Call to landingpad not in landing pad!"); 1821 1822 MachineBasicBlock *MBB = FuncInfo.MBB; 1823 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1824 AddLandingPadInfo(LP, MMI, MBB); 1825 1826 SmallVector<EVT, 2> ValueVTs; 1827 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1828 1829 // Insert the EXCEPTIONADDR instruction. 1830 assert(FuncInfo.MBB->isLandingPad() && 1831 "Call to eh.exception not in landing pad!"); 1832 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1833 SDValue Ops[2]; 1834 Ops[0] = DAG.getRoot(); 1835 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1836 SDValue Chain = Op1.getValue(1); 1837 1838 // Insert the EHSELECTION instruction. 1839 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1840 Ops[0] = Op1; 1841 Ops[1] = Chain; 1842 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1843 Chain = Op2.getValue(1); 1844 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1845 1846 Ops[0] = Op1; 1847 Ops[1] = Op2; 1848 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1849 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1850 &Ops[0], 2); 1851 1852 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1853 setValue(&LP, RetPair.first); 1854 DAG.setRoot(RetPair.second); 1855} 1856 1857/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1858/// small case ranges). 1859bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1860 CaseRecVector& WorkList, 1861 const Value* SV, 1862 MachineBasicBlock *Default, 1863 MachineBasicBlock *SwitchBB) { 1864 Case& BackCase = *(CR.Range.second-1); 1865 1866 // Size is the number of Cases represented by this range. 1867 size_t Size = CR.Range.second - CR.Range.first; 1868 if (Size > 3) 1869 return false; 1870 1871 // Get the MachineFunction which holds the current MBB. This is used when 1872 // inserting any additional MBBs necessary to represent the switch. 1873 MachineFunction *CurMF = FuncInfo.MF; 1874 1875 // Figure out which block is immediately after the current one. 1876 MachineBasicBlock *NextBlock = 0; 1877 MachineFunction::iterator BBI = CR.CaseBB; 1878 1879 if (++BBI != FuncInfo.MF->end()) 1880 NextBlock = BBI; 1881 1882 // If any two of the cases has the same destination, and if one value 1883 // is the same as the other, but has one bit unset that the other has set, 1884 // use bit manipulation to do two compares at once. For example: 1885 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1886 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1887 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1888 if (Size == 2 && CR.CaseBB == SwitchBB) { 1889 Case &Small = *CR.Range.first; 1890 Case &Big = *(CR.Range.second-1); 1891 1892 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1893 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1894 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1895 1896 // Check that there is only one bit different. 1897 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1898 (SmallValue | BigValue) == BigValue) { 1899 // Isolate the common bit. 1900 APInt CommonBit = BigValue & ~SmallValue; 1901 assert((SmallValue | CommonBit) == BigValue && 1902 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1903 1904 SDValue CondLHS = getValue(SV); 1905 EVT VT = CondLHS.getValueType(); 1906 DebugLoc DL = getCurDebugLoc(); 1907 1908 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1909 DAG.getConstant(CommonBit, VT)); 1910 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1911 Or, DAG.getConstant(BigValue, VT), 1912 ISD::SETEQ); 1913 1914 // Update successor info. 1915 addSuccessorWithWeight(SwitchBB, Small.BB); 1916 addSuccessorWithWeight(SwitchBB, Default); 1917 1918 // Insert the true branch. 1919 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1920 getControlRoot(), Cond, 1921 DAG.getBasicBlock(Small.BB)); 1922 1923 // Insert the false branch. 1924 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1925 DAG.getBasicBlock(Default)); 1926 1927 DAG.setRoot(BrCond); 1928 return true; 1929 } 1930 } 1931 } 1932 1933 // Rearrange the case blocks so that the last one falls through if possible. 1934 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1935 // The last case block won't fall through into 'NextBlock' if we emit the 1936 // branches in this order. See if rearranging a case value would help. 1937 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1938 if (I->BB == NextBlock) { 1939 std::swap(*I, BackCase); 1940 break; 1941 } 1942 } 1943 } 1944 1945 // Create a CaseBlock record representing a conditional branch to 1946 // the Case's target mbb if the value being switched on SV is equal 1947 // to C. 1948 MachineBasicBlock *CurBlock = CR.CaseBB; 1949 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1950 MachineBasicBlock *FallThrough; 1951 if (I != E-1) { 1952 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1953 CurMF->insert(BBI, FallThrough); 1954 1955 // Put SV in a virtual register to make it available from the new blocks. 1956 ExportFromCurrentBlock(SV); 1957 } else { 1958 // If the last case doesn't match, go to the default block. 1959 FallThrough = Default; 1960 } 1961 1962 const Value *RHS, *LHS, *MHS; 1963 ISD::CondCode CC; 1964 if (I->High == I->Low) { 1965 // This is just small small case range :) containing exactly 1 case 1966 CC = ISD::SETEQ; 1967 LHS = SV; RHS = I->High; MHS = NULL; 1968 } else { 1969 CC = ISD::SETLE; 1970 LHS = I->Low; MHS = SV; RHS = I->High; 1971 } 1972 1973 uint32_t ExtraWeight = I->ExtraWeight; 1974 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 1975 /* me */ CurBlock, 1976 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 1977 1978 // If emitting the first comparison, just call visitSwitchCase to emit the 1979 // code into the current block. Otherwise, push the CaseBlock onto the 1980 // vector to be later processed by SDISel, and insert the node's MBB 1981 // before the next MBB. 1982 if (CurBlock == SwitchBB) 1983 visitSwitchCase(CB, SwitchBB); 1984 else 1985 SwitchCases.push_back(CB); 1986 1987 CurBlock = FallThrough; 1988 } 1989 1990 return true; 1991} 1992 1993static inline bool areJTsAllowed(const TargetLowering &TLI) { 1994 return !DisableJumpTables && 1995 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1996 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1997} 1998 1999static APInt ComputeRange(const APInt &First, const APInt &Last) { 2000 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2001 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 2002 return (LastExt - FirstExt + 1ULL); 2003} 2004 2005/// handleJTSwitchCase - Emit jumptable for current switch case range 2006bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 2007 CaseRecVector& WorkList, 2008 const Value* SV, 2009 MachineBasicBlock* Default, 2010 MachineBasicBlock *SwitchBB) { 2011 Case& FrontCase = *CR.Range.first; 2012 Case& BackCase = *(CR.Range.second-1); 2013 2014 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2015 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2016 2017 APInt TSize(First.getBitWidth(), 0); 2018 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2019 I!=E; ++I) 2020 TSize += I->size(); 2021 2022 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2023 return false; 2024 2025 APInt Range = ComputeRange(First, Last); 2026 double Density = TSize.roundToDouble() / Range.roundToDouble(); 2027 if (Density < 0.4) 2028 return false; 2029 2030 DEBUG(dbgs() << "Lowering jump table\n" 2031 << "First entry: " << First << ". Last entry: " << Last << '\n' 2032 << "Range: " << Range 2033 << ". Size: " << TSize << ". Density: " << Density << "\n\n"); 2034 2035 // Get the MachineFunction which holds the current MBB. This is used when 2036 // inserting any additional MBBs necessary to represent the switch. 2037 MachineFunction *CurMF = FuncInfo.MF; 2038 2039 // Figure out which block is immediately after the current one. 2040 MachineFunction::iterator BBI = CR.CaseBB; 2041 ++BBI; 2042 2043 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2044 2045 // Create a new basic block to hold the code for loading the address 2046 // of the jump table, and jumping to it. Update successor information; 2047 // we will either branch to the default case for the switch, or the jump 2048 // table. 2049 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2050 CurMF->insert(BBI, JumpTableBB); 2051 2052 addSuccessorWithWeight(CR.CaseBB, Default); 2053 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2054 2055 // Build a vector of destination BBs, corresponding to each target 2056 // of the jump table. If the value of the jump table slot corresponds to 2057 // a case statement, push the case's BB onto the vector, otherwise, push 2058 // the default BB. 2059 std::vector<MachineBasicBlock*> DestBBs; 2060 APInt TEI = First; 2061 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2062 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2063 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2064 2065 if (Low.sle(TEI) && TEI.sle(High)) { 2066 DestBBs.push_back(I->BB); 2067 if (TEI==High) 2068 ++I; 2069 } else { 2070 DestBBs.push_back(Default); 2071 } 2072 } 2073 2074 // Update successor info. Add one edge to each unique successor. 2075 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2076 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2077 E = DestBBs.end(); I != E; ++I) { 2078 if (!SuccsHandled[(*I)->getNumber()]) { 2079 SuccsHandled[(*I)->getNumber()] = true; 2080 addSuccessorWithWeight(JumpTableBB, *I); 2081 } 2082 } 2083 2084 // Create a jump table index for this jump table. 2085 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2086 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2087 ->createJumpTableIndex(DestBBs); 2088 2089 // Set the jump table information so that we can codegen it as a second 2090 // MachineBasicBlock 2091 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2092 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2093 if (CR.CaseBB == SwitchBB) 2094 visitJumpTableHeader(JT, JTH, SwitchBB); 2095 2096 JTCases.push_back(JumpTableBlock(JTH, JT)); 2097 2098 return true; 2099} 2100 2101/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2102/// 2 subtrees. 2103bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2104 CaseRecVector& WorkList, 2105 const Value* SV, 2106 MachineBasicBlock *Default, 2107 MachineBasicBlock *SwitchBB) { 2108 // Get the MachineFunction which holds the current MBB. This is used when 2109 // inserting any additional MBBs necessary to represent the switch. 2110 MachineFunction *CurMF = FuncInfo.MF; 2111 2112 // Figure out which block is immediately after the current one. 2113 MachineFunction::iterator BBI = CR.CaseBB; 2114 ++BBI; 2115 2116 Case& FrontCase = *CR.Range.first; 2117 Case& BackCase = *(CR.Range.second-1); 2118 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2119 2120 // Size is the number of Cases represented by this range. 2121 unsigned Size = CR.Range.second - CR.Range.first; 2122 2123 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2124 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2125 double FMetric = 0; 2126 CaseItr Pivot = CR.Range.first + Size/2; 2127 2128 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2129 // (heuristically) allow us to emit JumpTable's later. 2130 APInt TSize(First.getBitWidth(), 0); 2131 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2132 I!=E; ++I) 2133 TSize += I->size(); 2134 2135 APInt LSize = FrontCase.size(); 2136 APInt RSize = TSize-LSize; 2137 DEBUG(dbgs() << "Selecting best pivot: \n" 2138 << "First: " << First << ", Last: " << Last <<'\n' 2139 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2140 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2141 J!=E; ++I, ++J) { 2142 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2143 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2144 APInt Range = ComputeRange(LEnd, RBegin); 2145 assert((Range - 2ULL).isNonNegative() && 2146 "Invalid case distance"); 2147 // Use volatile double here to avoid excess precision issues on some hosts, 2148 // e.g. that use 80-bit X87 registers. 2149 volatile double LDensity = 2150 (double)LSize.roundToDouble() / 2151 (LEnd - First + 1ULL).roundToDouble(); 2152 volatile double RDensity = 2153 (double)RSize.roundToDouble() / 2154 (Last - RBegin + 1ULL).roundToDouble(); 2155 double Metric = Range.logBase2()*(LDensity+RDensity); 2156 // Should always split in some non-trivial place 2157 DEBUG(dbgs() <<"=>Step\n" 2158 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2159 << "LDensity: " << LDensity 2160 << ", RDensity: " << RDensity << '\n' 2161 << "Metric: " << Metric << '\n'); 2162 if (FMetric < Metric) { 2163 Pivot = J; 2164 FMetric = Metric; 2165 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2166 } 2167 2168 LSize += J->size(); 2169 RSize -= J->size(); 2170 } 2171 if (areJTsAllowed(TLI)) { 2172 // If our case is dense we *really* should handle it earlier! 2173 assert((FMetric > 0) && "Should handle dense range earlier!"); 2174 } else { 2175 Pivot = CR.Range.first + Size/2; 2176 } 2177 2178 CaseRange LHSR(CR.Range.first, Pivot); 2179 CaseRange RHSR(Pivot, CR.Range.second); 2180 Constant *C = Pivot->Low; 2181 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2182 2183 // We know that we branch to the LHS if the Value being switched on is 2184 // less than the Pivot value, C. We use this to optimize our binary 2185 // tree a bit, by recognizing that if SV is greater than or equal to the 2186 // LHS's Case Value, and that Case Value is exactly one less than the 2187 // Pivot's Value, then we can branch directly to the LHS's Target, 2188 // rather than creating a leaf node for it. 2189 if ((LHSR.second - LHSR.first) == 1 && 2190 LHSR.first->High == CR.GE && 2191 cast<ConstantInt>(C)->getValue() == 2192 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2193 TrueBB = LHSR.first->BB; 2194 } else { 2195 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2196 CurMF->insert(BBI, TrueBB); 2197 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2198 2199 // Put SV in a virtual register to make it available from the new blocks. 2200 ExportFromCurrentBlock(SV); 2201 } 2202 2203 // Similar to the optimization above, if the Value being switched on is 2204 // known to be less than the Constant CR.LT, and the current Case Value 2205 // is CR.LT - 1, then we can branch directly to the target block for 2206 // the current Case Value, rather than emitting a RHS leaf node for it. 2207 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2208 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2209 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2210 FalseBB = RHSR.first->BB; 2211 } else { 2212 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2213 CurMF->insert(BBI, FalseBB); 2214 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2215 2216 // Put SV in a virtual register to make it available from the new blocks. 2217 ExportFromCurrentBlock(SV); 2218 } 2219 2220 // Create a CaseBlock record representing a conditional branch to 2221 // the LHS node if the value being switched on SV is less than C. 2222 // Otherwise, branch to LHS. 2223 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2224 2225 if (CR.CaseBB == SwitchBB) 2226 visitSwitchCase(CB, SwitchBB); 2227 else 2228 SwitchCases.push_back(CB); 2229 2230 return true; 2231} 2232 2233/// handleBitTestsSwitchCase - if current case range has few destination and 2234/// range span less, than machine word bitwidth, encode case range into series 2235/// of masks and emit bit tests with these masks. 2236bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2237 CaseRecVector& WorkList, 2238 const Value* SV, 2239 MachineBasicBlock* Default, 2240 MachineBasicBlock *SwitchBB){ 2241 EVT PTy = TLI.getPointerTy(); 2242 unsigned IntPtrBits = PTy.getSizeInBits(); 2243 2244 Case& FrontCase = *CR.Range.first; 2245 Case& BackCase = *(CR.Range.second-1); 2246 2247 // Get the MachineFunction which holds the current MBB. This is used when 2248 // inserting any additional MBBs necessary to represent the switch. 2249 MachineFunction *CurMF = FuncInfo.MF; 2250 2251 // If target does not have legal shift left, do not emit bit tests at all. 2252 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2253 return false; 2254 2255 size_t numCmps = 0; 2256 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2257 I!=E; ++I) { 2258 // Single case counts one, case range - two. 2259 numCmps += (I->Low == I->High ? 1 : 2); 2260 } 2261 2262 // Count unique destinations 2263 SmallSet<MachineBasicBlock*, 4> Dests; 2264 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2265 Dests.insert(I->BB); 2266 if (Dests.size() > 3) 2267 // Don't bother the code below, if there are too much unique destinations 2268 return false; 2269 } 2270 DEBUG(dbgs() << "Total number of unique destinations: " 2271 << Dests.size() << '\n' 2272 << "Total number of comparisons: " << numCmps << '\n'); 2273 2274 // Compute span of values. 2275 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2276 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2277 APInt cmpRange = maxValue - minValue; 2278 2279 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2280 << "Low bound: " << minValue << '\n' 2281 << "High bound: " << maxValue << '\n'); 2282 2283 if (cmpRange.uge(IntPtrBits) || 2284 (!(Dests.size() == 1 && numCmps >= 3) && 2285 !(Dests.size() == 2 && numCmps >= 5) && 2286 !(Dests.size() >= 3 && numCmps >= 6))) 2287 return false; 2288 2289 DEBUG(dbgs() << "Emitting bit tests\n"); 2290 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2291 2292 // Optimize the case where all the case values fit in a 2293 // word without having to subtract minValue. In this case, 2294 // we can optimize away the subtraction. 2295 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2296 cmpRange = maxValue; 2297 } else { 2298 lowBound = minValue; 2299 } 2300 2301 CaseBitsVector CasesBits; 2302 unsigned i, count = 0; 2303 2304 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2305 MachineBasicBlock* Dest = I->BB; 2306 for (i = 0; i < count; ++i) 2307 if (Dest == CasesBits[i].BB) 2308 break; 2309 2310 if (i == count) { 2311 assert((count < 3) && "Too much destinations to test!"); 2312 CasesBits.push_back(CaseBits(0, Dest, 0)); 2313 count++; 2314 } 2315 2316 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2317 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2318 2319 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2320 uint64_t hi = (highValue - lowBound).getZExtValue(); 2321 2322 for (uint64_t j = lo; j <= hi; j++) { 2323 CasesBits[i].Mask |= 1ULL << j; 2324 CasesBits[i].Bits++; 2325 } 2326 2327 } 2328 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2329 2330 BitTestInfo BTC; 2331 2332 // Figure out which block is immediately after the current one. 2333 MachineFunction::iterator BBI = CR.CaseBB; 2334 ++BBI; 2335 2336 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2337 2338 DEBUG(dbgs() << "Cases:\n"); 2339 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2340 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2341 << ", Bits: " << CasesBits[i].Bits 2342 << ", BB: " << CasesBits[i].BB << '\n'); 2343 2344 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2345 CurMF->insert(BBI, CaseBB); 2346 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2347 CaseBB, 2348 CasesBits[i].BB)); 2349 2350 // Put SV in a virtual register to make it available from the new blocks. 2351 ExportFromCurrentBlock(SV); 2352 } 2353 2354 BitTestBlock BTB(lowBound, cmpRange, SV, 2355 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2356 CR.CaseBB, Default, BTC); 2357 2358 if (CR.CaseBB == SwitchBB) 2359 visitBitTestHeader(BTB, SwitchBB); 2360 2361 BitTestCases.push_back(BTB); 2362 2363 return true; 2364} 2365 2366/// Clusterify - Transform simple list of Cases into list of CaseRange's 2367size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2368 const SwitchInst& SI) { 2369 size_t numCmps = 0; 2370 2371 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2372 // Start with "simple" cases 2373 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2374 BasicBlock *SuccBB = SI.getSuccessor(i); 2375 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2376 2377 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0; 2378 2379 Cases.push_back(Case(SI.getSuccessorValue(i), 2380 SI.getSuccessorValue(i), 2381 SMBB, ExtraWeight)); 2382 } 2383 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2384 2385 // Merge case into clusters 2386 if (Cases.size() >= 2) 2387 // Must recompute end() each iteration because it may be 2388 // invalidated by erase if we hold on to it 2389 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2390 J != Cases.end(); ) { 2391 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2392 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2393 MachineBasicBlock* nextBB = J->BB; 2394 MachineBasicBlock* currentBB = I->BB; 2395 2396 // If the two neighboring cases go to the same destination, merge them 2397 // into a single case. 2398 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2399 I->High = J->High; 2400 J = Cases.erase(J); 2401 2402 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) { 2403 uint32_t CurWeight = currentBB->getBasicBlock() ? 2404 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16; 2405 uint32_t NextWeight = nextBB->getBasicBlock() ? 2406 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16; 2407 2408 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(), 2409 CurWeight + NextWeight); 2410 } 2411 } else { 2412 I = J++; 2413 } 2414 } 2415 2416 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2417 if (I->Low != I->High) 2418 // A range counts double, since it requires two compares. 2419 ++numCmps; 2420 } 2421 2422 return numCmps; 2423} 2424 2425void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2426 MachineBasicBlock *Last) { 2427 // Update JTCases. 2428 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2429 if (JTCases[i].first.HeaderBB == First) 2430 JTCases[i].first.HeaderBB = Last; 2431 2432 // Update BitTestCases. 2433 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2434 if (BitTestCases[i].Parent == First) 2435 BitTestCases[i].Parent = Last; 2436} 2437 2438void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2439 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2440 2441 // Figure out which block is immediately after the current one. 2442 MachineBasicBlock *NextBlock = 0; 2443 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2444 2445 // If there is only the default destination, branch to it if it is not the 2446 // next basic block. Otherwise, just fall through. 2447 if (SI.getNumOperands() == 2) { 2448 // Update machine-CFG edges. 2449 2450 // If this is not a fall-through branch, emit the branch. 2451 SwitchMBB->addSuccessor(Default); 2452 if (Default != NextBlock) 2453 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2454 MVT::Other, getControlRoot(), 2455 DAG.getBasicBlock(Default))); 2456 2457 return; 2458 } 2459 2460 // If there are any non-default case statements, create a vector of Cases 2461 // representing each one, and sort the vector so that we can efficiently 2462 // create a binary search tree from them. 2463 CaseVector Cases; 2464 size_t numCmps = Clusterify(Cases, SI); 2465 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2466 << ". Total compares: " << numCmps << '\n'); 2467 numCmps = 0; 2468 2469 // Get the Value to be switched on and default basic blocks, which will be 2470 // inserted into CaseBlock records, representing basic blocks in the binary 2471 // search tree. 2472 const Value *SV = SI.getOperand(0); 2473 2474 // Push the initial CaseRec onto the worklist 2475 CaseRecVector WorkList; 2476 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2477 CaseRange(Cases.begin(),Cases.end()))); 2478 2479 while (!WorkList.empty()) { 2480 // Grab a record representing a case range to process off the worklist 2481 CaseRec CR = WorkList.back(); 2482 WorkList.pop_back(); 2483 2484 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2485 continue; 2486 2487 // If the range has few cases (two or less) emit a series of specific 2488 // tests. 2489 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2490 continue; 2491 2492 // If the switch has more than 5 blocks, and at least 40% dense, and the 2493 // target supports indirect branches, then emit a jump table rather than 2494 // lowering the switch to a binary tree of conditional branches. 2495 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2496 continue; 2497 2498 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2499 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2500 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2501 } 2502} 2503 2504void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2505 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2506 2507 // Update machine-CFG edges with unique successors. 2508 SmallVector<BasicBlock*, 32> succs; 2509 succs.reserve(I.getNumSuccessors()); 2510 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2511 succs.push_back(I.getSuccessor(i)); 2512 array_pod_sort(succs.begin(), succs.end()); 2513 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2514 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2515 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2516 addSuccessorWithWeight(IndirectBrMBB, Succ); 2517 } 2518 2519 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2520 MVT::Other, getControlRoot(), 2521 getValue(I.getAddress()))); 2522} 2523 2524void SelectionDAGBuilder::visitFSub(const User &I) { 2525 // -0.0 - X --> fneg 2526 Type *Ty = I.getType(); 2527 if (isa<Constant>(I.getOperand(0)) && 2528 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2529 SDValue Op2 = getValue(I.getOperand(1)); 2530 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2531 Op2.getValueType(), Op2)); 2532 return; 2533 } 2534 2535 visitBinary(I, ISD::FSUB); 2536} 2537 2538void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2539 SDValue Op1 = getValue(I.getOperand(0)); 2540 SDValue Op2 = getValue(I.getOperand(1)); 2541 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2542 Op1.getValueType(), Op1, Op2)); 2543} 2544 2545void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2546 SDValue Op1 = getValue(I.getOperand(0)); 2547 SDValue Op2 = getValue(I.getOperand(1)); 2548 2549 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2550 2551 // Coerce the shift amount to the right type if we can. 2552 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2553 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2554 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2555 DebugLoc DL = getCurDebugLoc(); 2556 2557 // If the operand is smaller than the shift count type, promote it. 2558 if (ShiftSize > Op2Size) 2559 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2560 2561 // If the operand is larger than the shift count type but the shift 2562 // count type has enough bits to represent any shift value, truncate 2563 // it now. This is a common case and it exposes the truncate to 2564 // optimization early. 2565 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2566 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2567 // Otherwise we'll need to temporarily settle for some other convenient 2568 // type. Type legalization will make adjustments once the shiftee is split. 2569 else 2570 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2571 } 2572 2573 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2574 Op1.getValueType(), Op1, Op2)); 2575} 2576 2577void SelectionDAGBuilder::visitSDiv(const User &I) { 2578 SDValue Op1 = getValue(I.getOperand(0)); 2579 SDValue Op2 = getValue(I.getOperand(1)); 2580 2581 // Turn exact SDivs into multiplications. 2582 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2583 // exact bit. 2584 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2585 !isa<ConstantSDNode>(Op1) && 2586 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2587 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2588 else 2589 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2590 Op1, Op2)); 2591} 2592 2593void SelectionDAGBuilder::visitICmp(const User &I) { 2594 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2595 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2596 predicate = IC->getPredicate(); 2597 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2598 predicate = ICmpInst::Predicate(IC->getPredicate()); 2599 SDValue Op1 = getValue(I.getOperand(0)); 2600 SDValue Op2 = getValue(I.getOperand(1)); 2601 ISD::CondCode Opcode = getICmpCondCode(predicate); 2602 2603 EVT DestVT = TLI.getValueType(I.getType()); 2604 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2605} 2606 2607void SelectionDAGBuilder::visitFCmp(const User &I) { 2608 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2609 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2610 predicate = FC->getPredicate(); 2611 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2612 predicate = FCmpInst::Predicate(FC->getPredicate()); 2613 SDValue Op1 = getValue(I.getOperand(0)); 2614 SDValue Op2 = getValue(I.getOperand(1)); 2615 ISD::CondCode Condition = getFCmpCondCode(predicate); 2616 EVT DestVT = TLI.getValueType(I.getType()); 2617 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2618} 2619 2620void SelectionDAGBuilder::visitSelect(const User &I) { 2621 SmallVector<EVT, 4> ValueVTs; 2622 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2623 unsigned NumValues = ValueVTs.size(); 2624 if (NumValues == 0) return; 2625 2626 SmallVector<SDValue, 4> Values(NumValues); 2627 SDValue Cond = getValue(I.getOperand(0)); 2628 SDValue TrueVal = getValue(I.getOperand(1)); 2629 SDValue FalseVal = getValue(I.getOperand(2)); 2630 2631 for (unsigned i = 0; i != NumValues; ++i) 2632 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2633 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2634 Cond, 2635 SDValue(TrueVal.getNode(), 2636 TrueVal.getResNo() + i), 2637 SDValue(FalseVal.getNode(), 2638 FalseVal.getResNo() + i)); 2639 2640 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2641 DAG.getVTList(&ValueVTs[0], NumValues), 2642 &Values[0], NumValues)); 2643} 2644 2645void SelectionDAGBuilder::visitTrunc(const User &I) { 2646 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2647 SDValue N = getValue(I.getOperand(0)); 2648 EVT DestVT = TLI.getValueType(I.getType()); 2649 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2650} 2651 2652void SelectionDAGBuilder::visitZExt(const User &I) { 2653 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2654 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2655 SDValue N = getValue(I.getOperand(0)); 2656 EVT DestVT = TLI.getValueType(I.getType()); 2657 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2658} 2659 2660void SelectionDAGBuilder::visitSExt(const User &I) { 2661 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2662 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2663 SDValue N = getValue(I.getOperand(0)); 2664 EVT DestVT = TLI.getValueType(I.getType()); 2665 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2666} 2667 2668void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2669 // FPTrunc is never a no-op cast, no need to check 2670 SDValue N = getValue(I.getOperand(0)); 2671 EVT DestVT = TLI.getValueType(I.getType()); 2672 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2673 DestVT, N, DAG.getIntPtrConstant(0))); 2674} 2675 2676void SelectionDAGBuilder::visitFPExt(const User &I){ 2677 // FPTrunc is never a no-op cast, no need to check 2678 SDValue N = getValue(I.getOperand(0)); 2679 EVT DestVT = TLI.getValueType(I.getType()); 2680 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2681} 2682 2683void SelectionDAGBuilder::visitFPToUI(const User &I) { 2684 // FPToUI is never a no-op cast, no need to check 2685 SDValue N = getValue(I.getOperand(0)); 2686 EVT DestVT = TLI.getValueType(I.getType()); 2687 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2688} 2689 2690void SelectionDAGBuilder::visitFPToSI(const User &I) { 2691 // FPToSI is never a no-op cast, no need to check 2692 SDValue N = getValue(I.getOperand(0)); 2693 EVT DestVT = TLI.getValueType(I.getType()); 2694 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2695} 2696 2697void SelectionDAGBuilder::visitUIToFP(const User &I) { 2698 // UIToFP is never a no-op cast, no need to check 2699 SDValue N = getValue(I.getOperand(0)); 2700 EVT DestVT = TLI.getValueType(I.getType()); 2701 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2702} 2703 2704void SelectionDAGBuilder::visitSIToFP(const User &I){ 2705 // SIToFP is never a no-op cast, no need to check 2706 SDValue N = getValue(I.getOperand(0)); 2707 EVT DestVT = TLI.getValueType(I.getType()); 2708 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2709} 2710 2711void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2712 // What to do depends on the size of the integer and the size of the pointer. 2713 // We can either truncate, zero extend, or no-op, accordingly. 2714 SDValue N = getValue(I.getOperand(0)); 2715 EVT DestVT = TLI.getValueType(I.getType()); 2716 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2717} 2718 2719void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2720 // What to do depends on the size of the integer and the size of the pointer. 2721 // We can either truncate, zero extend, or no-op, accordingly. 2722 SDValue N = getValue(I.getOperand(0)); 2723 EVT DestVT = TLI.getValueType(I.getType()); 2724 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2725} 2726 2727void SelectionDAGBuilder::visitBitCast(const User &I) { 2728 SDValue N = getValue(I.getOperand(0)); 2729 EVT DestVT = TLI.getValueType(I.getType()); 2730 2731 // BitCast assures us that source and destination are the same size so this is 2732 // either a BITCAST or a no-op. 2733 if (DestVT != N.getValueType()) 2734 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2735 DestVT, N)); // convert types. 2736 else 2737 setValue(&I, N); // noop cast. 2738} 2739 2740void SelectionDAGBuilder::visitInsertElement(const User &I) { 2741 SDValue InVec = getValue(I.getOperand(0)); 2742 SDValue InVal = getValue(I.getOperand(1)); 2743 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2744 TLI.getPointerTy(), 2745 getValue(I.getOperand(2))); 2746 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2747 TLI.getValueType(I.getType()), 2748 InVec, InVal, InIdx)); 2749} 2750 2751void SelectionDAGBuilder::visitExtractElement(const User &I) { 2752 SDValue InVec = getValue(I.getOperand(0)); 2753 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2754 TLI.getPointerTy(), 2755 getValue(I.getOperand(1))); 2756 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2757 TLI.getValueType(I.getType()), InVec, InIdx)); 2758} 2759 2760// Utility for visitShuffleVector - Returns true if the mask is mask starting 2761// from SIndx and increasing to the element length (undefs are allowed). 2762static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2763 unsigned MaskNumElts = Mask.size(); 2764 for (unsigned i = 0; i != MaskNumElts; ++i) 2765 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2766 return false; 2767 return true; 2768} 2769 2770void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2771 SmallVector<int, 8> Mask; 2772 SDValue Src1 = getValue(I.getOperand(0)); 2773 SDValue Src2 = getValue(I.getOperand(1)); 2774 2775 // Convert the ConstantVector mask operand into an array of ints, with -1 2776 // representing undef values. 2777 SmallVector<Constant*, 8> MaskElts; 2778 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2779 unsigned MaskNumElts = MaskElts.size(); 2780 for (unsigned i = 0; i != MaskNumElts; ++i) { 2781 if (isa<UndefValue>(MaskElts[i])) 2782 Mask.push_back(-1); 2783 else 2784 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2785 } 2786 2787 EVT VT = TLI.getValueType(I.getType()); 2788 EVT SrcVT = Src1.getValueType(); 2789 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2790 2791 if (SrcNumElts == MaskNumElts) { 2792 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2793 &Mask[0])); 2794 return; 2795 } 2796 2797 // Normalize the shuffle vector since mask and vector length don't match. 2798 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2799 // Mask is longer than the source vectors and is a multiple of the source 2800 // vectors. We can use concatenate vector to make the mask and vectors 2801 // lengths match. 2802 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2803 // The shuffle is concatenating two vectors together. 2804 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2805 VT, Src1, Src2)); 2806 return; 2807 } 2808 2809 // Pad both vectors with undefs to make them the same length as the mask. 2810 unsigned NumConcat = MaskNumElts / SrcNumElts; 2811 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2812 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2813 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2814 2815 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2816 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2817 MOps1[0] = Src1; 2818 MOps2[0] = Src2; 2819 2820 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2821 getCurDebugLoc(), VT, 2822 &MOps1[0], NumConcat); 2823 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2824 getCurDebugLoc(), VT, 2825 &MOps2[0], NumConcat); 2826 2827 // Readjust mask for new input vector length. 2828 SmallVector<int, 8> MappedOps; 2829 for (unsigned i = 0; i != MaskNumElts; ++i) { 2830 int Idx = Mask[i]; 2831 if (Idx < (int)SrcNumElts) 2832 MappedOps.push_back(Idx); 2833 else 2834 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2835 } 2836 2837 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2838 &MappedOps[0])); 2839 return; 2840 } 2841 2842 if (SrcNumElts > MaskNumElts) { 2843 // Analyze the access pattern of the vector to see if we can extract 2844 // two subvectors and do the shuffle. The analysis is done by calculating 2845 // the range of elements the mask access on both vectors. 2846 int MinRange[2] = { static_cast<int>(SrcNumElts+1), 2847 static_cast<int>(SrcNumElts+1)}; 2848 int MaxRange[2] = {-1, -1}; 2849 2850 for (unsigned i = 0; i != MaskNumElts; ++i) { 2851 int Idx = Mask[i]; 2852 int Input = 0; 2853 if (Idx < 0) 2854 continue; 2855 2856 if (Idx >= (int)SrcNumElts) { 2857 Input = 1; 2858 Idx -= SrcNumElts; 2859 } 2860 if (Idx > MaxRange[Input]) 2861 MaxRange[Input] = Idx; 2862 if (Idx < MinRange[Input]) 2863 MinRange[Input] = Idx; 2864 } 2865 2866 // Check if the access is smaller than the vector size and can we find 2867 // a reasonable extract index. 2868 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2869 // Extract. 2870 int StartIdx[2]; // StartIdx to extract from 2871 for (int Input=0; Input < 2; ++Input) { 2872 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2873 RangeUse[Input] = 0; // Unused 2874 StartIdx[Input] = 0; 2875 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2876 // Fits within range but we should see if we can find a good 2877 // start index that is a multiple of the mask length. 2878 if (MaxRange[Input] < (int)MaskNumElts) { 2879 RangeUse[Input] = 1; // Extract from beginning of the vector 2880 StartIdx[Input] = 0; 2881 } else { 2882 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2883 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2884 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2885 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2886 } 2887 } 2888 } 2889 2890 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2891 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2892 return; 2893 } 2894 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2895 // Extract appropriate subvector and generate a vector shuffle 2896 for (int Input=0; Input < 2; ++Input) { 2897 SDValue &Src = Input == 0 ? Src1 : Src2; 2898 if (RangeUse[Input] == 0) 2899 Src = DAG.getUNDEF(VT); 2900 else 2901 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2902 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2903 } 2904 2905 // Calculate new mask. 2906 SmallVector<int, 8> MappedOps; 2907 for (unsigned i = 0; i != MaskNumElts; ++i) { 2908 int Idx = Mask[i]; 2909 if (Idx < 0) 2910 MappedOps.push_back(Idx); 2911 else if (Idx < (int)SrcNumElts) 2912 MappedOps.push_back(Idx - StartIdx[0]); 2913 else 2914 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2915 } 2916 2917 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2918 &MappedOps[0])); 2919 return; 2920 } 2921 } 2922 2923 // We can't use either concat vectors or extract subvectors so fall back to 2924 // replacing the shuffle with extract and build vector. 2925 // to insert and build vector. 2926 EVT EltVT = VT.getVectorElementType(); 2927 EVT PtrVT = TLI.getPointerTy(); 2928 SmallVector<SDValue,8> Ops; 2929 for (unsigned i = 0; i != MaskNumElts; ++i) { 2930 if (Mask[i] < 0) { 2931 Ops.push_back(DAG.getUNDEF(EltVT)); 2932 } else { 2933 int Idx = Mask[i]; 2934 SDValue Res; 2935 2936 if (Idx < (int)SrcNumElts) 2937 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2938 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2939 else 2940 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2941 EltVT, Src2, 2942 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2943 2944 Ops.push_back(Res); 2945 } 2946 } 2947 2948 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2949 VT, &Ops[0], Ops.size())); 2950} 2951 2952void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2953 const Value *Op0 = I.getOperand(0); 2954 const Value *Op1 = I.getOperand(1); 2955 Type *AggTy = I.getType(); 2956 Type *ValTy = Op1->getType(); 2957 bool IntoUndef = isa<UndefValue>(Op0); 2958 bool FromUndef = isa<UndefValue>(Op1); 2959 2960 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2961 2962 SmallVector<EVT, 4> AggValueVTs; 2963 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2964 SmallVector<EVT, 4> ValValueVTs; 2965 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2966 2967 unsigned NumAggValues = AggValueVTs.size(); 2968 unsigned NumValValues = ValValueVTs.size(); 2969 SmallVector<SDValue, 4> Values(NumAggValues); 2970 2971 SDValue Agg = getValue(Op0); 2972 unsigned i = 0; 2973 // Copy the beginning value(s) from the original aggregate. 2974 for (; i != LinearIndex; ++i) 2975 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2976 SDValue(Agg.getNode(), Agg.getResNo() + i); 2977 // Copy values from the inserted value(s). 2978 if (NumValValues) { 2979 SDValue Val = getValue(Op1); 2980 for (; i != LinearIndex + NumValValues; ++i) 2981 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2982 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2983 } 2984 // Copy remaining value(s) from the original aggregate. 2985 for (; i != NumAggValues; ++i) 2986 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2987 SDValue(Agg.getNode(), Agg.getResNo() + i); 2988 2989 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2990 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2991 &Values[0], NumAggValues)); 2992} 2993 2994void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2995 const Value *Op0 = I.getOperand(0); 2996 Type *AggTy = Op0->getType(); 2997 Type *ValTy = I.getType(); 2998 bool OutOfUndef = isa<UndefValue>(Op0); 2999 3000 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3001 3002 SmallVector<EVT, 4> ValValueVTs; 3003 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3004 3005 unsigned NumValValues = ValValueVTs.size(); 3006 3007 // Ignore a extractvalue that produces an empty object 3008 if (!NumValValues) { 3009 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3010 return; 3011 } 3012 3013 SmallVector<SDValue, 4> Values(NumValValues); 3014 3015 SDValue Agg = getValue(Op0); 3016 // Copy out the selected value(s). 3017 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3018 Values[i - LinearIndex] = 3019 OutOfUndef ? 3020 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3021 SDValue(Agg.getNode(), Agg.getResNo() + i); 3022 3023 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3024 DAG.getVTList(&ValValueVTs[0], NumValValues), 3025 &Values[0], NumValValues)); 3026} 3027 3028void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3029 SDValue N = getValue(I.getOperand(0)); 3030 Type *Ty = I.getOperand(0)->getType(); 3031 3032 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3033 OI != E; ++OI) { 3034 const Value *Idx = *OI; 3035 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3036 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3037 if (Field) { 3038 // N = N + Offset 3039 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3040 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3041 DAG.getIntPtrConstant(Offset)); 3042 } 3043 3044 Ty = StTy->getElementType(Field); 3045 } else { 3046 Ty = cast<SequentialType>(Ty)->getElementType(); 3047 3048 // If this is a constant subscript, handle it quickly. 3049 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3050 if (CI->isZero()) continue; 3051 uint64_t Offs = 3052 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3053 SDValue OffsVal; 3054 EVT PTy = TLI.getPointerTy(); 3055 unsigned PtrBits = PTy.getSizeInBits(); 3056 if (PtrBits < 64) 3057 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3058 TLI.getPointerTy(), 3059 DAG.getConstant(Offs, MVT::i64)); 3060 else 3061 OffsVal = DAG.getIntPtrConstant(Offs); 3062 3063 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3064 OffsVal); 3065 continue; 3066 } 3067 3068 // N = N + Idx * ElementSize; 3069 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3070 TD->getTypeAllocSize(Ty)); 3071 SDValue IdxN = getValue(Idx); 3072 3073 // If the index is smaller or larger than intptr_t, truncate or extend 3074 // it. 3075 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3076 3077 // If this is a multiply by a power of two, turn it into a shl 3078 // immediately. This is a very common case. 3079 if (ElementSize != 1) { 3080 if (ElementSize.isPowerOf2()) { 3081 unsigned Amt = ElementSize.logBase2(); 3082 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3083 N.getValueType(), IdxN, 3084 DAG.getConstant(Amt, TLI.getPointerTy())); 3085 } else { 3086 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3087 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3088 N.getValueType(), IdxN, Scale); 3089 } 3090 } 3091 3092 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3093 N.getValueType(), N, IdxN); 3094 } 3095 } 3096 3097 setValue(&I, N); 3098} 3099 3100void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3101 // If this is a fixed sized alloca in the entry block of the function, 3102 // allocate it statically on the stack. 3103 if (FuncInfo.StaticAllocaMap.count(&I)) 3104 return; // getValue will auto-populate this. 3105 3106 Type *Ty = I.getAllocatedType(); 3107 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3108 unsigned Align = 3109 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3110 I.getAlignment()); 3111 3112 SDValue AllocSize = getValue(I.getArraySize()); 3113 3114 EVT IntPtr = TLI.getPointerTy(); 3115 if (AllocSize.getValueType() != IntPtr) 3116 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3117 3118 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3119 AllocSize, 3120 DAG.getConstant(TySize, IntPtr)); 3121 3122 // Handle alignment. If the requested alignment is less than or equal to 3123 // the stack alignment, ignore it. If the size is greater than or equal to 3124 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3125 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3126 if (Align <= StackAlign) 3127 Align = 0; 3128 3129 // Round the size of the allocation up to the stack alignment size 3130 // by add SA-1 to the size. 3131 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3132 AllocSize.getValueType(), AllocSize, 3133 DAG.getIntPtrConstant(StackAlign-1)); 3134 3135 // Mask out the low bits for alignment purposes. 3136 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3137 AllocSize.getValueType(), AllocSize, 3138 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3139 3140 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3141 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3142 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3143 VTs, Ops, 3); 3144 setValue(&I, DSA); 3145 DAG.setRoot(DSA.getValue(1)); 3146 3147 // Inform the Frame Information that we have just allocated a variable-sized 3148 // object. 3149 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3150} 3151 3152void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3153 const Value *SV = I.getOperand(0); 3154 SDValue Ptr = getValue(SV); 3155 3156 Type *Ty = I.getType(); 3157 3158 bool isVolatile = I.isVolatile(); 3159 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3160 unsigned Alignment = I.getAlignment(); 3161 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3162 3163 SmallVector<EVT, 4> ValueVTs; 3164 SmallVector<uint64_t, 4> Offsets; 3165 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3166 unsigned NumValues = ValueVTs.size(); 3167 if (NumValues == 0) 3168 return; 3169 3170 SDValue Root; 3171 bool ConstantMemory = false; 3172 if (I.isVolatile() || NumValues > MaxParallelChains) 3173 // Serialize volatile loads with other side effects. 3174 Root = getRoot(); 3175 else if (AA->pointsToConstantMemory( 3176 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3177 // Do not serialize (non-volatile) loads of constant memory with anything. 3178 Root = DAG.getEntryNode(); 3179 ConstantMemory = true; 3180 } else { 3181 // Do not serialize non-volatile loads against each other. 3182 Root = DAG.getRoot(); 3183 } 3184 3185 SmallVector<SDValue, 4> Values(NumValues); 3186 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3187 NumValues)); 3188 EVT PtrVT = Ptr.getValueType(); 3189 unsigned ChainI = 0; 3190 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3191 // Serializing loads here may result in excessive register pressure, and 3192 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3193 // could recover a bit by hoisting nodes upward in the chain by recognizing 3194 // they are side-effect free or do not alias. The optimizer should really 3195 // avoid this case by converting large object/array copies to llvm.memcpy 3196 // (MaxParallelChains should always remain as failsafe). 3197 if (ChainI == MaxParallelChains) { 3198 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3199 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3200 MVT::Other, &Chains[0], ChainI); 3201 Root = Chain; 3202 ChainI = 0; 3203 } 3204 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3205 PtrVT, Ptr, 3206 DAG.getConstant(Offsets[i], PtrVT)); 3207 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3208 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3209 isNonTemporal, Alignment, TBAAInfo); 3210 3211 Values[i] = L; 3212 Chains[ChainI] = L.getValue(1); 3213 } 3214 3215 if (!ConstantMemory) { 3216 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3217 MVT::Other, &Chains[0], ChainI); 3218 if (isVolatile) 3219 DAG.setRoot(Chain); 3220 else 3221 PendingLoads.push_back(Chain); 3222 } 3223 3224 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3225 DAG.getVTList(&ValueVTs[0], NumValues), 3226 &Values[0], NumValues)); 3227} 3228 3229void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3230 const Value *SrcV = I.getOperand(0); 3231 const Value *PtrV = I.getOperand(1); 3232 3233 SmallVector<EVT, 4> ValueVTs; 3234 SmallVector<uint64_t, 4> Offsets; 3235 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3236 unsigned NumValues = ValueVTs.size(); 3237 if (NumValues == 0) 3238 return; 3239 3240 // Get the lowered operands. Note that we do this after 3241 // checking if NumResults is zero, because with zero results 3242 // the operands won't have values in the map. 3243 SDValue Src = getValue(SrcV); 3244 SDValue Ptr = getValue(PtrV); 3245 3246 SDValue Root = getRoot(); 3247 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3248 NumValues)); 3249 EVT PtrVT = Ptr.getValueType(); 3250 bool isVolatile = I.isVolatile(); 3251 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3252 unsigned Alignment = I.getAlignment(); 3253 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3254 3255 unsigned ChainI = 0; 3256 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3257 // See visitLoad comments. 3258 if (ChainI == MaxParallelChains) { 3259 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3260 MVT::Other, &Chains[0], ChainI); 3261 Root = Chain; 3262 ChainI = 0; 3263 } 3264 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3265 DAG.getConstant(Offsets[i], PtrVT)); 3266 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3267 SDValue(Src.getNode(), Src.getResNo() + i), 3268 Add, MachinePointerInfo(PtrV, Offsets[i]), 3269 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3270 Chains[ChainI] = St; 3271 } 3272 3273 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3274 MVT::Other, &Chains[0], ChainI); 3275 ++SDNodeOrder; 3276 AssignOrderingToNode(StoreNode.getNode()); 3277 DAG.setRoot(StoreNode); 3278} 3279 3280void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3281 SDValue Root = getRoot(); 3282 SDValue L = 3283 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 3284 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3285 Root, 3286 getValue(I.getPointerOperand()), 3287 getValue(I.getCompareOperand()), 3288 getValue(I.getNewValOperand()), 3289 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3290 I.getOrdering(), I.getSynchScope()); 3291 setValue(&I, L); 3292 DAG.setRoot(L.getValue(1)); 3293} 3294 3295void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3296 ISD::NodeType NT; 3297 switch (I.getOperation()) { 3298 default: llvm_unreachable("Unknown atomicrmw operation"); return; 3299 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3300 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3301 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3302 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3303 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3304 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3305 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3306 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3307 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3308 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3309 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3310 } 3311 SDValue L = 3312 DAG.getAtomic(NT, getCurDebugLoc(), 3313 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3314 getRoot(), 3315 getValue(I.getPointerOperand()), 3316 getValue(I.getValOperand()), 3317 I.getPointerOperand(), 0 /* Alignment */, 3318 I.getOrdering(), I.getSynchScope()); 3319 setValue(&I, L); 3320 DAG.setRoot(L.getValue(1)); 3321} 3322 3323void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3324 DebugLoc dl = getCurDebugLoc(); 3325 SDValue Ops[3]; 3326 Ops[0] = getRoot(); 3327 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3328 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3329 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3330} 3331 3332/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3333/// node. 3334void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3335 unsigned Intrinsic) { 3336 bool HasChain = !I.doesNotAccessMemory(); 3337 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3338 3339 // Build the operand list. 3340 SmallVector<SDValue, 8> Ops; 3341 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3342 if (OnlyLoad) { 3343 // We don't need to serialize loads against other loads. 3344 Ops.push_back(DAG.getRoot()); 3345 } else { 3346 Ops.push_back(getRoot()); 3347 } 3348 } 3349 3350 // Info is set by getTgtMemInstrinsic 3351 TargetLowering::IntrinsicInfo Info; 3352 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3353 3354 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3355 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3356 Info.opc == ISD::INTRINSIC_W_CHAIN) 3357 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3358 3359 // Add all operands of the call to the operand list. 3360 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3361 SDValue Op = getValue(I.getArgOperand(i)); 3362 assert(TLI.isTypeLegal(Op.getValueType()) && 3363 "Intrinsic uses a non-legal type?"); 3364 Ops.push_back(Op); 3365 } 3366 3367 SmallVector<EVT, 4> ValueVTs; 3368 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3369#ifndef NDEBUG 3370 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3371 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3372 "Intrinsic uses a non-legal type?"); 3373 } 3374#endif // NDEBUG 3375 3376 if (HasChain) 3377 ValueVTs.push_back(MVT::Other); 3378 3379 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3380 3381 // Create the node. 3382 SDValue Result; 3383 if (IsTgtIntrinsic) { 3384 // This is target intrinsic that touches memory 3385 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3386 VTs, &Ops[0], Ops.size(), 3387 Info.memVT, 3388 MachinePointerInfo(Info.ptrVal, Info.offset), 3389 Info.align, Info.vol, 3390 Info.readMem, Info.writeMem); 3391 } else if (!HasChain) { 3392 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3393 VTs, &Ops[0], Ops.size()); 3394 } else if (!I.getType()->isVoidTy()) { 3395 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3396 VTs, &Ops[0], Ops.size()); 3397 } else { 3398 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3399 VTs, &Ops[0], Ops.size()); 3400 } 3401 3402 if (HasChain) { 3403 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3404 if (OnlyLoad) 3405 PendingLoads.push_back(Chain); 3406 else 3407 DAG.setRoot(Chain); 3408 } 3409 3410 if (!I.getType()->isVoidTy()) { 3411 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3412 EVT VT = TLI.getValueType(PTy); 3413 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3414 } 3415 3416 setValue(&I, Result); 3417 } 3418} 3419 3420/// GetSignificand - Get the significand and build it into a floating-point 3421/// number with exponent of 1: 3422/// 3423/// Op = (Op & 0x007fffff) | 0x3f800000; 3424/// 3425/// where Op is the hexidecimal representation of floating point value. 3426static SDValue 3427GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3428 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3429 DAG.getConstant(0x007fffff, MVT::i32)); 3430 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3431 DAG.getConstant(0x3f800000, MVT::i32)); 3432 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3433} 3434 3435/// GetExponent - Get the exponent: 3436/// 3437/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3438/// 3439/// where Op is the hexidecimal representation of floating point value. 3440static SDValue 3441GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3442 DebugLoc dl) { 3443 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3444 DAG.getConstant(0x7f800000, MVT::i32)); 3445 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3446 DAG.getConstant(23, TLI.getPointerTy())); 3447 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3448 DAG.getConstant(127, MVT::i32)); 3449 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3450} 3451 3452/// getF32Constant - Get 32-bit floating point constant. 3453static SDValue 3454getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3455 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3456} 3457 3458/// Inlined utility function to implement binary input atomic intrinsics for 3459/// visitIntrinsicCall: I is a call instruction 3460/// Op is the associated NodeType for I 3461const char * 3462SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3463 ISD::NodeType Op) { 3464 SDValue Root = getRoot(); 3465 SDValue L = 3466 DAG.getAtomic(Op, getCurDebugLoc(), 3467 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3468 Root, 3469 getValue(I.getArgOperand(0)), 3470 getValue(I.getArgOperand(1)), 3471 I.getArgOperand(0), 0 /* Alignment */, 3472 Monotonic, CrossThread); 3473 setValue(&I, L); 3474 DAG.setRoot(L.getValue(1)); 3475 return 0; 3476} 3477 3478// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3479const char * 3480SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3481 SDValue Op1 = getValue(I.getArgOperand(0)); 3482 SDValue Op2 = getValue(I.getArgOperand(1)); 3483 3484 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3485 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3486 return 0; 3487} 3488 3489/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3490/// limited-precision mode. 3491void 3492SelectionDAGBuilder::visitExp(const CallInst &I) { 3493 SDValue result; 3494 DebugLoc dl = getCurDebugLoc(); 3495 3496 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3497 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3498 SDValue Op = getValue(I.getArgOperand(0)); 3499 3500 // Put the exponent in the right bit position for later addition to the 3501 // final result: 3502 // 3503 // #define LOG2OFe 1.4426950f 3504 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3505 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3506 getF32Constant(DAG, 0x3fb8aa3b)); 3507 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3508 3509 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3510 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3511 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3512 3513 // IntegerPartOfX <<= 23; 3514 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3515 DAG.getConstant(23, TLI.getPointerTy())); 3516 3517 if (LimitFloatPrecision <= 6) { 3518 // For floating-point precision of 6: 3519 // 3520 // TwoToFractionalPartOfX = 3521 // 0.997535578f + 3522 // (0.735607626f + 0.252464424f * x) * x; 3523 // 3524 // error 0.0144103317, which is 6 bits 3525 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3526 getF32Constant(DAG, 0x3e814304)); 3527 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3528 getF32Constant(DAG, 0x3f3c50c8)); 3529 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3530 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3531 getF32Constant(DAG, 0x3f7f5e7e)); 3532 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3533 3534 // Add the exponent into the result in integer domain. 3535 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3536 TwoToFracPartOfX, IntegerPartOfX); 3537 3538 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3539 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3540 // For floating-point precision of 12: 3541 // 3542 // TwoToFractionalPartOfX = 3543 // 0.999892986f + 3544 // (0.696457318f + 3545 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3546 // 3547 // 0.000107046256 error, which is 13 to 14 bits 3548 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3549 getF32Constant(DAG, 0x3da235e3)); 3550 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3551 getF32Constant(DAG, 0x3e65b8f3)); 3552 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3553 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3554 getF32Constant(DAG, 0x3f324b07)); 3555 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3556 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3557 getF32Constant(DAG, 0x3f7ff8fd)); 3558 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3559 3560 // Add the exponent into the result in integer domain. 3561 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3562 TwoToFracPartOfX, IntegerPartOfX); 3563 3564 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3565 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3566 // For floating-point precision of 18: 3567 // 3568 // TwoToFractionalPartOfX = 3569 // 0.999999982f + 3570 // (0.693148872f + 3571 // (0.240227044f + 3572 // (0.554906021e-1f + 3573 // (0.961591928e-2f + 3574 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3575 // 3576 // error 2.47208000*10^(-7), which is better than 18 bits 3577 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3578 getF32Constant(DAG, 0x3924b03e)); 3579 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3580 getF32Constant(DAG, 0x3ab24b87)); 3581 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3582 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3583 getF32Constant(DAG, 0x3c1d8c17)); 3584 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3585 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3586 getF32Constant(DAG, 0x3d634a1d)); 3587 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3588 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3589 getF32Constant(DAG, 0x3e75fe14)); 3590 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3591 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3592 getF32Constant(DAG, 0x3f317234)); 3593 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3594 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3595 getF32Constant(DAG, 0x3f800000)); 3596 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3597 MVT::i32, t13); 3598 3599 // Add the exponent into the result in integer domain. 3600 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3601 TwoToFracPartOfX, IntegerPartOfX); 3602 3603 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3604 } 3605 } else { 3606 // No special expansion. 3607 result = DAG.getNode(ISD::FEXP, dl, 3608 getValue(I.getArgOperand(0)).getValueType(), 3609 getValue(I.getArgOperand(0))); 3610 } 3611 3612 setValue(&I, result); 3613} 3614 3615/// visitLog - Lower a log intrinsic. Handles the special sequences for 3616/// limited-precision mode. 3617void 3618SelectionDAGBuilder::visitLog(const CallInst &I) { 3619 SDValue result; 3620 DebugLoc dl = getCurDebugLoc(); 3621 3622 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3623 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3624 SDValue Op = getValue(I.getArgOperand(0)); 3625 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3626 3627 // Scale the exponent by log(2) [0.69314718f]. 3628 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3629 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3630 getF32Constant(DAG, 0x3f317218)); 3631 3632 // Get the significand and build it into a floating-point number with 3633 // exponent of 1. 3634 SDValue X = GetSignificand(DAG, Op1, dl); 3635 3636 if (LimitFloatPrecision <= 6) { 3637 // For floating-point precision of 6: 3638 // 3639 // LogofMantissa = 3640 // -1.1609546f + 3641 // (1.4034025f - 0.23903021f * x) * x; 3642 // 3643 // error 0.0034276066, which is better than 8 bits 3644 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3645 getF32Constant(DAG, 0xbe74c456)); 3646 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3647 getF32Constant(DAG, 0x3fb3a2b1)); 3648 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3649 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3650 getF32Constant(DAG, 0x3f949a29)); 3651 3652 result = DAG.getNode(ISD::FADD, dl, 3653 MVT::f32, LogOfExponent, LogOfMantissa); 3654 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3655 // For floating-point precision of 12: 3656 // 3657 // LogOfMantissa = 3658 // -1.7417939f + 3659 // (2.8212026f + 3660 // (-1.4699568f + 3661 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3662 // 3663 // error 0.000061011436, which is 14 bits 3664 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3665 getF32Constant(DAG, 0xbd67b6d6)); 3666 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3667 getF32Constant(DAG, 0x3ee4f4b8)); 3668 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3669 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3670 getF32Constant(DAG, 0x3fbc278b)); 3671 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3672 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3673 getF32Constant(DAG, 0x40348e95)); 3674 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3675 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3676 getF32Constant(DAG, 0x3fdef31a)); 3677 3678 result = DAG.getNode(ISD::FADD, dl, 3679 MVT::f32, LogOfExponent, LogOfMantissa); 3680 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3681 // For floating-point precision of 18: 3682 // 3683 // LogOfMantissa = 3684 // -2.1072184f + 3685 // (4.2372794f + 3686 // (-3.7029485f + 3687 // (2.2781945f + 3688 // (-0.87823314f + 3689 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3690 // 3691 // error 0.0000023660568, which is better than 18 bits 3692 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3693 getF32Constant(DAG, 0xbc91e5ac)); 3694 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3695 getF32Constant(DAG, 0x3e4350aa)); 3696 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3697 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3698 getF32Constant(DAG, 0x3f60d3e3)); 3699 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3700 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3701 getF32Constant(DAG, 0x4011cdf0)); 3702 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3703 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3704 getF32Constant(DAG, 0x406cfd1c)); 3705 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3706 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3707 getF32Constant(DAG, 0x408797cb)); 3708 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3709 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3710 getF32Constant(DAG, 0x4006dcab)); 3711 3712 result = DAG.getNode(ISD::FADD, dl, 3713 MVT::f32, LogOfExponent, LogOfMantissa); 3714 } 3715 } else { 3716 // No special expansion. 3717 result = DAG.getNode(ISD::FLOG, dl, 3718 getValue(I.getArgOperand(0)).getValueType(), 3719 getValue(I.getArgOperand(0))); 3720 } 3721 3722 setValue(&I, result); 3723} 3724 3725/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3726/// limited-precision mode. 3727void 3728SelectionDAGBuilder::visitLog2(const CallInst &I) { 3729 SDValue result; 3730 DebugLoc dl = getCurDebugLoc(); 3731 3732 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3733 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3734 SDValue Op = getValue(I.getArgOperand(0)); 3735 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3736 3737 // Get the exponent. 3738 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3739 3740 // Get the significand and build it into a floating-point number with 3741 // exponent of 1. 3742 SDValue X = GetSignificand(DAG, Op1, dl); 3743 3744 // Different possible minimax approximations of significand in 3745 // floating-point for various degrees of accuracy over [1,2]. 3746 if (LimitFloatPrecision <= 6) { 3747 // For floating-point precision of 6: 3748 // 3749 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3750 // 3751 // error 0.0049451742, which is more than 7 bits 3752 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3753 getF32Constant(DAG, 0xbeb08fe0)); 3754 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3755 getF32Constant(DAG, 0x40019463)); 3756 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3757 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3758 getF32Constant(DAG, 0x3fd6633d)); 3759 3760 result = DAG.getNode(ISD::FADD, dl, 3761 MVT::f32, LogOfExponent, Log2ofMantissa); 3762 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3763 // For floating-point precision of 12: 3764 // 3765 // Log2ofMantissa = 3766 // -2.51285454f + 3767 // (4.07009056f + 3768 // (-2.12067489f + 3769 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3770 // 3771 // error 0.0000876136000, which is better than 13 bits 3772 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3773 getF32Constant(DAG, 0xbda7262e)); 3774 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3775 getF32Constant(DAG, 0x3f25280b)); 3776 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3777 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3778 getF32Constant(DAG, 0x4007b923)); 3779 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3780 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3781 getF32Constant(DAG, 0x40823e2f)); 3782 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3783 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3784 getF32Constant(DAG, 0x4020d29c)); 3785 3786 result = DAG.getNode(ISD::FADD, dl, 3787 MVT::f32, LogOfExponent, Log2ofMantissa); 3788 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3789 // For floating-point precision of 18: 3790 // 3791 // Log2ofMantissa = 3792 // -3.0400495f + 3793 // (6.1129976f + 3794 // (-5.3420409f + 3795 // (3.2865683f + 3796 // (-1.2669343f + 3797 // (0.27515199f - 3798 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3799 // 3800 // error 0.0000018516, which is better than 18 bits 3801 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3802 getF32Constant(DAG, 0xbcd2769e)); 3803 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3804 getF32Constant(DAG, 0x3e8ce0b9)); 3805 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3806 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3807 getF32Constant(DAG, 0x3fa22ae7)); 3808 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3809 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3810 getF32Constant(DAG, 0x40525723)); 3811 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3812 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3813 getF32Constant(DAG, 0x40aaf200)); 3814 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3815 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3816 getF32Constant(DAG, 0x40c39dad)); 3817 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3818 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3819 getF32Constant(DAG, 0x4042902c)); 3820 3821 result = DAG.getNode(ISD::FADD, dl, 3822 MVT::f32, LogOfExponent, Log2ofMantissa); 3823 } 3824 } else { 3825 // No special expansion. 3826 result = DAG.getNode(ISD::FLOG2, dl, 3827 getValue(I.getArgOperand(0)).getValueType(), 3828 getValue(I.getArgOperand(0))); 3829 } 3830 3831 setValue(&I, result); 3832} 3833 3834/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3835/// limited-precision mode. 3836void 3837SelectionDAGBuilder::visitLog10(const CallInst &I) { 3838 SDValue result; 3839 DebugLoc dl = getCurDebugLoc(); 3840 3841 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3842 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3843 SDValue Op = getValue(I.getArgOperand(0)); 3844 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3845 3846 // Scale the exponent by log10(2) [0.30102999f]. 3847 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3848 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3849 getF32Constant(DAG, 0x3e9a209a)); 3850 3851 // Get the significand and build it into a floating-point number with 3852 // exponent of 1. 3853 SDValue X = GetSignificand(DAG, Op1, dl); 3854 3855 if (LimitFloatPrecision <= 6) { 3856 // For floating-point precision of 6: 3857 // 3858 // Log10ofMantissa = 3859 // -0.50419619f + 3860 // (0.60948995f - 0.10380950f * x) * x; 3861 // 3862 // error 0.0014886165, which is 6 bits 3863 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3864 getF32Constant(DAG, 0xbdd49a13)); 3865 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3866 getF32Constant(DAG, 0x3f1c0789)); 3867 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3868 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3869 getF32Constant(DAG, 0x3f011300)); 3870 3871 result = DAG.getNode(ISD::FADD, dl, 3872 MVT::f32, LogOfExponent, Log10ofMantissa); 3873 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3874 // For floating-point precision of 12: 3875 // 3876 // Log10ofMantissa = 3877 // -0.64831180f + 3878 // (0.91751397f + 3879 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3880 // 3881 // error 0.00019228036, which is better than 12 bits 3882 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3883 getF32Constant(DAG, 0x3d431f31)); 3884 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3885 getF32Constant(DAG, 0x3ea21fb2)); 3886 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3887 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3888 getF32Constant(DAG, 0x3f6ae232)); 3889 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3890 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3891 getF32Constant(DAG, 0x3f25f7c3)); 3892 3893 result = DAG.getNode(ISD::FADD, dl, 3894 MVT::f32, LogOfExponent, Log10ofMantissa); 3895 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3896 // For floating-point precision of 18: 3897 // 3898 // Log10ofMantissa = 3899 // -0.84299375f + 3900 // (1.5327582f + 3901 // (-1.0688956f + 3902 // (0.49102474f + 3903 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3904 // 3905 // error 0.0000037995730, which is better than 18 bits 3906 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3907 getF32Constant(DAG, 0x3c5d51ce)); 3908 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3909 getF32Constant(DAG, 0x3e00685a)); 3910 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3911 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3912 getF32Constant(DAG, 0x3efb6798)); 3913 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3914 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3915 getF32Constant(DAG, 0x3f88d192)); 3916 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3917 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3918 getF32Constant(DAG, 0x3fc4316c)); 3919 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3920 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3921 getF32Constant(DAG, 0x3f57ce70)); 3922 3923 result = DAG.getNode(ISD::FADD, dl, 3924 MVT::f32, LogOfExponent, Log10ofMantissa); 3925 } 3926 } else { 3927 // No special expansion. 3928 result = DAG.getNode(ISD::FLOG10, dl, 3929 getValue(I.getArgOperand(0)).getValueType(), 3930 getValue(I.getArgOperand(0))); 3931 } 3932 3933 setValue(&I, result); 3934} 3935 3936/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3937/// limited-precision mode. 3938void 3939SelectionDAGBuilder::visitExp2(const CallInst &I) { 3940 SDValue result; 3941 DebugLoc dl = getCurDebugLoc(); 3942 3943 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3944 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3945 SDValue Op = getValue(I.getArgOperand(0)); 3946 3947 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3948 3949 // FractionalPartOfX = x - (float)IntegerPartOfX; 3950 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3951 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3952 3953 // IntegerPartOfX <<= 23; 3954 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3955 DAG.getConstant(23, TLI.getPointerTy())); 3956 3957 if (LimitFloatPrecision <= 6) { 3958 // For floating-point precision of 6: 3959 // 3960 // TwoToFractionalPartOfX = 3961 // 0.997535578f + 3962 // (0.735607626f + 0.252464424f * x) * x; 3963 // 3964 // error 0.0144103317, which is 6 bits 3965 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3966 getF32Constant(DAG, 0x3e814304)); 3967 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3968 getF32Constant(DAG, 0x3f3c50c8)); 3969 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3970 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3971 getF32Constant(DAG, 0x3f7f5e7e)); 3972 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3973 SDValue TwoToFractionalPartOfX = 3974 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3975 3976 result = DAG.getNode(ISD::BITCAST, dl, 3977 MVT::f32, TwoToFractionalPartOfX); 3978 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3979 // For floating-point precision of 12: 3980 // 3981 // TwoToFractionalPartOfX = 3982 // 0.999892986f + 3983 // (0.696457318f + 3984 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3985 // 3986 // error 0.000107046256, which is 13 to 14 bits 3987 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3988 getF32Constant(DAG, 0x3da235e3)); 3989 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3990 getF32Constant(DAG, 0x3e65b8f3)); 3991 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3992 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3993 getF32Constant(DAG, 0x3f324b07)); 3994 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3995 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3996 getF32Constant(DAG, 0x3f7ff8fd)); 3997 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3998 SDValue TwoToFractionalPartOfX = 3999 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4000 4001 result = DAG.getNode(ISD::BITCAST, dl, 4002 MVT::f32, TwoToFractionalPartOfX); 4003 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4004 // For floating-point precision of 18: 4005 // 4006 // TwoToFractionalPartOfX = 4007 // 0.999999982f + 4008 // (0.693148872f + 4009 // (0.240227044f + 4010 // (0.554906021e-1f + 4011 // (0.961591928e-2f + 4012 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4013 // error 2.47208000*10^(-7), which is better than 18 bits 4014 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4015 getF32Constant(DAG, 0x3924b03e)); 4016 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4017 getF32Constant(DAG, 0x3ab24b87)); 4018 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4019 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4020 getF32Constant(DAG, 0x3c1d8c17)); 4021 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4022 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4023 getF32Constant(DAG, 0x3d634a1d)); 4024 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4025 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4026 getF32Constant(DAG, 0x3e75fe14)); 4027 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4028 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4029 getF32Constant(DAG, 0x3f317234)); 4030 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4031 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4032 getF32Constant(DAG, 0x3f800000)); 4033 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4034 SDValue TwoToFractionalPartOfX = 4035 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4036 4037 result = DAG.getNode(ISD::BITCAST, dl, 4038 MVT::f32, TwoToFractionalPartOfX); 4039 } 4040 } else { 4041 // No special expansion. 4042 result = DAG.getNode(ISD::FEXP2, dl, 4043 getValue(I.getArgOperand(0)).getValueType(), 4044 getValue(I.getArgOperand(0))); 4045 } 4046 4047 setValue(&I, result); 4048} 4049 4050/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4051/// limited-precision mode with x == 10.0f. 4052void 4053SelectionDAGBuilder::visitPow(const CallInst &I) { 4054 SDValue result; 4055 const Value *Val = I.getArgOperand(0); 4056 DebugLoc dl = getCurDebugLoc(); 4057 bool IsExp10 = false; 4058 4059 if (getValue(Val).getValueType() == MVT::f32 && 4060 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4061 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4062 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4063 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4064 APFloat Ten(10.0f); 4065 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4066 } 4067 } 4068 } 4069 4070 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4071 SDValue Op = getValue(I.getArgOperand(1)); 4072 4073 // Put the exponent in the right bit position for later addition to the 4074 // final result: 4075 // 4076 // #define LOG2OF10 3.3219281f 4077 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4078 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4079 getF32Constant(DAG, 0x40549a78)); 4080 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4081 4082 // FractionalPartOfX = x - (float)IntegerPartOfX; 4083 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4084 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4085 4086 // IntegerPartOfX <<= 23; 4087 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4088 DAG.getConstant(23, TLI.getPointerTy())); 4089 4090 if (LimitFloatPrecision <= 6) { 4091 // For floating-point precision of 6: 4092 // 4093 // twoToFractionalPartOfX = 4094 // 0.997535578f + 4095 // (0.735607626f + 0.252464424f * x) * x; 4096 // 4097 // error 0.0144103317, which is 6 bits 4098 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4099 getF32Constant(DAG, 0x3e814304)); 4100 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4101 getF32Constant(DAG, 0x3f3c50c8)); 4102 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4103 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4104 getF32Constant(DAG, 0x3f7f5e7e)); 4105 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4106 SDValue TwoToFractionalPartOfX = 4107 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4108 4109 result = DAG.getNode(ISD::BITCAST, dl, 4110 MVT::f32, TwoToFractionalPartOfX); 4111 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4112 // For floating-point precision of 12: 4113 // 4114 // TwoToFractionalPartOfX = 4115 // 0.999892986f + 4116 // (0.696457318f + 4117 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4118 // 4119 // error 0.000107046256, which is 13 to 14 bits 4120 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4121 getF32Constant(DAG, 0x3da235e3)); 4122 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4123 getF32Constant(DAG, 0x3e65b8f3)); 4124 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4125 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4126 getF32Constant(DAG, 0x3f324b07)); 4127 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4128 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4129 getF32Constant(DAG, 0x3f7ff8fd)); 4130 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4131 SDValue TwoToFractionalPartOfX = 4132 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4133 4134 result = DAG.getNode(ISD::BITCAST, dl, 4135 MVT::f32, TwoToFractionalPartOfX); 4136 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4137 // For floating-point precision of 18: 4138 // 4139 // TwoToFractionalPartOfX = 4140 // 0.999999982f + 4141 // (0.693148872f + 4142 // (0.240227044f + 4143 // (0.554906021e-1f + 4144 // (0.961591928e-2f + 4145 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4146 // error 2.47208000*10^(-7), which is better than 18 bits 4147 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4148 getF32Constant(DAG, 0x3924b03e)); 4149 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4150 getF32Constant(DAG, 0x3ab24b87)); 4151 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4152 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4153 getF32Constant(DAG, 0x3c1d8c17)); 4154 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4155 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4156 getF32Constant(DAG, 0x3d634a1d)); 4157 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4158 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4159 getF32Constant(DAG, 0x3e75fe14)); 4160 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4161 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4162 getF32Constant(DAG, 0x3f317234)); 4163 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4164 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4165 getF32Constant(DAG, 0x3f800000)); 4166 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4167 SDValue TwoToFractionalPartOfX = 4168 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4169 4170 result = DAG.getNode(ISD::BITCAST, dl, 4171 MVT::f32, TwoToFractionalPartOfX); 4172 } 4173 } else { 4174 // No special expansion. 4175 result = DAG.getNode(ISD::FPOW, dl, 4176 getValue(I.getArgOperand(0)).getValueType(), 4177 getValue(I.getArgOperand(0)), 4178 getValue(I.getArgOperand(1))); 4179 } 4180 4181 setValue(&I, result); 4182} 4183 4184 4185/// ExpandPowI - Expand a llvm.powi intrinsic. 4186static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4187 SelectionDAG &DAG) { 4188 // If RHS is a constant, we can expand this out to a multiplication tree, 4189 // otherwise we end up lowering to a call to __powidf2 (for example). When 4190 // optimizing for size, we only want to do this if the expansion would produce 4191 // a small number of multiplies, otherwise we do the full expansion. 4192 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4193 // Get the exponent as a positive value. 4194 unsigned Val = RHSC->getSExtValue(); 4195 if ((int)Val < 0) Val = -Val; 4196 4197 // powi(x, 0) -> 1.0 4198 if (Val == 0) 4199 return DAG.getConstantFP(1.0, LHS.getValueType()); 4200 4201 const Function *F = DAG.getMachineFunction().getFunction(); 4202 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4203 // If optimizing for size, don't insert too many multiplies. This 4204 // inserts up to 5 multiplies. 4205 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4206 // We use the simple binary decomposition method to generate the multiply 4207 // sequence. There are more optimal ways to do this (for example, 4208 // powi(x,15) generates one more multiply than it should), but this has 4209 // the benefit of being both really simple and much better than a libcall. 4210 SDValue Res; // Logically starts equal to 1.0 4211 SDValue CurSquare = LHS; 4212 while (Val) { 4213 if (Val & 1) { 4214 if (Res.getNode()) 4215 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4216 else 4217 Res = CurSquare; // 1.0*CurSquare. 4218 } 4219 4220 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4221 CurSquare, CurSquare); 4222 Val >>= 1; 4223 } 4224 4225 // If the original was negative, invert the result, producing 1/(x*x*x). 4226 if (RHSC->getSExtValue() < 0) 4227 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4228 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4229 return Res; 4230 } 4231 } 4232 4233 // Otherwise, expand to a libcall. 4234 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4235} 4236 4237// getTruncatedArgReg - Find underlying register used for an truncated 4238// argument. 4239static unsigned getTruncatedArgReg(const SDValue &N) { 4240 if (N.getOpcode() != ISD::TRUNCATE) 4241 return 0; 4242 4243 const SDValue &Ext = N.getOperand(0); 4244 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4245 const SDValue &CFR = Ext.getOperand(0); 4246 if (CFR.getOpcode() == ISD::CopyFromReg) 4247 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4248 else 4249 if (CFR.getOpcode() == ISD::TRUNCATE) 4250 return getTruncatedArgReg(CFR); 4251 } 4252 return 0; 4253} 4254 4255/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4256/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4257/// At the end of instruction selection, they will be inserted to the entry BB. 4258bool 4259SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4260 int64_t Offset, 4261 const SDValue &N) { 4262 const Argument *Arg = dyn_cast<Argument>(V); 4263 if (!Arg) 4264 return false; 4265 4266 MachineFunction &MF = DAG.getMachineFunction(); 4267 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4268 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4269 4270 // Ignore inlined function arguments here. 4271 DIVariable DV(Variable); 4272 if (DV.isInlinedFnArgument(MF.getFunction())) 4273 return false; 4274 4275 unsigned Reg = 0; 4276 if (Arg->hasByValAttr()) { 4277 // Byval arguments' frame index is recorded during argument lowering. 4278 // Use this info directly. 4279 Reg = TRI->getFrameRegister(MF); 4280 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 4281 // If byval argument ofset is not recorded then ignore this. 4282 if (!Offset) 4283 Reg = 0; 4284 } 4285 4286 if (N.getNode()) { 4287 if (N.getOpcode() == ISD::CopyFromReg) 4288 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4289 else 4290 Reg = getTruncatedArgReg(N); 4291 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4292 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4293 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4294 if (PR) 4295 Reg = PR; 4296 } 4297 } 4298 4299 if (!Reg) { 4300 // Check if ValueMap has reg number. 4301 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4302 if (VMI != FuncInfo.ValueMap.end()) 4303 Reg = VMI->second; 4304 } 4305 4306 if (!Reg && N.getNode()) { 4307 // Check if frame index is available. 4308 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4309 if (FrameIndexSDNode *FINode = 4310 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4311 Reg = TRI->getFrameRegister(MF); 4312 Offset = FINode->getIndex(); 4313 } 4314 } 4315 4316 if (!Reg) 4317 return false; 4318 4319 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4320 TII->get(TargetOpcode::DBG_VALUE)) 4321 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4322 FuncInfo.ArgDbgValues.push_back(&*MIB); 4323 return true; 4324} 4325 4326// VisualStudio defines setjmp as _setjmp 4327#if defined(_MSC_VER) && defined(setjmp) && \ 4328 !defined(setjmp_undefined_for_msvc) 4329# pragma push_macro("setjmp") 4330# undef setjmp 4331# define setjmp_undefined_for_msvc 4332#endif 4333 4334/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4335/// we want to emit this as a call to a named external function, return the name 4336/// otherwise lower it and return null. 4337const char * 4338SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4339 DebugLoc dl = getCurDebugLoc(); 4340 SDValue Res; 4341 4342 switch (Intrinsic) { 4343 default: 4344 // By default, turn this into a target intrinsic node. 4345 visitTargetIntrinsic(I, Intrinsic); 4346 return 0; 4347 case Intrinsic::vastart: visitVAStart(I); return 0; 4348 case Intrinsic::vaend: visitVAEnd(I); return 0; 4349 case Intrinsic::vacopy: visitVACopy(I); return 0; 4350 case Intrinsic::returnaddress: 4351 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4352 getValue(I.getArgOperand(0)))); 4353 return 0; 4354 case Intrinsic::frameaddress: 4355 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4356 getValue(I.getArgOperand(0)))); 4357 return 0; 4358 case Intrinsic::setjmp: 4359 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4360 case Intrinsic::longjmp: 4361 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4362 case Intrinsic::memcpy: { 4363 // Assert for address < 256 since we support only user defined address 4364 // spaces. 4365 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4366 < 256 && 4367 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4368 < 256 && 4369 "Unknown address space"); 4370 SDValue Op1 = getValue(I.getArgOperand(0)); 4371 SDValue Op2 = getValue(I.getArgOperand(1)); 4372 SDValue Op3 = getValue(I.getArgOperand(2)); 4373 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4374 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4375 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4376 MachinePointerInfo(I.getArgOperand(0)), 4377 MachinePointerInfo(I.getArgOperand(1)))); 4378 return 0; 4379 } 4380 case Intrinsic::memset: { 4381 // Assert for address < 256 since we support only user defined address 4382 // spaces. 4383 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4384 < 256 && 4385 "Unknown address space"); 4386 SDValue Op1 = getValue(I.getArgOperand(0)); 4387 SDValue Op2 = getValue(I.getArgOperand(1)); 4388 SDValue Op3 = getValue(I.getArgOperand(2)); 4389 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4390 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4391 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4392 MachinePointerInfo(I.getArgOperand(0)))); 4393 return 0; 4394 } 4395 case Intrinsic::memmove: { 4396 // Assert for address < 256 since we support only user defined address 4397 // spaces. 4398 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4399 < 256 && 4400 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4401 < 256 && 4402 "Unknown address space"); 4403 SDValue Op1 = getValue(I.getArgOperand(0)); 4404 SDValue Op2 = getValue(I.getArgOperand(1)); 4405 SDValue Op3 = getValue(I.getArgOperand(2)); 4406 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4407 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4408 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4409 MachinePointerInfo(I.getArgOperand(0)), 4410 MachinePointerInfo(I.getArgOperand(1)))); 4411 return 0; 4412 } 4413 case Intrinsic::dbg_declare: { 4414 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4415 MDNode *Variable = DI.getVariable(); 4416 const Value *Address = DI.getAddress(); 4417 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4418 return 0; 4419 4420 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4421 // but do not always have a corresponding SDNode built. The SDNodeOrder 4422 // absolute, but not relative, values are different depending on whether 4423 // debug info exists. 4424 ++SDNodeOrder; 4425 4426 // Check if address has undef value. 4427 if (isa<UndefValue>(Address) || 4428 (Address->use_empty() && !isa<Argument>(Address))) { 4429 DEBUG(dbgs() << "Dropping debug info for " << DI); 4430 return 0; 4431 } 4432 4433 SDValue &N = NodeMap[Address]; 4434 if (!N.getNode() && isa<Argument>(Address)) 4435 // Check unused arguments map. 4436 N = UnusedArgNodeMap[Address]; 4437 SDDbgValue *SDV; 4438 if (N.getNode()) { 4439 // Parameters are handled specially. 4440 bool isParameter = 4441 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4442 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4443 Address = BCI->getOperand(0); 4444 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4445 4446 if (isParameter && !AI) { 4447 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4448 if (FINode) 4449 // Byval parameter. We have a frame index at this point. 4450 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4451 0, dl, SDNodeOrder); 4452 else { 4453 // Address is an argument, so try to emit its dbg value using 4454 // virtual register info from the FuncInfo.ValueMap. 4455 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4456 return 0; 4457 } 4458 } else if (AI) 4459 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4460 0, dl, SDNodeOrder); 4461 else { 4462 // Can't do anything with other non-AI cases yet. 4463 DEBUG(dbgs() << "Dropping debug info for " << DI); 4464 return 0; 4465 } 4466 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4467 } else { 4468 // If Address is an argument then try to emit its dbg value using 4469 // virtual register info from the FuncInfo.ValueMap. 4470 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4471 // If variable is pinned by a alloca in dominating bb then 4472 // use StaticAllocaMap. 4473 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4474 if (AI->getParent() != DI.getParent()) { 4475 DenseMap<const AllocaInst*, int>::iterator SI = 4476 FuncInfo.StaticAllocaMap.find(AI); 4477 if (SI != FuncInfo.StaticAllocaMap.end()) { 4478 SDV = DAG.getDbgValue(Variable, SI->second, 4479 0, dl, SDNodeOrder); 4480 DAG.AddDbgValue(SDV, 0, false); 4481 return 0; 4482 } 4483 } 4484 } 4485 DEBUG(dbgs() << "Dropping debug info for " << DI); 4486 } 4487 } 4488 return 0; 4489 } 4490 case Intrinsic::dbg_value: { 4491 const DbgValueInst &DI = cast<DbgValueInst>(I); 4492 if (!DIVariable(DI.getVariable()).Verify()) 4493 return 0; 4494 4495 MDNode *Variable = DI.getVariable(); 4496 uint64_t Offset = DI.getOffset(); 4497 const Value *V = DI.getValue(); 4498 if (!V) 4499 return 0; 4500 4501 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4502 // but do not always have a corresponding SDNode built. The SDNodeOrder 4503 // absolute, but not relative, values are different depending on whether 4504 // debug info exists. 4505 ++SDNodeOrder; 4506 SDDbgValue *SDV; 4507 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4508 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4509 DAG.AddDbgValue(SDV, 0, false); 4510 } else { 4511 // Do not use getValue() in here; we don't want to generate code at 4512 // this point if it hasn't been done yet. 4513 SDValue N = NodeMap[V]; 4514 if (!N.getNode() && isa<Argument>(V)) 4515 // Check unused arguments map. 4516 N = UnusedArgNodeMap[V]; 4517 if (N.getNode()) { 4518 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4519 SDV = DAG.getDbgValue(Variable, N.getNode(), 4520 N.getResNo(), Offset, dl, SDNodeOrder); 4521 DAG.AddDbgValue(SDV, N.getNode(), false); 4522 } 4523 } else if (!V->use_empty() ) { 4524 // Do not call getValue(V) yet, as we don't want to generate code. 4525 // Remember it for later. 4526 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4527 DanglingDebugInfoMap[V] = DDI; 4528 } else { 4529 // We may expand this to cover more cases. One case where we have no 4530 // data available is an unreferenced parameter. 4531 DEBUG(dbgs() << "Dropping debug info for " << DI); 4532 } 4533 } 4534 4535 // Build a debug info table entry. 4536 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4537 V = BCI->getOperand(0); 4538 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4539 // Don't handle byval struct arguments or VLAs, for example. 4540 if (!AI) 4541 return 0; 4542 DenseMap<const AllocaInst*, int>::iterator SI = 4543 FuncInfo.StaticAllocaMap.find(AI); 4544 if (SI == FuncInfo.StaticAllocaMap.end()) 4545 return 0; // VLAs. 4546 int FI = SI->second; 4547 4548 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4549 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4550 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4551 return 0; 4552 } 4553 case Intrinsic::eh_exception: { 4554 // Insert the EXCEPTIONADDR instruction. 4555 assert(FuncInfo.MBB->isLandingPad() && 4556 "Call to eh.exception not in landing pad!"); 4557 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4558 SDValue Ops[1]; 4559 Ops[0] = DAG.getRoot(); 4560 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4561 setValue(&I, Op); 4562 DAG.setRoot(Op.getValue(1)); 4563 return 0; 4564 } 4565 4566 case Intrinsic::eh_selector: { 4567 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4568 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4569 if (CallMBB->isLandingPad()) 4570 AddCatchInfo(I, &MMI, CallMBB); 4571 else { 4572#ifndef NDEBUG 4573 FuncInfo.CatchInfoLost.insert(&I); 4574#endif 4575 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4576 unsigned Reg = TLI.getExceptionSelectorRegister(); 4577 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4578 } 4579 4580 // Insert the EHSELECTION instruction. 4581 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4582 SDValue Ops[2]; 4583 Ops[0] = getValue(I.getArgOperand(0)); 4584 Ops[1] = getRoot(); 4585 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4586 DAG.setRoot(Op.getValue(1)); 4587 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4588 return 0; 4589 } 4590 4591 case Intrinsic::eh_typeid_for: { 4592 // Find the type id for the given typeinfo. 4593 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4594 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4595 Res = DAG.getConstant(TypeID, MVT::i32); 4596 setValue(&I, Res); 4597 return 0; 4598 } 4599 4600 case Intrinsic::eh_return_i32: 4601 case Intrinsic::eh_return_i64: 4602 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4603 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4604 MVT::Other, 4605 getControlRoot(), 4606 getValue(I.getArgOperand(0)), 4607 getValue(I.getArgOperand(1)))); 4608 return 0; 4609 case Intrinsic::eh_unwind_init: 4610 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4611 return 0; 4612 case Intrinsic::eh_dwarf_cfa: { 4613 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4614 TLI.getPointerTy()); 4615 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4616 TLI.getPointerTy(), 4617 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4618 TLI.getPointerTy()), 4619 CfaArg); 4620 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4621 TLI.getPointerTy(), 4622 DAG.getConstant(0, TLI.getPointerTy())); 4623 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4624 FA, Offset)); 4625 return 0; 4626 } 4627 case Intrinsic::eh_sjlj_callsite: { 4628 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4629 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4630 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4631 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4632 4633 MMI.setCurrentCallSite(CI->getZExtValue()); 4634 return 0; 4635 } 4636 case Intrinsic::eh_sjlj_setjmp: { 4637 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4638 getValue(I.getArgOperand(0)))); 4639 return 0; 4640 } 4641 case Intrinsic::eh_sjlj_longjmp: { 4642 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4643 getRoot(), getValue(I.getArgOperand(0)))); 4644 return 0; 4645 } 4646 case Intrinsic::eh_sjlj_dispatch_setup: { 4647 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4648 getRoot(), getValue(I.getArgOperand(0)))); 4649 return 0; 4650 } 4651 4652 case Intrinsic::x86_mmx_pslli_w: 4653 case Intrinsic::x86_mmx_pslli_d: 4654 case Intrinsic::x86_mmx_pslli_q: 4655 case Intrinsic::x86_mmx_psrli_w: 4656 case Intrinsic::x86_mmx_psrli_d: 4657 case Intrinsic::x86_mmx_psrli_q: 4658 case Intrinsic::x86_mmx_psrai_w: 4659 case Intrinsic::x86_mmx_psrai_d: { 4660 SDValue ShAmt = getValue(I.getArgOperand(1)); 4661 if (isa<ConstantSDNode>(ShAmt)) { 4662 visitTargetIntrinsic(I, Intrinsic); 4663 return 0; 4664 } 4665 unsigned NewIntrinsic = 0; 4666 EVT ShAmtVT = MVT::v2i32; 4667 switch (Intrinsic) { 4668 case Intrinsic::x86_mmx_pslli_w: 4669 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4670 break; 4671 case Intrinsic::x86_mmx_pslli_d: 4672 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4673 break; 4674 case Intrinsic::x86_mmx_pslli_q: 4675 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4676 break; 4677 case Intrinsic::x86_mmx_psrli_w: 4678 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4679 break; 4680 case Intrinsic::x86_mmx_psrli_d: 4681 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4682 break; 4683 case Intrinsic::x86_mmx_psrli_q: 4684 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4685 break; 4686 case Intrinsic::x86_mmx_psrai_w: 4687 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4688 break; 4689 case Intrinsic::x86_mmx_psrai_d: 4690 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4691 break; 4692 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4693 } 4694 4695 // The vector shift intrinsics with scalars uses 32b shift amounts but 4696 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4697 // to be zero. 4698 // We must do this early because v2i32 is not a legal type. 4699 DebugLoc dl = getCurDebugLoc(); 4700 SDValue ShOps[2]; 4701 ShOps[0] = ShAmt; 4702 ShOps[1] = DAG.getConstant(0, MVT::i32); 4703 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4704 EVT DestVT = TLI.getValueType(I.getType()); 4705 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4706 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4707 DAG.getConstant(NewIntrinsic, MVT::i32), 4708 getValue(I.getArgOperand(0)), ShAmt); 4709 setValue(&I, Res); 4710 return 0; 4711 } 4712 case Intrinsic::convertff: 4713 case Intrinsic::convertfsi: 4714 case Intrinsic::convertfui: 4715 case Intrinsic::convertsif: 4716 case Intrinsic::convertuif: 4717 case Intrinsic::convertss: 4718 case Intrinsic::convertsu: 4719 case Intrinsic::convertus: 4720 case Intrinsic::convertuu: { 4721 ISD::CvtCode Code = ISD::CVT_INVALID; 4722 switch (Intrinsic) { 4723 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4724 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4725 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4726 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4727 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4728 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4729 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4730 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4731 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4732 } 4733 EVT DestVT = TLI.getValueType(I.getType()); 4734 const Value *Op1 = I.getArgOperand(0); 4735 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4736 DAG.getValueType(DestVT), 4737 DAG.getValueType(getValue(Op1).getValueType()), 4738 getValue(I.getArgOperand(1)), 4739 getValue(I.getArgOperand(2)), 4740 Code); 4741 setValue(&I, Res); 4742 return 0; 4743 } 4744 case Intrinsic::sqrt: 4745 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4746 getValue(I.getArgOperand(0)).getValueType(), 4747 getValue(I.getArgOperand(0)))); 4748 return 0; 4749 case Intrinsic::powi: 4750 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4751 getValue(I.getArgOperand(1)), DAG)); 4752 return 0; 4753 case Intrinsic::sin: 4754 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4755 getValue(I.getArgOperand(0)).getValueType(), 4756 getValue(I.getArgOperand(0)))); 4757 return 0; 4758 case Intrinsic::cos: 4759 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4760 getValue(I.getArgOperand(0)).getValueType(), 4761 getValue(I.getArgOperand(0)))); 4762 return 0; 4763 case Intrinsic::log: 4764 visitLog(I); 4765 return 0; 4766 case Intrinsic::log2: 4767 visitLog2(I); 4768 return 0; 4769 case Intrinsic::log10: 4770 visitLog10(I); 4771 return 0; 4772 case Intrinsic::exp: 4773 visitExp(I); 4774 return 0; 4775 case Intrinsic::exp2: 4776 visitExp2(I); 4777 return 0; 4778 case Intrinsic::pow: 4779 visitPow(I); 4780 return 0; 4781 case Intrinsic::fma: 4782 setValue(&I, DAG.getNode(ISD::FMA, dl, 4783 getValue(I.getArgOperand(0)).getValueType(), 4784 getValue(I.getArgOperand(0)), 4785 getValue(I.getArgOperand(1)), 4786 getValue(I.getArgOperand(2)))); 4787 return 0; 4788 case Intrinsic::convert_to_fp16: 4789 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4790 MVT::i16, getValue(I.getArgOperand(0)))); 4791 return 0; 4792 case Intrinsic::convert_from_fp16: 4793 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4794 MVT::f32, getValue(I.getArgOperand(0)))); 4795 return 0; 4796 case Intrinsic::pcmarker: { 4797 SDValue Tmp = getValue(I.getArgOperand(0)); 4798 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4799 return 0; 4800 } 4801 case Intrinsic::readcyclecounter: { 4802 SDValue Op = getRoot(); 4803 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4804 DAG.getVTList(MVT::i64, MVT::Other), 4805 &Op, 1); 4806 setValue(&I, Res); 4807 DAG.setRoot(Res.getValue(1)); 4808 return 0; 4809 } 4810 case Intrinsic::bswap: 4811 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4812 getValue(I.getArgOperand(0)).getValueType(), 4813 getValue(I.getArgOperand(0)))); 4814 return 0; 4815 case Intrinsic::cttz: { 4816 SDValue Arg = getValue(I.getArgOperand(0)); 4817 EVT Ty = Arg.getValueType(); 4818 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4819 return 0; 4820 } 4821 case Intrinsic::ctlz: { 4822 SDValue Arg = getValue(I.getArgOperand(0)); 4823 EVT Ty = Arg.getValueType(); 4824 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4825 return 0; 4826 } 4827 case Intrinsic::ctpop: { 4828 SDValue Arg = getValue(I.getArgOperand(0)); 4829 EVT Ty = Arg.getValueType(); 4830 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4831 return 0; 4832 } 4833 case Intrinsic::stacksave: { 4834 SDValue Op = getRoot(); 4835 Res = DAG.getNode(ISD::STACKSAVE, dl, 4836 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4837 setValue(&I, Res); 4838 DAG.setRoot(Res.getValue(1)); 4839 return 0; 4840 } 4841 case Intrinsic::stackrestore: { 4842 Res = getValue(I.getArgOperand(0)); 4843 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4844 return 0; 4845 } 4846 case Intrinsic::stackprotector: { 4847 // Emit code into the DAG to store the stack guard onto the stack. 4848 MachineFunction &MF = DAG.getMachineFunction(); 4849 MachineFrameInfo *MFI = MF.getFrameInfo(); 4850 EVT PtrTy = TLI.getPointerTy(); 4851 4852 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4853 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4854 4855 int FI = FuncInfo.StaticAllocaMap[Slot]; 4856 MFI->setStackProtectorIndex(FI); 4857 4858 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4859 4860 // Store the stack protector onto the stack. 4861 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4862 MachinePointerInfo::getFixedStack(FI), 4863 true, false, 0); 4864 setValue(&I, Res); 4865 DAG.setRoot(Res); 4866 return 0; 4867 } 4868 case Intrinsic::objectsize: { 4869 // If we don't know by now, we're never going to know. 4870 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4871 4872 assert(CI && "Non-constant type in __builtin_object_size?"); 4873 4874 SDValue Arg = getValue(I.getCalledValue()); 4875 EVT Ty = Arg.getValueType(); 4876 4877 if (CI->isZero()) 4878 Res = DAG.getConstant(-1ULL, Ty); 4879 else 4880 Res = DAG.getConstant(0, Ty); 4881 4882 setValue(&I, Res); 4883 return 0; 4884 } 4885 case Intrinsic::var_annotation: 4886 // Discard annotate attributes 4887 return 0; 4888 4889 case Intrinsic::init_trampoline: { 4890 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4891 4892 SDValue Ops[6]; 4893 Ops[0] = getRoot(); 4894 Ops[1] = getValue(I.getArgOperand(0)); 4895 Ops[2] = getValue(I.getArgOperand(1)); 4896 Ops[3] = getValue(I.getArgOperand(2)); 4897 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4898 Ops[5] = DAG.getSrcValue(F); 4899 4900 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4901 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4902 Ops, 6); 4903 4904 setValue(&I, Res); 4905 DAG.setRoot(Res.getValue(1)); 4906 return 0; 4907 } 4908 case Intrinsic::gcroot: 4909 if (GFI) { 4910 const Value *Alloca = I.getArgOperand(0); 4911 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4912 4913 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4914 GFI->addStackRoot(FI->getIndex(), TypeMap); 4915 } 4916 return 0; 4917 case Intrinsic::gcread: 4918 case Intrinsic::gcwrite: 4919 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4920 return 0; 4921 case Intrinsic::flt_rounds: 4922 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4923 return 0; 4924 4925 case Intrinsic::expect: { 4926 // Just replace __builtin_expect(exp, c) with EXP. 4927 setValue(&I, getValue(I.getArgOperand(0))); 4928 return 0; 4929 } 4930 4931 case Intrinsic::trap: { 4932 StringRef TrapFuncName = getTrapFunctionName(); 4933 if (TrapFuncName.empty()) { 4934 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4935 return 0; 4936 } 4937 TargetLowering::ArgListTy Args; 4938 std::pair<SDValue, SDValue> Result = 4939 TLI.LowerCallTo(getRoot(), I.getType(), 4940 false, false, false, false, 0, CallingConv::C, 4941 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 4942 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 4943 Args, DAG, getCurDebugLoc()); 4944 DAG.setRoot(Result.second); 4945 return 0; 4946 } 4947 case Intrinsic::uadd_with_overflow: 4948 return implVisitAluOverflow(I, ISD::UADDO); 4949 case Intrinsic::sadd_with_overflow: 4950 return implVisitAluOverflow(I, ISD::SADDO); 4951 case Intrinsic::usub_with_overflow: 4952 return implVisitAluOverflow(I, ISD::USUBO); 4953 case Intrinsic::ssub_with_overflow: 4954 return implVisitAluOverflow(I, ISD::SSUBO); 4955 case Intrinsic::umul_with_overflow: 4956 return implVisitAluOverflow(I, ISD::UMULO); 4957 case Intrinsic::smul_with_overflow: 4958 return implVisitAluOverflow(I, ISD::SMULO); 4959 4960 case Intrinsic::prefetch: { 4961 SDValue Ops[5]; 4962 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 4963 Ops[0] = getRoot(); 4964 Ops[1] = getValue(I.getArgOperand(0)); 4965 Ops[2] = getValue(I.getArgOperand(1)); 4966 Ops[3] = getValue(I.getArgOperand(2)); 4967 Ops[4] = getValue(I.getArgOperand(3)); 4968 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 4969 DAG.getVTList(MVT::Other), 4970 &Ops[0], 5, 4971 EVT::getIntegerVT(*Context, 8), 4972 MachinePointerInfo(I.getArgOperand(0)), 4973 0, /* align */ 4974 false, /* volatile */ 4975 rw==0, /* read */ 4976 rw==1)); /* write */ 4977 return 0; 4978 } 4979 case Intrinsic::memory_barrier: { 4980 SDValue Ops[6]; 4981 Ops[0] = getRoot(); 4982 for (int x = 1; x < 6; ++x) 4983 Ops[x] = getValue(I.getArgOperand(x - 1)); 4984 4985 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4986 return 0; 4987 } 4988 case Intrinsic::atomic_cmp_swap: { 4989 SDValue Root = getRoot(); 4990 SDValue L = 4991 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4992 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4993 Root, 4994 getValue(I.getArgOperand(0)), 4995 getValue(I.getArgOperand(1)), 4996 getValue(I.getArgOperand(2)), 4997 MachinePointerInfo(I.getArgOperand(0)), 0 /* Alignment */, 4998 Monotonic, CrossThread); 4999 setValue(&I, L); 5000 DAG.setRoot(L.getValue(1)); 5001 return 0; 5002 } 5003 case Intrinsic::atomic_load_add: 5004 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 5005 case Intrinsic::atomic_load_sub: 5006 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 5007 case Intrinsic::atomic_load_or: 5008 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 5009 case Intrinsic::atomic_load_xor: 5010 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 5011 case Intrinsic::atomic_load_and: 5012 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 5013 case Intrinsic::atomic_load_nand: 5014 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 5015 case Intrinsic::atomic_load_max: 5016 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 5017 case Intrinsic::atomic_load_min: 5018 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 5019 case Intrinsic::atomic_load_umin: 5020 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 5021 case Intrinsic::atomic_load_umax: 5022 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 5023 case Intrinsic::atomic_swap: 5024 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 5025 5026 case Intrinsic::invariant_start: 5027 case Intrinsic::lifetime_start: 5028 // Discard region information. 5029 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5030 return 0; 5031 case Intrinsic::invariant_end: 5032 case Intrinsic::lifetime_end: 5033 // Discard region information. 5034 return 0; 5035 } 5036} 5037 5038void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5039 bool isTailCall, 5040 MachineBasicBlock *LandingPad) { 5041 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5042 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5043 Type *RetTy = FTy->getReturnType(); 5044 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5045 MCSymbol *BeginLabel = 0; 5046 5047 TargetLowering::ArgListTy Args; 5048 TargetLowering::ArgListEntry Entry; 5049 Args.reserve(CS.arg_size()); 5050 5051 // Check whether the function can return without sret-demotion. 5052 SmallVector<ISD::OutputArg, 4> Outs; 5053 SmallVector<uint64_t, 4> Offsets; 5054 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5055 Outs, TLI, &Offsets); 5056 5057 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5058 DAG.getMachineFunction(), 5059 FTy->isVarArg(), Outs, 5060 FTy->getContext()); 5061 5062 SDValue DemoteStackSlot; 5063 int DemoteStackIdx = -100; 5064 5065 if (!CanLowerReturn) { 5066 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5067 FTy->getReturnType()); 5068 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5069 FTy->getReturnType()); 5070 MachineFunction &MF = DAG.getMachineFunction(); 5071 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5072 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5073 5074 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5075 Entry.Node = DemoteStackSlot; 5076 Entry.Ty = StackSlotPtrType; 5077 Entry.isSExt = false; 5078 Entry.isZExt = false; 5079 Entry.isInReg = false; 5080 Entry.isSRet = true; 5081 Entry.isNest = false; 5082 Entry.isByVal = false; 5083 Entry.Alignment = Align; 5084 Args.push_back(Entry); 5085 RetTy = Type::getVoidTy(FTy->getContext()); 5086 } 5087 5088 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5089 i != e; ++i) { 5090 const Value *V = *i; 5091 5092 // Skip empty types 5093 if (V->getType()->isEmptyTy()) 5094 continue; 5095 5096 SDValue ArgNode = getValue(V); 5097 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5098 5099 unsigned attrInd = i - CS.arg_begin() + 1; 5100 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5101 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5102 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5103 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5104 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5105 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5106 Entry.Alignment = CS.getParamAlignment(attrInd); 5107 Args.push_back(Entry); 5108 } 5109 5110 if (LandingPad) { 5111 // Insert a label before the invoke call to mark the try range. This can be 5112 // used to detect deletion of the invoke via the MachineModuleInfo. 5113 BeginLabel = MMI.getContext().CreateTempSymbol(); 5114 5115 // For SjLj, keep track of which landing pads go with which invokes 5116 // so as to maintain the ordering of pads in the LSDA. 5117 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5118 if (CallSiteIndex) { 5119 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5120 // Now that the call site is handled, stop tracking it. 5121 MMI.setCurrentCallSite(0); 5122 } 5123 5124 // Both PendingLoads and PendingExports must be flushed here; 5125 // this call might not return. 5126 (void)getRoot(); 5127 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5128 } 5129 5130 // Check if target-independent constraints permit a tail call here. 5131 // Target-dependent constraints are checked within TLI.LowerCallTo. 5132 if (isTailCall && 5133 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5134 isTailCall = false; 5135 5136 // If there's a possibility that fast-isel has already selected some amount 5137 // of the current basic block, don't emit a tail call. 5138 if (isTailCall && EnableFastISel) 5139 isTailCall = false; 5140 5141 std::pair<SDValue,SDValue> Result = 5142 TLI.LowerCallTo(getRoot(), RetTy, 5143 CS.paramHasAttr(0, Attribute::SExt), 5144 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5145 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5146 CS.getCallingConv(), 5147 isTailCall, 5148 !CS.getInstruction()->use_empty(), 5149 Callee, Args, DAG, getCurDebugLoc()); 5150 assert((isTailCall || Result.second.getNode()) && 5151 "Non-null chain expected with non-tail call!"); 5152 assert((Result.second.getNode() || !Result.first.getNode()) && 5153 "Null value expected with tail call!"); 5154 if (Result.first.getNode()) { 5155 setValue(CS.getInstruction(), Result.first); 5156 } else if (!CanLowerReturn && Result.second.getNode()) { 5157 // The instruction result is the result of loading from the 5158 // hidden sret parameter. 5159 SmallVector<EVT, 1> PVTs; 5160 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5161 5162 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5163 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5164 EVT PtrVT = PVTs[0]; 5165 unsigned NumValues = Outs.size(); 5166 SmallVector<SDValue, 4> Values(NumValues); 5167 SmallVector<SDValue, 4> Chains(NumValues); 5168 5169 for (unsigned i = 0; i < NumValues; ++i) { 5170 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5171 DemoteStackSlot, 5172 DAG.getConstant(Offsets[i], PtrVT)); 5173 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5174 Add, 5175 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5176 false, false, 1); 5177 Values[i] = L; 5178 Chains[i] = L.getValue(1); 5179 } 5180 5181 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5182 MVT::Other, &Chains[0], NumValues); 5183 PendingLoads.push_back(Chain); 5184 5185 // Collect the legal value parts into potentially illegal values 5186 // that correspond to the original function's return values. 5187 SmallVector<EVT, 4> RetTys; 5188 RetTy = FTy->getReturnType(); 5189 ComputeValueVTs(TLI, RetTy, RetTys); 5190 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5191 SmallVector<SDValue, 4> ReturnValues; 5192 unsigned CurReg = 0; 5193 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5194 EVT VT = RetTys[I]; 5195 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5196 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5197 5198 SDValue ReturnValue = 5199 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5200 RegisterVT, VT, AssertOp); 5201 ReturnValues.push_back(ReturnValue); 5202 CurReg += NumRegs; 5203 } 5204 5205 setValue(CS.getInstruction(), 5206 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5207 DAG.getVTList(&RetTys[0], RetTys.size()), 5208 &ReturnValues[0], ReturnValues.size())); 5209 } 5210 5211 // Assign order to nodes here. If the call does not produce a result, it won't 5212 // be mapped to a SDNode and visit() will not assign it an order number. 5213 if (!Result.second.getNode()) { 5214 // As a special case, a null chain means that a tail call has been emitted and 5215 // the DAG root is already updated. 5216 HasTailCall = true; 5217 ++SDNodeOrder; 5218 AssignOrderingToNode(DAG.getRoot().getNode()); 5219 } else { 5220 DAG.setRoot(Result.second); 5221 ++SDNodeOrder; 5222 AssignOrderingToNode(Result.second.getNode()); 5223 } 5224 5225 if (LandingPad) { 5226 // Insert a label at the end of the invoke call to mark the try range. This 5227 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5228 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5229 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5230 5231 // Inform MachineModuleInfo of range. 5232 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5233 } 5234} 5235 5236/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5237/// value is equal or not-equal to zero. 5238static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5239 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5240 UI != E; ++UI) { 5241 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5242 if (IC->isEquality()) 5243 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5244 if (C->isNullValue()) 5245 continue; 5246 // Unknown instruction. 5247 return false; 5248 } 5249 return true; 5250} 5251 5252static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5253 Type *LoadTy, 5254 SelectionDAGBuilder &Builder) { 5255 5256 // Check to see if this load can be trivially constant folded, e.g. if the 5257 // input is from a string literal. 5258 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5259 // Cast pointer to the type we really want to load. 5260 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5261 PointerType::getUnqual(LoadTy)); 5262 5263 if (const Constant *LoadCst = 5264 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5265 Builder.TD)) 5266 return Builder.getValue(LoadCst); 5267 } 5268 5269 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5270 // still constant memory, the input chain can be the entry node. 5271 SDValue Root; 5272 bool ConstantMemory = false; 5273 5274 // Do not serialize (non-volatile) loads of constant memory with anything. 5275 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5276 Root = Builder.DAG.getEntryNode(); 5277 ConstantMemory = true; 5278 } else { 5279 // Do not serialize non-volatile loads against each other. 5280 Root = Builder.DAG.getRoot(); 5281 } 5282 5283 SDValue Ptr = Builder.getValue(PtrVal); 5284 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5285 Ptr, MachinePointerInfo(PtrVal), 5286 false /*volatile*/, 5287 false /*nontemporal*/, 1 /* align=1 */); 5288 5289 if (!ConstantMemory) 5290 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5291 return LoadVal; 5292} 5293 5294 5295/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5296/// If so, return true and lower it, otherwise return false and it will be 5297/// lowered like a normal call. 5298bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5299 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5300 if (I.getNumArgOperands() != 3) 5301 return false; 5302 5303 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5304 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5305 !I.getArgOperand(2)->getType()->isIntegerTy() || 5306 !I.getType()->isIntegerTy()) 5307 return false; 5308 5309 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5310 5311 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5312 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5313 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5314 bool ActuallyDoIt = true; 5315 MVT LoadVT; 5316 Type *LoadTy; 5317 switch (Size->getZExtValue()) { 5318 default: 5319 LoadVT = MVT::Other; 5320 LoadTy = 0; 5321 ActuallyDoIt = false; 5322 break; 5323 case 2: 5324 LoadVT = MVT::i16; 5325 LoadTy = Type::getInt16Ty(Size->getContext()); 5326 break; 5327 case 4: 5328 LoadVT = MVT::i32; 5329 LoadTy = Type::getInt32Ty(Size->getContext()); 5330 break; 5331 case 8: 5332 LoadVT = MVT::i64; 5333 LoadTy = Type::getInt64Ty(Size->getContext()); 5334 break; 5335 /* 5336 case 16: 5337 LoadVT = MVT::v4i32; 5338 LoadTy = Type::getInt32Ty(Size->getContext()); 5339 LoadTy = VectorType::get(LoadTy, 4); 5340 break; 5341 */ 5342 } 5343 5344 // This turns into unaligned loads. We only do this if the target natively 5345 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5346 // we'll only produce a small number of byte loads. 5347 5348 // Require that we can find a legal MVT, and only do this if the target 5349 // supports unaligned loads of that type. Expanding into byte loads would 5350 // bloat the code. 5351 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5352 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5353 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5354 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5355 ActuallyDoIt = false; 5356 } 5357 5358 if (ActuallyDoIt) { 5359 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5360 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5361 5362 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5363 ISD::SETNE); 5364 EVT CallVT = TLI.getValueType(I.getType(), true); 5365 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5366 return true; 5367 } 5368 } 5369 5370 5371 return false; 5372} 5373 5374 5375void SelectionDAGBuilder::visitCall(const CallInst &I) { 5376 // Handle inline assembly differently. 5377 if (isa<InlineAsm>(I.getCalledValue())) { 5378 visitInlineAsm(&I); 5379 return; 5380 } 5381 5382 // See if any floating point values are being passed to this function. This is 5383 // used to emit an undefined reference to fltused on Windows. 5384 FunctionType *FT = 5385 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5386 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5387 if (FT->isVarArg() && 5388 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5389 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5390 Type* T = I.getArgOperand(i)->getType(); 5391 for (po_iterator<Type*> i = po_begin(T), e = po_end(T); 5392 i != e; ++i) { 5393 if (!i->isFloatingPointTy()) continue; 5394 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5395 break; 5396 } 5397 } 5398 } 5399 5400 const char *RenameFn = 0; 5401 if (Function *F = I.getCalledFunction()) { 5402 if (F->isDeclaration()) { 5403 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5404 if (unsigned IID = II->getIntrinsicID(F)) { 5405 RenameFn = visitIntrinsicCall(I, IID); 5406 if (!RenameFn) 5407 return; 5408 } 5409 } 5410 if (unsigned IID = F->getIntrinsicID()) { 5411 RenameFn = visitIntrinsicCall(I, IID); 5412 if (!RenameFn) 5413 return; 5414 } 5415 } 5416 5417 // Check for well-known libc/libm calls. If the function is internal, it 5418 // can't be a library call. 5419 if (!F->hasLocalLinkage() && F->hasName()) { 5420 StringRef Name = F->getName(); 5421 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5422 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5423 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5424 I.getType() == I.getArgOperand(0)->getType() && 5425 I.getType() == I.getArgOperand(1)->getType()) { 5426 SDValue LHS = getValue(I.getArgOperand(0)); 5427 SDValue RHS = getValue(I.getArgOperand(1)); 5428 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5429 LHS.getValueType(), LHS, RHS)); 5430 return; 5431 } 5432 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5433 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5434 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5435 I.getType() == I.getArgOperand(0)->getType()) { 5436 SDValue Tmp = getValue(I.getArgOperand(0)); 5437 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5438 Tmp.getValueType(), Tmp)); 5439 return; 5440 } 5441 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5442 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5443 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5444 I.getType() == I.getArgOperand(0)->getType() && 5445 I.onlyReadsMemory()) { 5446 SDValue Tmp = getValue(I.getArgOperand(0)); 5447 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5448 Tmp.getValueType(), Tmp)); 5449 return; 5450 } 5451 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5452 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5453 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5454 I.getType() == I.getArgOperand(0)->getType() && 5455 I.onlyReadsMemory()) { 5456 SDValue Tmp = getValue(I.getArgOperand(0)); 5457 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5458 Tmp.getValueType(), Tmp)); 5459 return; 5460 } 5461 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5462 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5463 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5464 I.getType() == I.getArgOperand(0)->getType() && 5465 I.onlyReadsMemory()) { 5466 SDValue Tmp = getValue(I.getArgOperand(0)); 5467 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5468 Tmp.getValueType(), Tmp)); 5469 return; 5470 } 5471 } else if (Name == "memcmp") { 5472 if (visitMemCmpCall(I)) 5473 return; 5474 } 5475 } 5476 } 5477 5478 SDValue Callee; 5479 if (!RenameFn) 5480 Callee = getValue(I.getCalledValue()); 5481 else 5482 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5483 5484 // Check if we can potentially perform a tail call. More detailed checking is 5485 // be done within LowerCallTo, after more information about the call is known. 5486 LowerCallTo(&I, Callee, I.isTailCall()); 5487} 5488 5489namespace { 5490 5491/// AsmOperandInfo - This contains information for each constraint that we are 5492/// lowering. 5493class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5494public: 5495 /// CallOperand - If this is the result output operand or a clobber 5496 /// this is null, otherwise it is the incoming operand to the CallInst. 5497 /// This gets modified as the asm is processed. 5498 SDValue CallOperand; 5499 5500 /// AssignedRegs - If this is a register or register class operand, this 5501 /// contains the set of register corresponding to the operand. 5502 RegsForValue AssignedRegs; 5503 5504 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5505 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5506 } 5507 5508 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5509 /// busy in OutputRegs/InputRegs. 5510 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5511 std::set<unsigned> &OutputRegs, 5512 std::set<unsigned> &InputRegs, 5513 const TargetRegisterInfo &TRI) const { 5514 if (isOutReg) { 5515 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5516 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5517 } 5518 if (isInReg) { 5519 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5520 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5521 } 5522 } 5523 5524 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5525 /// corresponds to. If there is no Value* for this operand, it returns 5526 /// MVT::Other. 5527 EVT getCallOperandValEVT(LLVMContext &Context, 5528 const TargetLowering &TLI, 5529 const TargetData *TD) const { 5530 if (CallOperandVal == 0) return MVT::Other; 5531 5532 if (isa<BasicBlock>(CallOperandVal)) 5533 return TLI.getPointerTy(); 5534 5535 llvm::Type *OpTy = CallOperandVal->getType(); 5536 5537 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5538 // If this is an indirect operand, the operand is a pointer to the 5539 // accessed type. 5540 if (isIndirect) { 5541 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5542 if (!PtrTy) 5543 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5544 OpTy = PtrTy->getElementType(); 5545 } 5546 5547 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5548 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5549 if (STy->getNumElements() == 1) 5550 OpTy = STy->getElementType(0); 5551 5552 // If OpTy is not a single value, it may be a struct/union that we 5553 // can tile with integers. 5554 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5555 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5556 switch (BitSize) { 5557 default: break; 5558 case 1: 5559 case 8: 5560 case 16: 5561 case 32: 5562 case 64: 5563 case 128: 5564 OpTy = IntegerType::get(Context, BitSize); 5565 break; 5566 } 5567 } 5568 5569 return TLI.getValueType(OpTy, true); 5570 } 5571 5572private: 5573 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5574 /// specified set. 5575 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5576 const TargetRegisterInfo &TRI) { 5577 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5578 Regs.insert(Reg); 5579 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5580 for (; *Aliases; ++Aliases) 5581 Regs.insert(*Aliases); 5582 } 5583}; 5584 5585typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5586 5587} // end anonymous namespace 5588 5589/// GetRegistersForValue - Assign registers (virtual or physical) for the 5590/// specified operand. We prefer to assign virtual registers, to allow the 5591/// register allocator to handle the assignment process. However, if the asm 5592/// uses features that we can't model on machineinstrs, we have SDISel do the 5593/// allocation. This produces generally horrible, but correct, code. 5594/// 5595/// OpInfo describes the operand. 5596/// Input and OutputRegs are the set of already allocated physical registers. 5597/// 5598static void GetRegistersForValue(SelectionDAG &DAG, 5599 const TargetLowering &TLI, 5600 DebugLoc DL, 5601 SDISelAsmOperandInfo &OpInfo, 5602 std::set<unsigned> &OutputRegs, 5603 std::set<unsigned> &InputRegs) { 5604 LLVMContext &Context = *DAG.getContext(); 5605 5606 // Compute whether this value requires an input register, an output register, 5607 // or both. 5608 bool isOutReg = false; 5609 bool isInReg = false; 5610 switch (OpInfo.Type) { 5611 case InlineAsm::isOutput: 5612 isOutReg = true; 5613 5614 // If there is an input constraint that matches this, we need to reserve 5615 // the input register so no other inputs allocate to it. 5616 isInReg = OpInfo.hasMatchingInput(); 5617 break; 5618 case InlineAsm::isInput: 5619 isInReg = true; 5620 isOutReg = false; 5621 break; 5622 case InlineAsm::isClobber: 5623 isOutReg = true; 5624 isInReg = true; 5625 break; 5626 } 5627 5628 5629 MachineFunction &MF = DAG.getMachineFunction(); 5630 SmallVector<unsigned, 4> Regs; 5631 5632 // If this is a constraint for a single physreg, or a constraint for a 5633 // register class, find it. 5634 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5635 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5636 OpInfo.ConstraintVT); 5637 5638 unsigned NumRegs = 1; 5639 if (OpInfo.ConstraintVT != MVT::Other) { 5640 // If this is a FP input in an integer register (or visa versa) insert a bit 5641 // cast of the input value. More generally, handle any case where the input 5642 // value disagrees with the register class we plan to stick this in. 5643 if (OpInfo.Type == InlineAsm::isInput && 5644 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5645 // Try to convert to the first EVT that the reg class contains. If the 5646 // types are identical size, use a bitcast to convert (e.g. two differing 5647 // vector types). 5648 EVT RegVT = *PhysReg.second->vt_begin(); 5649 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5650 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5651 RegVT, OpInfo.CallOperand); 5652 OpInfo.ConstraintVT = RegVT; 5653 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5654 // If the input is a FP value and we want it in FP registers, do a 5655 // bitcast to the corresponding integer type. This turns an f64 value 5656 // into i64, which can be passed with two i32 values on a 32-bit 5657 // machine. 5658 RegVT = EVT::getIntegerVT(Context, 5659 OpInfo.ConstraintVT.getSizeInBits()); 5660 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5661 RegVT, OpInfo.CallOperand); 5662 OpInfo.ConstraintVT = RegVT; 5663 } 5664 } 5665 5666 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5667 } 5668 5669 EVT RegVT; 5670 EVT ValueVT = OpInfo.ConstraintVT; 5671 5672 // If this is a constraint for a specific physical register, like {r17}, 5673 // assign it now. 5674 if (unsigned AssignedReg = PhysReg.first) { 5675 const TargetRegisterClass *RC = PhysReg.second; 5676 if (OpInfo.ConstraintVT == MVT::Other) 5677 ValueVT = *RC->vt_begin(); 5678 5679 // Get the actual register value type. This is important, because the user 5680 // may have asked for (e.g.) the AX register in i32 type. We need to 5681 // remember that AX is actually i16 to get the right extension. 5682 RegVT = *RC->vt_begin(); 5683 5684 // This is a explicit reference to a physical register. 5685 Regs.push_back(AssignedReg); 5686 5687 // If this is an expanded reference, add the rest of the regs to Regs. 5688 if (NumRegs != 1) { 5689 TargetRegisterClass::iterator I = RC->begin(); 5690 for (; *I != AssignedReg; ++I) 5691 assert(I != RC->end() && "Didn't find reg!"); 5692 5693 // Already added the first reg. 5694 --NumRegs; ++I; 5695 for (; NumRegs; --NumRegs, ++I) { 5696 assert(I != RC->end() && "Ran out of registers to allocate!"); 5697 Regs.push_back(*I); 5698 } 5699 } 5700 5701 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5702 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5703 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5704 return; 5705 } 5706 5707 // Otherwise, if this was a reference to an LLVM register class, create vregs 5708 // for this reference. 5709 if (const TargetRegisterClass *RC = PhysReg.second) { 5710 RegVT = *RC->vt_begin(); 5711 if (OpInfo.ConstraintVT == MVT::Other) 5712 ValueVT = RegVT; 5713 5714 // Create the appropriate number of virtual registers. 5715 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5716 for (; NumRegs; --NumRegs) 5717 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5718 5719 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5720 return; 5721 } 5722 5723 // Otherwise, we couldn't allocate enough registers for this. 5724} 5725 5726/// visitInlineAsm - Handle a call to an InlineAsm object. 5727/// 5728void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5729 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5730 5731 /// ConstraintOperands - Information about all of the constraints. 5732 SDISelAsmOperandInfoVector ConstraintOperands; 5733 5734 std::set<unsigned> OutputRegs, InputRegs; 5735 5736 TargetLowering::AsmOperandInfoVector 5737 TargetConstraints = TLI.ParseConstraints(CS); 5738 5739 bool hasMemory = false; 5740 5741 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5742 unsigned ResNo = 0; // ResNo - The result number of the next output. 5743 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5744 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5745 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5746 5747 EVT OpVT = MVT::Other; 5748 5749 // Compute the value type for each operand. 5750 switch (OpInfo.Type) { 5751 case InlineAsm::isOutput: 5752 // Indirect outputs just consume an argument. 5753 if (OpInfo.isIndirect) { 5754 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5755 break; 5756 } 5757 5758 // The return value of the call is this value. As such, there is no 5759 // corresponding argument. 5760 assert(!CS.getType()->isVoidTy() && 5761 "Bad inline asm!"); 5762 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5763 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5764 } else { 5765 assert(ResNo == 0 && "Asm only has one result!"); 5766 OpVT = TLI.getValueType(CS.getType()); 5767 } 5768 ++ResNo; 5769 break; 5770 case InlineAsm::isInput: 5771 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5772 break; 5773 case InlineAsm::isClobber: 5774 // Nothing to do. 5775 break; 5776 } 5777 5778 // If this is an input or an indirect output, process the call argument. 5779 // BasicBlocks are labels, currently appearing only in asm's. 5780 if (OpInfo.CallOperandVal) { 5781 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5782 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5783 } else { 5784 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5785 } 5786 5787 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5788 } 5789 5790 OpInfo.ConstraintVT = OpVT; 5791 5792 // Indirect operand accesses access memory. 5793 if (OpInfo.isIndirect) 5794 hasMemory = true; 5795 else { 5796 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5797 TargetLowering::ConstraintType 5798 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5799 if (CType == TargetLowering::C_Memory) { 5800 hasMemory = true; 5801 break; 5802 } 5803 } 5804 } 5805 } 5806 5807 SDValue Chain, Flag; 5808 5809 // We won't need to flush pending loads if this asm doesn't touch 5810 // memory and is nonvolatile. 5811 if (hasMemory || IA->hasSideEffects()) 5812 Chain = getRoot(); 5813 else 5814 Chain = DAG.getRoot(); 5815 5816 // Second pass over the constraints: compute which constraint option to use 5817 // and assign registers to constraints that want a specific physreg. 5818 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5819 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5820 5821 // If this is an output operand with a matching input operand, look up the 5822 // matching input. If their types mismatch, e.g. one is an integer, the 5823 // other is floating point, or their sizes are different, flag it as an 5824 // error. 5825 if (OpInfo.hasMatchingInput()) { 5826 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5827 5828 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5829 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5830 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); 5831 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5832 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT); 5833 if ((OpInfo.ConstraintVT.isInteger() != 5834 Input.ConstraintVT.isInteger()) || 5835 (MatchRC.second != InputRC.second)) { 5836 report_fatal_error("Unsupported asm: input constraint" 5837 " with a matching output constraint of" 5838 " incompatible type!"); 5839 } 5840 Input.ConstraintVT = OpInfo.ConstraintVT; 5841 } 5842 } 5843 5844 // Compute the constraint code and ConstraintType to use. 5845 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5846 5847 // If this is a memory input, and if the operand is not indirect, do what we 5848 // need to to provide an address for the memory input. 5849 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5850 !OpInfo.isIndirect) { 5851 assert((OpInfo.isMultipleAlternative || 5852 (OpInfo.Type == InlineAsm::isInput)) && 5853 "Can only indirectify direct input operands!"); 5854 5855 // Memory operands really want the address of the value. If we don't have 5856 // an indirect input, put it in the constpool if we can, otherwise spill 5857 // it to a stack slot. 5858 // TODO: This isn't quite right. We need to handle these according to 5859 // the addressing mode that the constraint wants. Also, this may take 5860 // an additional register for the computation and we don't want that 5861 // either. 5862 5863 // If the operand is a float, integer, or vector constant, spill to a 5864 // constant pool entry to get its address. 5865 const Value *OpVal = OpInfo.CallOperandVal; 5866 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5867 isa<ConstantVector>(OpVal)) { 5868 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5869 TLI.getPointerTy()); 5870 } else { 5871 // Otherwise, create a stack slot and emit a store to it before the 5872 // asm. 5873 Type *Ty = OpVal->getType(); 5874 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5875 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5876 MachineFunction &MF = DAG.getMachineFunction(); 5877 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5878 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5879 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5880 OpInfo.CallOperand, StackSlot, 5881 MachinePointerInfo::getFixedStack(SSFI), 5882 false, false, 0); 5883 OpInfo.CallOperand = StackSlot; 5884 } 5885 5886 // There is no longer a Value* corresponding to this operand. 5887 OpInfo.CallOperandVal = 0; 5888 5889 // It is now an indirect operand. 5890 OpInfo.isIndirect = true; 5891 } 5892 5893 // If this constraint is for a specific register, allocate it before 5894 // anything else. 5895 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5896 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5897 InputRegs); 5898 } 5899 5900 // Second pass - Loop over all of the operands, assigning virtual or physregs 5901 // to register class operands. 5902 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5903 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5904 5905 // C_Register operands have already been allocated, Other/Memory don't need 5906 // to be. 5907 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5908 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5909 InputRegs); 5910 } 5911 5912 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5913 std::vector<SDValue> AsmNodeOperands; 5914 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5915 AsmNodeOperands.push_back( 5916 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5917 TLI.getPointerTy())); 5918 5919 // If we have a !srcloc metadata node associated with it, we want to attach 5920 // this to the ultimately generated inline asm machineinstr. To do this, we 5921 // pass in the third operand as this (potentially null) inline asm MDNode. 5922 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5923 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5924 5925 // Remember the HasSideEffect and AlignStack bits as operand 3. 5926 unsigned ExtraInfo = 0; 5927 if (IA->hasSideEffects()) 5928 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 5929 if (IA->isAlignStack()) 5930 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 5931 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 5932 TLI.getPointerTy())); 5933 5934 // Loop over all of the inputs, copying the operand values into the 5935 // appropriate registers and processing the output regs. 5936 RegsForValue RetValRegs; 5937 5938 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5939 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5940 5941 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5942 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5943 5944 switch (OpInfo.Type) { 5945 case InlineAsm::isOutput: { 5946 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5947 OpInfo.ConstraintType != TargetLowering::C_Register) { 5948 // Memory output, or 'other' output (e.g. 'X' constraint). 5949 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5950 5951 // Add information to the INLINEASM node to know about this output. 5952 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5953 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5954 TLI.getPointerTy())); 5955 AsmNodeOperands.push_back(OpInfo.CallOperand); 5956 break; 5957 } 5958 5959 // Otherwise, this is a register or register class output. 5960 5961 // Copy the output from the appropriate register. Find a register that 5962 // we can use. 5963 if (OpInfo.AssignedRegs.Regs.empty()) 5964 report_fatal_error("Couldn't allocate output reg for constraint '" + 5965 Twine(OpInfo.ConstraintCode) + "'!"); 5966 5967 // If this is an indirect operand, store through the pointer after the 5968 // asm. 5969 if (OpInfo.isIndirect) { 5970 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5971 OpInfo.CallOperandVal)); 5972 } else { 5973 // This is the result value of the call. 5974 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5975 // Concatenate this output onto the outputs list. 5976 RetValRegs.append(OpInfo.AssignedRegs); 5977 } 5978 5979 // Add information to the INLINEASM node to know that this register is 5980 // set. 5981 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5982 InlineAsm::Kind_RegDefEarlyClobber : 5983 InlineAsm::Kind_RegDef, 5984 false, 5985 0, 5986 DAG, 5987 AsmNodeOperands); 5988 break; 5989 } 5990 case InlineAsm::isInput: { 5991 SDValue InOperandVal = OpInfo.CallOperand; 5992 5993 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5994 // If this is required to match an output register we have already set, 5995 // just use its register. 5996 unsigned OperandNo = OpInfo.getMatchedOperand(); 5997 5998 // Scan until we find the definition we already emitted of this operand. 5999 // When we find it, create a RegsForValue operand. 6000 unsigned CurOp = InlineAsm::Op_FirstOperand; 6001 for (; OperandNo; --OperandNo) { 6002 // Advance to the next operand. 6003 unsigned OpFlag = 6004 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6005 assert((InlineAsm::isRegDefKind(OpFlag) || 6006 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6007 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6008 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6009 } 6010 6011 unsigned OpFlag = 6012 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6013 if (InlineAsm::isRegDefKind(OpFlag) || 6014 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6015 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6016 if (OpInfo.isIndirect) { 6017 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6018 LLVMContext &Ctx = *DAG.getContext(); 6019 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6020 " don't know how to handle tied " 6021 "indirect register inputs"); 6022 } 6023 6024 RegsForValue MatchedRegs; 6025 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6026 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6027 MatchedRegs.RegVTs.push_back(RegVT); 6028 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6029 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6030 i != e; ++i) 6031 MatchedRegs.Regs.push_back 6032 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6033 6034 // Use the produced MatchedRegs object to 6035 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6036 Chain, &Flag); 6037 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6038 true, OpInfo.getMatchedOperand(), 6039 DAG, AsmNodeOperands); 6040 break; 6041 } 6042 6043 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6044 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6045 "Unexpected number of operands"); 6046 // Add information to the INLINEASM node to know about this input. 6047 // See InlineAsm.h isUseOperandTiedToDef. 6048 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6049 OpInfo.getMatchedOperand()); 6050 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6051 TLI.getPointerTy())); 6052 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6053 break; 6054 } 6055 6056 // Treat indirect 'X' constraint as memory. 6057 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6058 OpInfo.isIndirect) 6059 OpInfo.ConstraintType = TargetLowering::C_Memory; 6060 6061 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6062 std::vector<SDValue> Ops; 6063 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6064 Ops, DAG); 6065 if (Ops.empty()) 6066 report_fatal_error("Invalid operand for inline asm constraint '" + 6067 Twine(OpInfo.ConstraintCode) + "'!"); 6068 6069 // Add information to the INLINEASM node to know about this input. 6070 unsigned ResOpType = 6071 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6072 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6073 TLI.getPointerTy())); 6074 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6075 break; 6076 } 6077 6078 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6079 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6080 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6081 "Memory operands expect pointer values"); 6082 6083 // Add information to the INLINEASM node to know about this input. 6084 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6085 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6086 TLI.getPointerTy())); 6087 AsmNodeOperands.push_back(InOperandVal); 6088 break; 6089 } 6090 6091 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6092 OpInfo.ConstraintType == TargetLowering::C_Register) && 6093 "Unknown constraint type!"); 6094 assert(!OpInfo.isIndirect && 6095 "Don't know how to handle indirect register inputs yet!"); 6096 6097 // Copy the input into the appropriate registers. 6098 if (OpInfo.AssignedRegs.Regs.empty()) 6099 report_fatal_error("Couldn't allocate input reg for constraint '" + 6100 Twine(OpInfo.ConstraintCode) + "'!"); 6101 6102 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6103 Chain, &Flag); 6104 6105 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6106 DAG, AsmNodeOperands); 6107 break; 6108 } 6109 case InlineAsm::isClobber: { 6110 // Add the clobbered value to the operand list, so that the register 6111 // allocator is aware that the physreg got clobbered. 6112 if (!OpInfo.AssignedRegs.Regs.empty()) 6113 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6114 false, 0, DAG, 6115 AsmNodeOperands); 6116 break; 6117 } 6118 } 6119 } 6120 6121 // Finish up input operands. Set the input chain and add the flag last. 6122 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6123 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6124 6125 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6126 DAG.getVTList(MVT::Other, MVT::Glue), 6127 &AsmNodeOperands[0], AsmNodeOperands.size()); 6128 Flag = Chain.getValue(1); 6129 6130 // If this asm returns a register value, copy the result from that register 6131 // and set it as the value of the call. 6132 if (!RetValRegs.Regs.empty()) { 6133 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6134 Chain, &Flag); 6135 6136 // FIXME: Why don't we do this for inline asms with MRVs? 6137 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6138 EVT ResultType = TLI.getValueType(CS.getType()); 6139 6140 // If any of the results of the inline asm is a vector, it may have the 6141 // wrong width/num elts. This can happen for register classes that can 6142 // contain multiple different value types. The preg or vreg allocated may 6143 // not have the same VT as was expected. Convert it to the right type 6144 // with bit_convert. 6145 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6146 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6147 ResultType, Val); 6148 6149 } else if (ResultType != Val.getValueType() && 6150 ResultType.isInteger() && Val.getValueType().isInteger()) { 6151 // If a result value was tied to an input value, the computed result may 6152 // have a wider width than the expected result. Extract the relevant 6153 // portion. 6154 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6155 } 6156 6157 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6158 } 6159 6160 setValue(CS.getInstruction(), Val); 6161 // Don't need to use this as a chain in this case. 6162 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6163 return; 6164 } 6165 6166 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6167 6168 // Process indirect outputs, first output all of the flagged copies out of 6169 // physregs. 6170 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6171 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6172 const Value *Ptr = IndirectStoresToEmit[i].second; 6173 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6174 Chain, &Flag); 6175 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6176 } 6177 6178 // Emit the non-flagged stores from the physregs. 6179 SmallVector<SDValue, 8> OutChains; 6180 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6181 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6182 StoresToEmit[i].first, 6183 getValue(StoresToEmit[i].second), 6184 MachinePointerInfo(StoresToEmit[i].second), 6185 false, false, 0); 6186 OutChains.push_back(Val); 6187 } 6188 6189 if (!OutChains.empty()) 6190 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6191 &OutChains[0], OutChains.size()); 6192 6193 DAG.setRoot(Chain); 6194} 6195 6196void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6197 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6198 MVT::Other, getRoot(), 6199 getValue(I.getArgOperand(0)), 6200 DAG.getSrcValue(I.getArgOperand(0)))); 6201} 6202 6203void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6204 const TargetData &TD = *TLI.getTargetData(); 6205 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6206 getRoot(), getValue(I.getOperand(0)), 6207 DAG.getSrcValue(I.getOperand(0)), 6208 TD.getABITypeAlignment(I.getType())); 6209 setValue(&I, V); 6210 DAG.setRoot(V.getValue(1)); 6211} 6212 6213void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6214 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6215 MVT::Other, getRoot(), 6216 getValue(I.getArgOperand(0)), 6217 DAG.getSrcValue(I.getArgOperand(0)))); 6218} 6219 6220void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6221 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6222 MVT::Other, getRoot(), 6223 getValue(I.getArgOperand(0)), 6224 getValue(I.getArgOperand(1)), 6225 DAG.getSrcValue(I.getArgOperand(0)), 6226 DAG.getSrcValue(I.getArgOperand(1)))); 6227} 6228 6229/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6230/// implementation, which just calls LowerCall. 6231/// FIXME: When all targets are 6232/// migrated to using LowerCall, this hook should be integrated into SDISel. 6233std::pair<SDValue, SDValue> 6234TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6235 bool RetSExt, bool RetZExt, bool isVarArg, 6236 bool isInreg, unsigned NumFixedArgs, 6237 CallingConv::ID CallConv, bool isTailCall, 6238 bool isReturnValueUsed, 6239 SDValue Callee, 6240 ArgListTy &Args, SelectionDAG &DAG, 6241 DebugLoc dl) const { 6242 // Handle all of the outgoing arguments. 6243 SmallVector<ISD::OutputArg, 32> Outs; 6244 SmallVector<SDValue, 32> OutVals; 6245 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6246 SmallVector<EVT, 4> ValueVTs; 6247 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6248 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6249 Value != NumValues; ++Value) { 6250 EVT VT = ValueVTs[Value]; 6251 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6252 SDValue Op = SDValue(Args[i].Node.getNode(), 6253 Args[i].Node.getResNo() + Value); 6254 ISD::ArgFlagsTy Flags; 6255 unsigned OriginalAlignment = 6256 getTargetData()->getABITypeAlignment(ArgTy); 6257 6258 if (Args[i].isZExt) 6259 Flags.setZExt(); 6260 if (Args[i].isSExt) 6261 Flags.setSExt(); 6262 if (Args[i].isInReg) 6263 Flags.setInReg(); 6264 if (Args[i].isSRet) 6265 Flags.setSRet(); 6266 if (Args[i].isByVal) { 6267 Flags.setByVal(); 6268 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6269 Type *ElementTy = Ty->getElementType(); 6270 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6271 // For ByVal, alignment should come from FE. BE will guess if this 6272 // info is not there but there are cases it cannot get right. 6273 unsigned FrameAlign; 6274 if (Args[i].Alignment) 6275 FrameAlign = Args[i].Alignment; 6276 else 6277 FrameAlign = getByValTypeAlignment(ElementTy); 6278 Flags.setByValAlign(FrameAlign); 6279 } 6280 if (Args[i].isNest) 6281 Flags.setNest(); 6282 Flags.setOrigAlign(OriginalAlignment); 6283 6284 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6285 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6286 SmallVector<SDValue, 4> Parts(NumParts); 6287 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6288 6289 if (Args[i].isSExt) 6290 ExtendKind = ISD::SIGN_EXTEND; 6291 else if (Args[i].isZExt) 6292 ExtendKind = ISD::ZERO_EXTEND; 6293 6294 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6295 PartVT, ExtendKind); 6296 6297 for (unsigned j = 0; j != NumParts; ++j) { 6298 // if it isn't first piece, alignment must be 1 6299 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6300 i < NumFixedArgs); 6301 if (NumParts > 1 && j == 0) 6302 MyFlags.Flags.setSplit(); 6303 else if (j != 0) 6304 MyFlags.Flags.setOrigAlign(1); 6305 6306 Outs.push_back(MyFlags); 6307 OutVals.push_back(Parts[j]); 6308 } 6309 } 6310 } 6311 6312 // Handle the incoming return values from the call. 6313 SmallVector<ISD::InputArg, 32> Ins; 6314 SmallVector<EVT, 4> RetTys; 6315 ComputeValueVTs(*this, RetTy, RetTys); 6316 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6317 EVT VT = RetTys[I]; 6318 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6319 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6320 for (unsigned i = 0; i != NumRegs; ++i) { 6321 ISD::InputArg MyFlags; 6322 MyFlags.VT = RegisterVT.getSimpleVT(); 6323 MyFlags.Used = isReturnValueUsed; 6324 if (RetSExt) 6325 MyFlags.Flags.setSExt(); 6326 if (RetZExt) 6327 MyFlags.Flags.setZExt(); 6328 if (isInreg) 6329 MyFlags.Flags.setInReg(); 6330 Ins.push_back(MyFlags); 6331 } 6332 } 6333 6334 SmallVector<SDValue, 4> InVals; 6335 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6336 Outs, OutVals, Ins, dl, DAG, InVals); 6337 6338 // Verify that the target's LowerCall behaved as expected. 6339 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6340 "LowerCall didn't return a valid chain!"); 6341 assert((!isTailCall || InVals.empty()) && 6342 "LowerCall emitted a return value for a tail call!"); 6343 assert((isTailCall || InVals.size() == Ins.size()) && 6344 "LowerCall didn't emit the correct number of values!"); 6345 6346 // For a tail call, the return value is merely live-out and there aren't 6347 // any nodes in the DAG representing it. Return a special value to 6348 // indicate that a tail call has been emitted and no more Instructions 6349 // should be processed in the current block. 6350 if (isTailCall) { 6351 DAG.setRoot(Chain); 6352 return std::make_pair(SDValue(), SDValue()); 6353 } 6354 6355 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6356 assert(InVals[i].getNode() && 6357 "LowerCall emitted a null value!"); 6358 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6359 "LowerCall emitted a value with the wrong type!"); 6360 }); 6361 6362 // Collect the legal value parts into potentially illegal values 6363 // that correspond to the original function's return values. 6364 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6365 if (RetSExt) 6366 AssertOp = ISD::AssertSext; 6367 else if (RetZExt) 6368 AssertOp = ISD::AssertZext; 6369 SmallVector<SDValue, 4> ReturnValues; 6370 unsigned CurReg = 0; 6371 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6372 EVT VT = RetTys[I]; 6373 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6374 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6375 6376 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6377 NumRegs, RegisterVT, VT, 6378 AssertOp)); 6379 CurReg += NumRegs; 6380 } 6381 6382 // For a function returning void, there is no return value. We can't create 6383 // such a node, so we just return a null return value in that case. In 6384 // that case, nothing will actually look at the value. 6385 if (ReturnValues.empty()) 6386 return std::make_pair(SDValue(), Chain); 6387 6388 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6389 DAG.getVTList(&RetTys[0], RetTys.size()), 6390 &ReturnValues[0], ReturnValues.size()); 6391 return std::make_pair(Res, Chain); 6392} 6393 6394void TargetLowering::LowerOperationWrapper(SDNode *N, 6395 SmallVectorImpl<SDValue> &Results, 6396 SelectionDAG &DAG) const { 6397 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6398 if (Res.getNode()) 6399 Results.push_back(Res); 6400} 6401 6402SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6403 llvm_unreachable("LowerOperation not implemented for this target!"); 6404 return SDValue(); 6405} 6406 6407void 6408SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6409 SDValue Op = getNonRegisterValue(V); 6410 assert((Op.getOpcode() != ISD::CopyFromReg || 6411 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6412 "Copy from a reg to the same reg!"); 6413 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6414 6415 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6416 SDValue Chain = DAG.getEntryNode(); 6417 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6418 PendingExports.push_back(Chain); 6419} 6420 6421#include "llvm/CodeGen/SelectionDAGISel.h" 6422 6423/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6424/// entry block, return true. This includes arguments used by switches, since 6425/// the switch may expand into multiple basic blocks. 6426static bool isOnlyUsedInEntryBlock(const Argument *A) { 6427 // With FastISel active, we may be splitting blocks, so force creation 6428 // of virtual registers for all non-dead arguments. 6429 if (EnableFastISel) 6430 return A->use_empty(); 6431 6432 const BasicBlock *Entry = A->getParent()->begin(); 6433 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6434 UI != E; ++UI) { 6435 const User *U = *UI; 6436 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6437 return false; // Use not in entry block. 6438 } 6439 return true; 6440} 6441 6442void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6443 // If this is the entry block, emit arguments. 6444 const Function &F = *LLVMBB->getParent(); 6445 SelectionDAG &DAG = SDB->DAG; 6446 DebugLoc dl = SDB->getCurDebugLoc(); 6447 const TargetData *TD = TLI.getTargetData(); 6448 SmallVector<ISD::InputArg, 16> Ins; 6449 6450 // Check whether the function can return without sret-demotion. 6451 SmallVector<ISD::OutputArg, 4> Outs; 6452 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6453 Outs, TLI); 6454 6455 if (!FuncInfo->CanLowerReturn) { 6456 // Put in an sret pointer parameter before all the other parameters. 6457 SmallVector<EVT, 1> ValueVTs; 6458 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6459 6460 // NOTE: Assuming that a pointer will never break down to more than one VT 6461 // or one register. 6462 ISD::ArgFlagsTy Flags; 6463 Flags.setSRet(); 6464 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6465 ISD::InputArg RetArg(Flags, RegisterVT, true); 6466 Ins.push_back(RetArg); 6467 } 6468 6469 // Set up the incoming argument description vector. 6470 unsigned Idx = 1; 6471 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6472 I != E; ++I, ++Idx) { 6473 SmallVector<EVT, 4> ValueVTs; 6474 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6475 bool isArgValueUsed = !I->use_empty(); 6476 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6477 Value != NumValues; ++Value) { 6478 EVT VT = ValueVTs[Value]; 6479 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6480 ISD::ArgFlagsTy Flags; 6481 unsigned OriginalAlignment = 6482 TD->getABITypeAlignment(ArgTy); 6483 6484 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6485 Flags.setZExt(); 6486 if (F.paramHasAttr(Idx, Attribute::SExt)) 6487 Flags.setSExt(); 6488 if (F.paramHasAttr(Idx, Attribute::InReg)) 6489 Flags.setInReg(); 6490 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6491 Flags.setSRet(); 6492 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6493 Flags.setByVal(); 6494 PointerType *Ty = cast<PointerType>(I->getType()); 6495 Type *ElementTy = Ty->getElementType(); 6496 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6497 // For ByVal, alignment should be passed from FE. BE will guess if 6498 // this info is not there but there are cases it cannot get right. 6499 unsigned FrameAlign; 6500 if (F.getParamAlignment(Idx)) 6501 FrameAlign = F.getParamAlignment(Idx); 6502 else 6503 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6504 Flags.setByValAlign(FrameAlign); 6505 } 6506 if (F.paramHasAttr(Idx, Attribute::Nest)) 6507 Flags.setNest(); 6508 Flags.setOrigAlign(OriginalAlignment); 6509 6510 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6511 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6512 for (unsigned i = 0; i != NumRegs; ++i) { 6513 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6514 if (NumRegs > 1 && i == 0) 6515 MyFlags.Flags.setSplit(); 6516 // if it isn't first piece, alignment must be 1 6517 else if (i > 0) 6518 MyFlags.Flags.setOrigAlign(1); 6519 Ins.push_back(MyFlags); 6520 } 6521 } 6522 } 6523 6524 // Call the target to set up the argument values. 6525 SmallVector<SDValue, 8> InVals; 6526 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6527 F.isVarArg(), Ins, 6528 dl, DAG, InVals); 6529 6530 // Verify that the target's LowerFormalArguments behaved as expected. 6531 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6532 "LowerFormalArguments didn't return a valid chain!"); 6533 assert(InVals.size() == Ins.size() && 6534 "LowerFormalArguments didn't emit the correct number of values!"); 6535 DEBUG({ 6536 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6537 assert(InVals[i].getNode() && 6538 "LowerFormalArguments emitted a null value!"); 6539 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6540 "LowerFormalArguments emitted a value with the wrong type!"); 6541 } 6542 }); 6543 6544 // Update the DAG with the new chain value resulting from argument lowering. 6545 DAG.setRoot(NewRoot); 6546 6547 // Set up the argument values. 6548 unsigned i = 0; 6549 Idx = 1; 6550 if (!FuncInfo->CanLowerReturn) { 6551 // Create a virtual register for the sret pointer, and put in a copy 6552 // from the sret argument into it. 6553 SmallVector<EVT, 1> ValueVTs; 6554 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6555 EVT VT = ValueVTs[0]; 6556 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6557 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6558 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6559 RegVT, VT, AssertOp); 6560 6561 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6562 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6563 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6564 FuncInfo->DemoteRegister = SRetReg; 6565 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6566 SRetReg, ArgValue); 6567 DAG.setRoot(NewRoot); 6568 6569 // i indexes lowered arguments. Bump it past the hidden sret argument. 6570 // Idx indexes LLVM arguments. Don't touch it. 6571 ++i; 6572 } 6573 6574 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6575 ++I, ++Idx) { 6576 SmallVector<SDValue, 4> ArgValues; 6577 SmallVector<EVT, 4> ValueVTs; 6578 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6579 unsigned NumValues = ValueVTs.size(); 6580 6581 // If this argument is unused then remember its value. It is used to generate 6582 // debugging information. 6583 if (I->use_empty() && NumValues) 6584 SDB->setUnusedArgValue(I, InVals[i]); 6585 6586 for (unsigned Val = 0; Val != NumValues; ++Val) { 6587 EVT VT = ValueVTs[Val]; 6588 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6589 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6590 6591 if (!I->use_empty()) { 6592 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6593 if (F.paramHasAttr(Idx, Attribute::SExt)) 6594 AssertOp = ISD::AssertSext; 6595 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6596 AssertOp = ISD::AssertZext; 6597 6598 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6599 NumParts, PartVT, VT, 6600 AssertOp)); 6601 } 6602 6603 i += NumParts; 6604 } 6605 6606 // We don't need to do anything else for unused arguments. 6607 if (ArgValues.empty()) 6608 continue; 6609 6610 // Note down frame index for byval arguments. 6611 if (I->hasByValAttr()) 6612 if (FrameIndexSDNode *FI = 6613 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6614 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6615 6616 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6617 SDB->getCurDebugLoc()); 6618 SDB->setValue(I, Res); 6619 6620 // If this argument is live outside of the entry block, insert a copy from 6621 // wherever we got it to the vreg that other BB's will reference it as. 6622 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6623 // If we can, though, try to skip creating an unnecessary vreg. 6624 // FIXME: This isn't very clean... it would be nice to make this more 6625 // general. It's also subtly incompatible with the hacks FastISel 6626 // uses with vregs. 6627 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6628 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6629 FuncInfo->ValueMap[I] = Reg; 6630 continue; 6631 } 6632 } 6633 if (!isOnlyUsedInEntryBlock(I)) { 6634 FuncInfo->InitializeRegForValue(I); 6635 SDB->CopyToExportRegsIfNeeded(I); 6636 } 6637 } 6638 6639 assert(i == InVals.size() && "Argument register count mismatch!"); 6640 6641 // Finally, if the target has anything special to do, allow it to do so. 6642 // FIXME: this should insert code into the DAG! 6643 EmitFunctionEntryCode(); 6644} 6645 6646/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6647/// ensure constants are generated when needed. Remember the virtual registers 6648/// that need to be added to the Machine PHI nodes as input. We cannot just 6649/// directly add them, because expansion might result in multiple MBB's for one 6650/// BB. As such, the start of the BB might correspond to a different MBB than 6651/// the end. 6652/// 6653void 6654SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6655 const TerminatorInst *TI = LLVMBB->getTerminator(); 6656 6657 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6658 6659 // Check successor nodes' PHI nodes that expect a constant to be available 6660 // from this block. 6661 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6662 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6663 if (!isa<PHINode>(SuccBB->begin())) continue; 6664 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6665 6666 // If this terminator has multiple identical successors (common for 6667 // switches), only handle each succ once. 6668 if (!SuccsHandled.insert(SuccMBB)) continue; 6669 6670 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6671 6672 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6673 // nodes and Machine PHI nodes, but the incoming operands have not been 6674 // emitted yet. 6675 for (BasicBlock::const_iterator I = SuccBB->begin(); 6676 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6677 // Ignore dead phi's. 6678 if (PN->use_empty()) continue; 6679 6680 // Skip empty types 6681 if (PN->getType()->isEmptyTy()) 6682 continue; 6683 6684 unsigned Reg; 6685 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6686 6687 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6688 unsigned &RegOut = ConstantsOut[C]; 6689 if (RegOut == 0) { 6690 RegOut = FuncInfo.CreateRegs(C->getType()); 6691 CopyValueToVirtualRegister(C, RegOut); 6692 } 6693 Reg = RegOut; 6694 } else { 6695 DenseMap<const Value *, unsigned>::iterator I = 6696 FuncInfo.ValueMap.find(PHIOp); 6697 if (I != FuncInfo.ValueMap.end()) 6698 Reg = I->second; 6699 else { 6700 assert(isa<AllocaInst>(PHIOp) && 6701 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6702 "Didn't codegen value into a register!??"); 6703 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6704 CopyValueToVirtualRegister(PHIOp, Reg); 6705 } 6706 } 6707 6708 // Remember that this register needs to added to the machine PHI node as 6709 // the input for this MBB. 6710 SmallVector<EVT, 4> ValueVTs; 6711 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6712 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6713 EVT VT = ValueVTs[vti]; 6714 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6715 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6716 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6717 Reg += NumRegisters; 6718 } 6719 } 6720 } 6721 ConstantsOut.clear(); 6722} 6723