SelectionDAGBuilder.cpp revision f1b4eafbfec976f939ec0ea3e8acf91cef5363e3
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/PseudoSourceValue.h" 45#include "llvm/CodeGen/SelectionDAG.h" 46#include "llvm/Analysis/DebugInfo.h" 47#include "llvm/Target/TargetRegisterInfo.h" 48#include "llvm/Target/TargetData.h" 49#include "llvm/Target/TargetFrameInfo.h" 50#include "llvm/Target/TargetInstrInfo.h" 51#include "llvm/Target/TargetIntrinsicInfo.h" 52#include "llvm/Target/TargetLowering.h" 53#include "llvm/Target/TargetOptions.h" 54#include "llvm/Support/Compiler.h" 55#include "llvm/Support/CommandLine.h" 56#include "llvm/Support/Debug.h" 57#include "llvm/Support/ErrorHandling.h" 58#include "llvm/Support/MathExtras.h" 59#include "llvm/Support/raw_ostream.h" 60#include <algorithm> 61using namespace llvm; 62 63/// LimitFloatPrecision - Generate low-precision inline sequences for 64/// some float libcalls (6, 8 or 12 bits). 65static unsigned LimitFloatPrecision; 66 67static cl::opt<unsigned, true> 68LimitFPPrecision("limit-float-precision", 69 cl::desc("Generate low-precision inline sequences " 70 "for some float libcalls"), 71 cl::location(LimitFloatPrecision), 72 cl::init(0)); 73 74// Limit the width of DAG chains. This is important in general to prevent 75// prevent DAG-based analysis from blowing up. For example, alias analysis and 76// load clustering may not complete in reasonable time. It is difficult to 77// recognize and avoid this situation within each individual analysis, and 78// future analyses are likely to have the same behavior. Limiting DAG width is 79// the safe approach, and will be especially important with global DAGs. 80// 81// MaxParallelChains default is arbitrarily high to avoid affecting 82// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 83// sequence over this should have been converted to llvm.memcpy by the 84// frontend. It easy to induce this behavior with .ll code such as: 85// %buffer = alloca [4096 x i8] 86// %data = load [4096 x i8]* %argPtr 87// store [4096 x i8] %data, [4096 x i8]* %buffer 88static cl::opt<unsigned> 89MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"), 90 cl::init(64), cl::Hidden); 91 92static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 93 const SDValue *Parts, unsigned NumParts, 94 EVT PartVT, EVT ValueVT); 95 96/// getCopyFromParts - Create a value that contains the specified legal parts 97/// combined into the value they represent. If the parts combine to a type 98/// larger then ValueVT then AssertOp can be used to specify whether the extra 99/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 100/// (ISD::AssertSext). 101static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 102 const SDValue *Parts, 103 unsigned NumParts, EVT PartVT, EVT ValueVT, 104 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 105 if (ValueVT.isVector()) 106 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 107 108 assert(NumParts > 0 && "No parts to assemble!"); 109 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 110 SDValue Val = Parts[0]; 111 112 if (NumParts > 1) { 113 // Assemble the value from multiple parts. 114 if (ValueVT.isInteger()) { 115 unsigned PartBits = PartVT.getSizeInBits(); 116 unsigned ValueBits = ValueVT.getSizeInBits(); 117 118 // Assemble the power of 2 part. 119 unsigned RoundParts = NumParts & (NumParts - 1) ? 120 1 << Log2_32(NumParts) : NumParts; 121 unsigned RoundBits = PartBits * RoundParts; 122 EVT RoundVT = RoundBits == ValueBits ? 123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 124 SDValue Lo, Hi; 125 126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 127 128 if (RoundParts > 2) { 129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 130 PartVT, HalfVT); 131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 132 RoundParts / 2, PartVT, HalfVT); 133 } else { 134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 136 } 137 138 if (TLI.isBigEndian()) 139 std::swap(Lo, Hi); 140 141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 142 143 if (RoundParts < NumParts) { 144 // Assemble the trailing non-power-of-2 part. 145 unsigned OddParts = NumParts - RoundParts; 146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 147 Hi = getCopyFromParts(DAG, DL, 148 Parts + RoundParts, OddParts, PartVT, OddVT); 149 150 // Combine the round and odd parts. 151 Lo = Val; 152 if (TLI.isBigEndian()) 153 std::swap(Lo, Hi); 154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 157 DAG.getConstant(Lo.getValueType().getSizeInBits(), 158 TLI.getPointerTy())); 159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 161 } 162 } else if (PartVT.isFloatingPoint()) { 163 // FP split into multiple FP parts (for ppcf128) 164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 165 "Unexpected split"); 166 SDValue Lo, Hi; 167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 169 if (TLI.isBigEndian()) 170 std::swap(Lo, Hi); 171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 172 } else { 173 // FP split into integer parts (soft fp) 174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 175 !PartVT.isVector() && "Unexpected split"); 176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 178 } 179 } 180 181 // There is now one part, held in Val. Correct it to match ValueVT. 182 PartVT = Val.getValueType(); 183 184 if (PartVT == ValueVT) 185 return Val; 186 187 if (PartVT.isInteger() && ValueVT.isInteger()) { 188 if (ValueVT.bitsLT(PartVT)) { 189 // For a truncate, see if we have any information to 190 // indicate whether the truncated bits will always be 191 // zero or sign-extension. 192 if (AssertOp != ISD::DELETED_NODE) 193 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 194 DAG.getValueType(ValueVT)); 195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 196 } 197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 198 } 199 200 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 201 // FP_ROUND's are always exact here. 202 if (ValueVT.bitsLT(Val.getValueType())) 203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 204 DAG.getIntPtrConstant(1)); 205 206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 207 } 208 209 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 211 212 llvm_unreachable("Unknown mismatch!"); 213 return SDValue(); 214} 215 216/// getCopyFromParts - Create a value that contains the specified legal parts 217/// combined into the value they represent. If the parts combine to a type 218/// larger then ValueVT then AssertOp can be used to specify whether the extra 219/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 220/// (ISD::AssertSext). 221static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 222 const SDValue *Parts, unsigned NumParts, 223 EVT PartVT, EVT ValueVT) { 224 assert(ValueVT.isVector() && "Not a vector value"); 225 assert(NumParts > 0 && "No parts to assemble!"); 226 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 227 SDValue Val = Parts[0]; 228 229 // Handle a multi-element vector. 230 if (NumParts > 1) { 231 EVT IntermediateVT, RegisterVT; 232 unsigned NumIntermediates; 233 unsigned NumRegs = 234 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 235 NumIntermediates, RegisterVT); 236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 237 NumParts = NumRegs; // Silence a compiler warning. 238 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 239 assert(RegisterVT == Parts[0].getValueType() && 240 "Part type doesn't match part!"); 241 242 // Assemble the parts into intermediate operands. 243 SmallVector<SDValue, 8> Ops(NumIntermediates); 244 if (NumIntermediates == NumParts) { 245 // If the register was not expanded, truncate or copy the value, 246 // as appropriate. 247 for (unsigned i = 0; i != NumParts; ++i) 248 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 249 PartVT, IntermediateVT); 250 } else if (NumParts > 0) { 251 // If the intermediate type was expanded, build the intermediate 252 // operands from the parts. 253 assert(NumParts % NumIntermediates == 0 && 254 "Must expand into a divisible number of parts!"); 255 unsigned Factor = NumParts / NumIntermediates; 256 for (unsigned i = 0; i != NumIntermediates; ++i) 257 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 258 PartVT, IntermediateVT); 259 } 260 261 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 262 // intermediate operands. 263 Val = DAG.getNode(IntermediateVT.isVector() ? 264 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 265 ValueVT, &Ops[0], NumIntermediates); 266 } 267 268 // There is now one part, held in Val. Correct it to match ValueVT. 269 PartVT = Val.getValueType(); 270 271 if (PartVT == ValueVT) 272 return Val; 273 274 if (PartVT.isVector()) { 275 // If the element type of the source/dest vectors are the same, but the 276 // parts vector has more elements than the value vector, then we have a 277 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 278 // elements we want. 279 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 280 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 281 "Cannot narrow, it would be a lossy transformation"); 282 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 283 DAG.getIntPtrConstant(0)); 284 } 285 286 // Vector/Vector bitcast. 287 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 288 } 289 290 assert(ValueVT.getVectorElementType() == PartVT && 291 ValueVT.getVectorNumElements() == 1 && 292 "Only trivial scalar-to-vector conversions should get here!"); 293 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 294} 295 296 297 298 299static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 300 SDValue Val, SDValue *Parts, unsigned NumParts, 301 EVT PartVT); 302 303/// getCopyToParts - Create a series of nodes that contain the specified value 304/// split into legal parts. If the parts contain more bits than Val, then, for 305/// integers, ExtendKind can be used to specify how to generate the extra bits. 306static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 307 SDValue Val, SDValue *Parts, unsigned NumParts, 308 EVT PartVT, 309 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 310 EVT ValueVT = Val.getValueType(); 311 312 // Handle the vector case separately. 313 if (ValueVT.isVector()) 314 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 315 316 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 317 unsigned PartBits = PartVT.getSizeInBits(); 318 unsigned OrigNumParts = NumParts; 319 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 320 321 if (NumParts == 0) 322 return; 323 324 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 325 if (PartVT == ValueVT) { 326 assert(NumParts == 1 && "No-op copy with multiple parts!"); 327 Parts[0] = Val; 328 return; 329 } 330 331 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 332 // If the parts cover more bits than the value has, promote the value. 333 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 334 assert(NumParts == 1 && "Do not know what to promote to!"); 335 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 336 } else { 337 assert(PartVT.isInteger() && ValueVT.isInteger() && 338 "Unknown mismatch!"); 339 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 340 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 341 } 342 } else if (PartBits == ValueVT.getSizeInBits()) { 343 // Different types of the same size. 344 assert(NumParts == 1 && PartVT != ValueVT); 345 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 346 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 347 // If the parts cover less bits than value has, truncate the value. 348 assert(PartVT.isInteger() && ValueVT.isInteger() && 349 "Unknown mismatch!"); 350 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 351 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 352 } 353 354 // The value may have changed - recompute ValueVT. 355 ValueVT = Val.getValueType(); 356 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 357 "Failed to tile the value with PartVT!"); 358 359 if (NumParts == 1) { 360 assert(PartVT == ValueVT && "Type conversion failed!"); 361 Parts[0] = Val; 362 return; 363 } 364 365 // Expand the value into multiple parts. 366 if (NumParts & (NumParts - 1)) { 367 // The number of parts is not a power of 2. Split off and copy the tail. 368 assert(PartVT.isInteger() && ValueVT.isInteger() && 369 "Do not know what to expand to!"); 370 unsigned RoundParts = 1 << Log2_32(NumParts); 371 unsigned RoundBits = RoundParts * PartBits; 372 unsigned OddParts = NumParts - RoundParts; 373 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 374 DAG.getIntPtrConstant(RoundBits)); 375 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 376 377 if (TLI.isBigEndian()) 378 // The odd parts were reversed by getCopyToParts - unreverse them. 379 std::reverse(Parts + RoundParts, Parts + NumParts); 380 381 NumParts = RoundParts; 382 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 383 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 384 } 385 386 // The number of parts is a power of 2. Repeatedly bisect the value using 387 // EXTRACT_ELEMENT. 388 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 389 EVT::getIntegerVT(*DAG.getContext(), 390 ValueVT.getSizeInBits()), 391 Val); 392 393 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 394 for (unsigned i = 0; i < NumParts; i += StepSize) { 395 unsigned ThisBits = StepSize * PartBits / 2; 396 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 397 SDValue &Part0 = Parts[i]; 398 SDValue &Part1 = Parts[i+StepSize/2]; 399 400 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 401 ThisVT, Part0, DAG.getIntPtrConstant(1)); 402 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 403 ThisVT, Part0, DAG.getIntPtrConstant(0)); 404 405 if (ThisBits == PartBits && ThisVT != PartVT) { 406 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 407 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 408 } 409 } 410 } 411 412 if (TLI.isBigEndian()) 413 std::reverse(Parts, Parts + OrigNumParts); 414} 415 416 417/// getCopyToPartsVector - Create a series of nodes that contain the specified 418/// value split into legal parts. 419static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 420 SDValue Val, SDValue *Parts, unsigned NumParts, 421 EVT PartVT) { 422 EVT ValueVT = Val.getValueType(); 423 assert(ValueVT.isVector() && "Not a vector"); 424 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 425 426 if (NumParts == 1) { 427 if (PartVT == ValueVT) { 428 // Nothing to do. 429 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 430 // Bitconvert vector->vector case. 431 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 432 } else if (PartVT.isVector() && 433 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&& 434 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 435 EVT ElementVT = PartVT.getVectorElementType(); 436 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 437 // undef elements. 438 SmallVector<SDValue, 16> Ops; 439 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 440 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 441 ElementVT, Val, DAG.getIntPtrConstant(i))); 442 443 for (unsigned i = ValueVT.getVectorNumElements(), 444 e = PartVT.getVectorNumElements(); i != e; ++i) 445 Ops.push_back(DAG.getUNDEF(ElementVT)); 446 447 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 448 449 // FIXME: Use CONCAT for 2x -> 4x. 450 451 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 452 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 453 } else { 454 // Vector -> scalar conversion. 455 assert(ValueVT.getVectorElementType() == PartVT && 456 ValueVT.getVectorNumElements() == 1 && 457 "Only trivial vector-to-scalar conversions should get here!"); 458 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 459 PartVT, Val, DAG.getIntPtrConstant(0)); 460 } 461 462 Parts[0] = Val; 463 return; 464 } 465 466 // Handle a multi-element vector. 467 EVT IntermediateVT, RegisterVT; 468 unsigned NumIntermediates; 469 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 470 IntermediateVT, 471 NumIntermediates, RegisterVT); 472 unsigned NumElements = ValueVT.getVectorNumElements(); 473 474 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 475 NumParts = NumRegs; // Silence a compiler warning. 476 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 477 478 // Split the vector into intermediate operands. 479 SmallVector<SDValue, 8> Ops(NumIntermediates); 480 for (unsigned i = 0; i != NumIntermediates; ++i) { 481 if (IntermediateVT.isVector()) 482 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 483 IntermediateVT, Val, 484 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 485 else 486 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 487 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 488 } 489 490 // Split the intermediate operands into legal parts. 491 if (NumParts == NumIntermediates) { 492 // If the register was not expanded, promote or copy the value, 493 // as appropriate. 494 for (unsigned i = 0; i != NumParts; ++i) 495 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 496 } else if (NumParts > 0) { 497 // If the intermediate type was expanded, split each the value into 498 // legal parts. 499 assert(NumParts % NumIntermediates == 0 && 500 "Must expand into a divisible number of parts!"); 501 unsigned Factor = NumParts / NumIntermediates; 502 for (unsigned i = 0; i != NumIntermediates; ++i) 503 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 504 } 505} 506 507 508 509 510namespace { 511 /// RegsForValue - This struct represents the registers (physical or virtual) 512 /// that a particular set of values is assigned, and the type information 513 /// about the value. The most common situation is to represent one value at a 514 /// time, but struct or array values are handled element-wise as multiple 515 /// values. The splitting of aggregates is performed recursively, so that we 516 /// never have aggregate-typed registers. The values at this point do not 517 /// necessarily have legal types, so each value may require one or more 518 /// registers of some legal type. 519 /// 520 struct RegsForValue { 521 /// ValueVTs - The value types of the values, which may not be legal, and 522 /// may need be promoted or synthesized from one or more registers. 523 /// 524 SmallVector<EVT, 4> ValueVTs; 525 526 /// RegVTs - The value types of the registers. This is the same size as 527 /// ValueVTs and it records, for each value, what the type of the assigned 528 /// register or registers are. (Individual values are never synthesized 529 /// from more than one type of register.) 530 /// 531 /// With virtual registers, the contents of RegVTs is redundant with TLI's 532 /// getRegisterType member function, however when with physical registers 533 /// it is necessary to have a separate record of the types. 534 /// 535 SmallVector<EVT, 4> RegVTs; 536 537 /// Regs - This list holds the registers assigned to the values. 538 /// Each legal or promoted value requires one register, and each 539 /// expanded value requires multiple registers. 540 /// 541 SmallVector<unsigned, 4> Regs; 542 543 RegsForValue() {} 544 545 RegsForValue(const SmallVector<unsigned, 4> ®s, 546 EVT regvt, EVT valuevt) 547 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 548 549 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 550 unsigned Reg, const Type *Ty) { 551 ComputeValueVTs(tli, Ty, ValueVTs); 552 553 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 554 EVT ValueVT = ValueVTs[Value]; 555 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 556 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 557 for (unsigned i = 0; i != NumRegs; ++i) 558 Regs.push_back(Reg + i); 559 RegVTs.push_back(RegisterVT); 560 Reg += NumRegs; 561 } 562 } 563 564 /// areValueTypesLegal - Return true if types of all the values are legal. 565 bool areValueTypesLegal(const TargetLowering &TLI) { 566 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 567 EVT RegisterVT = RegVTs[Value]; 568 if (!TLI.isTypeLegal(RegisterVT)) 569 return false; 570 } 571 return true; 572 } 573 574 /// append - Add the specified values to this one. 575 void append(const RegsForValue &RHS) { 576 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 577 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 578 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 579 } 580 581 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 582 /// this value and returns the result as a ValueVTs value. This uses 583 /// Chain/Flag as the input and updates them for the output Chain/Flag. 584 /// If the Flag pointer is NULL, no flag is used. 585 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 586 DebugLoc dl, 587 SDValue &Chain, SDValue *Flag) const; 588 589 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 590 /// specified value into the registers specified by this object. This uses 591 /// Chain/Flag as the input and updates them for the output Chain/Flag. 592 /// If the Flag pointer is NULL, no flag is used. 593 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 594 SDValue &Chain, SDValue *Flag) const; 595 596 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 597 /// operand list. This adds the code marker, matching input operand index 598 /// (if applicable), and includes the number of values added into it. 599 void AddInlineAsmOperands(unsigned Kind, 600 bool HasMatching, unsigned MatchingIdx, 601 SelectionDAG &DAG, 602 std::vector<SDValue> &Ops) const; 603 }; 604} 605 606/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 607/// this value and returns the result as a ValueVT value. This uses 608/// Chain/Flag as the input and updates them for the output Chain/Flag. 609/// If the Flag pointer is NULL, no flag is used. 610SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 611 FunctionLoweringInfo &FuncInfo, 612 DebugLoc dl, 613 SDValue &Chain, SDValue *Flag) const { 614 // A Value with type {} or [0 x %t] needs no registers. 615 if (ValueVTs.empty()) 616 return SDValue(); 617 618 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 619 620 // Assemble the legal parts into the final values. 621 SmallVector<SDValue, 4> Values(ValueVTs.size()); 622 SmallVector<SDValue, 8> Parts; 623 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 624 // Copy the legal parts from the registers. 625 EVT ValueVT = ValueVTs[Value]; 626 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 627 EVT RegisterVT = RegVTs[Value]; 628 629 Parts.resize(NumRegs); 630 for (unsigned i = 0; i != NumRegs; ++i) { 631 SDValue P; 632 if (Flag == 0) { 633 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 634 } else { 635 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 636 *Flag = P.getValue(2); 637 } 638 639 Chain = P.getValue(1); 640 Parts[i] = P; 641 642 // If the source register was virtual and if we know something about it, 643 // add an assert node. 644 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 645 !RegisterVT.isInteger() || RegisterVT.isVector()) 646 continue; 647 648 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; 649 if (SlotNo >= FuncInfo.LiveOutRegInfo.size()) continue; 650 651 const FunctionLoweringInfo::LiveOutInfo &LOI = 652 FuncInfo.LiveOutRegInfo[SlotNo]; 653 654 unsigned RegSize = RegisterVT.getSizeInBits(); 655 unsigned NumSignBits = LOI.NumSignBits; 656 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); 657 658 // FIXME: We capture more information than the dag can represent. For 659 // now, just use the tightest assertzext/assertsext possible. 660 bool isSExt = true; 661 EVT FromVT(MVT::Other); 662 if (NumSignBits == RegSize) 663 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 664 else if (NumZeroBits >= RegSize-1) 665 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 666 else if (NumSignBits > RegSize-8) 667 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 668 else if (NumZeroBits >= RegSize-8) 669 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 670 else if (NumSignBits > RegSize-16) 671 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 672 else if (NumZeroBits >= RegSize-16) 673 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 674 else if (NumSignBits > RegSize-32) 675 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 676 else if (NumZeroBits >= RegSize-32) 677 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 678 else 679 continue; 680 681 // Add an assertion node. 682 assert(FromVT != MVT::Other); 683 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 684 RegisterVT, P, DAG.getValueType(FromVT)); 685 } 686 687 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 688 NumRegs, RegisterVT, ValueVT); 689 Part += NumRegs; 690 Parts.clear(); 691 } 692 693 return DAG.getNode(ISD::MERGE_VALUES, dl, 694 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 695 &Values[0], ValueVTs.size()); 696} 697 698/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 699/// specified value into the registers specified by this object. This uses 700/// Chain/Flag as the input and updates them for the output Chain/Flag. 701/// If the Flag pointer is NULL, no flag is used. 702void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 703 SDValue &Chain, SDValue *Flag) const { 704 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 705 706 // Get the list of the values's legal parts. 707 unsigned NumRegs = Regs.size(); 708 SmallVector<SDValue, 8> Parts(NumRegs); 709 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 710 EVT ValueVT = ValueVTs[Value]; 711 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 712 EVT RegisterVT = RegVTs[Value]; 713 714 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 715 &Parts[Part], NumParts, RegisterVT); 716 Part += NumParts; 717 } 718 719 // Copy the parts into the registers. 720 SmallVector<SDValue, 8> Chains(NumRegs); 721 for (unsigned i = 0; i != NumRegs; ++i) { 722 SDValue Part; 723 if (Flag == 0) { 724 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 725 } else { 726 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 727 *Flag = Part.getValue(1); 728 } 729 730 Chains[i] = Part.getValue(0); 731 } 732 733 if (NumRegs == 1 || Flag) 734 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 735 // flagged to it. That is the CopyToReg nodes and the user are considered 736 // a single scheduling unit. If we create a TokenFactor and return it as 737 // chain, then the TokenFactor is both a predecessor (operand) of the 738 // user as well as a successor (the TF operands are flagged to the user). 739 // c1, f1 = CopyToReg 740 // c2, f2 = CopyToReg 741 // c3 = TokenFactor c1, c2 742 // ... 743 // = op c3, ..., f2 744 Chain = Chains[NumRegs-1]; 745 else 746 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 747} 748 749/// AddInlineAsmOperands - Add this value to the specified inlineasm node 750/// operand list. This adds the code marker and includes the number of 751/// values added into it. 752void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 753 unsigned MatchingIdx, 754 SelectionDAG &DAG, 755 std::vector<SDValue> &Ops) const { 756 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 757 758 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 759 if (HasMatching) 760 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 761 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 762 Ops.push_back(Res); 763 764 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 765 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 766 EVT RegisterVT = RegVTs[Value]; 767 for (unsigned i = 0; i != NumRegs; ++i) { 768 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 769 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 770 } 771 } 772} 773 774void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 775 AA = &aa; 776 GFI = gfi; 777 TD = DAG.getTarget().getTargetData(); 778} 779 780/// clear - Clear out the current SelectionDAG and the associated 781/// state and prepare this SelectionDAGBuilder object to be used 782/// for a new block. This doesn't clear out information about 783/// additional blocks that are needed to complete switch lowering 784/// or PHI node updating; that information is cleared out as it is 785/// consumed. 786void SelectionDAGBuilder::clear() { 787 NodeMap.clear(); 788 UnusedArgNodeMap.clear(); 789 PendingLoads.clear(); 790 PendingExports.clear(); 791 DanglingDebugInfoMap.clear(); 792 CurDebugLoc = DebugLoc(); 793 HasTailCall = false; 794} 795 796/// getRoot - Return the current virtual root of the Selection DAG, 797/// flushing any PendingLoad items. This must be done before emitting 798/// a store or any other node that may need to be ordered after any 799/// prior load instructions. 800/// 801SDValue SelectionDAGBuilder::getRoot() { 802 if (PendingLoads.empty()) 803 return DAG.getRoot(); 804 805 if (PendingLoads.size() == 1) { 806 SDValue Root = PendingLoads[0]; 807 DAG.setRoot(Root); 808 PendingLoads.clear(); 809 return Root; 810 } 811 812 // Otherwise, we have to make a token factor node. 813 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 814 &PendingLoads[0], PendingLoads.size()); 815 PendingLoads.clear(); 816 DAG.setRoot(Root); 817 return Root; 818} 819 820/// getControlRoot - Similar to getRoot, but instead of flushing all the 821/// PendingLoad items, flush all the PendingExports items. It is necessary 822/// to do this before emitting a terminator instruction. 823/// 824SDValue SelectionDAGBuilder::getControlRoot() { 825 SDValue Root = DAG.getRoot(); 826 827 if (PendingExports.empty()) 828 return Root; 829 830 // Turn all of the CopyToReg chains into one factored node. 831 if (Root.getOpcode() != ISD::EntryToken) { 832 unsigned i = 0, e = PendingExports.size(); 833 for (; i != e; ++i) { 834 assert(PendingExports[i].getNode()->getNumOperands() > 1); 835 if (PendingExports[i].getNode()->getOperand(0) == Root) 836 break; // Don't add the root if we already indirectly depend on it. 837 } 838 839 if (i == e) 840 PendingExports.push_back(Root); 841 } 842 843 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 844 &PendingExports[0], 845 PendingExports.size()); 846 PendingExports.clear(); 847 DAG.setRoot(Root); 848 return Root; 849} 850 851void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 852 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 853 DAG.AssignOrdering(Node, SDNodeOrder); 854 855 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 856 AssignOrderingToNode(Node->getOperand(I).getNode()); 857} 858 859void SelectionDAGBuilder::visit(const Instruction &I) { 860 // Set up outgoing PHI node register values before emitting the terminator. 861 if (isa<TerminatorInst>(&I)) 862 HandlePHINodesInSuccessorBlocks(I.getParent()); 863 864 CurDebugLoc = I.getDebugLoc(); 865 866 visit(I.getOpcode(), I); 867 868 if (!isa<TerminatorInst>(&I) && !HasTailCall) 869 CopyToExportRegsIfNeeded(&I); 870 871 CurDebugLoc = DebugLoc(); 872} 873 874void SelectionDAGBuilder::visitPHI(const PHINode &) { 875 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 876} 877 878void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 879 // Note: this doesn't use InstVisitor, because it has to work with 880 // ConstantExpr's in addition to instructions. 881 switch (Opcode) { 882 default: llvm_unreachable("Unknown instruction type encountered!"); 883 // Build the switch statement using the Instruction.def file. 884#define HANDLE_INST(NUM, OPCODE, CLASS) \ 885 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 886#include "llvm/Instruction.def" 887 } 888 889 // Assign the ordering to the freshly created DAG nodes. 890 if (NodeMap.count(&I)) { 891 ++SDNodeOrder; 892 AssignOrderingToNode(getValue(&I).getNode()); 893 } 894} 895 896// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 897// generate the debug data structures now that we've seen its definition. 898void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 899 SDValue Val) { 900 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 901 if (DDI.getDI()) { 902 const DbgValueInst *DI = DDI.getDI(); 903 DebugLoc dl = DDI.getdl(); 904 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 905 MDNode *Variable = DI->getVariable(); 906 uint64_t Offset = DI->getOffset(); 907 SDDbgValue *SDV; 908 if (Val.getNode()) { 909 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 910 SDV = DAG.getDbgValue(Variable, Val.getNode(), 911 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 912 DAG.AddDbgValue(SDV, Val.getNode(), false); 913 } 914 } else 915 DEBUG(dbgs() << "Dropping debug info for " << DI); 916 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 917 } 918} 919 920// getValue - Return an SDValue for the given Value. 921SDValue SelectionDAGBuilder::getValue(const Value *V) { 922 // If we already have an SDValue for this value, use it. It's important 923 // to do this first, so that we don't create a CopyFromReg if we already 924 // have a regular SDValue. 925 SDValue &N = NodeMap[V]; 926 if (N.getNode()) return N; 927 928 // If there's a virtual register allocated and initialized for this 929 // value, use it. 930 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 931 if (It != FuncInfo.ValueMap.end()) { 932 unsigned InReg = It->second; 933 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 934 SDValue Chain = DAG.getEntryNode(); 935 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); 936 } 937 938 // Otherwise create a new SDValue and remember it. 939 SDValue Val = getValueImpl(V); 940 NodeMap[V] = Val; 941 resolveDanglingDebugInfo(V, Val); 942 return Val; 943} 944 945/// getNonRegisterValue - Return an SDValue for the given Value, but 946/// don't look in FuncInfo.ValueMap for a virtual register. 947SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 948 // If we already have an SDValue for this value, use it. 949 SDValue &N = NodeMap[V]; 950 if (N.getNode()) return N; 951 952 // Otherwise create a new SDValue and remember it. 953 SDValue Val = getValueImpl(V); 954 NodeMap[V] = Val; 955 resolveDanglingDebugInfo(V, Val); 956 return Val; 957} 958 959/// getValueImpl - Helper function for getValue and getNonRegisterValue. 960/// Create an SDValue for the given value. 961SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 962 if (const Constant *C = dyn_cast<Constant>(V)) { 963 EVT VT = TLI.getValueType(V->getType(), true); 964 965 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 966 return DAG.getConstant(*CI, VT); 967 968 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 969 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 970 971 if (isa<ConstantPointerNull>(C)) 972 return DAG.getConstant(0, TLI.getPointerTy()); 973 974 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 975 return DAG.getConstantFP(*CFP, VT); 976 977 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 978 return DAG.getUNDEF(VT); 979 980 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 981 visit(CE->getOpcode(), *CE); 982 SDValue N1 = NodeMap[V]; 983 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 984 return N1; 985 } 986 987 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 988 SmallVector<SDValue, 4> Constants; 989 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 990 OI != OE; ++OI) { 991 SDNode *Val = getValue(*OI).getNode(); 992 // If the operand is an empty aggregate, there are no values. 993 if (!Val) continue; 994 // Add each leaf value from the operand to the Constants list 995 // to form a flattened list of all the values. 996 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 997 Constants.push_back(SDValue(Val, i)); 998 } 999 1000 return DAG.getMergeValues(&Constants[0], Constants.size(), 1001 getCurDebugLoc()); 1002 } 1003 1004 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1005 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1006 "Unknown struct or array constant!"); 1007 1008 SmallVector<EVT, 4> ValueVTs; 1009 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1010 unsigned NumElts = ValueVTs.size(); 1011 if (NumElts == 0) 1012 return SDValue(); // empty struct 1013 SmallVector<SDValue, 4> Constants(NumElts); 1014 for (unsigned i = 0; i != NumElts; ++i) { 1015 EVT EltVT = ValueVTs[i]; 1016 if (isa<UndefValue>(C)) 1017 Constants[i] = DAG.getUNDEF(EltVT); 1018 else if (EltVT.isFloatingPoint()) 1019 Constants[i] = DAG.getConstantFP(0, EltVT); 1020 else 1021 Constants[i] = DAG.getConstant(0, EltVT); 1022 } 1023 1024 return DAG.getMergeValues(&Constants[0], NumElts, 1025 getCurDebugLoc()); 1026 } 1027 1028 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1029 return DAG.getBlockAddress(BA, VT); 1030 1031 const VectorType *VecTy = cast<VectorType>(V->getType()); 1032 unsigned NumElements = VecTy->getNumElements(); 1033 1034 // Now that we know the number and type of the elements, get that number of 1035 // elements into the Ops array based on what kind of constant it is. 1036 SmallVector<SDValue, 16> Ops; 1037 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1038 for (unsigned i = 0; i != NumElements; ++i) 1039 Ops.push_back(getValue(CP->getOperand(i))); 1040 } else { 1041 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1042 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1043 1044 SDValue Op; 1045 if (EltVT.isFloatingPoint()) 1046 Op = DAG.getConstantFP(0, EltVT); 1047 else 1048 Op = DAG.getConstant(0, EltVT); 1049 Ops.assign(NumElements, Op); 1050 } 1051 1052 // Create a BUILD_VECTOR node. 1053 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1054 VT, &Ops[0], Ops.size()); 1055 } 1056 1057 // If this is a static alloca, generate it as the frameindex instead of 1058 // computation. 1059 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1060 DenseMap<const AllocaInst*, int>::iterator SI = 1061 FuncInfo.StaticAllocaMap.find(AI); 1062 if (SI != FuncInfo.StaticAllocaMap.end()) 1063 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1064 } 1065 1066 // If this is an instruction which fast-isel has deferred, select it now. 1067 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1068 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1069 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1070 SDValue Chain = DAG.getEntryNode(); 1071 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1072 } 1073 1074 llvm_unreachable("Can't get register for value!"); 1075 return SDValue(); 1076} 1077 1078void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1079 SDValue Chain = getControlRoot(); 1080 SmallVector<ISD::OutputArg, 8> Outs; 1081 SmallVector<SDValue, 8> OutVals; 1082 1083 if (!FuncInfo.CanLowerReturn) { 1084 unsigned DemoteReg = FuncInfo.DemoteRegister; 1085 const Function *F = I.getParent()->getParent(); 1086 1087 // Emit a store of the return value through the virtual register. 1088 // Leave Outs empty so that LowerReturn won't try to load return 1089 // registers the usual way. 1090 SmallVector<EVT, 1> PtrValueVTs; 1091 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1092 PtrValueVTs); 1093 1094 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1095 SDValue RetOp = getValue(I.getOperand(0)); 1096 1097 SmallVector<EVT, 4> ValueVTs; 1098 SmallVector<uint64_t, 4> Offsets; 1099 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1100 unsigned NumValues = ValueVTs.size(); 1101 1102 SmallVector<SDValue, 4> Chains(NumValues); 1103 for (unsigned i = 0; i != NumValues; ++i) { 1104 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1105 RetPtr.getValueType(), RetPtr, 1106 DAG.getIntPtrConstant(Offsets[i])); 1107 Chains[i] = 1108 DAG.getStore(Chain, getCurDebugLoc(), 1109 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1110 // FIXME: better loc info would be nice. 1111 Add, MachinePointerInfo(), false, false, 0); 1112 } 1113 1114 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1115 MVT::Other, &Chains[0], NumValues); 1116 } else if (I.getNumOperands() != 0) { 1117 SmallVector<EVT, 4> ValueVTs; 1118 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1119 unsigned NumValues = ValueVTs.size(); 1120 if (NumValues) { 1121 SDValue RetOp = getValue(I.getOperand(0)); 1122 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1123 EVT VT = ValueVTs[j]; 1124 1125 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1126 1127 const Function *F = I.getParent()->getParent(); 1128 if (F->paramHasAttr(0, Attribute::SExt)) 1129 ExtendKind = ISD::SIGN_EXTEND; 1130 else if (F->paramHasAttr(0, Attribute::ZExt)) 1131 ExtendKind = ISD::ZERO_EXTEND; 1132 1133 // FIXME: C calling convention requires the return type to be promoted 1134 // to at least 32-bit. But this is not necessary for non-C calling 1135 // conventions. The frontend should mark functions whose return values 1136 // require promoting with signext or zeroext attributes. 1137 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1138 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32); 1139 if (VT.bitsLT(MinVT)) 1140 VT = MinVT; 1141 } 1142 1143 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1144 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1145 SmallVector<SDValue, 4> Parts(NumParts); 1146 getCopyToParts(DAG, getCurDebugLoc(), 1147 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1148 &Parts[0], NumParts, PartVT, ExtendKind); 1149 1150 // 'inreg' on function refers to return value 1151 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1152 if (F->paramHasAttr(0, Attribute::InReg)) 1153 Flags.setInReg(); 1154 1155 // Propagate extension type if any 1156 if (F->paramHasAttr(0, Attribute::SExt)) 1157 Flags.setSExt(); 1158 else if (F->paramHasAttr(0, Attribute::ZExt)) 1159 Flags.setZExt(); 1160 1161 for (unsigned i = 0; i < NumParts; ++i) { 1162 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1163 /*isfixed=*/true)); 1164 OutVals.push_back(Parts[i]); 1165 } 1166 } 1167 } 1168 } 1169 1170 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1171 CallingConv::ID CallConv = 1172 DAG.getMachineFunction().getFunction()->getCallingConv(); 1173 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1174 Outs, OutVals, getCurDebugLoc(), DAG); 1175 1176 // Verify that the target's LowerReturn behaved as expected. 1177 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1178 "LowerReturn didn't return a valid chain!"); 1179 1180 // Update the DAG with the new chain value resulting from return lowering. 1181 DAG.setRoot(Chain); 1182} 1183 1184/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1185/// created for it, emit nodes to copy the value into the virtual 1186/// registers. 1187void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1188 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1189 if (VMI != FuncInfo.ValueMap.end()) { 1190 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1191 CopyValueToVirtualRegister(V, VMI->second); 1192 } 1193} 1194 1195/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1196/// the current basic block, add it to ValueMap now so that we'll get a 1197/// CopyTo/FromReg. 1198void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1199 // No need to export constants. 1200 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1201 1202 // Already exported? 1203 if (FuncInfo.isExportedInst(V)) return; 1204 1205 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1206 CopyValueToVirtualRegister(V, Reg); 1207} 1208 1209bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1210 const BasicBlock *FromBB) { 1211 // The operands of the setcc have to be in this block. We don't know 1212 // how to export them from some other block. 1213 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1214 // Can export from current BB. 1215 if (VI->getParent() == FromBB) 1216 return true; 1217 1218 // Is already exported, noop. 1219 return FuncInfo.isExportedInst(V); 1220 } 1221 1222 // If this is an argument, we can export it if the BB is the entry block or 1223 // if it is already exported. 1224 if (isa<Argument>(V)) { 1225 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1226 return true; 1227 1228 // Otherwise, can only export this if it is already exported. 1229 return FuncInfo.isExportedInst(V); 1230 } 1231 1232 // Otherwise, constants can always be exported. 1233 return true; 1234} 1235 1236static bool InBlock(const Value *V, const BasicBlock *BB) { 1237 if (const Instruction *I = dyn_cast<Instruction>(V)) 1238 return I->getParent() == BB; 1239 return true; 1240} 1241 1242/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1243/// This function emits a branch and is used at the leaves of an OR or an 1244/// AND operator tree. 1245/// 1246void 1247SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1248 MachineBasicBlock *TBB, 1249 MachineBasicBlock *FBB, 1250 MachineBasicBlock *CurBB, 1251 MachineBasicBlock *SwitchBB) { 1252 const BasicBlock *BB = CurBB->getBasicBlock(); 1253 1254 // If the leaf of the tree is a comparison, merge the condition into 1255 // the caseblock. 1256 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1257 // The operands of the cmp have to be in this block. We don't know 1258 // how to export them from some other block. If this is the first block 1259 // of the sequence, no exporting is needed. 1260 if (CurBB == SwitchBB || 1261 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1262 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1263 ISD::CondCode Condition; 1264 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1265 Condition = getICmpCondCode(IC->getPredicate()); 1266 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1267 Condition = getFCmpCondCode(FC->getPredicate()); 1268 } else { 1269 Condition = ISD::SETEQ; // silence warning. 1270 llvm_unreachable("Unknown compare instruction"); 1271 } 1272 1273 CaseBlock CB(Condition, BOp->getOperand(0), 1274 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1275 SwitchCases.push_back(CB); 1276 return; 1277 } 1278 } 1279 1280 // Create a CaseBlock record representing this branch. 1281 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1282 NULL, TBB, FBB, CurBB); 1283 SwitchCases.push_back(CB); 1284} 1285 1286/// FindMergedConditions - If Cond is an expression like 1287void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1288 MachineBasicBlock *TBB, 1289 MachineBasicBlock *FBB, 1290 MachineBasicBlock *CurBB, 1291 MachineBasicBlock *SwitchBB, 1292 unsigned Opc) { 1293 // If this node is not part of the or/and tree, emit it as a branch. 1294 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1295 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1296 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1297 BOp->getParent() != CurBB->getBasicBlock() || 1298 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1299 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1300 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1301 return; 1302 } 1303 1304 // Create TmpBB after CurBB. 1305 MachineFunction::iterator BBI = CurBB; 1306 MachineFunction &MF = DAG.getMachineFunction(); 1307 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1308 CurBB->getParent()->insert(++BBI, TmpBB); 1309 1310 if (Opc == Instruction::Or) { 1311 // Codegen X | Y as: 1312 // jmp_if_X TBB 1313 // jmp TmpBB 1314 // TmpBB: 1315 // jmp_if_Y TBB 1316 // jmp FBB 1317 // 1318 1319 // Emit the LHS condition. 1320 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1321 1322 // Emit the RHS condition into TmpBB. 1323 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1324 } else { 1325 assert(Opc == Instruction::And && "Unknown merge op!"); 1326 // Codegen X & Y as: 1327 // jmp_if_X TmpBB 1328 // jmp FBB 1329 // TmpBB: 1330 // jmp_if_Y TBB 1331 // jmp FBB 1332 // 1333 // This requires creation of TmpBB after CurBB. 1334 1335 // Emit the LHS condition. 1336 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1337 1338 // Emit the RHS condition into TmpBB. 1339 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1340 } 1341} 1342 1343/// If the set of cases should be emitted as a series of branches, return true. 1344/// If we should emit this as a bunch of and/or'd together conditions, return 1345/// false. 1346bool 1347SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1348 if (Cases.size() != 2) return true; 1349 1350 // If this is two comparisons of the same values or'd or and'd together, they 1351 // will get folded into a single comparison, so don't emit two blocks. 1352 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1353 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1354 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1355 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1356 return false; 1357 } 1358 1359 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1360 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1361 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1362 Cases[0].CC == Cases[1].CC && 1363 isa<Constant>(Cases[0].CmpRHS) && 1364 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1365 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1366 return false; 1367 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1368 return false; 1369 } 1370 1371 return true; 1372} 1373 1374void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1375 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1376 1377 // Update machine-CFG edges. 1378 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1379 1380 // Figure out which block is immediately after the current one. 1381 MachineBasicBlock *NextBlock = 0; 1382 MachineFunction::iterator BBI = BrMBB; 1383 if (++BBI != FuncInfo.MF->end()) 1384 NextBlock = BBI; 1385 1386 if (I.isUnconditional()) { 1387 // Update machine-CFG edges. 1388 BrMBB->addSuccessor(Succ0MBB); 1389 1390 // If this is not a fall-through branch, emit the branch. 1391 if (Succ0MBB != NextBlock) 1392 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1393 MVT::Other, getControlRoot(), 1394 DAG.getBasicBlock(Succ0MBB))); 1395 1396 return; 1397 } 1398 1399 // If this condition is one of the special cases we handle, do special stuff 1400 // now. 1401 const Value *CondVal = I.getCondition(); 1402 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1403 1404 // If this is a series of conditions that are or'd or and'd together, emit 1405 // this as a sequence of branches instead of setcc's with and/or operations. 1406 // As long as jumps are not expensive, this should improve performance. 1407 // For example, instead of something like: 1408 // cmp A, B 1409 // C = seteq 1410 // cmp D, E 1411 // F = setle 1412 // or C, F 1413 // jnz foo 1414 // Emit: 1415 // cmp A, B 1416 // je foo 1417 // cmp D, E 1418 // jle foo 1419 // 1420 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1421 if (!TLI.isJumpExpensive() && 1422 BOp->hasOneUse() && 1423 (BOp->getOpcode() == Instruction::And || 1424 BOp->getOpcode() == Instruction::Or)) { 1425 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1426 BOp->getOpcode()); 1427 // If the compares in later blocks need to use values not currently 1428 // exported from this block, export them now. This block should always 1429 // be the first entry. 1430 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1431 1432 // Allow some cases to be rejected. 1433 if (ShouldEmitAsBranches(SwitchCases)) { 1434 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1435 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1436 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1437 } 1438 1439 // Emit the branch for this block. 1440 visitSwitchCase(SwitchCases[0], BrMBB); 1441 SwitchCases.erase(SwitchCases.begin()); 1442 return; 1443 } 1444 1445 // Okay, we decided not to do this, remove any inserted MBB's and clear 1446 // SwitchCases. 1447 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1448 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1449 1450 SwitchCases.clear(); 1451 } 1452 } 1453 1454 // Create a CaseBlock record representing this branch. 1455 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1456 NULL, Succ0MBB, Succ1MBB, BrMBB); 1457 1458 // Use visitSwitchCase to actually insert the fast branch sequence for this 1459 // cond branch. 1460 visitSwitchCase(CB, BrMBB); 1461} 1462 1463/// visitSwitchCase - Emits the necessary code to represent a single node in 1464/// the binary search tree resulting from lowering a switch instruction. 1465void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1466 MachineBasicBlock *SwitchBB) { 1467 SDValue Cond; 1468 SDValue CondLHS = getValue(CB.CmpLHS); 1469 DebugLoc dl = getCurDebugLoc(); 1470 1471 // Build the setcc now. 1472 if (CB.CmpMHS == NULL) { 1473 // Fold "(X == true)" to X and "(X == false)" to !X to 1474 // handle common cases produced by branch lowering. 1475 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1476 CB.CC == ISD::SETEQ) 1477 Cond = CondLHS; 1478 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1479 CB.CC == ISD::SETEQ) { 1480 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1481 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1482 } else 1483 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1484 } else { 1485 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1486 1487 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1488 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1489 1490 SDValue CmpOp = getValue(CB.CmpMHS); 1491 EVT VT = CmpOp.getValueType(); 1492 1493 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1494 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1495 ISD::SETLE); 1496 } else { 1497 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1498 VT, CmpOp, DAG.getConstant(Low, VT)); 1499 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1500 DAG.getConstant(High-Low, VT), ISD::SETULE); 1501 } 1502 } 1503 1504 // Update successor info 1505 SwitchBB->addSuccessor(CB.TrueBB); 1506 SwitchBB->addSuccessor(CB.FalseBB); 1507 1508 // Set NextBlock to be the MBB immediately after the current one, if any. 1509 // This is used to avoid emitting unnecessary branches to the next block. 1510 MachineBasicBlock *NextBlock = 0; 1511 MachineFunction::iterator BBI = SwitchBB; 1512 if (++BBI != FuncInfo.MF->end()) 1513 NextBlock = BBI; 1514 1515 // If the lhs block is the next block, invert the condition so that we can 1516 // fall through to the lhs instead of the rhs block. 1517 if (CB.TrueBB == NextBlock) { 1518 std::swap(CB.TrueBB, CB.FalseBB); 1519 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1520 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1521 } 1522 1523 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1524 MVT::Other, getControlRoot(), Cond, 1525 DAG.getBasicBlock(CB.TrueBB)); 1526 1527 // Insert the false branch. Do this even if it's a fall through branch, 1528 // this makes it easier to do DAG optimizations which require inverting 1529 // the branch condition. 1530 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1531 DAG.getBasicBlock(CB.FalseBB)); 1532 1533 DAG.setRoot(BrCond); 1534} 1535 1536/// visitJumpTable - Emit JumpTable node in the current MBB 1537void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1538 // Emit the code for the jump table 1539 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1540 EVT PTy = TLI.getPointerTy(); 1541 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1542 JT.Reg, PTy); 1543 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1544 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1545 MVT::Other, Index.getValue(1), 1546 Table, Index); 1547 DAG.setRoot(BrJumpTable); 1548} 1549 1550/// visitJumpTableHeader - This function emits necessary code to produce index 1551/// in the JumpTable from switch case. 1552void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1553 JumpTableHeader &JTH, 1554 MachineBasicBlock *SwitchBB) { 1555 // Subtract the lowest switch case value from the value being switched on and 1556 // conditional branch to default mbb if the result is greater than the 1557 // difference between smallest and largest cases. 1558 SDValue SwitchOp = getValue(JTH.SValue); 1559 EVT VT = SwitchOp.getValueType(); 1560 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1561 DAG.getConstant(JTH.First, VT)); 1562 1563 // The SDNode we just created, which holds the value being switched on minus 1564 // the smallest case value, needs to be copied to a virtual register so it 1565 // can be used as an index into the jump table in a subsequent basic block. 1566 // This value may be smaller or larger than the target's pointer type, and 1567 // therefore require extension or truncating. 1568 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1569 1570 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1571 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1572 JumpTableReg, SwitchOp); 1573 JT.Reg = JumpTableReg; 1574 1575 // Emit the range check for the jump table, and branch to the default block 1576 // for the switch statement if the value being switched on exceeds the largest 1577 // case in the switch. 1578 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1579 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1580 DAG.getConstant(JTH.Last-JTH.First,VT), 1581 ISD::SETUGT); 1582 1583 // Set NextBlock to be the MBB immediately after the current one, if any. 1584 // This is used to avoid emitting unnecessary branches to the next block. 1585 MachineBasicBlock *NextBlock = 0; 1586 MachineFunction::iterator BBI = SwitchBB; 1587 1588 if (++BBI != FuncInfo.MF->end()) 1589 NextBlock = BBI; 1590 1591 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1592 MVT::Other, CopyTo, CMP, 1593 DAG.getBasicBlock(JT.Default)); 1594 1595 if (JT.MBB != NextBlock) 1596 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1597 DAG.getBasicBlock(JT.MBB)); 1598 1599 DAG.setRoot(BrCond); 1600} 1601 1602/// visitBitTestHeader - This function emits necessary code to produce value 1603/// suitable for "bit tests" 1604void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1605 MachineBasicBlock *SwitchBB) { 1606 // Subtract the minimum value 1607 SDValue SwitchOp = getValue(B.SValue); 1608 EVT VT = SwitchOp.getValueType(); 1609 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1610 DAG.getConstant(B.First, VT)); 1611 1612 // Check range 1613 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1614 TLI.getSetCCResultType(Sub.getValueType()), 1615 Sub, DAG.getConstant(B.Range, VT), 1616 ISD::SETUGT); 1617 1618 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), 1619 TLI.getPointerTy()); 1620 1621 B.Reg = FuncInfo.CreateReg(TLI.getPointerTy()); 1622 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1623 B.Reg, ShiftOp); 1624 1625 // Set NextBlock to be the MBB immediately after the current one, if any. 1626 // This is used to avoid emitting unnecessary branches to the next block. 1627 MachineBasicBlock *NextBlock = 0; 1628 MachineFunction::iterator BBI = SwitchBB; 1629 if (++BBI != FuncInfo.MF->end()) 1630 NextBlock = BBI; 1631 1632 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1633 1634 SwitchBB->addSuccessor(B.Default); 1635 SwitchBB->addSuccessor(MBB); 1636 1637 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1638 MVT::Other, CopyTo, RangeCmp, 1639 DAG.getBasicBlock(B.Default)); 1640 1641 if (MBB != NextBlock) 1642 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1643 DAG.getBasicBlock(MBB)); 1644 1645 DAG.setRoot(BrRange); 1646} 1647 1648/// visitBitTestCase - this function produces one "bit test" 1649void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB, 1650 unsigned Reg, 1651 BitTestCase &B, 1652 MachineBasicBlock *SwitchBB) { 1653 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, 1654 TLI.getPointerTy()); 1655 SDValue Cmp; 1656 if (CountPopulation_64(B.Mask) == 1) { 1657 // Testing for a single bit; just compare the shift count with what it 1658 // would need to be to shift a 1 bit in that position. 1659 Cmp = DAG.getSetCC(getCurDebugLoc(), 1660 TLI.getSetCCResultType(ShiftOp.getValueType()), 1661 ShiftOp, 1662 DAG.getConstant(CountTrailingZeros_64(B.Mask), 1663 TLI.getPointerTy()), 1664 ISD::SETEQ); 1665 } else { 1666 // Make desired shift 1667 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), 1668 TLI.getPointerTy(), 1669 DAG.getConstant(1, TLI.getPointerTy()), 1670 ShiftOp); 1671 1672 // Emit bit tests and jumps 1673 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1674 TLI.getPointerTy(), SwitchVal, 1675 DAG.getConstant(B.Mask, TLI.getPointerTy())); 1676 Cmp = DAG.getSetCC(getCurDebugLoc(), 1677 TLI.getSetCCResultType(AndOp.getValueType()), 1678 AndOp, DAG.getConstant(0, TLI.getPointerTy()), 1679 ISD::SETNE); 1680 } 1681 1682 SwitchBB->addSuccessor(B.TargetBB); 1683 SwitchBB->addSuccessor(NextMBB); 1684 1685 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1686 MVT::Other, getControlRoot(), 1687 Cmp, DAG.getBasicBlock(B.TargetBB)); 1688 1689 // Set NextBlock to be the MBB immediately after the current one, if any. 1690 // This is used to avoid emitting unnecessary branches to the next block. 1691 MachineBasicBlock *NextBlock = 0; 1692 MachineFunction::iterator BBI = SwitchBB; 1693 if (++BBI != FuncInfo.MF->end()) 1694 NextBlock = BBI; 1695 1696 if (NextMBB != NextBlock) 1697 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1698 DAG.getBasicBlock(NextMBB)); 1699 1700 DAG.setRoot(BrAnd); 1701} 1702 1703void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1704 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1705 1706 // Retrieve successors. 1707 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1708 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1709 1710 const Value *Callee(I.getCalledValue()); 1711 if (isa<InlineAsm>(Callee)) 1712 visitInlineAsm(&I); 1713 else 1714 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1715 1716 // If the value of the invoke is used outside of its defining block, make it 1717 // available as a virtual register. 1718 CopyToExportRegsIfNeeded(&I); 1719 1720 // Update successor info 1721 InvokeMBB->addSuccessor(Return); 1722 InvokeMBB->addSuccessor(LandingPad); 1723 1724 // Drop into normal successor. 1725 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1726 MVT::Other, getControlRoot(), 1727 DAG.getBasicBlock(Return))); 1728} 1729 1730void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1731} 1732 1733/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1734/// small case ranges). 1735bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1736 CaseRecVector& WorkList, 1737 const Value* SV, 1738 MachineBasicBlock *Default, 1739 MachineBasicBlock *SwitchBB) { 1740 Case& BackCase = *(CR.Range.second-1); 1741 1742 // Size is the number of Cases represented by this range. 1743 size_t Size = CR.Range.second - CR.Range.first; 1744 if (Size > 3) 1745 return false; 1746 1747 // Get the MachineFunction which holds the current MBB. This is used when 1748 // inserting any additional MBBs necessary to represent the switch. 1749 MachineFunction *CurMF = FuncInfo.MF; 1750 1751 // Figure out which block is immediately after the current one. 1752 MachineBasicBlock *NextBlock = 0; 1753 MachineFunction::iterator BBI = CR.CaseBB; 1754 1755 if (++BBI != FuncInfo.MF->end()) 1756 NextBlock = BBI; 1757 1758 // If any two of the cases has the same destination, and if one value 1759 // is the same as the other, but has one bit unset that the other has set, 1760 // use bit manipulation to do two compares at once. For example: 1761 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1762 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1763 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1764 if (Size == 2 && CR.CaseBB == SwitchBB) { 1765 Case &Small = *CR.Range.first; 1766 Case &Big = *(CR.Range.second-1); 1767 1768 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1769 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1770 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1771 1772 // Check that there is only one bit different. 1773 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1774 (SmallValue | BigValue) == BigValue) { 1775 // Isolate the common bit. 1776 APInt CommonBit = BigValue & ~SmallValue; 1777 assert((SmallValue | CommonBit) == BigValue && 1778 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1779 1780 SDValue CondLHS = getValue(SV); 1781 EVT VT = CondLHS.getValueType(); 1782 DebugLoc DL = getCurDebugLoc(); 1783 1784 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1785 DAG.getConstant(CommonBit, VT)); 1786 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1787 Or, DAG.getConstant(BigValue, VT), 1788 ISD::SETEQ); 1789 1790 // Update successor info. 1791 SwitchBB->addSuccessor(Small.BB); 1792 SwitchBB->addSuccessor(Default); 1793 1794 // Insert the true branch. 1795 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1796 getControlRoot(), Cond, 1797 DAG.getBasicBlock(Small.BB)); 1798 1799 // Insert the false branch. 1800 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1801 DAG.getBasicBlock(Default)); 1802 1803 DAG.setRoot(BrCond); 1804 return true; 1805 } 1806 } 1807 } 1808 1809 // Rearrange the case blocks so that the last one falls through if possible. 1810 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1811 // The last case block won't fall through into 'NextBlock' if we emit the 1812 // branches in this order. See if rearranging a case value would help. 1813 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1814 if (I->BB == NextBlock) { 1815 std::swap(*I, BackCase); 1816 break; 1817 } 1818 } 1819 } 1820 1821 // Create a CaseBlock record representing a conditional branch to 1822 // the Case's target mbb if the value being switched on SV is equal 1823 // to C. 1824 MachineBasicBlock *CurBlock = CR.CaseBB; 1825 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1826 MachineBasicBlock *FallThrough; 1827 if (I != E-1) { 1828 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1829 CurMF->insert(BBI, FallThrough); 1830 1831 // Put SV in a virtual register to make it available from the new blocks. 1832 ExportFromCurrentBlock(SV); 1833 } else { 1834 // If the last case doesn't match, go to the default block. 1835 FallThrough = Default; 1836 } 1837 1838 const Value *RHS, *LHS, *MHS; 1839 ISD::CondCode CC; 1840 if (I->High == I->Low) { 1841 // This is just small small case range :) containing exactly 1 case 1842 CC = ISD::SETEQ; 1843 LHS = SV; RHS = I->High; MHS = NULL; 1844 } else { 1845 CC = ISD::SETLE; 1846 LHS = I->Low; MHS = SV; RHS = I->High; 1847 } 1848 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); 1849 1850 // If emitting the first comparison, just call visitSwitchCase to emit the 1851 // code into the current block. Otherwise, push the CaseBlock onto the 1852 // vector to be later processed by SDISel, and insert the node's MBB 1853 // before the next MBB. 1854 if (CurBlock == SwitchBB) 1855 visitSwitchCase(CB, SwitchBB); 1856 else 1857 SwitchCases.push_back(CB); 1858 1859 CurBlock = FallThrough; 1860 } 1861 1862 return true; 1863} 1864 1865static inline bool areJTsAllowed(const TargetLowering &TLI) { 1866 return !DisableJumpTables && 1867 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1868 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 1869} 1870 1871static APInt ComputeRange(const APInt &First, const APInt &Last) { 1872 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 1873 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 1874 return (LastExt - FirstExt + 1ULL); 1875} 1876 1877/// handleJTSwitchCase - Emit jumptable for current switch case range 1878bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR, 1879 CaseRecVector& WorkList, 1880 const Value* SV, 1881 MachineBasicBlock* Default, 1882 MachineBasicBlock *SwitchBB) { 1883 Case& FrontCase = *CR.Range.first; 1884 Case& BackCase = *(CR.Range.second-1); 1885 1886 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1887 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1888 1889 APInt TSize(First.getBitWidth(), 0); 1890 for (CaseItr I = CR.Range.first, E = CR.Range.second; 1891 I!=E; ++I) 1892 TSize += I->size(); 1893 1894 if (!areJTsAllowed(TLI) || TSize.ult(4)) 1895 return false; 1896 1897 APInt Range = ComputeRange(First, Last); 1898 double Density = TSize.roundToDouble() / Range.roundToDouble(); 1899 if (Density < 0.4) 1900 return false; 1901 1902 DEBUG(dbgs() << "Lowering jump table\n" 1903 << "First entry: " << First << ". Last entry: " << Last << '\n' 1904 << "Range: " << Range 1905 << "Size: " << TSize << ". Density: " << Density << "\n\n"); 1906 1907 // Get the MachineFunction which holds the current MBB. This is used when 1908 // inserting any additional MBBs necessary to represent the switch. 1909 MachineFunction *CurMF = FuncInfo.MF; 1910 1911 // Figure out which block is immediately after the current one. 1912 MachineFunction::iterator BBI = CR.CaseBB; 1913 ++BBI; 1914 1915 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1916 1917 // Create a new basic block to hold the code for loading the address 1918 // of the jump table, and jumping to it. Update successor information; 1919 // we will either branch to the default case for the switch, or the jump 1920 // table. 1921 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 1922 CurMF->insert(BBI, JumpTableBB); 1923 CR.CaseBB->addSuccessor(Default); 1924 CR.CaseBB->addSuccessor(JumpTableBB); 1925 1926 // Build a vector of destination BBs, corresponding to each target 1927 // of the jump table. If the value of the jump table slot corresponds to 1928 // a case statement, push the case's BB onto the vector, otherwise, push 1929 // the default BB. 1930 std::vector<MachineBasicBlock*> DestBBs; 1931 APInt TEI = First; 1932 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 1933 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 1934 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 1935 1936 if (Low.sle(TEI) && TEI.sle(High)) { 1937 DestBBs.push_back(I->BB); 1938 if (TEI==High) 1939 ++I; 1940 } else { 1941 DestBBs.push_back(Default); 1942 } 1943 } 1944 1945 // Update successor info. Add one edge to each unique successor. 1946 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 1947 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 1948 E = DestBBs.end(); I != E; ++I) { 1949 if (!SuccsHandled[(*I)->getNumber()]) { 1950 SuccsHandled[(*I)->getNumber()] = true; 1951 JumpTableBB->addSuccessor(*I); 1952 } 1953 } 1954 1955 // Create a jump table index for this jump table. 1956 unsigned JTEncoding = TLI.getJumpTableEncoding(); 1957 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 1958 ->createJumpTableIndex(DestBBs); 1959 1960 // Set the jump table information so that we can codegen it as a second 1961 // MachineBasicBlock 1962 JumpTable JT(-1U, JTI, JumpTableBB, Default); 1963 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 1964 if (CR.CaseBB == SwitchBB) 1965 visitJumpTableHeader(JT, JTH, SwitchBB); 1966 1967 JTCases.push_back(JumpTableBlock(JTH, JT)); 1968 1969 return true; 1970} 1971 1972/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 1973/// 2 subtrees. 1974bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 1975 CaseRecVector& WorkList, 1976 const Value* SV, 1977 MachineBasicBlock *Default, 1978 MachineBasicBlock *SwitchBB) { 1979 // Get the MachineFunction which holds the current MBB. This is used when 1980 // inserting any additional MBBs necessary to represent the switch. 1981 MachineFunction *CurMF = FuncInfo.MF; 1982 1983 // Figure out which block is immediately after the current one. 1984 MachineFunction::iterator BBI = CR.CaseBB; 1985 ++BBI; 1986 1987 Case& FrontCase = *CR.Range.first; 1988 Case& BackCase = *(CR.Range.second-1); 1989 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 1990 1991 // Size is the number of Cases represented by this range. 1992 unsigned Size = CR.Range.second - CR.Range.first; 1993 1994 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 1995 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 1996 double FMetric = 0; 1997 CaseItr Pivot = CR.Range.first + Size/2; 1998 1999 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2000 // (heuristically) allow us to emit JumpTable's later. 2001 APInt TSize(First.getBitWidth(), 0); 2002 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2003 I!=E; ++I) 2004 TSize += I->size(); 2005 2006 APInt LSize = FrontCase.size(); 2007 APInt RSize = TSize-LSize; 2008 DEBUG(dbgs() << "Selecting best pivot: \n" 2009 << "First: " << First << ", Last: " << Last <<'\n' 2010 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2011 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2012 J!=E; ++I, ++J) { 2013 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2014 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2015 APInt Range = ComputeRange(LEnd, RBegin); 2016 assert((Range - 2ULL).isNonNegative() && 2017 "Invalid case distance"); 2018 double LDensity = (double)LSize.roundToDouble() / 2019 (LEnd - First + 1ULL).roundToDouble(); 2020 double RDensity = (double)RSize.roundToDouble() / 2021 (Last - RBegin + 1ULL).roundToDouble(); 2022 double Metric = Range.logBase2()*(LDensity+RDensity); 2023 // Should always split in some non-trivial place 2024 DEBUG(dbgs() <<"=>Step\n" 2025 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2026 << "LDensity: " << LDensity 2027 << ", RDensity: " << RDensity << '\n' 2028 << "Metric: " << Metric << '\n'); 2029 if (FMetric < Metric) { 2030 Pivot = J; 2031 FMetric = Metric; 2032 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2033 } 2034 2035 LSize += J->size(); 2036 RSize -= J->size(); 2037 } 2038 if (areJTsAllowed(TLI)) { 2039 // If our case is dense we *really* should handle it earlier! 2040 assert((FMetric > 0) && "Should handle dense range earlier!"); 2041 } else { 2042 Pivot = CR.Range.first + Size/2; 2043 } 2044 2045 CaseRange LHSR(CR.Range.first, Pivot); 2046 CaseRange RHSR(Pivot, CR.Range.second); 2047 Constant *C = Pivot->Low; 2048 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2049 2050 // We know that we branch to the LHS if the Value being switched on is 2051 // less than the Pivot value, C. We use this to optimize our binary 2052 // tree a bit, by recognizing that if SV is greater than or equal to the 2053 // LHS's Case Value, and that Case Value is exactly one less than the 2054 // Pivot's Value, then we can branch directly to the LHS's Target, 2055 // rather than creating a leaf node for it. 2056 if ((LHSR.second - LHSR.first) == 1 && 2057 LHSR.first->High == CR.GE && 2058 cast<ConstantInt>(C)->getValue() == 2059 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2060 TrueBB = LHSR.first->BB; 2061 } else { 2062 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2063 CurMF->insert(BBI, TrueBB); 2064 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2065 2066 // Put SV in a virtual register to make it available from the new blocks. 2067 ExportFromCurrentBlock(SV); 2068 } 2069 2070 // Similar to the optimization above, if the Value being switched on is 2071 // known to be less than the Constant CR.LT, and the current Case Value 2072 // is CR.LT - 1, then we can branch directly to the target block for 2073 // the current Case Value, rather than emitting a RHS leaf node for it. 2074 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2075 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2076 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2077 FalseBB = RHSR.first->BB; 2078 } else { 2079 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2080 CurMF->insert(BBI, FalseBB); 2081 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2082 2083 // Put SV in a virtual register to make it available from the new blocks. 2084 ExportFromCurrentBlock(SV); 2085 } 2086 2087 // Create a CaseBlock record representing a conditional branch to 2088 // the LHS node if the value being switched on SV is less than C. 2089 // Otherwise, branch to LHS. 2090 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2091 2092 if (CR.CaseBB == SwitchBB) 2093 visitSwitchCase(CB, SwitchBB); 2094 else 2095 SwitchCases.push_back(CB); 2096 2097 return true; 2098} 2099 2100/// handleBitTestsSwitchCase - if current case range has few destination and 2101/// range span less, than machine word bitwidth, encode case range into series 2102/// of masks and emit bit tests with these masks. 2103bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2104 CaseRecVector& WorkList, 2105 const Value* SV, 2106 MachineBasicBlock* Default, 2107 MachineBasicBlock *SwitchBB){ 2108 EVT PTy = TLI.getPointerTy(); 2109 unsigned IntPtrBits = PTy.getSizeInBits(); 2110 2111 Case& FrontCase = *CR.Range.first; 2112 Case& BackCase = *(CR.Range.second-1); 2113 2114 // Get the MachineFunction which holds the current MBB. This is used when 2115 // inserting any additional MBBs necessary to represent the switch. 2116 MachineFunction *CurMF = FuncInfo.MF; 2117 2118 // If target does not have legal shift left, do not emit bit tests at all. 2119 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2120 return false; 2121 2122 size_t numCmps = 0; 2123 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2124 I!=E; ++I) { 2125 // Single case counts one, case range - two. 2126 numCmps += (I->Low == I->High ? 1 : 2); 2127 } 2128 2129 // Count unique destinations 2130 SmallSet<MachineBasicBlock*, 4> Dests; 2131 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2132 Dests.insert(I->BB); 2133 if (Dests.size() > 3) 2134 // Don't bother the code below, if there are too much unique destinations 2135 return false; 2136 } 2137 DEBUG(dbgs() << "Total number of unique destinations: " 2138 << Dests.size() << '\n' 2139 << "Total number of comparisons: " << numCmps << '\n'); 2140 2141 // Compute span of values. 2142 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2143 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2144 APInt cmpRange = maxValue - minValue; 2145 2146 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2147 << "Low bound: " << minValue << '\n' 2148 << "High bound: " << maxValue << '\n'); 2149 2150 if (cmpRange.uge(IntPtrBits) || 2151 (!(Dests.size() == 1 && numCmps >= 3) && 2152 !(Dests.size() == 2 && numCmps >= 5) && 2153 !(Dests.size() >= 3 && numCmps >= 6))) 2154 return false; 2155 2156 DEBUG(dbgs() << "Emitting bit tests\n"); 2157 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2158 2159 // Optimize the case where all the case values fit in a 2160 // word without having to subtract minValue. In this case, 2161 // we can optimize away the subtraction. 2162 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2163 cmpRange = maxValue; 2164 } else { 2165 lowBound = minValue; 2166 } 2167 2168 CaseBitsVector CasesBits; 2169 unsigned i, count = 0; 2170 2171 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2172 MachineBasicBlock* Dest = I->BB; 2173 for (i = 0; i < count; ++i) 2174 if (Dest == CasesBits[i].BB) 2175 break; 2176 2177 if (i == count) { 2178 assert((count < 3) && "Too much destinations to test!"); 2179 CasesBits.push_back(CaseBits(0, Dest, 0)); 2180 count++; 2181 } 2182 2183 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2184 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2185 2186 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2187 uint64_t hi = (highValue - lowBound).getZExtValue(); 2188 2189 for (uint64_t j = lo; j <= hi; j++) { 2190 CasesBits[i].Mask |= 1ULL << j; 2191 CasesBits[i].Bits++; 2192 } 2193 2194 } 2195 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2196 2197 BitTestInfo BTC; 2198 2199 // Figure out which block is immediately after the current one. 2200 MachineFunction::iterator BBI = CR.CaseBB; 2201 ++BBI; 2202 2203 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2204 2205 DEBUG(dbgs() << "Cases:\n"); 2206 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2207 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2208 << ", Bits: " << CasesBits[i].Bits 2209 << ", BB: " << CasesBits[i].BB << '\n'); 2210 2211 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2212 CurMF->insert(BBI, CaseBB); 2213 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2214 CaseBB, 2215 CasesBits[i].BB)); 2216 2217 // Put SV in a virtual register to make it available from the new blocks. 2218 ExportFromCurrentBlock(SV); 2219 } 2220 2221 BitTestBlock BTB(lowBound, cmpRange, SV, 2222 -1U, (CR.CaseBB == SwitchBB), 2223 CR.CaseBB, Default, BTC); 2224 2225 if (CR.CaseBB == SwitchBB) 2226 visitBitTestHeader(BTB, SwitchBB); 2227 2228 BitTestCases.push_back(BTB); 2229 2230 return true; 2231} 2232 2233/// Clusterify - Transform simple list of Cases into list of CaseRange's 2234size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2235 const SwitchInst& SI) { 2236 size_t numCmps = 0; 2237 2238 // Start with "simple" cases 2239 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2240 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; 2241 Cases.push_back(Case(SI.getSuccessorValue(i), 2242 SI.getSuccessorValue(i), 2243 SMBB)); 2244 } 2245 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2246 2247 // Merge case into clusters 2248 if (Cases.size() >= 2) 2249 // Must recompute end() each iteration because it may be 2250 // invalidated by erase if we hold on to it 2251 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) { 2252 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2253 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2254 MachineBasicBlock* nextBB = J->BB; 2255 MachineBasicBlock* currentBB = I->BB; 2256 2257 // If the two neighboring cases go to the same destination, merge them 2258 // into a single case. 2259 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2260 I->High = J->High; 2261 J = Cases.erase(J); 2262 } else { 2263 I = J++; 2264 } 2265 } 2266 2267 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2268 if (I->Low != I->High) 2269 // A range counts double, since it requires two compares. 2270 ++numCmps; 2271 } 2272 2273 return numCmps; 2274} 2275 2276void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2277 MachineBasicBlock *Last) { 2278 // Update JTCases. 2279 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2280 if (JTCases[i].first.HeaderBB == First) 2281 JTCases[i].first.HeaderBB = Last; 2282 2283 // Update BitTestCases. 2284 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2285 if (BitTestCases[i].Parent == First) 2286 BitTestCases[i].Parent = Last; 2287} 2288 2289void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2290 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2291 2292 // Figure out which block is immediately after the current one. 2293 MachineBasicBlock *NextBlock = 0; 2294 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2295 2296 // If there is only the default destination, branch to it if it is not the 2297 // next basic block. Otherwise, just fall through. 2298 if (SI.getNumOperands() == 2) { 2299 // Update machine-CFG edges. 2300 2301 // If this is not a fall-through branch, emit the branch. 2302 SwitchMBB->addSuccessor(Default); 2303 if (Default != NextBlock) 2304 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2305 MVT::Other, getControlRoot(), 2306 DAG.getBasicBlock(Default))); 2307 2308 return; 2309 } 2310 2311 // If there are any non-default case statements, create a vector of Cases 2312 // representing each one, and sort the vector so that we can efficiently 2313 // create a binary search tree from them. 2314 CaseVector Cases; 2315 size_t numCmps = Clusterify(Cases, SI); 2316 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2317 << ". Total compares: " << numCmps << '\n'); 2318 numCmps = 0; 2319 2320 // Get the Value to be switched on and default basic blocks, which will be 2321 // inserted into CaseBlock records, representing basic blocks in the binary 2322 // search tree. 2323 const Value *SV = SI.getOperand(0); 2324 2325 // Push the initial CaseRec onto the worklist 2326 CaseRecVector WorkList; 2327 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2328 CaseRange(Cases.begin(),Cases.end()))); 2329 2330 while (!WorkList.empty()) { 2331 // Grab a record representing a case range to process off the worklist 2332 CaseRec CR = WorkList.back(); 2333 WorkList.pop_back(); 2334 2335 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2336 continue; 2337 2338 // If the range has few cases (two or less) emit a series of specific 2339 // tests. 2340 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2341 continue; 2342 2343 // If the switch has more than 5 blocks, and at least 40% dense, and the 2344 // target supports indirect branches, then emit a jump table rather than 2345 // lowering the switch to a binary tree of conditional branches. 2346 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2347 continue; 2348 2349 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2350 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2351 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2352 } 2353} 2354 2355void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2356 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2357 2358 // Update machine-CFG edges with unique successors. 2359 SmallVector<BasicBlock*, 32> succs; 2360 succs.reserve(I.getNumSuccessors()); 2361 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2362 succs.push_back(I.getSuccessor(i)); 2363 array_pod_sort(succs.begin(), succs.end()); 2364 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2365 for (unsigned i = 0, e = succs.size(); i != e; ++i) 2366 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]); 2367 2368 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2369 MVT::Other, getControlRoot(), 2370 getValue(I.getAddress()))); 2371} 2372 2373void SelectionDAGBuilder::visitFSub(const User &I) { 2374 // -0.0 - X --> fneg 2375 const Type *Ty = I.getType(); 2376 if (Ty->isVectorTy()) { 2377 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) { 2378 const VectorType *DestTy = cast<VectorType>(I.getType()); 2379 const Type *ElTy = DestTy->getElementType(); 2380 unsigned VL = DestTy->getNumElements(); 2381 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy)); 2382 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); 2383 if (CV == CNZ) { 2384 SDValue Op2 = getValue(I.getOperand(1)); 2385 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2386 Op2.getValueType(), Op2)); 2387 return; 2388 } 2389 } 2390 } 2391 2392 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) 2393 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { 2394 SDValue Op2 = getValue(I.getOperand(1)); 2395 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2396 Op2.getValueType(), Op2)); 2397 return; 2398 } 2399 2400 visitBinary(I, ISD::FSUB); 2401} 2402 2403void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2404 SDValue Op1 = getValue(I.getOperand(0)); 2405 SDValue Op2 = getValue(I.getOperand(1)); 2406 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2407 Op1.getValueType(), Op1, Op2)); 2408} 2409 2410void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2411 SDValue Op1 = getValue(I.getOperand(0)); 2412 SDValue Op2 = getValue(I.getOperand(1)); 2413 if (!I.getType()->isVectorTy() && 2414 Op2.getValueType() != TLI.getShiftAmountTy()) { 2415 // If the operand is smaller than the shift count type, promote it. 2416 EVT PTy = TLI.getPointerTy(); 2417 EVT STy = TLI.getShiftAmountTy(); 2418 if (STy.bitsGT(Op2.getValueType())) 2419 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2420 TLI.getShiftAmountTy(), Op2); 2421 // If the operand is larger than the shift count type but the shift 2422 // count type has enough bits to represent any shift value, truncate 2423 // it now. This is a common case and it exposes the truncate to 2424 // optimization early. 2425 else if (STy.getSizeInBits() >= 2426 Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2427 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2428 TLI.getShiftAmountTy(), Op2); 2429 // Otherwise we'll need to temporarily settle for some other 2430 // convenient type; type legalization will make adjustments as 2431 // needed. 2432 else if (PTy.bitsLT(Op2.getValueType())) 2433 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2434 TLI.getPointerTy(), Op2); 2435 else if (PTy.bitsGT(Op2.getValueType())) 2436 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), 2437 TLI.getPointerTy(), Op2); 2438 } 2439 2440 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2441 Op1.getValueType(), Op1, Op2)); 2442} 2443 2444void SelectionDAGBuilder::visitICmp(const User &I) { 2445 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2446 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2447 predicate = IC->getPredicate(); 2448 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2449 predicate = ICmpInst::Predicate(IC->getPredicate()); 2450 SDValue Op1 = getValue(I.getOperand(0)); 2451 SDValue Op2 = getValue(I.getOperand(1)); 2452 ISD::CondCode Opcode = getICmpCondCode(predicate); 2453 2454 EVT DestVT = TLI.getValueType(I.getType()); 2455 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2456} 2457 2458void SelectionDAGBuilder::visitFCmp(const User &I) { 2459 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2460 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2461 predicate = FC->getPredicate(); 2462 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2463 predicate = FCmpInst::Predicate(FC->getPredicate()); 2464 SDValue Op1 = getValue(I.getOperand(0)); 2465 SDValue Op2 = getValue(I.getOperand(1)); 2466 ISD::CondCode Condition = getFCmpCondCode(predicate); 2467 EVT DestVT = TLI.getValueType(I.getType()); 2468 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2469} 2470 2471void SelectionDAGBuilder::visitSelect(const User &I) { 2472 SmallVector<EVT, 4> ValueVTs; 2473 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2474 unsigned NumValues = ValueVTs.size(); 2475 if (NumValues == 0) return; 2476 2477 SmallVector<SDValue, 4> Values(NumValues); 2478 SDValue Cond = getValue(I.getOperand(0)); 2479 SDValue TrueVal = getValue(I.getOperand(1)); 2480 SDValue FalseVal = getValue(I.getOperand(2)); 2481 2482 for (unsigned i = 0; i != NumValues; ++i) 2483 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), 2484 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2485 Cond, 2486 SDValue(TrueVal.getNode(), 2487 TrueVal.getResNo() + i), 2488 SDValue(FalseVal.getNode(), 2489 FalseVal.getResNo() + i)); 2490 2491 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2492 DAG.getVTList(&ValueVTs[0], NumValues), 2493 &Values[0], NumValues)); 2494} 2495 2496void SelectionDAGBuilder::visitTrunc(const User &I) { 2497 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2498 SDValue N = getValue(I.getOperand(0)); 2499 EVT DestVT = TLI.getValueType(I.getType()); 2500 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2501} 2502 2503void SelectionDAGBuilder::visitZExt(const User &I) { 2504 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2505 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2506 SDValue N = getValue(I.getOperand(0)); 2507 EVT DestVT = TLI.getValueType(I.getType()); 2508 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2509} 2510 2511void SelectionDAGBuilder::visitSExt(const User &I) { 2512 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2513 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2514 SDValue N = getValue(I.getOperand(0)); 2515 EVT DestVT = TLI.getValueType(I.getType()); 2516 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2517} 2518 2519void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2520 // FPTrunc is never a no-op cast, no need to check 2521 SDValue N = getValue(I.getOperand(0)); 2522 EVT DestVT = TLI.getValueType(I.getType()); 2523 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2524 DestVT, N, DAG.getIntPtrConstant(0))); 2525} 2526 2527void SelectionDAGBuilder::visitFPExt(const User &I){ 2528 // FPTrunc is never a no-op cast, no need to check 2529 SDValue N = getValue(I.getOperand(0)); 2530 EVT DestVT = TLI.getValueType(I.getType()); 2531 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2532} 2533 2534void SelectionDAGBuilder::visitFPToUI(const User &I) { 2535 // FPToUI is never a no-op cast, no need to check 2536 SDValue N = getValue(I.getOperand(0)); 2537 EVT DestVT = TLI.getValueType(I.getType()); 2538 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2539} 2540 2541void SelectionDAGBuilder::visitFPToSI(const User &I) { 2542 // FPToSI is never a no-op cast, no need to check 2543 SDValue N = getValue(I.getOperand(0)); 2544 EVT DestVT = TLI.getValueType(I.getType()); 2545 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2546} 2547 2548void SelectionDAGBuilder::visitUIToFP(const User &I) { 2549 // UIToFP is never a no-op cast, no need to check 2550 SDValue N = getValue(I.getOperand(0)); 2551 EVT DestVT = TLI.getValueType(I.getType()); 2552 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2553} 2554 2555void SelectionDAGBuilder::visitSIToFP(const User &I){ 2556 // SIToFP is never a no-op cast, no need to check 2557 SDValue N = getValue(I.getOperand(0)); 2558 EVT DestVT = TLI.getValueType(I.getType()); 2559 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2560} 2561 2562void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2563 // What to do depends on the size of the integer and the size of the pointer. 2564 // We can either truncate, zero extend, or no-op, accordingly. 2565 SDValue N = getValue(I.getOperand(0)); 2566 EVT DestVT = TLI.getValueType(I.getType()); 2567 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2568} 2569 2570void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2571 // What to do depends on the size of the integer and the size of the pointer. 2572 // We can either truncate, zero extend, or no-op, accordingly. 2573 SDValue N = getValue(I.getOperand(0)); 2574 EVT DestVT = TLI.getValueType(I.getType()); 2575 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2576} 2577 2578void SelectionDAGBuilder::visitBitCast(const User &I) { 2579 SDValue N = getValue(I.getOperand(0)); 2580 EVT DestVT = TLI.getValueType(I.getType()); 2581 2582 // BitCast assures us that source and destination are the same size so this is 2583 // either a BITCAST or a no-op. 2584 if (DestVT != N.getValueType()) 2585 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2586 DestVT, N)); // convert types. 2587 else 2588 setValue(&I, N); // noop cast. 2589} 2590 2591void SelectionDAGBuilder::visitInsertElement(const User &I) { 2592 SDValue InVec = getValue(I.getOperand(0)); 2593 SDValue InVal = getValue(I.getOperand(1)); 2594 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2595 TLI.getPointerTy(), 2596 getValue(I.getOperand(2))); 2597 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2598 TLI.getValueType(I.getType()), 2599 InVec, InVal, InIdx)); 2600} 2601 2602void SelectionDAGBuilder::visitExtractElement(const User &I) { 2603 SDValue InVec = getValue(I.getOperand(0)); 2604 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2605 TLI.getPointerTy(), 2606 getValue(I.getOperand(1))); 2607 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2608 TLI.getValueType(I.getType()), InVec, InIdx)); 2609} 2610 2611// Utility for visitShuffleVector - Returns true if the mask is mask starting 2612// from SIndx and increasing to the element length (undefs are allowed). 2613static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2614 unsigned MaskNumElts = Mask.size(); 2615 for (unsigned i = 0; i != MaskNumElts; ++i) 2616 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2617 return false; 2618 return true; 2619} 2620 2621void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2622 SmallVector<int, 8> Mask; 2623 SDValue Src1 = getValue(I.getOperand(0)); 2624 SDValue Src2 = getValue(I.getOperand(1)); 2625 2626 // Convert the ConstantVector mask operand into an array of ints, with -1 2627 // representing undef values. 2628 SmallVector<Constant*, 8> MaskElts; 2629 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2630 unsigned MaskNumElts = MaskElts.size(); 2631 for (unsigned i = 0; i != MaskNumElts; ++i) { 2632 if (isa<UndefValue>(MaskElts[i])) 2633 Mask.push_back(-1); 2634 else 2635 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2636 } 2637 2638 EVT VT = TLI.getValueType(I.getType()); 2639 EVT SrcVT = Src1.getValueType(); 2640 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2641 2642 if (SrcNumElts == MaskNumElts) { 2643 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2644 &Mask[0])); 2645 return; 2646 } 2647 2648 // Normalize the shuffle vector since mask and vector length don't match. 2649 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2650 // Mask is longer than the source vectors and is a multiple of the source 2651 // vectors. We can use concatenate vector to make the mask and vectors 2652 // lengths match. 2653 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2654 // The shuffle is concatenating two vectors together. 2655 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2656 VT, Src1, Src2)); 2657 return; 2658 } 2659 2660 // Pad both vectors with undefs to make them the same length as the mask. 2661 unsigned NumConcat = MaskNumElts / SrcNumElts; 2662 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2663 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2664 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2665 2666 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2667 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2668 MOps1[0] = Src1; 2669 MOps2[0] = Src2; 2670 2671 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2672 getCurDebugLoc(), VT, 2673 &MOps1[0], NumConcat); 2674 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2675 getCurDebugLoc(), VT, 2676 &MOps2[0], NumConcat); 2677 2678 // Readjust mask for new input vector length. 2679 SmallVector<int, 8> MappedOps; 2680 for (unsigned i = 0; i != MaskNumElts; ++i) { 2681 int Idx = Mask[i]; 2682 if (Idx < (int)SrcNumElts) 2683 MappedOps.push_back(Idx); 2684 else 2685 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2686 } 2687 2688 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2689 &MappedOps[0])); 2690 return; 2691 } 2692 2693 if (SrcNumElts > MaskNumElts) { 2694 // Analyze the access pattern of the vector to see if we can extract 2695 // two subvectors and do the shuffle. The analysis is done by calculating 2696 // the range of elements the mask access on both vectors. 2697 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1}; 2698 int MaxRange[2] = {-1, -1}; 2699 2700 for (unsigned i = 0; i != MaskNumElts; ++i) { 2701 int Idx = Mask[i]; 2702 int Input = 0; 2703 if (Idx < 0) 2704 continue; 2705 2706 if (Idx >= (int)SrcNumElts) { 2707 Input = 1; 2708 Idx -= SrcNumElts; 2709 } 2710 if (Idx > MaxRange[Input]) 2711 MaxRange[Input] = Idx; 2712 if (Idx < MinRange[Input]) 2713 MinRange[Input] = Idx; 2714 } 2715 2716 // Check if the access is smaller than the vector size and can we find 2717 // a reasonable extract index. 2718 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2719 // Extract. 2720 int StartIdx[2]; // StartIdx to extract from 2721 for (int Input=0; Input < 2; ++Input) { 2722 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2723 RangeUse[Input] = 0; // Unused 2724 StartIdx[Input] = 0; 2725 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2726 // Fits within range but we should see if we can find a good 2727 // start index that is a multiple of the mask length. 2728 if (MaxRange[Input] < (int)MaskNumElts) { 2729 RangeUse[Input] = 1; // Extract from beginning of the vector 2730 StartIdx[Input] = 0; 2731 } else { 2732 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2733 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2734 StartIdx[Input] + MaskNumElts < SrcNumElts) 2735 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2736 } 2737 } 2738 } 2739 2740 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2741 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2742 return; 2743 } 2744 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2745 // Extract appropriate subvector and generate a vector shuffle 2746 for (int Input=0; Input < 2; ++Input) { 2747 SDValue &Src = Input == 0 ? Src1 : Src2; 2748 if (RangeUse[Input] == 0) 2749 Src = DAG.getUNDEF(VT); 2750 else 2751 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2752 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2753 } 2754 2755 // Calculate new mask. 2756 SmallVector<int, 8> MappedOps; 2757 for (unsigned i = 0; i != MaskNumElts; ++i) { 2758 int Idx = Mask[i]; 2759 if (Idx < 0) 2760 MappedOps.push_back(Idx); 2761 else if (Idx < (int)SrcNumElts) 2762 MappedOps.push_back(Idx - StartIdx[0]); 2763 else 2764 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2765 } 2766 2767 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2768 &MappedOps[0])); 2769 return; 2770 } 2771 } 2772 2773 // We can't use either concat vectors or extract subvectors so fall back to 2774 // replacing the shuffle with extract and build vector. 2775 // to insert and build vector. 2776 EVT EltVT = VT.getVectorElementType(); 2777 EVT PtrVT = TLI.getPointerTy(); 2778 SmallVector<SDValue,8> Ops; 2779 for (unsigned i = 0; i != MaskNumElts; ++i) { 2780 if (Mask[i] < 0) { 2781 Ops.push_back(DAG.getUNDEF(EltVT)); 2782 } else { 2783 int Idx = Mask[i]; 2784 SDValue Res; 2785 2786 if (Idx < (int)SrcNumElts) 2787 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2788 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2789 else 2790 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2791 EltVT, Src2, 2792 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2793 2794 Ops.push_back(Res); 2795 } 2796 } 2797 2798 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2799 VT, &Ops[0], Ops.size())); 2800} 2801 2802void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2803 const Value *Op0 = I.getOperand(0); 2804 const Value *Op1 = I.getOperand(1); 2805 const Type *AggTy = I.getType(); 2806 const Type *ValTy = Op1->getType(); 2807 bool IntoUndef = isa<UndefValue>(Op0); 2808 bool FromUndef = isa<UndefValue>(Op1); 2809 2810 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2811 2812 SmallVector<EVT, 4> AggValueVTs; 2813 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2814 SmallVector<EVT, 4> ValValueVTs; 2815 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2816 2817 unsigned NumAggValues = AggValueVTs.size(); 2818 unsigned NumValValues = ValValueVTs.size(); 2819 SmallVector<SDValue, 4> Values(NumAggValues); 2820 2821 SDValue Agg = getValue(Op0); 2822 SDValue Val = getValue(Op1); 2823 unsigned i = 0; 2824 // Copy the beginning value(s) from the original aggregate. 2825 for (; i != LinearIndex; ++i) 2826 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2827 SDValue(Agg.getNode(), Agg.getResNo() + i); 2828 // Copy values from the inserted value(s). 2829 for (; i != LinearIndex + NumValValues; ++i) 2830 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2831 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2832 // Copy remaining value(s) from the original aggregate. 2833 for (; i != NumAggValues; ++i) 2834 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2835 SDValue(Agg.getNode(), Agg.getResNo() + i); 2836 2837 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2838 DAG.getVTList(&AggValueVTs[0], NumAggValues), 2839 &Values[0], NumAggValues)); 2840} 2841 2842void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 2843 const Value *Op0 = I.getOperand(0); 2844 const Type *AggTy = Op0->getType(); 2845 const Type *ValTy = I.getType(); 2846 bool OutOfUndef = isa<UndefValue>(Op0); 2847 2848 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end()); 2849 2850 SmallVector<EVT, 4> ValValueVTs; 2851 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2852 2853 unsigned NumValValues = ValValueVTs.size(); 2854 SmallVector<SDValue, 4> Values(NumValValues); 2855 2856 SDValue Agg = getValue(Op0); 2857 // Copy out the selected value(s). 2858 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 2859 Values[i - LinearIndex] = 2860 OutOfUndef ? 2861 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 2862 SDValue(Agg.getNode(), Agg.getResNo() + i); 2863 2864 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2865 DAG.getVTList(&ValValueVTs[0], NumValValues), 2866 &Values[0], NumValValues)); 2867} 2868 2869void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 2870 SDValue N = getValue(I.getOperand(0)); 2871 const Type *Ty = I.getOperand(0)->getType(); 2872 2873 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 2874 OI != E; ++OI) { 2875 const Value *Idx = *OI; 2876 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 2877 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 2878 if (Field) { 2879 // N = N + Offset 2880 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 2881 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2882 DAG.getIntPtrConstant(Offset)); 2883 } 2884 2885 Ty = StTy->getElementType(Field); 2886 } else { 2887 Ty = cast<SequentialType>(Ty)->getElementType(); 2888 2889 // If this is a constant subscript, handle it quickly. 2890 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 2891 if (CI->isZero()) continue; 2892 uint64_t Offs = 2893 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 2894 SDValue OffsVal; 2895 EVT PTy = TLI.getPointerTy(); 2896 unsigned PtrBits = PTy.getSizeInBits(); 2897 if (PtrBits < 64) 2898 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 2899 TLI.getPointerTy(), 2900 DAG.getConstant(Offs, MVT::i64)); 2901 else 2902 OffsVal = DAG.getIntPtrConstant(Offs); 2903 2904 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 2905 OffsVal); 2906 continue; 2907 } 2908 2909 // N = N + Idx * ElementSize; 2910 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 2911 TD->getTypeAllocSize(Ty)); 2912 SDValue IdxN = getValue(Idx); 2913 2914 // If the index is smaller or larger than intptr_t, truncate or extend 2915 // it. 2916 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 2917 2918 // If this is a multiply by a power of two, turn it into a shl 2919 // immediately. This is a very common case. 2920 if (ElementSize != 1) { 2921 if (ElementSize.isPowerOf2()) { 2922 unsigned Amt = ElementSize.logBase2(); 2923 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 2924 N.getValueType(), IdxN, 2925 DAG.getConstant(Amt, TLI.getPointerTy())); 2926 } else { 2927 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 2928 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 2929 N.getValueType(), IdxN, Scale); 2930 } 2931 } 2932 2933 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2934 N.getValueType(), N, IdxN); 2935 } 2936 } 2937 2938 setValue(&I, N); 2939} 2940 2941void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 2942 // If this is a fixed sized alloca in the entry block of the function, 2943 // allocate it statically on the stack. 2944 if (FuncInfo.StaticAllocaMap.count(&I)) 2945 return; // getValue will auto-populate this. 2946 2947 const Type *Ty = I.getAllocatedType(); 2948 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 2949 unsigned Align = 2950 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 2951 I.getAlignment()); 2952 2953 SDValue AllocSize = getValue(I.getArraySize()); 2954 2955 EVT IntPtr = TLI.getPointerTy(); 2956 if (AllocSize.getValueType() != IntPtr) 2957 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 2958 2959 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 2960 AllocSize, 2961 DAG.getConstant(TySize, IntPtr)); 2962 2963 // Handle alignment. If the requested alignment is less than or equal to 2964 // the stack alignment, ignore it. If the size is greater than or equal to 2965 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 2966 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 2967 if (Align <= StackAlign) 2968 Align = 0; 2969 2970 // Round the size of the allocation up to the stack alignment size 2971 // by add SA-1 to the size. 2972 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 2973 AllocSize.getValueType(), AllocSize, 2974 DAG.getIntPtrConstant(StackAlign-1)); 2975 2976 // Mask out the low bits for alignment purposes. 2977 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 2978 AllocSize.getValueType(), AllocSize, 2979 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 2980 2981 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 2982 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 2983 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 2984 VTs, Ops, 3); 2985 setValue(&I, DSA); 2986 DAG.setRoot(DSA.getValue(1)); 2987 2988 // Inform the Frame Information that we have just allocated a variable-sized 2989 // object. 2990 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 2991} 2992 2993void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 2994 const Value *SV = I.getOperand(0); 2995 SDValue Ptr = getValue(SV); 2996 2997 const Type *Ty = I.getType(); 2998 2999 bool isVolatile = I.isVolatile(); 3000 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3001 unsigned Alignment = I.getAlignment(); 3002 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3003 3004 SmallVector<EVT, 4> ValueVTs; 3005 SmallVector<uint64_t, 4> Offsets; 3006 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3007 unsigned NumValues = ValueVTs.size(); 3008 if (NumValues == 0) 3009 return; 3010 3011 SDValue Root; 3012 bool ConstantMemory = false; 3013 if (I.isVolatile() || NumValues > MaxParallelChains) 3014 // Serialize volatile loads with other side effects. 3015 Root = getRoot(); 3016 else if (AA->pointsToConstantMemory( 3017 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3018 // Do not serialize (non-volatile) loads of constant memory with anything. 3019 Root = DAG.getEntryNode(); 3020 ConstantMemory = true; 3021 } else { 3022 // Do not serialize non-volatile loads against each other. 3023 Root = DAG.getRoot(); 3024 } 3025 3026 SmallVector<SDValue, 4> Values(NumValues); 3027 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3028 NumValues)); 3029 EVT PtrVT = Ptr.getValueType(); 3030 unsigned ChainI = 0; 3031 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3032 // Serializing loads here may result in excessive register pressure, and 3033 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3034 // could recover a bit by hoisting nodes upward in the chain by recognizing 3035 // they are side-effect free or do not alias. The optimizer should really 3036 // avoid this case by converting large object/array copies to llvm.memcpy 3037 // (MaxParallelChains should always remain as failsafe). 3038 if (ChainI == MaxParallelChains) { 3039 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3040 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3041 MVT::Other, &Chains[0], ChainI); 3042 Root = Chain; 3043 ChainI = 0; 3044 } 3045 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3046 PtrVT, Ptr, 3047 DAG.getConstant(Offsets[i], PtrVT)); 3048 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3049 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3050 isNonTemporal, Alignment, TBAAInfo); 3051 3052 Values[i] = L; 3053 Chains[ChainI] = L.getValue(1); 3054 } 3055 3056 if (!ConstantMemory) { 3057 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3058 MVT::Other, &Chains[0], ChainI); 3059 if (isVolatile) 3060 DAG.setRoot(Chain); 3061 else 3062 PendingLoads.push_back(Chain); 3063 } 3064 3065 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3066 DAG.getVTList(&ValueVTs[0], NumValues), 3067 &Values[0], NumValues)); 3068} 3069 3070void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3071 const Value *SrcV = I.getOperand(0); 3072 const Value *PtrV = I.getOperand(1); 3073 3074 SmallVector<EVT, 4> ValueVTs; 3075 SmallVector<uint64_t, 4> Offsets; 3076 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3077 unsigned NumValues = ValueVTs.size(); 3078 if (NumValues == 0) 3079 return; 3080 3081 // Get the lowered operands. Note that we do this after 3082 // checking if NumResults is zero, because with zero results 3083 // the operands won't have values in the map. 3084 SDValue Src = getValue(SrcV); 3085 SDValue Ptr = getValue(PtrV); 3086 3087 SDValue Root = getRoot(); 3088 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3089 NumValues)); 3090 EVT PtrVT = Ptr.getValueType(); 3091 bool isVolatile = I.isVolatile(); 3092 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3093 unsigned Alignment = I.getAlignment(); 3094 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3095 3096 unsigned ChainI = 0; 3097 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3098 // See visitLoad comments. 3099 if (ChainI == MaxParallelChains) { 3100 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3101 MVT::Other, &Chains[0], ChainI); 3102 Root = Chain; 3103 ChainI = 0; 3104 } 3105 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3106 DAG.getConstant(Offsets[i], PtrVT)); 3107 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3108 SDValue(Src.getNode(), Src.getResNo() + i), 3109 Add, MachinePointerInfo(PtrV, Offsets[i]), 3110 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3111 Chains[ChainI] = St; 3112 } 3113 3114 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3115 MVT::Other, &Chains[0], ChainI); 3116 ++SDNodeOrder; 3117 AssignOrderingToNode(StoreNode.getNode()); 3118 DAG.setRoot(StoreNode); 3119} 3120 3121/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3122/// node. 3123void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3124 unsigned Intrinsic) { 3125 bool HasChain = !I.doesNotAccessMemory(); 3126 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3127 3128 // Build the operand list. 3129 SmallVector<SDValue, 8> Ops; 3130 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3131 if (OnlyLoad) { 3132 // We don't need to serialize loads against other loads. 3133 Ops.push_back(DAG.getRoot()); 3134 } else { 3135 Ops.push_back(getRoot()); 3136 } 3137 } 3138 3139 // Info is set by getTgtMemInstrinsic 3140 TargetLowering::IntrinsicInfo Info; 3141 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3142 3143 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3144 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3145 Info.opc == ISD::INTRINSIC_W_CHAIN) 3146 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3147 3148 // Add all operands of the call to the operand list. 3149 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3150 SDValue Op = getValue(I.getArgOperand(i)); 3151 assert(TLI.isTypeLegal(Op.getValueType()) && 3152 "Intrinsic uses a non-legal type?"); 3153 Ops.push_back(Op); 3154 } 3155 3156 SmallVector<EVT, 4> ValueVTs; 3157 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3158#ifndef NDEBUG 3159 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3160 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3161 "Intrinsic uses a non-legal type?"); 3162 } 3163#endif // NDEBUG 3164 3165 if (HasChain) 3166 ValueVTs.push_back(MVT::Other); 3167 3168 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3169 3170 // Create the node. 3171 SDValue Result; 3172 if (IsTgtIntrinsic) { 3173 // This is target intrinsic that touches memory 3174 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3175 VTs, &Ops[0], Ops.size(), 3176 Info.memVT, 3177 MachinePointerInfo(Info.ptrVal, Info.offset), 3178 Info.align, Info.vol, 3179 Info.readMem, Info.writeMem); 3180 } else if (!HasChain) { 3181 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3182 VTs, &Ops[0], Ops.size()); 3183 } else if (!I.getType()->isVoidTy()) { 3184 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3185 VTs, &Ops[0], Ops.size()); 3186 } else { 3187 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3188 VTs, &Ops[0], Ops.size()); 3189 } 3190 3191 if (HasChain) { 3192 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3193 if (OnlyLoad) 3194 PendingLoads.push_back(Chain); 3195 else 3196 DAG.setRoot(Chain); 3197 } 3198 3199 if (!I.getType()->isVoidTy()) { 3200 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3201 EVT VT = TLI.getValueType(PTy); 3202 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3203 } 3204 3205 setValue(&I, Result); 3206 } 3207} 3208 3209/// GetSignificand - Get the significand and build it into a floating-point 3210/// number with exponent of 1: 3211/// 3212/// Op = (Op & 0x007fffff) | 0x3f800000; 3213/// 3214/// where Op is the hexidecimal representation of floating point value. 3215static SDValue 3216GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3217 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3218 DAG.getConstant(0x007fffff, MVT::i32)); 3219 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3220 DAG.getConstant(0x3f800000, MVT::i32)); 3221 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3222} 3223 3224/// GetExponent - Get the exponent: 3225/// 3226/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3227/// 3228/// where Op is the hexidecimal representation of floating point value. 3229static SDValue 3230GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3231 DebugLoc dl) { 3232 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3233 DAG.getConstant(0x7f800000, MVT::i32)); 3234 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3235 DAG.getConstant(23, TLI.getPointerTy())); 3236 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3237 DAG.getConstant(127, MVT::i32)); 3238 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3239} 3240 3241/// getF32Constant - Get 32-bit floating point constant. 3242static SDValue 3243getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3244 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3245} 3246 3247/// Inlined utility function to implement binary input atomic intrinsics for 3248/// visitIntrinsicCall: I is a call instruction 3249/// Op is the associated NodeType for I 3250const char * 3251SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I, 3252 ISD::NodeType Op) { 3253 SDValue Root = getRoot(); 3254 SDValue L = 3255 DAG.getAtomic(Op, getCurDebugLoc(), 3256 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 3257 Root, 3258 getValue(I.getArgOperand(0)), 3259 getValue(I.getArgOperand(1)), 3260 I.getArgOperand(0)); 3261 setValue(&I, L); 3262 DAG.setRoot(L.getValue(1)); 3263 return 0; 3264} 3265 3266// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3267const char * 3268SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3269 SDValue Op1 = getValue(I.getArgOperand(0)); 3270 SDValue Op2 = getValue(I.getArgOperand(1)); 3271 3272 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3273 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3274 return 0; 3275} 3276 3277/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3278/// limited-precision mode. 3279void 3280SelectionDAGBuilder::visitExp(const CallInst &I) { 3281 SDValue result; 3282 DebugLoc dl = getCurDebugLoc(); 3283 3284 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3285 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3286 SDValue Op = getValue(I.getArgOperand(0)); 3287 3288 // Put the exponent in the right bit position for later addition to the 3289 // final result: 3290 // 3291 // #define LOG2OFe 1.4426950f 3292 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3293 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3294 getF32Constant(DAG, 0x3fb8aa3b)); 3295 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3296 3297 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3298 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3299 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3300 3301 // IntegerPartOfX <<= 23; 3302 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3303 DAG.getConstant(23, TLI.getPointerTy())); 3304 3305 if (LimitFloatPrecision <= 6) { 3306 // For floating-point precision of 6: 3307 // 3308 // TwoToFractionalPartOfX = 3309 // 0.997535578f + 3310 // (0.735607626f + 0.252464424f * x) * x; 3311 // 3312 // error 0.0144103317, which is 6 bits 3313 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3314 getF32Constant(DAG, 0x3e814304)); 3315 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3316 getF32Constant(DAG, 0x3f3c50c8)); 3317 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3318 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3319 getF32Constant(DAG, 0x3f7f5e7e)); 3320 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3321 3322 // Add the exponent into the result in integer domain. 3323 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3324 TwoToFracPartOfX, IntegerPartOfX); 3325 3326 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3327 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3328 // For floating-point precision of 12: 3329 // 3330 // TwoToFractionalPartOfX = 3331 // 0.999892986f + 3332 // (0.696457318f + 3333 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3334 // 3335 // 0.000107046256 error, which is 13 to 14 bits 3336 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3337 getF32Constant(DAG, 0x3da235e3)); 3338 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3339 getF32Constant(DAG, 0x3e65b8f3)); 3340 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3341 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3342 getF32Constant(DAG, 0x3f324b07)); 3343 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3344 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3345 getF32Constant(DAG, 0x3f7ff8fd)); 3346 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3347 3348 // Add the exponent into the result in integer domain. 3349 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3350 TwoToFracPartOfX, IntegerPartOfX); 3351 3352 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3353 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3354 // For floating-point precision of 18: 3355 // 3356 // TwoToFractionalPartOfX = 3357 // 0.999999982f + 3358 // (0.693148872f + 3359 // (0.240227044f + 3360 // (0.554906021e-1f + 3361 // (0.961591928e-2f + 3362 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3363 // 3364 // error 2.47208000*10^(-7), which is better than 18 bits 3365 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3366 getF32Constant(DAG, 0x3924b03e)); 3367 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3368 getF32Constant(DAG, 0x3ab24b87)); 3369 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3370 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3371 getF32Constant(DAG, 0x3c1d8c17)); 3372 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3373 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3374 getF32Constant(DAG, 0x3d634a1d)); 3375 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3376 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3377 getF32Constant(DAG, 0x3e75fe14)); 3378 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3379 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3380 getF32Constant(DAG, 0x3f317234)); 3381 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3382 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3383 getF32Constant(DAG, 0x3f800000)); 3384 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3385 MVT::i32, t13); 3386 3387 // Add the exponent into the result in integer domain. 3388 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3389 TwoToFracPartOfX, IntegerPartOfX); 3390 3391 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3392 } 3393 } else { 3394 // No special expansion. 3395 result = DAG.getNode(ISD::FEXP, dl, 3396 getValue(I.getArgOperand(0)).getValueType(), 3397 getValue(I.getArgOperand(0))); 3398 } 3399 3400 setValue(&I, result); 3401} 3402 3403/// visitLog - Lower a log intrinsic. Handles the special sequences for 3404/// limited-precision mode. 3405void 3406SelectionDAGBuilder::visitLog(const CallInst &I) { 3407 SDValue result; 3408 DebugLoc dl = getCurDebugLoc(); 3409 3410 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3411 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3412 SDValue Op = getValue(I.getArgOperand(0)); 3413 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3414 3415 // Scale the exponent by log(2) [0.69314718f]. 3416 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3417 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3418 getF32Constant(DAG, 0x3f317218)); 3419 3420 // Get the significand and build it into a floating-point number with 3421 // exponent of 1. 3422 SDValue X = GetSignificand(DAG, Op1, dl); 3423 3424 if (LimitFloatPrecision <= 6) { 3425 // For floating-point precision of 6: 3426 // 3427 // LogofMantissa = 3428 // -1.1609546f + 3429 // (1.4034025f - 0.23903021f * x) * x; 3430 // 3431 // error 0.0034276066, which is better than 8 bits 3432 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3433 getF32Constant(DAG, 0xbe74c456)); 3434 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3435 getF32Constant(DAG, 0x3fb3a2b1)); 3436 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3437 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3438 getF32Constant(DAG, 0x3f949a29)); 3439 3440 result = DAG.getNode(ISD::FADD, dl, 3441 MVT::f32, LogOfExponent, LogOfMantissa); 3442 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3443 // For floating-point precision of 12: 3444 // 3445 // LogOfMantissa = 3446 // -1.7417939f + 3447 // (2.8212026f + 3448 // (-1.4699568f + 3449 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3450 // 3451 // error 0.000061011436, which is 14 bits 3452 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3453 getF32Constant(DAG, 0xbd67b6d6)); 3454 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3455 getF32Constant(DAG, 0x3ee4f4b8)); 3456 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3457 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3458 getF32Constant(DAG, 0x3fbc278b)); 3459 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3460 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3461 getF32Constant(DAG, 0x40348e95)); 3462 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3463 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3464 getF32Constant(DAG, 0x3fdef31a)); 3465 3466 result = DAG.getNode(ISD::FADD, dl, 3467 MVT::f32, LogOfExponent, LogOfMantissa); 3468 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3469 // For floating-point precision of 18: 3470 // 3471 // LogOfMantissa = 3472 // -2.1072184f + 3473 // (4.2372794f + 3474 // (-3.7029485f + 3475 // (2.2781945f + 3476 // (-0.87823314f + 3477 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3478 // 3479 // error 0.0000023660568, which is better than 18 bits 3480 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3481 getF32Constant(DAG, 0xbc91e5ac)); 3482 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3483 getF32Constant(DAG, 0x3e4350aa)); 3484 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3485 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3486 getF32Constant(DAG, 0x3f60d3e3)); 3487 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3488 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3489 getF32Constant(DAG, 0x4011cdf0)); 3490 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3491 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3492 getF32Constant(DAG, 0x406cfd1c)); 3493 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3494 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3495 getF32Constant(DAG, 0x408797cb)); 3496 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3497 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3498 getF32Constant(DAG, 0x4006dcab)); 3499 3500 result = DAG.getNode(ISD::FADD, dl, 3501 MVT::f32, LogOfExponent, LogOfMantissa); 3502 } 3503 } else { 3504 // No special expansion. 3505 result = DAG.getNode(ISD::FLOG, dl, 3506 getValue(I.getArgOperand(0)).getValueType(), 3507 getValue(I.getArgOperand(0))); 3508 } 3509 3510 setValue(&I, result); 3511} 3512 3513/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3514/// limited-precision mode. 3515void 3516SelectionDAGBuilder::visitLog2(const CallInst &I) { 3517 SDValue result; 3518 DebugLoc dl = getCurDebugLoc(); 3519 3520 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3521 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3522 SDValue Op = getValue(I.getArgOperand(0)); 3523 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3524 3525 // Get the exponent. 3526 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3527 3528 // Get the significand and build it into a floating-point number with 3529 // exponent of 1. 3530 SDValue X = GetSignificand(DAG, Op1, dl); 3531 3532 // Different possible minimax approximations of significand in 3533 // floating-point for various degrees of accuracy over [1,2]. 3534 if (LimitFloatPrecision <= 6) { 3535 // For floating-point precision of 6: 3536 // 3537 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3538 // 3539 // error 0.0049451742, which is more than 7 bits 3540 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3541 getF32Constant(DAG, 0xbeb08fe0)); 3542 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3543 getF32Constant(DAG, 0x40019463)); 3544 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3545 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3546 getF32Constant(DAG, 0x3fd6633d)); 3547 3548 result = DAG.getNode(ISD::FADD, dl, 3549 MVT::f32, LogOfExponent, Log2ofMantissa); 3550 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3551 // For floating-point precision of 12: 3552 // 3553 // Log2ofMantissa = 3554 // -2.51285454f + 3555 // (4.07009056f + 3556 // (-2.12067489f + 3557 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3558 // 3559 // error 0.0000876136000, which is better than 13 bits 3560 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3561 getF32Constant(DAG, 0xbda7262e)); 3562 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3563 getF32Constant(DAG, 0x3f25280b)); 3564 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3565 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3566 getF32Constant(DAG, 0x4007b923)); 3567 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3568 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3569 getF32Constant(DAG, 0x40823e2f)); 3570 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3571 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3572 getF32Constant(DAG, 0x4020d29c)); 3573 3574 result = DAG.getNode(ISD::FADD, dl, 3575 MVT::f32, LogOfExponent, Log2ofMantissa); 3576 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3577 // For floating-point precision of 18: 3578 // 3579 // Log2ofMantissa = 3580 // -3.0400495f + 3581 // (6.1129976f + 3582 // (-5.3420409f + 3583 // (3.2865683f + 3584 // (-1.2669343f + 3585 // (0.27515199f - 3586 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3587 // 3588 // error 0.0000018516, which is better than 18 bits 3589 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3590 getF32Constant(DAG, 0xbcd2769e)); 3591 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3592 getF32Constant(DAG, 0x3e8ce0b9)); 3593 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3594 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3595 getF32Constant(DAG, 0x3fa22ae7)); 3596 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3597 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3598 getF32Constant(DAG, 0x40525723)); 3599 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3600 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3601 getF32Constant(DAG, 0x40aaf200)); 3602 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3603 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3604 getF32Constant(DAG, 0x40c39dad)); 3605 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3606 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3607 getF32Constant(DAG, 0x4042902c)); 3608 3609 result = DAG.getNode(ISD::FADD, dl, 3610 MVT::f32, LogOfExponent, Log2ofMantissa); 3611 } 3612 } else { 3613 // No special expansion. 3614 result = DAG.getNode(ISD::FLOG2, dl, 3615 getValue(I.getArgOperand(0)).getValueType(), 3616 getValue(I.getArgOperand(0))); 3617 } 3618 3619 setValue(&I, result); 3620} 3621 3622/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3623/// limited-precision mode. 3624void 3625SelectionDAGBuilder::visitLog10(const CallInst &I) { 3626 SDValue result; 3627 DebugLoc dl = getCurDebugLoc(); 3628 3629 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3630 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3631 SDValue Op = getValue(I.getArgOperand(0)); 3632 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3633 3634 // Scale the exponent by log10(2) [0.30102999f]. 3635 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3636 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3637 getF32Constant(DAG, 0x3e9a209a)); 3638 3639 // Get the significand and build it into a floating-point number with 3640 // exponent of 1. 3641 SDValue X = GetSignificand(DAG, Op1, dl); 3642 3643 if (LimitFloatPrecision <= 6) { 3644 // For floating-point precision of 6: 3645 // 3646 // Log10ofMantissa = 3647 // -0.50419619f + 3648 // (0.60948995f - 0.10380950f * x) * x; 3649 // 3650 // error 0.0014886165, which is 6 bits 3651 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3652 getF32Constant(DAG, 0xbdd49a13)); 3653 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3654 getF32Constant(DAG, 0x3f1c0789)); 3655 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3656 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3657 getF32Constant(DAG, 0x3f011300)); 3658 3659 result = DAG.getNode(ISD::FADD, dl, 3660 MVT::f32, LogOfExponent, Log10ofMantissa); 3661 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3662 // For floating-point precision of 12: 3663 // 3664 // Log10ofMantissa = 3665 // -0.64831180f + 3666 // (0.91751397f + 3667 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3668 // 3669 // error 0.00019228036, which is better than 12 bits 3670 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3671 getF32Constant(DAG, 0x3d431f31)); 3672 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3673 getF32Constant(DAG, 0x3ea21fb2)); 3674 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3675 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3676 getF32Constant(DAG, 0x3f6ae232)); 3677 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3678 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3679 getF32Constant(DAG, 0x3f25f7c3)); 3680 3681 result = DAG.getNode(ISD::FADD, dl, 3682 MVT::f32, LogOfExponent, Log10ofMantissa); 3683 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3684 // For floating-point precision of 18: 3685 // 3686 // Log10ofMantissa = 3687 // -0.84299375f + 3688 // (1.5327582f + 3689 // (-1.0688956f + 3690 // (0.49102474f + 3691 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 3692 // 3693 // error 0.0000037995730, which is better than 18 bits 3694 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3695 getF32Constant(DAG, 0x3c5d51ce)); 3696 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 3697 getF32Constant(DAG, 0x3e00685a)); 3698 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3699 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3700 getF32Constant(DAG, 0x3efb6798)); 3701 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3702 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 3703 getF32Constant(DAG, 0x3f88d192)); 3704 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3705 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3706 getF32Constant(DAG, 0x3fc4316c)); 3707 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3708 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 3709 getF32Constant(DAG, 0x3f57ce70)); 3710 3711 result = DAG.getNode(ISD::FADD, dl, 3712 MVT::f32, LogOfExponent, Log10ofMantissa); 3713 } 3714 } else { 3715 // No special expansion. 3716 result = DAG.getNode(ISD::FLOG10, dl, 3717 getValue(I.getArgOperand(0)).getValueType(), 3718 getValue(I.getArgOperand(0))); 3719 } 3720 3721 setValue(&I, result); 3722} 3723 3724/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 3725/// limited-precision mode. 3726void 3727SelectionDAGBuilder::visitExp2(const CallInst &I) { 3728 SDValue result; 3729 DebugLoc dl = getCurDebugLoc(); 3730 3731 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3732 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3733 SDValue Op = getValue(I.getArgOperand(0)); 3734 3735 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 3736 3737 // FractionalPartOfX = x - (float)IntegerPartOfX; 3738 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3739 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 3740 3741 // IntegerPartOfX <<= 23; 3742 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3743 DAG.getConstant(23, TLI.getPointerTy())); 3744 3745 if (LimitFloatPrecision <= 6) { 3746 // For floating-point precision of 6: 3747 // 3748 // TwoToFractionalPartOfX = 3749 // 0.997535578f + 3750 // (0.735607626f + 0.252464424f * x) * x; 3751 // 3752 // error 0.0144103317, which is 6 bits 3753 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3754 getF32Constant(DAG, 0x3e814304)); 3755 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3756 getF32Constant(DAG, 0x3f3c50c8)); 3757 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3758 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3759 getF32Constant(DAG, 0x3f7f5e7e)); 3760 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3761 SDValue TwoToFractionalPartOfX = 3762 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3763 3764 result = DAG.getNode(ISD::BITCAST, dl, 3765 MVT::f32, TwoToFractionalPartOfX); 3766 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3767 // For floating-point precision of 12: 3768 // 3769 // TwoToFractionalPartOfX = 3770 // 0.999892986f + 3771 // (0.696457318f + 3772 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3773 // 3774 // error 0.000107046256, which is 13 to 14 bits 3775 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3776 getF32Constant(DAG, 0x3da235e3)); 3777 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3778 getF32Constant(DAG, 0x3e65b8f3)); 3779 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3780 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3781 getF32Constant(DAG, 0x3f324b07)); 3782 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3783 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3784 getF32Constant(DAG, 0x3f7ff8fd)); 3785 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3786 SDValue TwoToFractionalPartOfX = 3787 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3788 3789 result = DAG.getNode(ISD::BITCAST, dl, 3790 MVT::f32, TwoToFractionalPartOfX); 3791 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3792 // For floating-point precision of 18: 3793 // 3794 // TwoToFractionalPartOfX = 3795 // 0.999999982f + 3796 // (0.693148872f + 3797 // (0.240227044f + 3798 // (0.554906021e-1f + 3799 // (0.961591928e-2f + 3800 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3801 // error 2.47208000*10^(-7), which is better than 18 bits 3802 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3803 getF32Constant(DAG, 0x3924b03e)); 3804 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3805 getF32Constant(DAG, 0x3ab24b87)); 3806 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3807 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3808 getF32Constant(DAG, 0x3c1d8c17)); 3809 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3810 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3811 getF32Constant(DAG, 0x3d634a1d)); 3812 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3813 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3814 getF32Constant(DAG, 0x3e75fe14)); 3815 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3816 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3817 getF32Constant(DAG, 0x3f317234)); 3818 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3819 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3820 getF32Constant(DAG, 0x3f800000)); 3821 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3822 SDValue TwoToFractionalPartOfX = 3823 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3824 3825 result = DAG.getNode(ISD::BITCAST, dl, 3826 MVT::f32, TwoToFractionalPartOfX); 3827 } 3828 } else { 3829 // No special expansion. 3830 result = DAG.getNode(ISD::FEXP2, dl, 3831 getValue(I.getArgOperand(0)).getValueType(), 3832 getValue(I.getArgOperand(0))); 3833 } 3834 3835 setValue(&I, result); 3836} 3837 3838/// visitPow - Lower a pow intrinsic. Handles the special sequences for 3839/// limited-precision mode with x == 10.0f. 3840void 3841SelectionDAGBuilder::visitPow(const CallInst &I) { 3842 SDValue result; 3843 const Value *Val = I.getArgOperand(0); 3844 DebugLoc dl = getCurDebugLoc(); 3845 bool IsExp10 = false; 3846 3847 if (getValue(Val).getValueType() == MVT::f32 && 3848 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 3849 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3850 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 3851 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 3852 APFloat Ten(10.0f); 3853 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 3854 } 3855 } 3856 } 3857 3858 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3859 SDValue Op = getValue(I.getArgOperand(1)); 3860 3861 // Put the exponent in the right bit position for later addition to the 3862 // final result: 3863 // 3864 // #define LOG2OF10 3.3219281f 3865 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 3866 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3867 getF32Constant(DAG, 0x40549a78)); 3868 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3869 3870 // FractionalPartOfX = x - (float)IntegerPartOfX; 3871 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3872 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3873 3874 // IntegerPartOfX <<= 23; 3875 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3876 DAG.getConstant(23, TLI.getPointerTy())); 3877 3878 if (LimitFloatPrecision <= 6) { 3879 // For floating-point precision of 6: 3880 // 3881 // twoToFractionalPartOfX = 3882 // 0.997535578f + 3883 // (0.735607626f + 0.252464424f * x) * x; 3884 // 3885 // error 0.0144103317, which is 6 bits 3886 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3887 getF32Constant(DAG, 0x3e814304)); 3888 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3889 getF32Constant(DAG, 0x3f3c50c8)); 3890 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3891 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3892 getF32Constant(DAG, 0x3f7f5e7e)); 3893 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 3894 SDValue TwoToFractionalPartOfX = 3895 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 3896 3897 result = DAG.getNode(ISD::BITCAST, dl, 3898 MVT::f32, TwoToFractionalPartOfX); 3899 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3900 // For floating-point precision of 12: 3901 // 3902 // TwoToFractionalPartOfX = 3903 // 0.999892986f + 3904 // (0.696457318f + 3905 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3906 // 3907 // error 0.000107046256, which is 13 to 14 bits 3908 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3909 getF32Constant(DAG, 0x3da235e3)); 3910 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3911 getF32Constant(DAG, 0x3e65b8f3)); 3912 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3913 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3914 getF32Constant(DAG, 0x3f324b07)); 3915 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3916 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3917 getF32Constant(DAG, 0x3f7ff8fd)); 3918 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 3919 SDValue TwoToFractionalPartOfX = 3920 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 3921 3922 result = DAG.getNode(ISD::BITCAST, dl, 3923 MVT::f32, TwoToFractionalPartOfX); 3924 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3925 // For floating-point precision of 18: 3926 // 3927 // TwoToFractionalPartOfX = 3928 // 0.999999982f + 3929 // (0.693148872f + 3930 // (0.240227044f + 3931 // (0.554906021e-1f + 3932 // (0.961591928e-2f + 3933 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3934 // error 2.47208000*10^(-7), which is better than 18 bits 3935 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3936 getF32Constant(DAG, 0x3924b03e)); 3937 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3938 getF32Constant(DAG, 0x3ab24b87)); 3939 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3940 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3941 getF32Constant(DAG, 0x3c1d8c17)); 3942 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3943 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3944 getF32Constant(DAG, 0x3d634a1d)); 3945 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3946 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3947 getF32Constant(DAG, 0x3e75fe14)); 3948 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3949 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3950 getF32Constant(DAG, 0x3f317234)); 3951 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3952 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3953 getF32Constant(DAG, 0x3f800000)); 3954 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 3955 SDValue TwoToFractionalPartOfX = 3956 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 3957 3958 result = DAG.getNode(ISD::BITCAST, dl, 3959 MVT::f32, TwoToFractionalPartOfX); 3960 } 3961 } else { 3962 // No special expansion. 3963 result = DAG.getNode(ISD::FPOW, dl, 3964 getValue(I.getArgOperand(0)).getValueType(), 3965 getValue(I.getArgOperand(0)), 3966 getValue(I.getArgOperand(1))); 3967 } 3968 3969 setValue(&I, result); 3970} 3971 3972 3973/// ExpandPowI - Expand a llvm.powi intrinsic. 3974static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 3975 SelectionDAG &DAG) { 3976 // If RHS is a constant, we can expand this out to a multiplication tree, 3977 // otherwise we end up lowering to a call to __powidf2 (for example). When 3978 // optimizing for size, we only want to do this if the expansion would produce 3979 // a small number of multiplies, otherwise we do the full expansion. 3980 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 3981 // Get the exponent as a positive value. 3982 unsigned Val = RHSC->getSExtValue(); 3983 if ((int)Val < 0) Val = -Val; 3984 3985 // powi(x, 0) -> 1.0 3986 if (Val == 0) 3987 return DAG.getConstantFP(1.0, LHS.getValueType()); 3988 3989 const Function *F = DAG.getMachineFunction().getFunction(); 3990 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 3991 // If optimizing for size, don't insert too many multiplies. This 3992 // inserts up to 5 multiplies. 3993 CountPopulation_32(Val)+Log2_32(Val) < 7) { 3994 // We use the simple binary decomposition method to generate the multiply 3995 // sequence. There are more optimal ways to do this (for example, 3996 // powi(x,15) generates one more multiply than it should), but this has 3997 // the benefit of being both really simple and much better than a libcall. 3998 SDValue Res; // Logically starts equal to 1.0 3999 SDValue CurSquare = LHS; 4000 while (Val) { 4001 if (Val & 1) { 4002 if (Res.getNode()) 4003 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4004 else 4005 Res = CurSquare; // 1.0*CurSquare. 4006 } 4007 4008 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4009 CurSquare, CurSquare); 4010 Val >>= 1; 4011 } 4012 4013 // If the original was negative, invert the result, producing 1/(x*x*x). 4014 if (RHSC->getSExtValue() < 0) 4015 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4016 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4017 return Res; 4018 } 4019 } 4020 4021 // Otherwise, expand to a libcall. 4022 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4023} 4024 4025/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4026/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4027/// At the end of instruction selection, they will be inserted to the entry BB. 4028bool 4029SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4030 int64_t Offset, 4031 const SDValue &N) { 4032 const Argument *Arg = dyn_cast<Argument>(V); 4033 if (!Arg) 4034 return false; 4035 4036 MachineFunction &MF = DAG.getMachineFunction(); 4037 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4038 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4039 4040 // Ignore inlined function arguments here. 4041 DIVariable DV(Variable); 4042 if (DV.isInlinedFnArgument(MF.getFunction())) 4043 return false; 4044 4045 MachineBasicBlock *MBB = FuncInfo.MBB; 4046 if (MBB != &MF.front()) 4047 return false; 4048 4049 unsigned Reg = 0; 4050 if (Arg->hasByValAttr()) { 4051 // Byval arguments' frame index is recorded during argument lowering. 4052 // Use this info directly. 4053 Reg = TRI->getFrameRegister(MF); 4054 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 4055 // If byval argument ofset is not recorded then ignore this. 4056 if (!Offset) 4057 Reg = 0; 4058 } 4059 4060 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { 4061 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4062 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4063 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4064 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4065 if (PR) 4066 Reg = PR; 4067 } 4068 } 4069 4070 if (!Reg) { 4071 // Check if ValueMap has reg number. 4072 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4073 if (VMI != FuncInfo.ValueMap.end()) 4074 Reg = VMI->second; 4075 } 4076 4077 if (!Reg && N.getNode()) { 4078 // Check if frame index is available. 4079 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4080 if (FrameIndexSDNode *FINode = 4081 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4082 Reg = TRI->getFrameRegister(MF); 4083 Offset = FINode->getIndex(); 4084 } 4085 } 4086 4087 if (!Reg) 4088 return false; 4089 4090 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4091 TII->get(TargetOpcode::DBG_VALUE)) 4092 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4093 FuncInfo.ArgDbgValues.push_back(&*MIB); 4094 return true; 4095} 4096 4097// VisualStudio defines setjmp as _setjmp 4098#if defined(_MSC_VER) && defined(setjmp) && \ 4099 !defined(setjmp_undefined_for_msvc) 4100# pragma push_macro("setjmp") 4101# undef setjmp 4102# define setjmp_undefined_for_msvc 4103#endif 4104 4105/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4106/// we want to emit this as a call to a named external function, return the name 4107/// otherwise lower it and return null. 4108const char * 4109SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4110 DebugLoc dl = getCurDebugLoc(); 4111 SDValue Res; 4112 4113 switch (Intrinsic) { 4114 default: 4115 // By default, turn this into a target intrinsic node. 4116 visitTargetIntrinsic(I, Intrinsic); 4117 return 0; 4118 case Intrinsic::vastart: visitVAStart(I); return 0; 4119 case Intrinsic::vaend: visitVAEnd(I); return 0; 4120 case Intrinsic::vacopy: visitVACopy(I); return 0; 4121 case Intrinsic::returnaddress: 4122 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4123 getValue(I.getArgOperand(0)))); 4124 return 0; 4125 case Intrinsic::frameaddress: 4126 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4127 getValue(I.getArgOperand(0)))); 4128 return 0; 4129 case Intrinsic::setjmp: 4130 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4131 case Intrinsic::longjmp: 4132 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4133 case Intrinsic::memcpy: { 4134 // Assert for address < 256 since we support only user defined address 4135 // spaces. 4136 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4137 < 256 && 4138 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4139 < 256 && 4140 "Unknown address space"); 4141 SDValue Op1 = getValue(I.getArgOperand(0)); 4142 SDValue Op2 = getValue(I.getArgOperand(1)); 4143 SDValue Op3 = getValue(I.getArgOperand(2)); 4144 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4145 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4146 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4147 MachinePointerInfo(I.getArgOperand(0)), 4148 MachinePointerInfo(I.getArgOperand(1)))); 4149 return 0; 4150 } 4151 case Intrinsic::memset: { 4152 // Assert for address < 256 since we support only user defined address 4153 // spaces. 4154 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4155 < 256 && 4156 "Unknown address space"); 4157 SDValue Op1 = getValue(I.getArgOperand(0)); 4158 SDValue Op2 = getValue(I.getArgOperand(1)); 4159 SDValue Op3 = getValue(I.getArgOperand(2)); 4160 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4161 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4162 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4163 MachinePointerInfo(I.getArgOperand(0)))); 4164 return 0; 4165 } 4166 case Intrinsic::memmove: { 4167 // Assert for address < 256 since we support only user defined address 4168 // spaces. 4169 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4170 < 256 && 4171 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4172 < 256 && 4173 "Unknown address space"); 4174 SDValue Op1 = getValue(I.getArgOperand(0)); 4175 SDValue Op2 = getValue(I.getArgOperand(1)); 4176 SDValue Op3 = getValue(I.getArgOperand(2)); 4177 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4178 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4179 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4180 MachinePointerInfo(I.getArgOperand(0)), 4181 MachinePointerInfo(I.getArgOperand(1)))); 4182 return 0; 4183 } 4184 case Intrinsic::dbg_declare: { 4185 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4186 MDNode *Variable = DI.getVariable(); 4187 const Value *Address = DI.getAddress(); 4188 if (!Address || !DIVariable(DI.getVariable()).Verify()) 4189 return 0; 4190 4191 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4192 // but do not always have a corresponding SDNode built. The SDNodeOrder 4193 // absolute, but not relative, values are different depending on whether 4194 // debug info exists. 4195 ++SDNodeOrder; 4196 4197 // Check if address has undef value. 4198 if (isa<UndefValue>(Address) || 4199 (Address->use_empty() && !isa<Argument>(Address))) { 4200 DEBUG(dbgs() << "Dropping debug info for " << DI); 4201 return 0; 4202 } 4203 4204 SDValue &N = NodeMap[Address]; 4205 if (!N.getNode() && isa<Argument>(Address)) 4206 // Check unused arguments map. 4207 N = UnusedArgNodeMap[Address]; 4208 SDDbgValue *SDV; 4209 if (N.getNode()) { 4210 // Parameters are handled specially. 4211 bool isParameter = 4212 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4213 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4214 Address = BCI->getOperand(0); 4215 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4216 4217 if (isParameter && !AI) { 4218 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4219 if (FINode) 4220 // Byval parameter. We have a frame index at this point. 4221 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4222 0, dl, SDNodeOrder); 4223 else { 4224 // Can't do anything with other non-AI cases yet. This might be a 4225 // parameter of a callee function that got inlined, for example. 4226 DEBUG(dbgs() << "Dropping debug info for " << DI); 4227 return 0; 4228 } 4229 } else if (AI) 4230 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4231 0, dl, SDNodeOrder); 4232 else { 4233 // Can't do anything with other non-AI cases yet. 4234 DEBUG(dbgs() << "Dropping debug info for " << DI); 4235 return 0; 4236 } 4237 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4238 } else { 4239 // If Address is an argument then try to emit its dbg value using 4240 // virtual register info from the FuncInfo.ValueMap. 4241 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4242 // If variable is pinned by a alloca in dominating bb then 4243 // use StaticAllocaMap. 4244 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4245 if (AI->getParent() != DI.getParent()) { 4246 DenseMap<const AllocaInst*, int>::iterator SI = 4247 FuncInfo.StaticAllocaMap.find(AI); 4248 if (SI != FuncInfo.StaticAllocaMap.end()) { 4249 SDV = DAG.getDbgValue(Variable, SI->second, 4250 0, dl, SDNodeOrder); 4251 DAG.AddDbgValue(SDV, 0, false); 4252 return 0; 4253 } 4254 } 4255 } 4256 DEBUG(dbgs() << "Dropping debug info for " << DI); 4257 } 4258 } 4259 return 0; 4260 } 4261 case Intrinsic::dbg_value: { 4262 const DbgValueInst &DI = cast<DbgValueInst>(I); 4263 if (!DIVariable(DI.getVariable()).Verify()) 4264 return 0; 4265 4266 MDNode *Variable = DI.getVariable(); 4267 uint64_t Offset = DI.getOffset(); 4268 const Value *V = DI.getValue(); 4269 if (!V) 4270 return 0; 4271 4272 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4273 // but do not always have a corresponding SDNode built. The SDNodeOrder 4274 // absolute, but not relative, values are different depending on whether 4275 // debug info exists. 4276 ++SDNodeOrder; 4277 SDDbgValue *SDV; 4278 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) { 4279 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4280 DAG.AddDbgValue(SDV, 0, false); 4281 } else { 4282 // Do not use getValue() in here; we don't want to generate code at 4283 // this point if it hasn't been done yet. 4284 SDValue N = NodeMap[V]; 4285 if (!N.getNode() && isa<Argument>(V)) 4286 // Check unused arguments map. 4287 N = UnusedArgNodeMap[V]; 4288 if (N.getNode()) { 4289 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4290 SDV = DAG.getDbgValue(Variable, N.getNode(), 4291 N.getResNo(), Offset, dl, SDNodeOrder); 4292 DAG.AddDbgValue(SDV, N.getNode(), false); 4293 } 4294 } else if (isa<PHINode>(V) && !V->use_empty() ) { 4295 // Do not call getValue(V) yet, as we don't want to generate code. 4296 // Remember it for later. 4297 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4298 DanglingDebugInfoMap[V] = DDI; 4299 } else { 4300 // We may expand this to cover more cases. One case where we have no 4301 // data available is an unreferenced parameter. 4302 DEBUG(dbgs() << "Dropping debug info for " << DI); 4303 } 4304 } 4305 4306 // Build a debug info table entry. 4307 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4308 V = BCI->getOperand(0); 4309 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4310 // Don't handle byval struct arguments or VLAs, for example. 4311 if (!AI) 4312 return 0; 4313 DenseMap<const AllocaInst*, int>::iterator SI = 4314 FuncInfo.StaticAllocaMap.find(AI); 4315 if (SI == FuncInfo.StaticAllocaMap.end()) 4316 return 0; // VLAs. 4317 int FI = SI->second; 4318 4319 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4320 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4321 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4322 return 0; 4323 } 4324 case Intrinsic::eh_exception: { 4325 // Insert the EXCEPTIONADDR instruction. 4326 assert(FuncInfo.MBB->isLandingPad() && 4327 "Call to eh.exception not in landing pad!"); 4328 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4329 SDValue Ops[1]; 4330 Ops[0] = DAG.getRoot(); 4331 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4332 setValue(&I, Op); 4333 DAG.setRoot(Op.getValue(1)); 4334 return 0; 4335 } 4336 4337 case Intrinsic::eh_selector: { 4338 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4339 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4340 if (CallMBB->isLandingPad()) 4341 AddCatchInfo(I, &MMI, CallMBB); 4342 else { 4343#ifndef NDEBUG 4344 FuncInfo.CatchInfoLost.insert(&I); 4345#endif 4346 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4347 unsigned Reg = TLI.getExceptionSelectorRegister(); 4348 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4349 } 4350 4351 // Insert the EHSELECTION instruction. 4352 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4353 SDValue Ops[2]; 4354 Ops[0] = getValue(I.getArgOperand(0)); 4355 Ops[1] = getRoot(); 4356 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4357 DAG.setRoot(Op.getValue(1)); 4358 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4359 return 0; 4360 } 4361 4362 case Intrinsic::eh_typeid_for: { 4363 // Find the type id for the given typeinfo. 4364 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4365 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4366 Res = DAG.getConstant(TypeID, MVT::i32); 4367 setValue(&I, Res); 4368 return 0; 4369 } 4370 4371 case Intrinsic::eh_return_i32: 4372 case Intrinsic::eh_return_i64: 4373 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4374 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4375 MVT::Other, 4376 getControlRoot(), 4377 getValue(I.getArgOperand(0)), 4378 getValue(I.getArgOperand(1)))); 4379 return 0; 4380 case Intrinsic::eh_unwind_init: 4381 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4382 return 0; 4383 case Intrinsic::eh_dwarf_cfa: { 4384 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4385 TLI.getPointerTy()); 4386 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4387 TLI.getPointerTy(), 4388 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4389 TLI.getPointerTy()), 4390 CfaArg); 4391 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4392 TLI.getPointerTy(), 4393 DAG.getConstant(0, TLI.getPointerTy())); 4394 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4395 FA, Offset)); 4396 return 0; 4397 } 4398 case Intrinsic::eh_sjlj_callsite: { 4399 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4400 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4401 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4402 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4403 4404 MMI.setCurrentCallSite(CI->getZExtValue()); 4405 return 0; 4406 } 4407 case Intrinsic::eh_sjlj_setjmp: { 4408 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(), 4409 getValue(I.getArgOperand(0)))); 4410 return 0; 4411 } 4412 case Intrinsic::eh_sjlj_longjmp: { 4413 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4414 getRoot(), getValue(I.getArgOperand(0)))); 4415 return 0; 4416 } 4417 case Intrinsic::eh_sjlj_dispatch_setup: { 4418 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4419 getRoot(), getValue(I.getArgOperand(0)))); 4420 return 0; 4421 } 4422 4423 case Intrinsic::x86_mmx_pslli_w: 4424 case Intrinsic::x86_mmx_pslli_d: 4425 case Intrinsic::x86_mmx_pslli_q: 4426 case Intrinsic::x86_mmx_psrli_w: 4427 case Intrinsic::x86_mmx_psrli_d: 4428 case Intrinsic::x86_mmx_psrli_q: 4429 case Intrinsic::x86_mmx_psrai_w: 4430 case Intrinsic::x86_mmx_psrai_d: { 4431 SDValue ShAmt = getValue(I.getArgOperand(1)); 4432 if (isa<ConstantSDNode>(ShAmt)) { 4433 visitTargetIntrinsic(I, Intrinsic); 4434 return 0; 4435 } 4436 unsigned NewIntrinsic = 0; 4437 EVT ShAmtVT = MVT::v2i32; 4438 switch (Intrinsic) { 4439 case Intrinsic::x86_mmx_pslli_w: 4440 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4441 break; 4442 case Intrinsic::x86_mmx_pslli_d: 4443 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4444 break; 4445 case Intrinsic::x86_mmx_pslli_q: 4446 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4447 break; 4448 case Intrinsic::x86_mmx_psrli_w: 4449 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4450 break; 4451 case Intrinsic::x86_mmx_psrli_d: 4452 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4453 break; 4454 case Intrinsic::x86_mmx_psrli_q: 4455 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4456 break; 4457 case Intrinsic::x86_mmx_psrai_w: 4458 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4459 break; 4460 case Intrinsic::x86_mmx_psrai_d: 4461 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4462 break; 4463 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4464 } 4465 4466 // The vector shift intrinsics with scalars uses 32b shift amounts but 4467 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4468 // to be zero. 4469 // We must do this early because v2i32 is not a legal type. 4470 DebugLoc dl = getCurDebugLoc(); 4471 SDValue ShOps[2]; 4472 ShOps[0] = ShAmt; 4473 ShOps[1] = DAG.getConstant(0, MVT::i32); 4474 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4475 EVT DestVT = TLI.getValueType(I.getType()); 4476 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4477 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4478 DAG.getConstant(NewIntrinsic, MVT::i32), 4479 getValue(I.getArgOperand(0)), ShAmt); 4480 setValue(&I, Res); 4481 return 0; 4482 } 4483 case Intrinsic::convertff: 4484 case Intrinsic::convertfsi: 4485 case Intrinsic::convertfui: 4486 case Intrinsic::convertsif: 4487 case Intrinsic::convertuif: 4488 case Intrinsic::convertss: 4489 case Intrinsic::convertsu: 4490 case Intrinsic::convertus: 4491 case Intrinsic::convertuu: { 4492 ISD::CvtCode Code = ISD::CVT_INVALID; 4493 switch (Intrinsic) { 4494 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4495 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4496 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4497 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4498 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4499 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4500 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4501 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4502 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4503 } 4504 EVT DestVT = TLI.getValueType(I.getType()); 4505 const Value *Op1 = I.getArgOperand(0); 4506 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4507 DAG.getValueType(DestVT), 4508 DAG.getValueType(getValue(Op1).getValueType()), 4509 getValue(I.getArgOperand(1)), 4510 getValue(I.getArgOperand(2)), 4511 Code); 4512 setValue(&I, Res); 4513 return 0; 4514 } 4515 case Intrinsic::sqrt: 4516 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4517 getValue(I.getArgOperand(0)).getValueType(), 4518 getValue(I.getArgOperand(0)))); 4519 return 0; 4520 case Intrinsic::powi: 4521 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4522 getValue(I.getArgOperand(1)), DAG)); 4523 return 0; 4524 case Intrinsic::sin: 4525 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4526 getValue(I.getArgOperand(0)).getValueType(), 4527 getValue(I.getArgOperand(0)))); 4528 return 0; 4529 case Intrinsic::cos: 4530 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4531 getValue(I.getArgOperand(0)).getValueType(), 4532 getValue(I.getArgOperand(0)))); 4533 return 0; 4534 case Intrinsic::log: 4535 visitLog(I); 4536 return 0; 4537 case Intrinsic::log2: 4538 visitLog2(I); 4539 return 0; 4540 case Intrinsic::log10: 4541 visitLog10(I); 4542 return 0; 4543 case Intrinsic::exp: 4544 visitExp(I); 4545 return 0; 4546 case Intrinsic::exp2: 4547 visitExp2(I); 4548 return 0; 4549 case Intrinsic::pow: 4550 visitPow(I); 4551 return 0; 4552 case Intrinsic::convert_to_fp16: 4553 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4554 MVT::i16, getValue(I.getArgOperand(0)))); 4555 return 0; 4556 case Intrinsic::convert_from_fp16: 4557 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4558 MVT::f32, getValue(I.getArgOperand(0)))); 4559 return 0; 4560 case Intrinsic::pcmarker: { 4561 SDValue Tmp = getValue(I.getArgOperand(0)); 4562 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4563 return 0; 4564 } 4565 case Intrinsic::readcyclecounter: { 4566 SDValue Op = getRoot(); 4567 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4568 DAG.getVTList(MVT::i64, MVT::Other), 4569 &Op, 1); 4570 setValue(&I, Res); 4571 DAG.setRoot(Res.getValue(1)); 4572 return 0; 4573 } 4574 case Intrinsic::bswap: 4575 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4576 getValue(I.getArgOperand(0)).getValueType(), 4577 getValue(I.getArgOperand(0)))); 4578 return 0; 4579 case Intrinsic::cttz: { 4580 SDValue Arg = getValue(I.getArgOperand(0)); 4581 EVT Ty = Arg.getValueType(); 4582 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4583 return 0; 4584 } 4585 case Intrinsic::ctlz: { 4586 SDValue Arg = getValue(I.getArgOperand(0)); 4587 EVT Ty = Arg.getValueType(); 4588 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4589 return 0; 4590 } 4591 case Intrinsic::ctpop: { 4592 SDValue Arg = getValue(I.getArgOperand(0)); 4593 EVT Ty = Arg.getValueType(); 4594 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4595 return 0; 4596 } 4597 case Intrinsic::stacksave: { 4598 SDValue Op = getRoot(); 4599 Res = DAG.getNode(ISD::STACKSAVE, dl, 4600 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4601 setValue(&I, Res); 4602 DAG.setRoot(Res.getValue(1)); 4603 return 0; 4604 } 4605 case Intrinsic::stackrestore: { 4606 Res = getValue(I.getArgOperand(0)); 4607 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4608 return 0; 4609 } 4610 case Intrinsic::stackprotector: { 4611 // Emit code into the DAG to store the stack guard onto the stack. 4612 MachineFunction &MF = DAG.getMachineFunction(); 4613 MachineFrameInfo *MFI = MF.getFrameInfo(); 4614 EVT PtrTy = TLI.getPointerTy(); 4615 4616 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4617 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4618 4619 int FI = FuncInfo.StaticAllocaMap[Slot]; 4620 MFI->setStackProtectorIndex(FI); 4621 4622 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4623 4624 // Store the stack protector onto the stack. 4625 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4626 MachinePointerInfo::getFixedStack(FI), 4627 true, false, 0); 4628 setValue(&I, Res); 4629 DAG.setRoot(Res); 4630 return 0; 4631 } 4632 case Intrinsic::objectsize: { 4633 // If we don't know by now, we're never going to know. 4634 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 4635 4636 assert(CI && "Non-constant type in __builtin_object_size?"); 4637 4638 SDValue Arg = getValue(I.getCalledValue()); 4639 EVT Ty = Arg.getValueType(); 4640 4641 if (CI->isZero()) 4642 Res = DAG.getConstant(-1ULL, Ty); 4643 else 4644 Res = DAG.getConstant(0, Ty); 4645 4646 setValue(&I, Res); 4647 return 0; 4648 } 4649 case Intrinsic::var_annotation: 4650 // Discard annotate attributes 4651 return 0; 4652 4653 case Intrinsic::init_trampoline: { 4654 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 4655 4656 SDValue Ops[6]; 4657 Ops[0] = getRoot(); 4658 Ops[1] = getValue(I.getArgOperand(0)); 4659 Ops[2] = getValue(I.getArgOperand(1)); 4660 Ops[3] = getValue(I.getArgOperand(2)); 4661 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 4662 Ops[5] = DAG.getSrcValue(F); 4663 4664 Res = DAG.getNode(ISD::TRAMPOLINE, dl, 4665 DAG.getVTList(TLI.getPointerTy(), MVT::Other), 4666 Ops, 6); 4667 4668 setValue(&I, Res); 4669 DAG.setRoot(Res.getValue(1)); 4670 return 0; 4671 } 4672 case Intrinsic::gcroot: 4673 if (GFI) { 4674 const Value *Alloca = I.getArgOperand(0); 4675 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 4676 4677 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 4678 GFI->addStackRoot(FI->getIndex(), TypeMap); 4679 } 4680 return 0; 4681 case Intrinsic::gcread: 4682 case Intrinsic::gcwrite: 4683 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 4684 return 0; 4685 case Intrinsic::flt_rounds: 4686 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 4687 return 0; 4688 case Intrinsic::trap: 4689 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 4690 return 0; 4691 case Intrinsic::uadd_with_overflow: 4692 return implVisitAluOverflow(I, ISD::UADDO); 4693 case Intrinsic::sadd_with_overflow: 4694 return implVisitAluOverflow(I, ISD::SADDO); 4695 case Intrinsic::usub_with_overflow: 4696 return implVisitAluOverflow(I, ISD::USUBO); 4697 case Intrinsic::ssub_with_overflow: 4698 return implVisitAluOverflow(I, ISD::SSUBO); 4699 case Intrinsic::umul_with_overflow: 4700 return implVisitAluOverflow(I, ISD::UMULO); 4701 case Intrinsic::smul_with_overflow: 4702 return implVisitAluOverflow(I, ISD::SMULO); 4703 4704 case Intrinsic::prefetch: { 4705 SDValue Ops[4]; 4706 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 4707 Ops[0] = getRoot(); 4708 Ops[1] = getValue(I.getArgOperand(0)); 4709 Ops[2] = getValue(I.getArgOperand(1)); 4710 Ops[3] = getValue(I.getArgOperand(2)); 4711 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 4712 DAG.getVTList(MVT::Other), 4713 &Ops[0], 4, 4714 EVT::getIntegerVT(*Context, 8), 4715 MachinePointerInfo(I.getArgOperand(0)), 4716 0, /* align */ 4717 false, /* volatile */ 4718 rw==0, /* read */ 4719 rw==1)); /* write */ 4720 return 0; 4721 } 4722 case Intrinsic::memory_barrier: { 4723 SDValue Ops[6]; 4724 Ops[0] = getRoot(); 4725 for (int x = 1; x < 6; ++x) 4726 Ops[x] = getValue(I.getArgOperand(x - 1)); 4727 4728 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); 4729 return 0; 4730 } 4731 case Intrinsic::atomic_cmp_swap: { 4732 SDValue Root = getRoot(); 4733 SDValue L = 4734 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), 4735 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(), 4736 Root, 4737 getValue(I.getArgOperand(0)), 4738 getValue(I.getArgOperand(1)), 4739 getValue(I.getArgOperand(2)), 4740 MachinePointerInfo(I.getArgOperand(0))); 4741 setValue(&I, L); 4742 DAG.setRoot(L.getValue(1)); 4743 return 0; 4744 } 4745 case Intrinsic::atomic_load_add: 4746 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); 4747 case Intrinsic::atomic_load_sub: 4748 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); 4749 case Intrinsic::atomic_load_or: 4750 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); 4751 case Intrinsic::atomic_load_xor: 4752 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); 4753 case Intrinsic::atomic_load_and: 4754 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); 4755 case Intrinsic::atomic_load_nand: 4756 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); 4757 case Intrinsic::atomic_load_max: 4758 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); 4759 case Intrinsic::atomic_load_min: 4760 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); 4761 case Intrinsic::atomic_load_umin: 4762 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); 4763 case Intrinsic::atomic_load_umax: 4764 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); 4765 case Intrinsic::atomic_swap: 4766 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); 4767 4768 case Intrinsic::invariant_start: 4769 case Intrinsic::lifetime_start: 4770 // Discard region information. 4771 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 4772 return 0; 4773 case Intrinsic::invariant_end: 4774 case Intrinsic::lifetime_end: 4775 // Discard region information. 4776 return 0; 4777 } 4778} 4779 4780void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 4781 bool isTailCall, 4782 MachineBasicBlock *LandingPad) { 4783 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 4784 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 4785 const Type *RetTy = FTy->getReturnType(); 4786 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4787 MCSymbol *BeginLabel = 0; 4788 4789 TargetLowering::ArgListTy Args; 4790 TargetLowering::ArgListEntry Entry; 4791 Args.reserve(CS.arg_size()); 4792 4793 // Check whether the function can return without sret-demotion. 4794 SmallVector<ISD::OutputArg, 4> Outs; 4795 SmallVector<uint64_t, 4> Offsets; 4796 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 4797 Outs, TLI, &Offsets); 4798 4799 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 4800 FTy->isVarArg(), Outs, FTy->getContext()); 4801 4802 SDValue DemoteStackSlot; 4803 int DemoteStackIdx = -100; 4804 4805 if (!CanLowerReturn) { 4806 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 4807 FTy->getReturnType()); 4808 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 4809 FTy->getReturnType()); 4810 MachineFunction &MF = DAG.getMachineFunction(); 4811 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 4812 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 4813 4814 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 4815 Entry.Node = DemoteStackSlot; 4816 Entry.Ty = StackSlotPtrType; 4817 Entry.isSExt = false; 4818 Entry.isZExt = false; 4819 Entry.isInReg = false; 4820 Entry.isSRet = true; 4821 Entry.isNest = false; 4822 Entry.isByVal = false; 4823 Entry.Alignment = Align; 4824 Args.push_back(Entry); 4825 RetTy = Type::getVoidTy(FTy->getContext()); 4826 } 4827 4828 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 4829 i != e; ++i) { 4830 SDValue ArgNode = getValue(*i); 4831 Entry.Node = ArgNode; Entry.Ty = (*i)->getType(); 4832 4833 unsigned attrInd = i - CS.arg_begin() + 1; 4834 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 4835 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 4836 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 4837 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 4838 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 4839 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 4840 Entry.Alignment = CS.getParamAlignment(attrInd); 4841 Args.push_back(Entry); 4842 } 4843 4844 if (LandingPad) { 4845 // Insert a label before the invoke call to mark the try range. This can be 4846 // used to detect deletion of the invoke via the MachineModuleInfo. 4847 BeginLabel = MMI.getContext().CreateTempSymbol(); 4848 4849 // For SjLj, keep track of which landing pads go with which invokes 4850 // so as to maintain the ordering of pads in the LSDA. 4851 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 4852 if (CallSiteIndex) { 4853 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 4854 // Now that the call site is handled, stop tracking it. 4855 MMI.setCurrentCallSite(0); 4856 } 4857 4858 // Both PendingLoads and PendingExports must be flushed here; 4859 // this call might not return. 4860 (void)getRoot(); 4861 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 4862 } 4863 4864 // Check if target-independent constraints permit a tail call here. 4865 // Target-dependent constraints are checked within TLI.LowerCallTo. 4866 if (isTailCall && 4867 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 4868 isTailCall = false; 4869 4870 // If there's a possibility that fast-isel has already selected some amount 4871 // of the current basic block, don't emit a tail call. 4872 if (isTailCall && EnableFastISel) 4873 isTailCall = false; 4874 4875 std::pair<SDValue,SDValue> Result = 4876 TLI.LowerCallTo(getRoot(), RetTy, 4877 CS.paramHasAttr(0, Attribute::SExt), 4878 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 4879 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 4880 CS.getCallingConv(), 4881 isTailCall, 4882 !CS.getInstruction()->use_empty(), 4883 Callee, Args, DAG, getCurDebugLoc()); 4884 assert((isTailCall || Result.second.getNode()) && 4885 "Non-null chain expected with non-tail call!"); 4886 assert((Result.second.getNode() || !Result.first.getNode()) && 4887 "Null value expected with tail call!"); 4888 if (Result.first.getNode()) { 4889 setValue(CS.getInstruction(), Result.first); 4890 } else if (!CanLowerReturn && Result.second.getNode()) { 4891 // The instruction result is the result of loading from the 4892 // hidden sret parameter. 4893 SmallVector<EVT, 1> PVTs; 4894 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 4895 4896 ComputeValueVTs(TLI, PtrRetTy, PVTs); 4897 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 4898 EVT PtrVT = PVTs[0]; 4899 unsigned NumValues = Outs.size(); 4900 SmallVector<SDValue, 4> Values(NumValues); 4901 SmallVector<SDValue, 4> Chains(NumValues); 4902 4903 for (unsigned i = 0; i < NumValues; ++i) { 4904 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 4905 DemoteStackSlot, 4906 DAG.getConstant(Offsets[i], PtrVT)); 4907 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 4908 Add, 4909 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 4910 false, false, 1); 4911 Values[i] = L; 4912 Chains[i] = L.getValue(1); 4913 } 4914 4915 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 4916 MVT::Other, &Chains[0], NumValues); 4917 PendingLoads.push_back(Chain); 4918 4919 // Collect the legal value parts into potentially illegal values 4920 // that correspond to the original function's return values. 4921 SmallVector<EVT, 4> RetTys; 4922 RetTy = FTy->getReturnType(); 4923 ComputeValueVTs(TLI, RetTy, RetTys); 4924 ISD::NodeType AssertOp = ISD::DELETED_NODE; 4925 SmallVector<SDValue, 4> ReturnValues; 4926 unsigned CurReg = 0; 4927 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 4928 EVT VT = RetTys[I]; 4929 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 4930 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 4931 4932 SDValue ReturnValue = 4933 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 4934 RegisterVT, VT, AssertOp); 4935 ReturnValues.push_back(ReturnValue); 4936 CurReg += NumRegs; 4937 } 4938 4939 setValue(CS.getInstruction(), 4940 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 4941 DAG.getVTList(&RetTys[0], RetTys.size()), 4942 &ReturnValues[0], ReturnValues.size())); 4943 4944 } 4945 4946 // As a special case, a null chain means that a tail call has been emitted and 4947 // the DAG root is already updated. 4948 if (Result.second.getNode()) 4949 DAG.setRoot(Result.second); 4950 else 4951 HasTailCall = true; 4952 4953 if (LandingPad) { 4954 // Insert a label at the end of the invoke call to mark the try range. This 4955 // can be used to detect deletion of the invoke via the MachineModuleInfo. 4956 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 4957 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 4958 4959 // Inform MachineModuleInfo of range. 4960 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 4961 } 4962} 4963 4964/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 4965/// value is equal or not-equal to zero. 4966static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 4967 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 4968 UI != E; ++UI) { 4969 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 4970 if (IC->isEquality()) 4971 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 4972 if (C->isNullValue()) 4973 continue; 4974 // Unknown instruction. 4975 return false; 4976 } 4977 return true; 4978} 4979 4980static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 4981 const Type *LoadTy, 4982 SelectionDAGBuilder &Builder) { 4983 4984 // Check to see if this load can be trivially constant folded, e.g. if the 4985 // input is from a string literal. 4986 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 4987 // Cast pointer to the type we really want to load. 4988 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 4989 PointerType::getUnqual(LoadTy)); 4990 4991 if (const Constant *LoadCst = 4992 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 4993 Builder.TD)) 4994 return Builder.getValue(LoadCst); 4995 } 4996 4997 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 4998 // still constant memory, the input chain can be the entry node. 4999 SDValue Root; 5000 bool ConstantMemory = false; 5001 5002 // Do not serialize (non-volatile) loads of constant memory with anything. 5003 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5004 Root = Builder.DAG.getEntryNode(); 5005 ConstantMemory = true; 5006 } else { 5007 // Do not serialize non-volatile loads against each other. 5008 Root = Builder.DAG.getRoot(); 5009 } 5010 5011 SDValue Ptr = Builder.getValue(PtrVal); 5012 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5013 Ptr, MachinePointerInfo(PtrVal), 5014 false /*volatile*/, 5015 false /*nontemporal*/, 1 /* align=1 */); 5016 5017 if (!ConstantMemory) 5018 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5019 return LoadVal; 5020} 5021 5022 5023/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5024/// If so, return true and lower it, otherwise return false and it will be 5025/// lowered like a normal call. 5026bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5027 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5028 if (I.getNumArgOperands() != 3) 5029 return false; 5030 5031 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5032 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5033 !I.getArgOperand(2)->getType()->isIntegerTy() || 5034 !I.getType()->isIntegerTy()) 5035 return false; 5036 5037 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5038 5039 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5040 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5041 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5042 bool ActuallyDoIt = true; 5043 MVT LoadVT; 5044 const Type *LoadTy; 5045 switch (Size->getZExtValue()) { 5046 default: 5047 LoadVT = MVT::Other; 5048 LoadTy = 0; 5049 ActuallyDoIt = false; 5050 break; 5051 case 2: 5052 LoadVT = MVT::i16; 5053 LoadTy = Type::getInt16Ty(Size->getContext()); 5054 break; 5055 case 4: 5056 LoadVT = MVT::i32; 5057 LoadTy = Type::getInt32Ty(Size->getContext()); 5058 break; 5059 case 8: 5060 LoadVT = MVT::i64; 5061 LoadTy = Type::getInt64Ty(Size->getContext()); 5062 break; 5063 /* 5064 case 16: 5065 LoadVT = MVT::v4i32; 5066 LoadTy = Type::getInt32Ty(Size->getContext()); 5067 LoadTy = VectorType::get(LoadTy, 4); 5068 break; 5069 */ 5070 } 5071 5072 // This turns into unaligned loads. We only do this if the target natively 5073 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5074 // we'll only produce a small number of byte loads. 5075 5076 // Require that we can find a legal MVT, and only do this if the target 5077 // supports unaligned loads of that type. Expanding into byte loads would 5078 // bloat the code. 5079 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5080 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5081 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5082 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5083 ActuallyDoIt = false; 5084 } 5085 5086 if (ActuallyDoIt) { 5087 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5088 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5089 5090 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5091 ISD::SETNE); 5092 EVT CallVT = TLI.getValueType(I.getType(), true); 5093 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5094 return true; 5095 } 5096 } 5097 5098 5099 return false; 5100} 5101 5102 5103void SelectionDAGBuilder::visitCall(const CallInst &I) { 5104 // Handle inline assembly differently. 5105 if (isa<InlineAsm>(I.getCalledValue())) { 5106 visitInlineAsm(&I); 5107 return; 5108 } 5109 5110 // See if any floating point values are being passed to this function. This is 5111 // used to emit an undefined reference to fltused on Windows. 5112 const FunctionType *FT = 5113 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5114 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5115 if (FT->isVarArg() && 5116 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5117 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5118 const Type* T = I.getArgOperand(i)->getType(); 5119 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T); 5120 i != e; ++i) { 5121 if (!i->isFloatingPointTy()) continue; 5122 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5123 break; 5124 } 5125 } 5126 } 5127 5128 const char *RenameFn = 0; 5129 if (Function *F = I.getCalledFunction()) { 5130 if (F->isDeclaration()) { 5131 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5132 if (unsigned IID = II->getIntrinsicID(F)) { 5133 RenameFn = visitIntrinsicCall(I, IID); 5134 if (!RenameFn) 5135 return; 5136 } 5137 } 5138 if (unsigned IID = F->getIntrinsicID()) { 5139 RenameFn = visitIntrinsicCall(I, IID); 5140 if (!RenameFn) 5141 return; 5142 } 5143 } 5144 5145 // Check for well-known libc/libm calls. If the function is internal, it 5146 // can't be a library call. 5147 if (!F->hasLocalLinkage() && F->hasName()) { 5148 StringRef Name = F->getName(); 5149 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5150 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5151 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5152 I.getType() == I.getArgOperand(0)->getType() && 5153 I.getType() == I.getArgOperand(1)->getType()) { 5154 SDValue LHS = getValue(I.getArgOperand(0)); 5155 SDValue RHS = getValue(I.getArgOperand(1)); 5156 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5157 LHS.getValueType(), LHS, RHS)); 5158 return; 5159 } 5160 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5161 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5162 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5163 I.getType() == I.getArgOperand(0)->getType()) { 5164 SDValue Tmp = getValue(I.getArgOperand(0)); 5165 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5166 Tmp.getValueType(), Tmp)); 5167 return; 5168 } 5169 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5170 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5171 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5172 I.getType() == I.getArgOperand(0)->getType() && 5173 I.onlyReadsMemory()) { 5174 SDValue Tmp = getValue(I.getArgOperand(0)); 5175 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5176 Tmp.getValueType(), Tmp)); 5177 return; 5178 } 5179 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5180 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5181 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5182 I.getType() == I.getArgOperand(0)->getType() && 5183 I.onlyReadsMemory()) { 5184 SDValue Tmp = getValue(I.getArgOperand(0)); 5185 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5186 Tmp.getValueType(), Tmp)); 5187 return; 5188 } 5189 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5190 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5191 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5192 I.getType() == I.getArgOperand(0)->getType() && 5193 I.onlyReadsMemory()) { 5194 SDValue Tmp = getValue(I.getArgOperand(0)); 5195 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5196 Tmp.getValueType(), Tmp)); 5197 return; 5198 } 5199 } else if (Name == "memcmp") { 5200 if (visitMemCmpCall(I)) 5201 return; 5202 } 5203 } 5204 } 5205 5206 SDValue Callee; 5207 if (!RenameFn) 5208 Callee = getValue(I.getCalledValue()); 5209 else 5210 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5211 5212 // Check if we can potentially perform a tail call. More detailed checking is 5213 // be done within LowerCallTo, after more information about the call is known. 5214 LowerCallTo(&I, Callee, I.isTailCall()); 5215} 5216 5217namespace llvm { 5218 5219/// AsmOperandInfo - This contains information for each constraint that we are 5220/// lowering. 5221class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo : 5222 public TargetLowering::AsmOperandInfo { 5223public: 5224 /// CallOperand - If this is the result output operand or a clobber 5225 /// this is null, otherwise it is the incoming operand to the CallInst. 5226 /// This gets modified as the asm is processed. 5227 SDValue CallOperand; 5228 5229 /// AssignedRegs - If this is a register or register class operand, this 5230 /// contains the set of register corresponding to the operand. 5231 RegsForValue AssignedRegs; 5232 5233 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5234 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5235 } 5236 5237 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5238 /// busy in OutputRegs/InputRegs. 5239 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5240 std::set<unsigned> &OutputRegs, 5241 std::set<unsigned> &InputRegs, 5242 const TargetRegisterInfo &TRI) const { 5243 if (isOutReg) { 5244 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5245 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5246 } 5247 if (isInReg) { 5248 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5249 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5250 } 5251 } 5252 5253 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5254 /// corresponds to. If there is no Value* for this operand, it returns 5255 /// MVT::Other. 5256 EVT getCallOperandValEVT(LLVMContext &Context, 5257 const TargetLowering &TLI, 5258 const TargetData *TD) const { 5259 if (CallOperandVal == 0) return MVT::Other; 5260 5261 if (isa<BasicBlock>(CallOperandVal)) 5262 return TLI.getPointerTy(); 5263 5264 const llvm::Type *OpTy = CallOperandVal->getType(); 5265 5266 // If this is an indirect operand, the operand is a pointer to the 5267 // accessed type. 5268 if (isIndirect) { 5269 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5270 if (!PtrTy) 5271 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5272 OpTy = PtrTy->getElementType(); 5273 } 5274 5275 // If OpTy is not a single value, it may be a struct/union that we 5276 // can tile with integers. 5277 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5278 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5279 switch (BitSize) { 5280 default: break; 5281 case 1: 5282 case 8: 5283 case 16: 5284 case 32: 5285 case 64: 5286 case 128: 5287 OpTy = IntegerType::get(Context, BitSize); 5288 break; 5289 } 5290 } 5291 5292 return TLI.getValueType(OpTy, true); 5293 } 5294 5295private: 5296 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5297 /// specified set. 5298 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5299 const TargetRegisterInfo &TRI) { 5300 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5301 Regs.insert(Reg); 5302 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5303 for (; *Aliases; ++Aliases) 5304 Regs.insert(*Aliases); 5305 } 5306}; 5307 5308typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5309 5310} // end llvm namespace. 5311 5312/// isAllocatableRegister - If the specified register is safe to allocate, 5313/// i.e. it isn't a stack pointer or some other special register, return the 5314/// register class for the register. Otherwise, return null. 5315static const TargetRegisterClass * 5316isAllocatableRegister(unsigned Reg, MachineFunction &MF, 5317 const TargetLowering &TLI, 5318 const TargetRegisterInfo *TRI) { 5319 EVT FoundVT = MVT::Other; 5320 const TargetRegisterClass *FoundRC = 0; 5321 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), 5322 E = TRI->regclass_end(); RCI != E; ++RCI) { 5323 EVT ThisVT = MVT::Other; 5324 5325 const TargetRegisterClass *RC = *RCI; 5326 // If none of the value types for this register class are valid, we 5327 // can't use it. For example, 64-bit reg classes on 32-bit targets. 5328 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 5329 I != E; ++I) { 5330 if (TLI.isTypeLegal(*I)) { 5331 // If we have already found this register in a different register class, 5332 // choose the one with the largest VT specified. For example, on 5333 // PowerPC, we favor f64 register classes over f32. 5334 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { 5335 ThisVT = *I; 5336 break; 5337 } 5338 } 5339 } 5340 5341 if (ThisVT == MVT::Other) continue; 5342 5343 // NOTE: This isn't ideal. In particular, this might allocate the 5344 // frame pointer in functions that need it (due to them not being taken 5345 // out of allocation, because a variable sized allocation hasn't been seen 5346 // yet). This is a slight code pessimization, but should still work. 5347 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), 5348 E = RC->allocation_order_end(MF); I != E; ++I) 5349 if (*I == Reg) { 5350 // We found a matching register class. Keep looking at others in case 5351 // we find one with larger registers that this physreg is also in. 5352 FoundRC = RC; 5353 FoundVT = ThisVT; 5354 break; 5355 } 5356 } 5357 return FoundRC; 5358} 5359 5360/// GetRegistersForValue - Assign registers (virtual or physical) for the 5361/// specified operand. We prefer to assign virtual registers, to allow the 5362/// register allocator to handle the assignment process. However, if the asm 5363/// uses features that we can't model on machineinstrs, we have SDISel do the 5364/// allocation. This produces generally horrible, but correct, code. 5365/// 5366/// OpInfo describes the operand. 5367/// Input and OutputRegs are the set of already allocated physical registers. 5368/// 5369void SelectionDAGBuilder:: 5370GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, 5371 std::set<unsigned> &OutputRegs, 5372 std::set<unsigned> &InputRegs) { 5373 LLVMContext &Context = FuncInfo.Fn->getContext(); 5374 5375 // Compute whether this value requires an input register, an output register, 5376 // or both. 5377 bool isOutReg = false; 5378 bool isInReg = false; 5379 switch (OpInfo.Type) { 5380 case InlineAsm::isOutput: 5381 isOutReg = true; 5382 5383 // If there is an input constraint that matches this, we need to reserve 5384 // the input register so no other inputs allocate to it. 5385 isInReg = OpInfo.hasMatchingInput(); 5386 break; 5387 case InlineAsm::isInput: 5388 isInReg = true; 5389 isOutReg = false; 5390 break; 5391 case InlineAsm::isClobber: 5392 isOutReg = true; 5393 isInReg = true; 5394 break; 5395 } 5396 5397 5398 MachineFunction &MF = DAG.getMachineFunction(); 5399 SmallVector<unsigned, 4> Regs; 5400 5401 // If this is a constraint for a single physreg, or a constraint for a 5402 // register class, find it. 5403 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5404 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5405 OpInfo.ConstraintVT); 5406 5407 unsigned NumRegs = 1; 5408 if (OpInfo.ConstraintVT != MVT::Other) { 5409 // If this is a FP input in an integer register (or visa versa) insert a bit 5410 // cast of the input value. More generally, handle any case where the input 5411 // value disagrees with the register class we plan to stick this in. 5412 if (OpInfo.Type == InlineAsm::isInput && 5413 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5414 // Try to convert to the first EVT that the reg class contains. If the 5415 // types are identical size, use a bitcast to convert (e.g. two differing 5416 // vector types). 5417 EVT RegVT = *PhysReg.second->vt_begin(); 5418 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5419 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5420 RegVT, OpInfo.CallOperand); 5421 OpInfo.ConstraintVT = RegVT; 5422 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5423 // If the input is a FP value and we want it in FP registers, do a 5424 // bitcast to the corresponding integer type. This turns an f64 value 5425 // into i64, which can be passed with two i32 values on a 32-bit 5426 // machine. 5427 RegVT = EVT::getIntegerVT(Context, 5428 OpInfo.ConstraintVT.getSizeInBits()); 5429 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5430 RegVT, OpInfo.CallOperand); 5431 OpInfo.ConstraintVT = RegVT; 5432 } 5433 } 5434 5435 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5436 } 5437 5438 EVT RegVT; 5439 EVT ValueVT = OpInfo.ConstraintVT; 5440 5441 // If this is a constraint for a specific physical register, like {r17}, 5442 // assign it now. 5443 if (unsigned AssignedReg = PhysReg.first) { 5444 const TargetRegisterClass *RC = PhysReg.second; 5445 if (OpInfo.ConstraintVT == MVT::Other) 5446 ValueVT = *RC->vt_begin(); 5447 5448 // Get the actual register value type. This is important, because the user 5449 // may have asked for (e.g.) the AX register in i32 type. We need to 5450 // remember that AX is actually i16 to get the right extension. 5451 RegVT = *RC->vt_begin(); 5452 5453 // This is a explicit reference to a physical register. 5454 Regs.push_back(AssignedReg); 5455 5456 // If this is an expanded reference, add the rest of the regs to Regs. 5457 if (NumRegs != 1) { 5458 TargetRegisterClass::iterator I = RC->begin(); 5459 for (; *I != AssignedReg; ++I) 5460 assert(I != RC->end() && "Didn't find reg!"); 5461 5462 // Already added the first reg. 5463 --NumRegs; ++I; 5464 for (; NumRegs; --NumRegs, ++I) { 5465 assert(I != RC->end() && "Ran out of registers to allocate!"); 5466 Regs.push_back(*I); 5467 } 5468 } 5469 5470 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5471 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5472 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5473 return; 5474 } 5475 5476 // Otherwise, if this was a reference to an LLVM register class, create vregs 5477 // for this reference. 5478 if (const TargetRegisterClass *RC = PhysReg.second) { 5479 RegVT = *RC->vt_begin(); 5480 if (OpInfo.ConstraintVT == MVT::Other) 5481 ValueVT = RegVT; 5482 5483 // Create the appropriate number of virtual registers. 5484 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5485 for (; NumRegs; --NumRegs) 5486 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5487 5488 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5489 return; 5490 } 5491 5492 // This is a reference to a register class that doesn't directly correspond 5493 // to an LLVM register class. Allocate NumRegs consecutive, available, 5494 // registers from the class. 5495 std::vector<unsigned> RegClassRegs 5496 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, 5497 OpInfo.ConstraintVT); 5498 5499 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5500 unsigned NumAllocated = 0; 5501 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { 5502 unsigned Reg = RegClassRegs[i]; 5503 // See if this register is available. 5504 if ((isOutReg && OutputRegs.count(Reg)) || // Already used. 5505 (isInReg && InputRegs.count(Reg))) { // Already used. 5506 // Make sure we find consecutive registers. 5507 NumAllocated = 0; 5508 continue; 5509 } 5510 5511 // Check to see if this register is allocatable (i.e. don't give out the 5512 // stack pointer). 5513 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); 5514 if (!RC) { // Couldn't allocate this register. 5515 // Reset NumAllocated to make sure we return consecutive registers. 5516 NumAllocated = 0; 5517 continue; 5518 } 5519 5520 // Okay, this register is good, we can use it. 5521 ++NumAllocated; 5522 5523 // If we allocated enough consecutive registers, succeed. 5524 if (NumAllocated == NumRegs) { 5525 unsigned RegStart = (i-NumAllocated)+1; 5526 unsigned RegEnd = i+1; 5527 // Mark all of the allocated registers used. 5528 for (unsigned i = RegStart; i != RegEnd; ++i) 5529 Regs.push_back(RegClassRegs[i]); 5530 5531 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), 5532 OpInfo.ConstraintVT); 5533 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5534 return; 5535 } 5536 } 5537 5538 // Otherwise, we couldn't allocate enough registers for this. 5539} 5540 5541/// visitInlineAsm - Handle a call to an InlineAsm object. 5542/// 5543void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5544 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5545 5546 /// ConstraintOperands - Information about all of the constraints. 5547 SDISelAsmOperandInfoVector ConstraintOperands; 5548 5549 std::set<unsigned> OutputRegs, InputRegs; 5550 5551 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS); 5552 bool hasMemory = false; 5553 5554 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5555 unsigned ResNo = 0; // ResNo - The result number of the next output. 5556 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5557 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5558 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5559 5560 EVT OpVT = MVT::Other; 5561 5562 // Compute the value type for each operand. 5563 switch (OpInfo.Type) { 5564 case InlineAsm::isOutput: 5565 // Indirect outputs just consume an argument. 5566 if (OpInfo.isIndirect) { 5567 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5568 break; 5569 } 5570 5571 // The return value of the call is this value. As such, there is no 5572 // corresponding argument. 5573 assert(!CS.getType()->isVoidTy() && 5574 "Bad inline asm!"); 5575 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) { 5576 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5577 } else { 5578 assert(ResNo == 0 && "Asm only has one result!"); 5579 OpVT = TLI.getValueType(CS.getType()); 5580 } 5581 ++ResNo; 5582 break; 5583 case InlineAsm::isInput: 5584 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5585 break; 5586 case InlineAsm::isClobber: 5587 // Nothing to do. 5588 break; 5589 } 5590 5591 // If this is an input or an indirect output, process the call argument. 5592 // BasicBlocks are labels, currently appearing only in asm's. 5593 if (OpInfo.CallOperandVal) { 5594 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5595 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5596 } else { 5597 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5598 } 5599 5600 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5601 } 5602 5603 OpInfo.ConstraintVT = OpVT; 5604 5605 // Indirect operand accesses access memory. 5606 if (OpInfo.isIndirect) 5607 hasMemory = true; 5608 else { 5609 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5610 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]); 5611 if (CType == TargetLowering::C_Memory) { 5612 hasMemory = true; 5613 break; 5614 } 5615 } 5616 } 5617 } 5618 5619 SDValue Chain, Flag; 5620 5621 // We won't need to flush pending loads if this asm doesn't touch 5622 // memory and is nonvolatile. 5623 if (hasMemory || IA->hasSideEffects()) 5624 Chain = getRoot(); 5625 else 5626 Chain = DAG.getRoot(); 5627 5628 // Second pass over the constraints: compute which constraint option to use 5629 // and assign registers to constraints that want a specific physreg. 5630 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5631 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5632 5633 // If this is an output operand with a matching input operand, look up the 5634 // matching input. If their types mismatch, e.g. one is an integer, the 5635 // other is floating point, or their sizes are different, flag it as an 5636 // error. 5637 if (OpInfo.hasMatchingInput()) { 5638 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5639 5640 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5641 if ((OpInfo.ConstraintVT.isInteger() != 5642 Input.ConstraintVT.isInteger()) || 5643 (OpInfo.ConstraintVT.getSizeInBits() != 5644 Input.ConstraintVT.getSizeInBits())) { 5645 report_fatal_error("Unsupported asm: input constraint" 5646 " with a matching output constraint of" 5647 " incompatible type!"); 5648 } 5649 Input.ConstraintVT = OpInfo.ConstraintVT; 5650 } 5651 } 5652 5653 // Compute the constraint code and ConstraintType to use. 5654 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5655 5656 // If this is a memory input, and if the operand is not indirect, do what we 5657 // need to to provide an address for the memory input. 5658 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5659 !OpInfo.isIndirect) { 5660 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) && 5661 "Can only indirectify direct input operands!"); 5662 5663 // Memory operands really want the address of the value. If we don't have 5664 // an indirect input, put it in the constpool if we can, otherwise spill 5665 // it to a stack slot. 5666 5667 // If the operand is a float, integer, or vector constant, spill to a 5668 // constant pool entry to get its address. 5669 const Value *OpVal = OpInfo.CallOperandVal; 5670 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5671 isa<ConstantVector>(OpVal)) { 5672 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5673 TLI.getPointerTy()); 5674 } else { 5675 // Otherwise, create a stack slot and emit a store to it before the 5676 // asm. 5677 const Type *Ty = OpVal->getType(); 5678 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5679 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5680 MachineFunction &MF = DAG.getMachineFunction(); 5681 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5682 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5683 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5684 OpInfo.CallOperand, StackSlot, 5685 MachinePointerInfo::getFixedStack(SSFI), 5686 false, false, 0); 5687 OpInfo.CallOperand = StackSlot; 5688 } 5689 5690 // There is no longer a Value* corresponding to this operand. 5691 OpInfo.CallOperandVal = 0; 5692 5693 // It is now an indirect operand. 5694 OpInfo.isIndirect = true; 5695 } 5696 5697 // If this constraint is for a specific register, allocate it before 5698 // anything else. 5699 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5700 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5701 } 5702 5703 // Second pass - Loop over all of the operands, assigning virtual or physregs 5704 // to register class operands. 5705 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5706 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5707 5708 // C_Register operands have already been allocated, Other/Memory don't need 5709 // to be. 5710 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5711 GetRegistersForValue(OpInfo, OutputRegs, InputRegs); 5712 } 5713 5714 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 5715 std::vector<SDValue> AsmNodeOperands; 5716 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 5717 AsmNodeOperands.push_back( 5718 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 5719 TLI.getPointerTy())); 5720 5721 // If we have a !srcloc metadata node associated with it, we want to attach 5722 // this to the ultimately generated inline asm machineinstr. To do this, we 5723 // pass in the third operand as this (potentially null) inline asm MDNode. 5724 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 5725 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 5726 5727 // Remember the AlignStack bit as operand 3. 5728 AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0, 5729 MVT::i1)); 5730 5731 // Loop over all of the inputs, copying the operand values into the 5732 // appropriate registers and processing the output regs. 5733 RegsForValue RetValRegs; 5734 5735 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 5736 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 5737 5738 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5739 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5740 5741 switch (OpInfo.Type) { 5742 case InlineAsm::isOutput: { 5743 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 5744 OpInfo.ConstraintType != TargetLowering::C_Register) { 5745 // Memory output, or 'other' output (e.g. 'X' constraint). 5746 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 5747 5748 // Add information to the INLINEASM node to know about this output. 5749 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5750 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 5751 TLI.getPointerTy())); 5752 AsmNodeOperands.push_back(OpInfo.CallOperand); 5753 break; 5754 } 5755 5756 // Otherwise, this is a register or register class output. 5757 5758 // Copy the output from the appropriate register. Find a register that 5759 // we can use. 5760 if (OpInfo.AssignedRegs.Regs.empty()) 5761 report_fatal_error("Couldn't allocate output reg for constraint '" + 5762 Twine(OpInfo.ConstraintCode) + "'!"); 5763 5764 // If this is an indirect operand, store through the pointer after the 5765 // asm. 5766 if (OpInfo.isIndirect) { 5767 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 5768 OpInfo.CallOperandVal)); 5769 } else { 5770 // This is the result value of the call. 5771 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5772 // Concatenate this output onto the outputs list. 5773 RetValRegs.append(OpInfo.AssignedRegs); 5774 } 5775 5776 // Add information to the INLINEASM node to know that this register is 5777 // set. 5778 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 5779 InlineAsm::Kind_RegDefEarlyClobber : 5780 InlineAsm::Kind_RegDef, 5781 false, 5782 0, 5783 DAG, 5784 AsmNodeOperands); 5785 break; 5786 } 5787 case InlineAsm::isInput: { 5788 SDValue InOperandVal = OpInfo.CallOperand; 5789 5790 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 5791 // If this is required to match an output register we have already set, 5792 // just use its register. 5793 unsigned OperandNo = OpInfo.getMatchedOperand(); 5794 5795 // Scan until we find the definition we already emitted of this operand. 5796 // When we find it, create a RegsForValue operand. 5797 unsigned CurOp = InlineAsm::Op_FirstOperand; 5798 for (; OperandNo; --OperandNo) { 5799 // Advance to the next operand. 5800 unsigned OpFlag = 5801 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5802 assert((InlineAsm::isRegDefKind(OpFlag) || 5803 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 5804 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 5805 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 5806 } 5807 5808 unsigned OpFlag = 5809 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 5810 if (InlineAsm::isRegDefKind(OpFlag) || 5811 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 5812 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 5813 if (OpInfo.isIndirect) { 5814 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 5815 LLVMContext &Ctx = *DAG.getContext(); 5816 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 5817 " don't know how to handle tied " 5818 "indirect register inputs"); 5819 } 5820 5821 RegsForValue MatchedRegs; 5822 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 5823 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 5824 MatchedRegs.RegVTs.push_back(RegVT); 5825 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 5826 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 5827 i != e; ++i) 5828 MatchedRegs.Regs.push_back 5829 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 5830 5831 // Use the produced MatchedRegs object to 5832 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5833 Chain, &Flag); 5834 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 5835 true, OpInfo.getMatchedOperand(), 5836 DAG, AsmNodeOperands); 5837 break; 5838 } 5839 5840 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 5841 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 5842 "Unexpected number of operands"); 5843 // Add information to the INLINEASM node to know about this input. 5844 // See InlineAsm.h isUseOperandTiedToDef. 5845 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 5846 OpInfo.getMatchedOperand()); 5847 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 5848 TLI.getPointerTy())); 5849 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 5850 break; 5851 } 5852 5853 // Treat indirect 'X' constraint as memory. 5854 if (OpInfo.ConstraintType == TargetLowering::C_Other && 5855 OpInfo.isIndirect) 5856 OpInfo.ConstraintType = TargetLowering::C_Memory; 5857 5858 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 5859 std::vector<SDValue> Ops; 5860 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], 5861 Ops, DAG); 5862 if (Ops.empty()) 5863 report_fatal_error("Invalid operand for inline asm constraint '" + 5864 Twine(OpInfo.ConstraintCode) + "'!"); 5865 5866 // Add information to the INLINEASM node to know about this input. 5867 unsigned ResOpType = 5868 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 5869 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5870 TLI.getPointerTy())); 5871 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 5872 break; 5873 } 5874 5875 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 5876 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 5877 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 5878 "Memory operands expect pointer values"); 5879 5880 // Add information to the INLINEASM node to know about this input. 5881 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 5882 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 5883 TLI.getPointerTy())); 5884 AsmNodeOperands.push_back(InOperandVal); 5885 break; 5886 } 5887 5888 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 5889 OpInfo.ConstraintType == TargetLowering::C_Register) && 5890 "Unknown constraint type!"); 5891 assert(!OpInfo.isIndirect && 5892 "Don't know how to handle indirect register inputs yet!"); 5893 5894 // Copy the input into the appropriate registers. 5895 if (OpInfo.AssignedRegs.Regs.empty() || 5896 !OpInfo.AssignedRegs.areValueTypesLegal(TLI)) 5897 report_fatal_error("Couldn't allocate input reg for constraint '" + 5898 Twine(OpInfo.ConstraintCode) + "'!"); 5899 5900 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 5901 Chain, &Flag); 5902 5903 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 5904 DAG, AsmNodeOperands); 5905 break; 5906 } 5907 case InlineAsm::isClobber: { 5908 // Add the clobbered value to the operand list, so that the register 5909 // allocator is aware that the physreg got clobbered. 5910 if (!OpInfo.AssignedRegs.Regs.empty()) 5911 OpInfo.AssignedRegs.AddInlineAsmOperands( 5912 InlineAsm::Kind_RegDefEarlyClobber, 5913 false, 0, DAG, 5914 AsmNodeOperands); 5915 break; 5916 } 5917 } 5918 } 5919 5920 // Finish up input operands. Set the input chain and add the flag last. 5921 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 5922 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 5923 5924 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 5925 DAG.getVTList(MVT::Other, MVT::Glue), 5926 &AsmNodeOperands[0], AsmNodeOperands.size()); 5927 Flag = Chain.getValue(1); 5928 5929 // If this asm returns a register value, copy the result from that register 5930 // and set it as the value of the call. 5931 if (!RetValRegs.Regs.empty()) { 5932 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5933 Chain, &Flag); 5934 5935 // FIXME: Why don't we do this for inline asms with MRVs? 5936 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 5937 EVT ResultType = TLI.getValueType(CS.getType()); 5938 5939 // If any of the results of the inline asm is a vector, it may have the 5940 // wrong width/num elts. This can happen for register classes that can 5941 // contain multiple different value types. The preg or vreg allocated may 5942 // not have the same VT as was expected. Convert it to the right type 5943 // with bit_convert. 5944 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 5945 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 5946 ResultType, Val); 5947 5948 } else if (ResultType != Val.getValueType() && 5949 ResultType.isInteger() && Val.getValueType().isInteger()) { 5950 // If a result value was tied to an input value, the computed result may 5951 // have a wider width than the expected result. Extract the relevant 5952 // portion. 5953 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 5954 } 5955 5956 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 5957 } 5958 5959 setValue(CS.getInstruction(), Val); 5960 // Don't need to use this as a chain in this case. 5961 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 5962 return; 5963 } 5964 5965 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 5966 5967 // Process indirect outputs, first output all of the flagged copies out of 5968 // physregs. 5969 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 5970 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 5971 const Value *Ptr = IndirectStoresToEmit[i].second; 5972 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 5973 Chain, &Flag); 5974 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 5975 } 5976 5977 // Emit the non-flagged stores from the physregs. 5978 SmallVector<SDValue, 8> OutChains; 5979 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 5980 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 5981 StoresToEmit[i].first, 5982 getValue(StoresToEmit[i].second), 5983 MachinePointerInfo(StoresToEmit[i].second), 5984 false, false, 0); 5985 OutChains.push_back(Val); 5986 } 5987 5988 if (!OutChains.empty()) 5989 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 5990 &OutChains[0], OutChains.size()); 5991 5992 DAG.setRoot(Chain); 5993} 5994 5995void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 5996 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 5997 MVT::Other, getRoot(), 5998 getValue(I.getArgOperand(0)), 5999 DAG.getSrcValue(I.getArgOperand(0)))); 6000} 6001 6002void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6003 const TargetData &TD = *TLI.getTargetData(); 6004 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6005 getRoot(), getValue(I.getOperand(0)), 6006 DAG.getSrcValue(I.getOperand(0)), 6007 TD.getABITypeAlignment(I.getType())); 6008 setValue(&I, V); 6009 DAG.setRoot(V.getValue(1)); 6010} 6011 6012void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6013 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6014 MVT::Other, getRoot(), 6015 getValue(I.getArgOperand(0)), 6016 DAG.getSrcValue(I.getArgOperand(0)))); 6017} 6018 6019void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6020 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6021 MVT::Other, getRoot(), 6022 getValue(I.getArgOperand(0)), 6023 getValue(I.getArgOperand(1)), 6024 DAG.getSrcValue(I.getArgOperand(0)), 6025 DAG.getSrcValue(I.getArgOperand(1)))); 6026} 6027 6028/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6029/// implementation, which just calls LowerCall. 6030/// FIXME: When all targets are 6031/// migrated to using LowerCall, this hook should be integrated into SDISel. 6032std::pair<SDValue, SDValue> 6033TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, 6034 bool RetSExt, bool RetZExt, bool isVarArg, 6035 bool isInreg, unsigned NumFixedArgs, 6036 CallingConv::ID CallConv, bool isTailCall, 6037 bool isReturnValueUsed, 6038 SDValue Callee, 6039 ArgListTy &Args, SelectionDAG &DAG, 6040 DebugLoc dl) const { 6041 // Handle all of the outgoing arguments. 6042 SmallVector<ISD::OutputArg, 32> Outs; 6043 SmallVector<SDValue, 32> OutVals; 6044 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6045 SmallVector<EVT, 4> ValueVTs; 6046 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6047 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6048 Value != NumValues; ++Value) { 6049 EVT VT = ValueVTs[Value]; 6050 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6051 SDValue Op = SDValue(Args[i].Node.getNode(), 6052 Args[i].Node.getResNo() + Value); 6053 ISD::ArgFlagsTy Flags; 6054 unsigned OriginalAlignment = 6055 getTargetData()->getABITypeAlignment(ArgTy); 6056 6057 if (Args[i].isZExt) 6058 Flags.setZExt(); 6059 if (Args[i].isSExt) 6060 Flags.setSExt(); 6061 if (Args[i].isInReg) 6062 Flags.setInReg(); 6063 if (Args[i].isSRet) 6064 Flags.setSRet(); 6065 if (Args[i].isByVal) { 6066 Flags.setByVal(); 6067 const PointerType *Ty = cast<PointerType>(Args[i].Ty); 6068 const Type *ElementTy = Ty->getElementType(); 6069 unsigned FrameAlign = getByValTypeAlignment(ElementTy); 6070 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy); 6071 // For ByVal, alignment should come from FE. BE will guess if this 6072 // info is not there but there are cases it cannot get right. 6073 if (Args[i].Alignment) 6074 FrameAlign = Args[i].Alignment; 6075 Flags.setByValAlign(FrameAlign); 6076 Flags.setByValSize(FrameSize); 6077 } 6078 if (Args[i].isNest) 6079 Flags.setNest(); 6080 Flags.setOrigAlign(OriginalAlignment); 6081 6082 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6083 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6084 SmallVector<SDValue, 4> Parts(NumParts); 6085 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6086 6087 if (Args[i].isSExt) 6088 ExtendKind = ISD::SIGN_EXTEND; 6089 else if (Args[i].isZExt) 6090 ExtendKind = ISD::ZERO_EXTEND; 6091 6092 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6093 PartVT, ExtendKind); 6094 6095 for (unsigned j = 0; j != NumParts; ++j) { 6096 // if it isn't first piece, alignment must be 1 6097 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6098 i < NumFixedArgs); 6099 if (NumParts > 1 && j == 0) 6100 MyFlags.Flags.setSplit(); 6101 else if (j != 0) 6102 MyFlags.Flags.setOrigAlign(1); 6103 6104 Outs.push_back(MyFlags); 6105 OutVals.push_back(Parts[j]); 6106 } 6107 } 6108 } 6109 6110 // Handle the incoming return values from the call. 6111 SmallVector<ISD::InputArg, 32> Ins; 6112 SmallVector<EVT, 4> RetTys; 6113 ComputeValueVTs(*this, RetTy, RetTys); 6114 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6115 EVT VT = RetTys[I]; 6116 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6117 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6118 for (unsigned i = 0; i != NumRegs; ++i) { 6119 ISD::InputArg MyFlags; 6120 MyFlags.VT = RegisterVT.getSimpleVT(); 6121 MyFlags.Used = isReturnValueUsed; 6122 if (RetSExt) 6123 MyFlags.Flags.setSExt(); 6124 if (RetZExt) 6125 MyFlags.Flags.setZExt(); 6126 if (isInreg) 6127 MyFlags.Flags.setInReg(); 6128 Ins.push_back(MyFlags); 6129 } 6130 } 6131 6132 SmallVector<SDValue, 4> InVals; 6133 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6134 Outs, OutVals, Ins, dl, DAG, InVals); 6135 6136 // Verify that the target's LowerCall behaved as expected. 6137 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6138 "LowerCall didn't return a valid chain!"); 6139 assert((!isTailCall || InVals.empty()) && 6140 "LowerCall emitted a return value for a tail call!"); 6141 assert((isTailCall || InVals.size() == Ins.size()) && 6142 "LowerCall didn't emit the correct number of values!"); 6143 6144 // For a tail call, the return value is merely live-out and there aren't 6145 // any nodes in the DAG representing it. Return a special value to 6146 // indicate that a tail call has been emitted and no more Instructions 6147 // should be processed in the current block. 6148 if (isTailCall) { 6149 DAG.setRoot(Chain); 6150 return std::make_pair(SDValue(), SDValue()); 6151 } 6152 6153 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6154 assert(InVals[i].getNode() && 6155 "LowerCall emitted a null value!"); 6156 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6157 "LowerCall emitted a value with the wrong type!"); 6158 }); 6159 6160 // Collect the legal value parts into potentially illegal values 6161 // that correspond to the original function's return values. 6162 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6163 if (RetSExt) 6164 AssertOp = ISD::AssertSext; 6165 else if (RetZExt) 6166 AssertOp = ISD::AssertZext; 6167 SmallVector<SDValue, 4> ReturnValues; 6168 unsigned CurReg = 0; 6169 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6170 EVT VT = RetTys[I]; 6171 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6172 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6173 6174 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6175 NumRegs, RegisterVT, VT, 6176 AssertOp)); 6177 CurReg += NumRegs; 6178 } 6179 6180 // For a function returning void, there is no return value. We can't create 6181 // such a node, so we just return a null return value in that case. In 6182 // that case, nothing will actualy look at the value. 6183 if (ReturnValues.empty()) 6184 return std::make_pair(SDValue(), Chain); 6185 6186 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6187 DAG.getVTList(&RetTys[0], RetTys.size()), 6188 &ReturnValues[0], ReturnValues.size()); 6189 return std::make_pair(Res, Chain); 6190} 6191 6192void TargetLowering::LowerOperationWrapper(SDNode *N, 6193 SmallVectorImpl<SDValue> &Results, 6194 SelectionDAG &DAG) const { 6195 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6196 if (Res.getNode()) 6197 Results.push_back(Res); 6198} 6199 6200SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6201 llvm_unreachable("LowerOperation not implemented for this target!"); 6202 return SDValue(); 6203} 6204 6205void 6206SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6207 SDValue Op = getNonRegisterValue(V); 6208 assert((Op.getOpcode() != ISD::CopyFromReg || 6209 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6210 "Copy from a reg to the same reg!"); 6211 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6212 6213 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6214 SDValue Chain = DAG.getEntryNode(); 6215 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6216 PendingExports.push_back(Chain); 6217} 6218 6219#include "llvm/CodeGen/SelectionDAGISel.h" 6220 6221void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6222 // If this is the entry block, emit arguments. 6223 const Function &F = *LLVMBB->getParent(); 6224 SelectionDAG &DAG = SDB->DAG; 6225 DebugLoc dl = SDB->getCurDebugLoc(); 6226 const TargetData *TD = TLI.getTargetData(); 6227 SmallVector<ISD::InputArg, 16> Ins; 6228 6229 // Check whether the function can return without sret-demotion. 6230 SmallVector<ISD::OutputArg, 4> Outs; 6231 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6232 Outs, TLI); 6233 6234 if (!FuncInfo->CanLowerReturn) { 6235 // Put in an sret pointer parameter before all the other parameters. 6236 SmallVector<EVT, 1> ValueVTs; 6237 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6238 6239 // NOTE: Assuming that a pointer will never break down to more than one VT 6240 // or one register. 6241 ISD::ArgFlagsTy Flags; 6242 Flags.setSRet(); 6243 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6244 ISD::InputArg RetArg(Flags, RegisterVT, true); 6245 Ins.push_back(RetArg); 6246 } 6247 6248 // Set up the incoming argument description vector. 6249 unsigned Idx = 1; 6250 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6251 I != E; ++I, ++Idx) { 6252 SmallVector<EVT, 4> ValueVTs; 6253 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6254 bool isArgValueUsed = !I->use_empty(); 6255 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6256 Value != NumValues; ++Value) { 6257 EVT VT = ValueVTs[Value]; 6258 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6259 ISD::ArgFlagsTy Flags; 6260 unsigned OriginalAlignment = 6261 TD->getABITypeAlignment(ArgTy); 6262 6263 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6264 Flags.setZExt(); 6265 if (F.paramHasAttr(Idx, Attribute::SExt)) 6266 Flags.setSExt(); 6267 if (F.paramHasAttr(Idx, Attribute::InReg)) 6268 Flags.setInReg(); 6269 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6270 Flags.setSRet(); 6271 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6272 Flags.setByVal(); 6273 const PointerType *Ty = cast<PointerType>(I->getType()); 6274 const Type *ElementTy = Ty->getElementType(); 6275 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6276 unsigned FrameSize = TD->getTypeAllocSize(ElementTy); 6277 // For ByVal, alignment should be passed from FE. BE will guess if 6278 // this info is not there but there are cases it cannot get right. 6279 if (F.getParamAlignment(Idx)) 6280 FrameAlign = F.getParamAlignment(Idx); 6281 Flags.setByValAlign(FrameAlign); 6282 Flags.setByValSize(FrameSize); 6283 } 6284 if (F.paramHasAttr(Idx, Attribute::Nest)) 6285 Flags.setNest(); 6286 Flags.setOrigAlign(OriginalAlignment); 6287 6288 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6289 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6290 for (unsigned i = 0; i != NumRegs; ++i) { 6291 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6292 if (NumRegs > 1 && i == 0) 6293 MyFlags.Flags.setSplit(); 6294 // if it isn't first piece, alignment must be 1 6295 else if (i > 0) 6296 MyFlags.Flags.setOrigAlign(1); 6297 Ins.push_back(MyFlags); 6298 } 6299 } 6300 } 6301 6302 // Call the target to set up the argument values. 6303 SmallVector<SDValue, 8> InVals; 6304 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6305 F.isVarArg(), Ins, 6306 dl, DAG, InVals); 6307 6308 // Verify that the target's LowerFormalArguments behaved as expected. 6309 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6310 "LowerFormalArguments didn't return a valid chain!"); 6311 assert(InVals.size() == Ins.size() && 6312 "LowerFormalArguments didn't emit the correct number of values!"); 6313 DEBUG({ 6314 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6315 assert(InVals[i].getNode() && 6316 "LowerFormalArguments emitted a null value!"); 6317 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6318 "LowerFormalArguments emitted a value with the wrong type!"); 6319 } 6320 }); 6321 6322 // Update the DAG with the new chain value resulting from argument lowering. 6323 DAG.setRoot(NewRoot); 6324 6325 // Set up the argument values. 6326 unsigned i = 0; 6327 Idx = 1; 6328 if (!FuncInfo->CanLowerReturn) { 6329 // Create a virtual register for the sret pointer, and put in a copy 6330 // from the sret argument into it. 6331 SmallVector<EVT, 1> ValueVTs; 6332 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6333 EVT VT = ValueVTs[0]; 6334 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6335 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6336 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6337 RegVT, VT, AssertOp); 6338 6339 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6340 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6341 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6342 FuncInfo->DemoteRegister = SRetReg; 6343 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6344 SRetReg, ArgValue); 6345 DAG.setRoot(NewRoot); 6346 6347 // i indexes lowered arguments. Bump it past the hidden sret argument. 6348 // Idx indexes LLVM arguments. Don't touch it. 6349 ++i; 6350 } 6351 6352 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6353 ++I, ++Idx) { 6354 SmallVector<SDValue, 4> ArgValues; 6355 SmallVector<EVT, 4> ValueVTs; 6356 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6357 unsigned NumValues = ValueVTs.size(); 6358 6359 // If this argument is unused then remember its value. It is used to generate 6360 // debugging information. 6361 if (I->use_empty() && NumValues) 6362 SDB->setUnusedArgValue(I, InVals[i]); 6363 6364 for (unsigned Value = 0; Value != NumValues; ++Value) { 6365 EVT VT = ValueVTs[Value]; 6366 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6367 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6368 6369 if (!I->use_empty()) { 6370 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6371 if (F.paramHasAttr(Idx, Attribute::SExt)) 6372 AssertOp = ISD::AssertSext; 6373 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6374 AssertOp = ISD::AssertZext; 6375 6376 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6377 NumParts, PartVT, VT, 6378 AssertOp)); 6379 } 6380 6381 i += NumParts; 6382 } 6383 6384 // Note down frame index for byval arguments. 6385 if (I->hasByValAttr() && !ArgValues.empty()) 6386 if (FrameIndexSDNode *FI = 6387 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6388 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); 6389 6390 if (!I->use_empty()) { 6391 SDValue Res; 6392 if (!ArgValues.empty()) 6393 Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6394 SDB->getCurDebugLoc()); 6395 SDB->setValue(I, Res); 6396 6397 // If this argument is live outside of the entry block, insert a copy from 6398 // whereever we got it to the vreg that other BB's will reference it as. 6399 SDB->CopyToExportRegsIfNeeded(I); 6400 } 6401 } 6402 6403 assert(i == InVals.size() && "Argument register count mismatch!"); 6404 6405 // Finally, if the target has anything special to do, allow it to do so. 6406 // FIXME: this should insert code into the DAG! 6407 EmitFunctionEntryCode(); 6408} 6409 6410/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6411/// ensure constants are generated when needed. Remember the virtual registers 6412/// that need to be added to the Machine PHI nodes as input. We cannot just 6413/// directly add them, because expansion might result in multiple MBB's for one 6414/// BB. As such, the start of the BB might correspond to a different MBB than 6415/// the end. 6416/// 6417void 6418SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6419 const TerminatorInst *TI = LLVMBB->getTerminator(); 6420 6421 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6422 6423 // Check successor nodes' PHI nodes that expect a constant to be available 6424 // from this block. 6425 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6426 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6427 if (!isa<PHINode>(SuccBB->begin())) continue; 6428 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6429 6430 // If this terminator has multiple identical successors (common for 6431 // switches), only handle each succ once. 6432 if (!SuccsHandled.insert(SuccMBB)) continue; 6433 6434 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6435 6436 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6437 // nodes and Machine PHI nodes, but the incoming operands have not been 6438 // emitted yet. 6439 for (BasicBlock::const_iterator I = SuccBB->begin(); 6440 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6441 // Ignore dead phi's. 6442 if (PN->use_empty()) continue; 6443 6444 unsigned Reg; 6445 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6446 6447 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6448 unsigned &RegOut = ConstantsOut[C]; 6449 if (RegOut == 0) { 6450 RegOut = FuncInfo.CreateRegs(C->getType()); 6451 CopyValueToVirtualRegister(C, RegOut); 6452 } 6453 Reg = RegOut; 6454 } else { 6455 DenseMap<const Value *, unsigned>::iterator I = 6456 FuncInfo.ValueMap.find(PHIOp); 6457 if (I != FuncInfo.ValueMap.end()) 6458 Reg = I->second; 6459 else { 6460 assert(isa<AllocaInst>(PHIOp) && 6461 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6462 "Didn't codegen value into a register!??"); 6463 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6464 CopyValueToVirtualRegister(PHIOp, Reg); 6465 } 6466 } 6467 6468 // Remember that this register needs to added to the machine PHI node as 6469 // the input for this MBB. 6470 SmallVector<EVT, 4> ValueVTs; 6471 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6472 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6473 EVT VT = ValueVTs[vti]; 6474 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6475 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6476 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6477 Reg += NumRegisters; 6478 } 6479 } 6480 } 6481 ConstantsOut.clear(); 6482} 6483