SelectionDAGBuilder.cpp revision f57e1c29dde4666ea4ec397dde72f991e5b9f854
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SDNodeDbgValue.h" 16#include "SelectionDAGBuilder.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/ConstantFolding.h" 22#include "llvm/Constants.h" 23#include "llvm/CallingConv.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/GlobalVariable.h" 27#include "llvm/InlineAsm.h" 28#include "llvm/Instructions.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/IntrinsicInst.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Module.h" 33#include "llvm/CodeGen/Analysis.h" 34#include "llvm/CodeGen/FastISel.h" 35#include "llvm/CodeGen/FunctionLoweringInfo.h" 36#include "llvm/CodeGen/GCStrategy.h" 37#include "llvm/CodeGen/GCMetadata.h" 38#include "llvm/CodeGen/MachineFunction.h" 39#include "llvm/CodeGen/MachineFrameInfo.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineJumpTableInfo.h" 42#include "llvm/CodeGen/MachineModuleInfo.h" 43#include "llvm/CodeGen/MachineRegisterInfo.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Analysis/DebugInfo.h" 46#include "llvm/Target/TargetData.h" 47#include "llvm/Target/TargetFrameLowering.h" 48#include "llvm/Target/TargetInstrInfo.h" 49#include "llvm/Target/TargetIntrinsicInfo.h" 50#include "llvm/Target/TargetLibraryInfo.h" 51#include "llvm/Target/TargetLowering.h" 52#include "llvm/Target/TargetOptions.h" 53#include "llvm/Support/CommandLine.h" 54#include "llvm/Support/Debug.h" 55#include "llvm/Support/ErrorHandling.h" 56#include "llvm/Support/MathExtras.h" 57#include "llvm/Support/raw_ostream.h" 58#include <algorithm> 59using namespace llvm; 60 61/// LimitFloatPrecision - Generate low-precision inline sequences for 62/// some float libcalls (6, 8 or 12 bits). 63static unsigned LimitFloatPrecision; 64 65static cl::opt<unsigned, true> 66LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72// Limit the width of DAG chains. This is important in general to prevent 73// prevent DAG-based analysis from blowing up. For example, alias analysis and 74// load clustering may not complete in reasonable time. It is difficult to 75// recognize and avoid this situation within each individual analysis, and 76// future analyses are likely to have the same behavior. Limiting DAG width is 77// the safe approach, and will be especially important with global DAGs. 78// 79// MaxParallelChains default is arbitrarily high to avoid affecting 80// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81// sequence over this should have been converted to llvm.memcpy by the 82// frontend. It easy to induce this behavior with .ll code such as: 83// %buffer = alloca [4096 x i8] 84// %data = load [4096 x i8]* %argPtr 85// store [4096 x i8] %data, [4096 x i8]* %buffer 86static const unsigned MaxParallelChains = 64; 87 88static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92/// getCopyFromParts - Create a value that contains the specified legal parts 93/// combined into the value they represent. If the parts combine to a type 94/// larger then ValueVT then AssertOp can be used to specify whether the extra 95/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96/// (ISD::AssertSext). 97static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getTargetConstant(1, TLI.getPointerTy())); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209 return SDValue(); 210} 211 212/// getCopyFromParts - Create a value that contains the specified legal parts 213/// combined into the value they represent. If the parts combine to a type 214/// larger then ValueVT then AssertOp can be used to specify whether the extra 215/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216/// (ISD::AssertSext). 217static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313} 314 315 316 317 318static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322/// getCopyToParts - Create a series of nodes that contain the specified value 323/// split into legal parts. If the parts contain more bits than Val, then, for 324/// integers, ExtendKind can be used to specify how to generate the extra bits. 325static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert(PartVT.isInteger() && ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 } 361 } else if (PartBits == ValueVT.getSizeInBits()) { 362 // Different types of the same size. 363 assert(NumParts == 1 && PartVT != ValueVT); 364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 366 // If the parts cover less bits than value has, truncate the value. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Unknown mismatch!"); 369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 371 } 372 373 // The value may have changed - recompute ValueVT. 374 ValueVT = Val.getValueType(); 375 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 376 "Failed to tile the value with PartVT!"); 377 378 if (NumParts == 1) { 379 assert(PartVT == ValueVT && "Type conversion failed!"); 380 Parts[0] = Val; 381 return; 382 } 383 384 // Expand the value into multiple parts. 385 if (NumParts & (NumParts - 1)) { 386 // The number of parts is not a power of 2. Split off and copy the tail. 387 assert(PartVT.isInteger() && ValueVT.isInteger() && 388 "Do not know what to expand to!"); 389 unsigned RoundParts = 1 << Log2_32(NumParts); 390 unsigned RoundBits = RoundParts * PartBits; 391 unsigned OddParts = NumParts - RoundParts; 392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 393 DAG.getIntPtrConstant(RoundBits)); 394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 395 396 if (TLI.isBigEndian()) 397 // The odd parts were reversed by getCopyToParts - unreverse them. 398 std::reverse(Parts + RoundParts, Parts + NumParts); 399 400 NumParts = RoundParts; 401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 403 } 404 405 // The number of parts is a power of 2. Repeatedly bisect the value using 406 // EXTRACT_ELEMENT. 407 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 408 EVT::getIntegerVT(*DAG.getContext(), 409 ValueVT.getSizeInBits()), 410 Val); 411 412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 413 for (unsigned i = 0; i < NumParts; i += StepSize) { 414 unsigned ThisBits = StepSize * PartBits / 2; 415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 416 SDValue &Part0 = Parts[i]; 417 SDValue &Part1 = Parts[i+StepSize/2]; 418 419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 420 ThisVT, Part0, DAG.getIntPtrConstant(1)); 421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 422 ThisVT, Part0, DAG.getIntPtrConstant(0)); 423 424 if (ThisBits == PartBits && ThisVT != PartVT) { 425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 427 } 428 } 429 } 430 431 if (TLI.isBigEndian()) 432 std::reverse(Parts, Parts + OrigNumParts); 433} 434 435 436/// getCopyToPartsVector - Create a series of nodes that contain the specified 437/// value split into legal parts. 438static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 439 SDValue Val, SDValue *Parts, unsigned NumParts, 440 EVT PartVT) { 441 EVT ValueVT = Val.getValueType(); 442 assert(ValueVT.isVector() && "Not a vector"); 443 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 444 445 if (NumParts == 1) { 446 if (PartVT == ValueVT) { 447 // Nothing to do. 448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 449 // Bitconvert vector->vector case. 450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 451 } else if (PartVT.isVector() && 452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 454 EVT ElementVT = PartVT.getVectorElementType(); 455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 456 // undef elements. 457 SmallVector<SDValue, 16> Ops; 458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 460 ElementVT, Val, DAG.getIntPtrConstant(i))); 461 462 for (unsigned i = ValueVT.getVectorNumElements(), 463 e = PartVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getUNDEF(ElementVT)); 465 466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 467 468 // FIXME: Use CONCAT for 2x -> 4x. 469 470 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 472 } else if (PartVT.isVector() && 473 PartVT.getVectorElementType().bitsGE( 474 ValueVT.getVectorElementType()) && 475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 476 477 // Promoted vector extract 478 bool Smaller = PartVT.bitsLE(ValueVT); 479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 480 DL, PartVT, Val); 481 } else{ 482 // Vector -> scalar conversion. 483 assert(ValueVT.getVectorNumElements() == 1 && 484 "Only trivial vector-to-scalar conversions should get here!"); 485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 PartVT, Val, DAG.getIntPtrConstant(0)); 487 488 bool Smaller = ValueVT.bitsLE(PartVT); 489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 490 DL, PartVT, Val); 491 } 492 493 Parts[0] = Val; 494 return; 495 } 496 497 // Handle a multi-element vector. 498 EVT IntermediateVT, RegisterVT; 499 unsigned NumIntermediates; 500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 501 IntermediateVT, 502 NumIntermediates, RegisterVT); 503 unsigned NumElements = ValueVT.getVectorNumElements(); 504 505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 506 NumParts = NumRegs; // Silence a compiler warning. 507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 508 509 // Split the vector into intermediate operands. 510 SmallVector<SDValue, 8> Ops(NumIntermediates); 511 for (unsigned i = 0; i != NumIntermediates; ++i) { 512 if (IntermediateVT.isVector()) 513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 514 IntermediateVT, Val, 515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 516 else 517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 519 } 520 521 // Split the intermediate operands into legal parts. 522 if (NumParts == NumIntermediates) { 523 // If the register was not expanded, promote or copy the value, 524 // as appropriate. 525 for (unsigned i = 0; i != NumParts; ++i) 526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 527 } else if (NumParts > 0) { 528 // If the intermediate type was expanded, split each the value into 529 // legal parts. 530 assert(NumParts % NumIntermediates == 0 && 531 "Must expand into a divisible number of parts!"); 532 unsigned Factor = NumParts / NumIntermediates; 533 for (unsigned i = 0; i != NumIntermediates; ++i) 534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 535 } 536} 537 538 539 540 541namespace { 542 /// RegsForValue - This struct represents the registers (physical or virtual) 543 /// that a particular set of values is assigned, and the type information 544 /// about the value. The most common situation is to represent one value at a 545 /// time, but struct or array values are handled element-wise as multiple 546 /// values. The splitting of aggregates is performed recursively, so that we 547 /// never have aggregate-typed registers. The values at this point do not 548 /// necessarily have legal types, so each value may require one or more 549 /// registers of some legal type. 550 /// 551 struct RegsForValue { 552 /// ValueVTs - The value types of the values, which may not be legal, and 553 /// may need be promoted or synthesized from one or more registers. 554 /// 555 SmallVector<EVT, 4> ValueVTs; 556 557 /// RegVTs - The value types of the registers. This is the same size as 558 /// ValueVTs and it records, for each value, what the type of the assigned 559 /// register or registers are. (Individual values are never synthesized 560 /// from more than one type of register.) 561 /// 562 /// With virtual registers, the contents of RegVTs is redundant with TLI's 563 /// getRegisterType member function, however when with physical registers 564 /// it is necessary to have a separate record of the types. 565 /// 566 SmallVector<EVT, 4> RegVTs; 567 568 /// Regs - This list holds the registers assigned to the values. 569 /// Each legal or promoted value requires one register, and each 570 /// expanded value requires multiple registers. 571 /// 572 SmallVector<unsigned, 4> Regs; 573 574 RegsForValue() {} 575 576 RegsForValue(const SmallVector<unsigned, 4> ®s, 577 EVT regvt, EVT valuevt) 578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 579 580 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 581 unsigned Reg, Type *Ty) { 582 ComputeValueVTs(tli, Ty, ValueVTs); 583 584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 585 EVT ValueVT = ValueVTs[Value]; 586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 588 for (unsigned i = 0; i != NumRegs; ++i) 589 Regs.push_back(Reg + i); 590 RegVTs.push_back(RegisterVT); 591 Reg += NumRegs; 592 } 593 } 594 595 /// areValueTypesLegal - Return true if types of all the values are legal. 596 bool areValueTypesLegal(const TargetLowering &TLI) { 597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 598 EVT RegisterVT = RegVTs[Value]; 599 if (!TLI.isTypeLegal(RegisterVT)) 600 return false; 601 } 602 return true; 603 } 604 605 /// append - Add the specified values to this one. 606 void append(const RegsForValue &RHS) { 607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 609 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 610 } 611 612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 613 /// this value and returns the result as a ValueVTs value. This uses 614 /// Chain/Flag as the input and updates them for the output Chain/Flag. 615 /// If the Flag pointer is NULL, no flag is used. 616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 617 DebugLoc dl, 618 SDValue &Chain, SDValue *Flag) const; 619 620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 621 /// specified value into the registers specified by this object. This uses 622 /// Chain/Flag as the input and updates them for the output Chain/Flag. 623 /// If the Flag pointer is NULL, no flag is used. 624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 625 SDValue &Chain, SDValue *Flag) const; 626 627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 628 /// operand list. This adds the code marker, matching input operand index 629 /// (if applicable), and includes the number of values added into it. 630 void AddInlineAsmOperands(unsigned Kind, 631 bool HasMatching, unsigned MatchingIdx, 632 SelectionDAG &DAG, 633 std::vector<SDValue> &Ops) const; 634 }; 635} 636 637/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 638/// this value and returns the result as a ValueVT value. This uses 639/// Chain/Flag as the input and updates them for the output Chain/Flag. 640/// If the Flag pointer is NULL, no flag is used. 641SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 642 FunctionLoweringInfo &FuncInfo, 643 DebugLoc dl, 644 SDValue &Chain, SDValue *Flag) const { 645 // A Value with type {} or [0 x %t] needs no registers. 646 if (ValueVTs.empty()) 647 return SDValue(); 648 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 650 651 // Assemble the legal parts into the final values. 652 SmallVector<SDValue, 4> Values(ValueVTs.size()); 653 SmallVector<SDValue, 8> Parts; 654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 655 // Copy the legal parts from the registers. 656 EVT ValueVT = ValueVTs[Value]; 657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 658 EVT RegisterVT = RegVTs[Value]; 659 660 Parts.resize(NumRegs); 661 for (unsigned i = 0; i != NumRegs; ++i) { 662 SDValue P; 663 if (Flag == 0) { 664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 665 } else { 666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 667 *Flag = P.getValue(2); 668 } 669 670 Chain = P.getValue(1); 671 Parts[i] = P; 672 673 // If the source register was virtual and if we know something about it, 674 // add an assert node. 675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 676 !RegisterVT.isInteger() || RegisterVT.isVector()) 677 continue; 678 679 const FunctionLoweringInfo::LiveOutInfo *LOI = 680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 681 if (!LOI) 682 continue; 683 684 unsigned RegSize = RegisterVT.getSizeInBits(); 685 unsigned NumSignBits = LOI->NumSignBits; 686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 687 688 // FIXME: We capture more information than the dag can represent. For 689 // now, just use the tightest assertzext/assertsext possible. 690 bool isSExt = true; 691 EVT FromVT(MVT::Other); 692 if (NumSignBits == RegSize) 693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 694 else if (NumZeroBits >= RegSize-1) 695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 696 else if (NumSignBits > RegSize-8) 697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 698 else if (NumZeroBits >= RegSize-8) 699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 700 else if (NumSignBits > RegSize-16) 701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 702 else if (NumZeroBits >= RegSize-16) 703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 704 else if (NumSignBits > RegSize-32) 705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 706 else if (NumZeroBits >= RegSize-32) 707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 708 else 709 continue; 710 711 // Add an assertion node. 712 assert(FromVT != MVT::Other); 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 714 RegisterVT, P, DAG.getValueType(FromVT)); 715 } 716 717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 718 NumRegs, RegisterVT, ValueVT); 719 Part += NumRegs; 720 Parts.clear(); 721 } 722 723 return DAG.getNode(ISD::MERGE_VALUES, dl, 724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 725 &Values[0], ValueVTs.size()); 726} 727 728/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 729/// specified value into the registers specified by this object. This uses 730/// Chain/Flag as the input and updates them for the output Chain/Flag. 731/// If the Flag pointer is NULL, no flag is used. 732void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 733 SDValue &Chain, SDValue *Flag) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 // Get the list of the values's legal parts. 737 unsigned NumRegs = Regs.size(); 738 SmallVector<SDValue, 8> Parts(NumRegs); 739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 740 EVT ValueVT = ValueVTs[Value]; 741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 742 EVT RegisterVT = RegVTs[Value]; 743 744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 745 &Parts[Part], NumParts, RegisterVT); 746 Part += NumParts; 747 } 748 749 // Copy the parts into the registers. 750 SmallVector<SDValue, 8> Chains(NumRegs); 751 for (unsigned i = 0; i != NumRegs; ++i) { 752 SDValue Part; 753 if (Flag == 0) { 754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 755 } else { 756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 757 *Flag = Part.getValue(1); 758 } 759 760 Chains[i] = Part.getValue(0); 761 } 762 763 if (NumRegs == 1 || Flag) 764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 765 // flagged to it. That is the CopyToReg nodes and the user are considered 766 // a single scheduling unit. If we create a TokenFactor and return it as 767 // chain, then the TokenFactor is both a predecessor (operand) of the 768 // user as well as a successor (the TF operands are flagged to the user). 769 // c1, f1 = CopyToReg 770 // c2, f2 = CopyToReg 771 // c3 = TokenFactor c1, c2 772 // ... 773 // = op c3, ..., f2 774 Chain = Chains[NumRegs-1]; 775 else 776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 777} 778 779/// AddInlineAsmOperands - Add this value to the specified inlineasm node 780/// operand list. This adds the code marker and includes the number of 781/// values added into it. 782void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 783 unsigned MatchingIdx, 784 SelectionDAG &DAG, 785 std::vector<SDValue> &Ops) const { 786 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 787 788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 789 if (HasMatching) 790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 791 else if (!Regs.empty() && 792 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 793 // Put the register class of the virtual registers in the flag word. That 794 // way, later passes can recompute register class constraints for inline 795 // assembly as well as normal instructions. 796 // Don't do this for tied operands that can use the regclass information 797 // from the def. 798 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 799 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 800 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 801 } 802 803 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 804 Ops.push_back(Res); 805 806 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 807 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 808 EVT RegisterVT = RegVTs[Value]; 809 for (unsigned i = 0; i != NumRegs; ++i) { 810 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 811 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 812 } 813 } 814} 815 816void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 817 const TargetLibraryInfo *li) { 818 AA = &aa; 819 GFI = gfi; 820 LibInfo = li; 821 TD = DAG.getTarget().getTargetData(); 822 LPadToCallSiteMap.clear(); 823} 824 825/// clear - Clear out the current SelectionDAG and the associated 826/// state and prepare this SelectionDAGBuilder object to be used 827/// for a new block. This doesn't clear out information about 828/// additional blocks that are needed to complete switch lowering 829/// or PHI node updating; that information is cleared out as it is 830/// consumed. 831void SelectionDAGBuilder::clear() { 832 NodeMap.clear(); 833 UnusedArgNodeMap.clear(); 834 PendingLoads.clear(); 835 PendingExports.clear(); 836 CurDebugLoc = DebugLoc(); 837 HasTailCall = false; 838} 839 840/// clearDanglingDebugInfo - Clear the dangling debug information 841/// map. This function is seperated from the clear so that debug 842/// information that is dangling in a basic block can be properly 843/// resolved in a different basic block. This allows the 844/// SelectionDAG to resolve dangling debug information attached 845/// to PHI nodes. 846void SelectionDAGBuilder::clearDanglingDebugInfo() { 847 DanglingDebugInfoMap.clear(); 848} 849 850/// getRoot - Return the current virtual root of the Selection DAG, 851/// flushing any PendingLoad items. This must be done before emitting 852/// a store or any other node that may need to be ordered after any 853/// prior load instructions. 854/// 855SDValue SelectionDAGBuilder::getRoot() { 856 if (PendingLoads.empty()) 857 return DAG.getRoot(); 858 859 if (PendingLoads.size() == 1) { 860 SDValue Root = PendingLoads[0]; 861 DAG.setRoot(Root); 862 PendingLoads.clear(); 863 return Root; 864 } 865 866 // Otherwise, we have to make a token factor node. 867 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 868 &PendingLoads[0], PendingLoads.size()); 869 PendingLoads.clear(); 870 DAG.setRoot(Root); 871 return Root; 872} 873 874/// getControlRoot - Similar to getRoot, but instead of flushing all the 875/// PendingLoad items, flush all the PendingExports items. It is necessary 876/// to do this before emitting a terminator instruction. 877/// 878SDValue SelectionDAGBuilder::getControlRoot() { 879 SDValue Root = DAG.getRoot(); 880 881 if (PendingExports.empty()) 882 return Root; 883 884 // Turn all of the CopyToReg chains into one factored node. 885 if (Root.getOpcode() != ISD::EntryToken) { 886 unsigned i = 0, e = PendingExports.size(); 887 for (; i != e; ++i) { 888 assert(PendingExports[i].getNode()->getNumOperands() > 1); 889 if (PendingExports[i].getNode()->getOperand(0) == Root) 890 break; // Don't add the root if we already indirectly depend on it. 891 } 892 893 if (i == e) 894 PendingExports.push_back(Root); 895 } 896 897 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 898 &PendingExports[0], 899 PendingExports.size()); 900 PendingExports.clear(); 901 DAG.setRoot(Root); 902 return Root; 903} 904 905void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 906 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 907 DAG.AssignOrdering(Node, SDNodeOrder); 908 909 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 910 AssignOrderingToNode(Node->getOperand(I).getNode()); 911} 912 913void SelectionDAGBuilder::visit(const Instruction &I) { 914 // Set up outgoing PHI node register values before emitting the terminator. 915 if (isa<TerminatorInst>(&I)) 916 HandlePHINodesInSuccessorBlocks(I.getParent()); 917 918 CurDebugLoc = I.getDebugLoc(); 919 920 visit(I.getOpcode(), I); 921 922 if (!isa<TerminatorInst>(&I) && !HasTailCall) 923 CopyToExportRegsIfNeeded(&I); 924 925 CurDebugLoc = DebugLoc(); 926} 927 928void SelectionDAGBuilder::visitPHI(const PHINode &) { 929 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 930} 931 932void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 933 // Note: this doesn't use InstVisitor, because it has to work with 934 // ConstantExpr's in addition to instructions. 935 switch (Opcode) { 936 default: llvm_unreachable("Unknown instruction type encountered!"); 937 // Build the switch statement using the Instruction.def file. 938#define HANDLE_INST(NUM, OPCODE, CLASS) \ 939 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 940#include "llvm/Instruction.def" 941 } 942 943 // Assign the ordering to the freshly created DAG nodes. 944 if (NodeMap.count(&I)) { 945 ++SDNodeOrder; 946 AssignOrderingToNode(getValue(&I).getNode()); 947 } 948} 949 950// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 951// generate the debug data structures now that we've seen its definition. 952void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 953 SDValue Val) { 954 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 955 if (DDI.getDI()) { 956 const DbgValueInst *DI = DDI.getDI(); 957 DebugLoc dl = DDI.getdl(); 958 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 959 MDNode *Variable = DI->getVariable(); 960 uint64_t Offset = DI->getOffset(); 961 SDDbgValue *SDV; 962 if (Val.getNode()) { 963 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 964 SDV = DAG.getDbgValue(Variable, Val.getNode(), 965 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 966 DAG.AddDbgValue(SDV, Val.getNode(), false); 967 } 968 } else 969 DEBUG(dbgs() << "Dropping debug info for " << DI); 970 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 971 } 972} 973 974/// getValue - Return an SDValue for the given Value. 975SDValue SelectionDAGBuilder::getValue(const Value *V) { 976 // If we already have an SDValue for this value, use it. It's important 977 // to do this first, so that we don't create a CopyFromReg if we already 978 // have a regular SDValue. 979 SDValue &N = NodeMap[V]; 980 if (N.getNode()) return N; 981 982 // If there's a virtual register allocated and initialized for this 983 // value, use it. 984 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 985 if (It != FuncInfo.ValueMap.end()) { 986 unsigned InReg = It->second; 987 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 988 SDValue Chain = DAG.getEntryNode(); 989 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 990 resolveDanglingDebugInfo(V, N); 991 return N; 992 } 993 994 // Otherwise create a new SDValue and remember it. 995 SDValue Val = getValueImpl(V); 996 NodeMap[V] = Val; 997 resolveDanglingDebugInfo(V, Val); 998 return Val; 999} 1000 1001/// getNonRegisterValue - Return an SDValue for the given Value, but 1002/// don't look in FuncInfo.ValueMap for a virtual register. 1003SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1004 // If we already have an SDValue for this value, use it. 1005 SDValue &N = NodeMap[V]; 1006 if (N.getNode()) return N; 1007 1008 // Otherwise create a new SDValue and remember it. 1009 SDValue Val = getValueImpl(V); 1010 NodeMap[V] = Val; 1011 resolveDanglingDebugInfo(V, Val); 1012 return Val; 1013} 1014 1015/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1016/// Create an SDValue for the given value. 1017SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1018 if (const Constant *C = dyn_cast<Constant>(V)) { 1019 EVT VT = TLI.getValueType(V->getType(), true); 1020 1021 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1022 return DAG.getConstant(*CI, VT); 1023 1024 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1025 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1026 1027 if (isa<ConstantPointerNull>(C)) 1028 return DAG.getConstant(0, TLI.getPointerTy()); 1029 1030 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1031 return DAG.getConstantFP(*CFP, VT); 1032 1033 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1034 return DAG.getUNDEF(VT); 1035 1036 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1037 visit(CE->getOpcode(), *CE); 1038 SDValue N1 = NodeMap[V]; 1039 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1040 return N1; 1041 } 1042 1043 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1044 SmallVector<SDValue, 4> Constants; 1045 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1046 OI != OE; ++OI) { 1047 SDNode *Val = getValue(*OI).getNode(); 1048 // If the operand is an empty aggregate, there are no values. 1049 if (!Val) continue; 1050 // Add each leaf value from the operand to the Constants list 1051 // to form a flattened list of all the values. 1052 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1053 Constants.push_back(SDValue(Val, i)); 1054 } 1055 1056 return DAG.getMergeValues(&Constants[0], Constants.size(), 1057 getCurDebugLoc()); 1058 } 1059 1060 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1061 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1062 "Unknown struct or array constant!"); 1063 1064 SmallVector<EVT, 4> ValueVTs; 1065 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1066 unsigned NumElts = ValueVTs.size(); 1067 if (NumElts == 0) 1068 return SDValue(); // empty struct 1069 SmallVector<SDValue, 4> Constants(NumElts); 1070 for (unsigned i = 0; i != NumElts; ++i) { 1071 EVT EltVT = ValueVTs[i]; 1072 if (isa<UndefValue>(C)) 1073 Constants[i] = DAG.getUNDEF(EltVT); 1074 else if (EltVT.isFloatingPoint()) 1075 Constants[i] = DAG.getConstantFP(0, EltVT); 1076 else 1077 Constants[i] = DAG.getConstant(0, EltVT); 1078 } 1079 1080 return DAG.getMergeValues(&Constants[0], NumElts, 1081 getCurDebugLoc()); 1082 } 1083 1084 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1085 return DAG.getBlockAddress(BA, VT); 1086 1087 VectorType *VecTy = cast<VectorType>(V->getType()); 1088 unsigned NumElements = VecTy->getNumElements(); 1089 1090 // Now that we know the number and type of the elements, get that number of 1091 // elements into the Ops array based on what kind of constant it is. 1092 SmallVector<SDValue, 16> Ops; 1093 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1094 for (unsigned i = 0; i != NumElements; ++i) 1095 Ops.push_back(getValue(CP->getOperand(i))); 1096 } else { 1097 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1098 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1099 1100 SDValue Op; 1101 if (EltVT.isFloatingPoint()) 1102 Op = DAG.getConstantFP(0, EltVT); 1103 else 1104 Op = DAG.getConstant(0, EltVT); 1105 Ops.assign(NumElements, Op); 1106 } 1107 1108 // Create a BUILD_VECTOR node. 1109 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1110 VT, &Ops[0], Ops.size()); 1111 } 1112 1113 // If this is a static alloca, generate it as the frameindex instead of 1114 // computation. 1115 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1116 DenseMap<const AllocaInst*, int>::iterator SI = 1117 FuncInfo.StaticAllocaMap.find(AI); 1118 if (SI != FuncInfo.StaticAllocaMap.end()) 1119 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1120 } 1121 1122 // If this is an instruction which fast-isel has deferred, select it now. 1123 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1124 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1125 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1126 SDValue Chain = DAG.getEntryNode(); 1127 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1128 } 1129 1130 llvm_unreachable("Can't get register for value!"); 1131 return SDValue(); 1132} 1133 1134void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1135 SDValue Chain = getControlRoot(); 1136 SmallVector<ISD::OutputArg, 8> Outs; 1137 SmallVector<SDValue, 8> OutVals; 1138 1139 if (!FuncInfo.CanLowerReturn) { 1140 unsigned DemoteReg = FuncInfo.DemoteRegister; 1141 const Function *F = I.getParent()->getParent(); 1142 1143 // Emit a store of the return value through the virtual register. 1144 // Leave Outs empty so that LowerReturn won't try to load return 1145 // registers the usual way. 1146 SmallVector<EVT, 1> PtrValueVTs; 1147 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1148 PtrValueVTs); 1149 1150 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1151 SDValue RetOp = getValue(I.getOperand(0)); 1152 1153 SmallVector<EVT, 4> ValueVTs; 1154 SmallVector<uint64_t, 4> Offsets; 1155 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1156 unsigned NumValues = ValueVTs.size(); 1157 1158 SmallVector<SDValue, 4> Chains(NumValues); 1159 for (unsigned i = 0; i != NumValues; ++i) { 1160 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1161 RetPtr.getValueType(), RetPtr, 1162 DAG.getIntPtrConstant(Offsets[i])); 1163 Chains[i] = 1164 DAG.getStore(Chain, getCurDebugLoc(), 1165 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1166 // FIXME: better loc info would be nice. 1167 Add, MachinePointerInfo(), false, false, 0); 1168 } 1169 1170 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1171 MVT::Other, &Chains[0], NumValues); 1172 } else if (I.getNumOperands() != 0) { 1173 SmallVector<EVT, 4> ValueVTs; 1174 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1175 unsigned NumValues = ValueVTs.size(); 1176 if (NumValues) { 1177 SDValue RetOp = getValue(I.getOperand(0)); 1178 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1179 EVT VT = ValueVTs[j]; 1180 1181 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1182 1183 const Function *F = I.getParent()->getParent(); 1184 if (F->paramHasAttr(0, Attribute::SExt)) 1185 ExtendKind = ISD::SIGN_EXTEND; 1186 else if (F->paramHasAttr(0, Attribute::ZExt)) 1187 ExtendKind = ISD::ZERO_EXTEND; 1188 1189 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1190 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1191 1192 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1193 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1194 SmallVector<SDValue, 4> Parts(NumParts); 1195 getCopyToParts(DAG, getCurDebugLoc(), 1196 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1197 &Parts[0], NumParts, PartVT, ExtendKind); 1198 1199 // 'inreg' on function refers to return value 1200 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1201 if (F->paramHasAttr(0, Attribute::InReg)) 1202 Flags.setInReg(); 1203 1204 // Propagate extension type if any 1205 if (ExtendKind == ISD::SIGN_EXTEND) 1206 Flags.setSExt(); 1207 else if (ExtendKind == ISD::ZERO_EXTEND) 1208 Flags.setZExt(); 1209 1210 for (unsigned i = 0; i < NumParts; ++i) { 1211 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1212 /*isfixed=*/true)); 1213 OutVals.push_back(Parts[i]); 1214 } 1215 } 1216 } 1217 } 1218 1219 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1220 CallingConv::ID CallConv = 1221 DAG.getMachineFunction().getFunction()->getCallingConv(); 1222 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1223 Outs, OutVals, getCurDebugLoc(), DAG); 1224 1225 // Verify that the target's LowerReturn behaved as expected. 1226 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1227 "LowerReturn didn't return a valid chain!"); 1228 1229 // Update the DAG with the new chain value resulting from return lowering. 1230 DAG.setRoot(Chain); 1231} 1232 1233/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1234/// created for it, emit nodes to copy the value into the virtual 1235/// registers. 1236void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1237 // Skip empty types 1238 if (V->getType()->isEmptyTy()) 1239 return; 1240 1241 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1242 if (VMI != FuncInfo.ValueMap.end()) { 1243 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1244 CopyValueToVirtualRegister(V, VMI->second); 1245 } 1246} 1247 1248/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1249/// the current basic block, add it to ValueMap now so that we'll get a 1250/// CopyTo/FromReg. 1251void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1252 // No need to export constants. 1253 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1254 1255 // Already exported? 1256 if (FuncInfo.isExportedInst(V)) return; 1257 1258 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1259 CopyValueToVirtualRegister(V, Reg); 1260} 1261 1262bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1263 const BasicBlock *FromBB) { 1264 // The operands of the setcc have to be in this block. We don't know 1265 // how to export them from some other block. 1266 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1267 // Can export from current BB. 1268 if (VI->getParent() == FromBB) 1269 return true; 1270 1271 // Is already exported, noop. 1272 return FuncInfo.isExportedInst(V); 1273 } 1274 1275 // If this is an argument, we can export it if the BB is the entry block or 1276 // if it is already exported. 1277 if (isa<Argument>(V)) { 1278 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1279 return true; 1280 1281 // Otherwise, can only export this if it is already exported. 1282 return FuncInfo.isExportedInst(V); 1283 } 1284 1285 // Otherwise, constants can always be exported. 1286 return true; 1287} 1288 1289/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1290uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1291 const MachineBasicBlock *Dst) const { 1292 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1293 if (!BPI) 1294 return 0; 1295 const BasicBlock *SrcBB = Src->getBasicBlock(); 1296 const BasicBlock *DstBB = Dst->getBasicBlock(); 1297 return BPI->getEdgeWeight(SrcBB, DstBB); 1298} 1299 1300void SelectionDAGBuilder:: 1301addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1302 uint32_t Weight /* = 0 */) { 1303 if (!Weight) 1304 Weight = getEdgeWeight(Src, Dst); 1305 Src->addSuccessor(Dst, Weight); 1306} 1307 1308 1309static bool InBlock(const Value *V, const BasicBlock *BB) { 1310 if (const Instruction *I = dyn_cast<Instruction>(V)) 1311 return I->getParent() == BB; 1312 return true; 1313} 1314 1315/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1316/// This function emits a branch and is used at the leaves of an OR or an 1317/// AND operator tree. 1318/// 1319void 1320SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1321 MachineBasicBlock *TBB, 1322 MachineBasicBlock *FBB, 1323 MachineBasicBlock *CurBB, 1324 MachineBasicBlock *SwitchBB) { 1325 const BasicBlock *BB = CurBB->getBasicBlock(); 1326 1327 // If the leaf of the tree is a comparison, merge the condition into 1328 // the caseblock. 1329 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1330 // The operands of the cmp have to be in this block. We don't know 1331 // how to export them from some other block. If this is the first block 1332 // of the sequence, no exporting is needed. 1333 if (CurBB == SwitchBB || 1334 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1335 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1336 ISD::CondCode Condition; 1337 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1338 Condition = getICmpCondCode(IC->getPredicate()); 1339 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1340 Condition = getFCmpCondCode(FC->getPredicate()); 1341 if (TM.Options.NoNaNsFPMath) 1342 Condition = getFCmpCodeWithoutNaN(Condition); 1343 } else { 1344 Condition = ISD::SETEQ; // silence warning. 1345 llvm_unreachable("Unknown compare instruction"); 1346 } 1347 1348 CaseBlock CB(Condition, BOp->getOperand(0), 1349 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1350 SwitchCases.push_back(CB); 1351 return; 1352 } 1353 } 1354 1355 // Create a CaseBlock record representing this branch. 1356 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1357 NULL, TBB, FBB, CurBB); 1358 SwitchCases.push_back(CB); 1359} 1360 1361/// FindMergedConditions - If Cond is an expression like 1362void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1363 MachineBasicBlock *TBB, 1364 MachineBasicBlock *FBB, 1365 MachineBasicBlock *CurBB, 1366 MachineBasicBlock *SwitchBB, 1367 unsigned Opc) { 1368 // If this node is not part of the or/and tree, emit it as a branch. 1369 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1370 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1371 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1372 BOp->getParent() != CurBB->getBasicBlock() || 1373 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1374 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1375 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1376 return; 1377 } 1378 1379 // Create TmpBB after CurBB. 1380 MachineFunction::iterator BBI = CurBB; 1381 MachineFunction &MF = DAG.getMachineFunction(); 1382 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1383 CurBB->getParent()->insert(++BBI, TmpBB); 1384 1385 if (Opc == Instruction::Or) { 1386 // Codegen X | Y as: 1387 // jmp_if_X TBB 1388 // jmp TmpBB 1389 // TmpBB: 1390 // jmp_if_Y TBB 1391 // jmp FBB 1392 // 1393 1394 // Emit the LHS condition. 1395 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1396 1397 // Emit the RHS condition into TmpBB. 1398 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1399 } else { 1400 assert(Opc == Instruction::And && "Unknown merge op!"); 1401 // Codegen X & Y as: 1402 // jmp_if_X TmpBB 1403 // jmp FBB 1404 // TmpBB: 1405 // jmp_if_Y TBB 1406 // jmp FBB 1407 // 1408 // This requires creation of TmpBB after CurBB. 1409 1410 // Emit the LHS condition. 1411 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1412 1413 // Emit the RHS condition into TmpBB. 1414 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1415 } 1416} 1417 1418/// If the set of cases should be emitted as a series of branches, return true. 1419/// If we should emit this as a bunch of and/or'd together conditions, return 1420/// false. 1421bool 1422SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1423 if (Cases.size() != 2) return true; 1424 1425 // If this is two comparisons of the same values or'd or and'd together, they 1426 // will get folded into a single comparison, so don't emit two blocks. 1427 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1428 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1429 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1430 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1431 return false; 1432 } 1433 1434 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1435 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1436 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1437 Cases[0].CC == Cases[1].CC && 1438 isa<Constant>(Cases[0].CmpRHS) && 1439 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1440 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1441 return false; 1442 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1443 return false; 1444 } 1445 1446 return true; 1447} 1448 1449void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1450 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1451 1452 // Update machine-CFG edges. 1453 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1454 1455 // Figure out which block is immediately after the current one. 1456 MachineBasicBlock *NextBlock = 0; 1457 MachineFunction::iterator BBI = BrMBB; 1458 if (++BBI != FuncInfo.MF->end()) 1459 NextBlock = BBI; 1460 1461 if (I.isUnconditional()) { 1462 // Update machine-CFG edges. 1463 BrMBB->addSuccessor(Succ0MBB); 1464 1465 // If this is not a fall-through branch, emit the branch. 1466 if (Succ0MBB != NextBlock) 1467 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1468 MVT::Other, getControlRoot(), 1469 DAG.getBasicBlock(Succ0MBB))); 1470 1471 return; 1472 } 1473 1474 // If this condition is one of the special cases we handle, do special stuff 1475 // now. 1476 const Value *CondVal = I.getCondition(); 1477 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1478 1479 // If this is a series of conditions that are or'd or and'd together, emit 1480 // this as a sequence of branches instead of setcc's with and/or operations. 1481 // As long as jumps are not expensive, this should improve performance. 1482 // For example, instead of something like: 1483 // cmp A, B 1484 // C = seteq 1485 // cmp D, E 1486 // F = setle 1487 // or C, F 1488 // jnz foo 1489 // Emit: 1490 // cmp A, B 1491 // je foo 1492 // cmp D, E 1493 // jle foo 1494 // 1495 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1496 if (!TLI.isJumpExpensive() && 1497 BOp->hasOneUse() && 1498 (BOp->getOpcode() == Instruction::And || 1499 BOp->getOpcode() == Instruction::Or)) { 1500 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1501 BOp->getOpcode()); 1502 // If the compares in later blocks need to use values not currently 1503 // exported from this block, export them now. This block should always 1504 // be the first entry. 1505 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1506 1507 // Allow some cases to be rejected. 1508 if (ShouldEmitAsBranches(SwitchCases)) { 1509 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1510 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1511 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1512 } 1513 1514 // Emit the branch for this block. 1515 visitSwitchCase(SwitchCases[0], BrMBB); 1516 SwitchCases.erase(SwitchCases.begin()); 1517 return; 1518 } 1519 1520 // Okay, we decided not to do this, remove any inserted MBB's and clear 1521 // SwitchCases. 1522 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1523 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1524 1525 SwitchCases.clear(); 1526 } 1527 } 1528 1529 // Create a CaseBlock record representing this branch. 1530 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1531 NULL, Succ0MBB, Succ1MBB, BrMBB); 1532 1533 // Use visitSwitchCase to actually insert the fast branch sequence for this 1534 // cond branch. 1535 visitSwitchCase(CB, BrMBB); 1536} 1537 1538/// visitSwitchCase - Emits the necessary code to represent a single node in 1539/// the binary search tree resulting from lowering a switch instruction. 1540void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1541 MachineBasicBlock *SwitchBB) { 1542 SDValue Cond; 1543 SDValue CondLHS = getValue(CB.CmpLHS); 1544 DebugLoc dl = getCurDebugLoc(); 1545 1546 // Build the setcc now. 1547 if (CB.CmpMHS == NULL) { 1548 // Fold "(X == true)" to X and "(X == false)" to !X to 1549 // handle common cases produced by branch lowering. 1550 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1551 CB.CC == ISD::SETEQ) 1552 Cond = CondLHS; 1553 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1554 CB.CC == ISD::SETEQ) { 1555 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1556 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1557 } else 1558 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1559 } else { 1560 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1561 1562 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1563 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1564 1565 SDValue CmpOp = getValue(CB.CmpMHS); 1566 EVT VT = CmpOp.getValueType(); 1567 1568 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1569 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1570 ISD::SETLE); 1571 } else { 1572 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1573 VT, CmpOp, DAG.getConstant(Low, VT)); 1574 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1575 DAG.getConstant(High-Low, VT), ISD::SETULE); 1576 } 1577 } 1578 1579 // Update successor info 1580 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1581 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1582 1583 // Set NextBlock to be the MBB immediately after the current one, if any. 1584 // This is used to avoid emitting unnecessary branches to the next block. 1585 MachineBasicBlock *NextBlock = 0; 1586 MachineFunction::iterator BBI = SwitchBB; 1587 if (++BBI != FuncInfo.MF->end()) 1588 NextBlock = BBI; 1589 1590 // If the lhs block is the next block, invert the condition so that we can 1591 // fall through to the lhs instead of the rhs block. 1592 if (CB.TrueBB == NextBlock) { 1593 std::swap(CB.TrueBB, CB.FalseBB); 1594 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1595 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1596 } 1597 1598 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1599 MVT::Other, getControlRoot(), Cond, 1600 DAG.getBasicBlock(CB.TrueBB)); 1601 1602 // Insert the false branch. Do this even if it's a fall through branch, 1603 // this makes it easier to do DAG optimizations which require inverting 1604 // the branch condition. 1605 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1606 DAG.getBasicBlock(CB.FalseBB)); 1607 1608 DAG.setRoot(BrCond); 1609} 1610 1611/// visitJumpTable - Emit JumpTable node in the current MBB 1612void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1613 // Emit the code for the jump table 1614 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1615 EVT PTy = TLI.getPointerTy(); 1616 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1617 JT.Reg, PTy); 1618 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1619 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1620 MVT::Other, Index.getValue(1), 1621 Table, Index); 1622 DAG.setRoot(BrJumpTable); 1623} 1624 1625/// visitJumpTableHeader - This function emits necessary code to produce index 1626/// in the JumpTable from switch case. 1627void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1628 JumpTableHeader &JTH, 1629 MachineBasicBlock *SwitchBB) { 1630 // Subtract the lowest switch case value from the value being switched on and 1631 // conditional branch to default mbb if the result is greater than the 1632 // difference between smallest and largest cases. 1633 SDValue SwitchOp = getValue(JTH.SValue); 1634 EVT VT = SwitchOp.getValueType(); 1635 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1636 DAG.getConstant(JTH.First, VT)); 1637 1638 // The SDNode we just created, which holds the value being switched on minus 1639 // the smallest case value, needs to be copied to a virtual register so it 1640 // can be used as an index into the jump table in a subsequent basic block. 1641 // This value may be smaller or larger than the target's pointer type, and 1642 // therefore require extension or truncating. 1643 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1644 1645 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1646 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1647 JumpTableReg, SwitchOp); 1648 JT.Reg = JumpTableReg; 1649 1650 // Emit the range check for the jump table, and branch to the default block 1651 // for the switch statement if the value being switched on exceeds the largest 1652 // case in the switch. 1653 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1654 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1655 DAG.getConstant(JTH.Last-JTH.First,VT), 1656 ISD::SETUGT); 1657 1658 // Set NextBlock to be the MBB immediately after the current one, if any. 1659 // This is used to avoid emitting unnecessary branches to the next block. 1660 MachineBasicBlock *NextBlock = 0; 1661 MachineFunction::iterator BBI = SwitchBB; 1662 1663 if (++BBI != FuncInfo.MF->end()) 1664 NextBlock = BBI; 1665 1666 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1667 MVT::Other, CopyTo, CMP, 1668 DAG.getBasicBlock(JT.Default)); 1669 1670 if (JT.MBB != NextBlock) 1671 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1672 DAG.getBasicBlock(JT.MBB)); 1673 1674 DAG.setRoot(BrCond); 1675} 1676 1677/// visitBitTestHeader - This function emits necessary code to produce value 1678/// suitable for "bit tests" 1679void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1680 MachineBasicBlock *SwitchBB) { 1681 // Subtract the minimum value 1682 SDValue SwitchOp = getValue(B.SValue); 1683 EVT VT = SwitchOp.getValueType(); 1684 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1685 DAG.getConstant(B.First, VT)); 1686 1687 // Check range 1688 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1689 TLI.getSetCCResultType(Sub.getValueType()), 1690 Sub, DAG.getConstant(B.Range, VT), 1691 ISD::SETUGT); 1692 1693 // Determine the type of the test operands. 1694 bool UsePtrType = false; 1695 if (!TLI.isTypeLegal(VT)) 1696 UsePtrType = true; 1697 else { 1698 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1699 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1700 // Switch table case range are encoded into series of masks. 1701 // Just use pointer type, it's guaranteed to fit. 1702 UsePtrType = true; 1703 break; 1704 } 1705 } 1706 if (UsePtrType) { 1707 VT = TLI.getPointerTy(); 1708 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1709 } 1710 1711 B.RegVT = VT; 1712 B.Reg = FuncInfo.CreateReg(VT); 1713 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1714 B.Reg, Sub); 1715 1716 // Set NextBlock to be the MBB immediately after the current one, if any. 1717 // This is used to avoid emitting unnecessary branches to the next block. 1718 MachineBasicBlock *NextBlock = 0; 1719 MachineFunction::iterator BBI = SwitchBB; 1720 if (++BBI != FuncInfo.MF->end()) 1721 NextBlock = BBI; 1722 1723 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1724 1725 addSuccessorWithWeight(SwitchBB, B.Default); 1726 addSuccessorWithWeight(SwitchBB, MBB); 1727 1728 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1729 MVT::Other, CopyTo, RangeCmp, 1730 DAG.getBasicBlock(B.Default)); 1731 1732 if (MBB != NextBlock) 1733 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1734 DAG.getBasicBlock(MBB)); 1735 1736 DAG.setRoot(BrRange); 1737} 1738 1739/// visitBitTestCase - this function produces one "bit test" 1740void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1741 MachineBasicBlock* NextMBB, 1742 unsigned Reg, 1743 BitTestCase &B, 1744 MachineBasicBlock *SwitchBB) { 1745 EVT VT = BB.RegVT; 1746 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1747 Reg, VT); 1748 SDValue Cmp; 1749 unsigned PopCount = CountPopulation_64(B.Mask); 1750 if (PopCount == 1) { 1751 // Testing for a single bit; just compare the shift count with what it 1752 // would need to be to shift a 1 bit in that position. 1753 Cmp = DAG.getSetCC(getCurDebugLoc(), 1754 TLI.getSetCCResultType(VT), 1755 ShiftOp, 1756 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1757 ISD::SETEQ); 1758 } else if (PopCount == BB.Range) { 1759 // There is only one zero bit in the range, test for it directly. 1760 Cmp = DAG.getSetCC(getCurDebugLoc(), 1761 TLI.getSetCCResultType(VT), 1762 ShiftOp, 1763 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1764 ISD::SETNE); 1765 } else { 1766 // Make desired shift 1767 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1768 DAG.getConstant(1, VT), ShiftOp); 1769 1770 // Emit bit tests and jumps 1771 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1772 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1773 Cmp = DAG.getSetCC(getCurDebugLoc(), 1774 TLI.getSetCCResultType(VT), 1775 AndOp, DAG.getConstant(0, VT), 1776 ISD::SETNE); 1777 } 1778 1779 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1780 addSuccessorWithWeight(SwitchBB, NextMBB); 1781 1782 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1783 MVT::Other, getControlRoot(), 1784 Cmp, DAG.getBasicBlock(B.TargetBB)); 1785 1786 // Set NextBlock to be the MBB immediately after the current one, if any. 1787 // This is used to avoid emitting unnecessary branches to the next block. 1788 MachineBasicBlock *NextBlock = 0; 1789 MachineFunction::iterator BBI = SwitchBB; 1790 if (++BBI != FuncInfo.MF->end()) 1791 NextBlock = BBI; 1792 1793 if (NextMBB != NextBlock) 1794 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1795 DAG.getBasicBlock(NextMBB)); 1796 1797 DAG.setRoot(BrAnd); 1798} 1799 1800void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1801 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1802 1803 // Retrieve successors. 1804 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1805 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1806 1807 const Value *Callee(I.getCalledValue()); 1808 if (isa<InlineAsm>(Callee)) 1809 visitInlineAsm(&I); 1810 else 1811 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1812 1813 // If the value of the invoke is used outside of its defining block, make it 1814 // available as a virtual register. 1815 CopyToExportRegsIfNeeded(&I); 1816 1817 // Update successor info 1818 addSuccessorWithWeight(InvokeMBB, Return); 1819 addSuccessorWithWeight(InvokeMBB, LandingPad); 1820 1821 // Drop into normal successor. 1822 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1823 MVT::Other, getControlRoot(), 1824 DAG.getBasicBlock(Return))); 1825} 1826 1827void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1828} 1829 1830void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1831 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1832} 1833 1834void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1835 assert(FuncInfo.MBB->isLandingPad() && 1836 "Call to landingpad not in landing pad!"); 1837 1838 MachineBasicBlock *MBB = FuncInfo.MBB; 1839 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1840 AddLandingPadInfo(LP, MMI, MBB); 1841 1842 SmallVector<EVT, 2> ValueVTs; 1843 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1844 1845 // Insert the EXCEPTIONADDR instruction. 1846 assert(FuncInfo.MBB->isLandingPad() && 1847 "Call to eh.exception not in landing pad!"); 1848 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1849 SDValue Ops[2]; 1850 Ops[0] = DAG.getRoot(); 1851 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1852 SDValue Chain = Op1.getValue(1); 1853 1854 // Insert the EHSELECTION instruction. 1855 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1856 Ops[0] = Op1; 1857 Ops[1] = Chain; 1858 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1859 Chain = Op2.getValue(1); 1860 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1861 1862 Ops[0] = Op1; 1863 Ops[1] = Op2; 1864 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1865 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1866 &Ops[0], 2); 1867 1868 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1869 setValue(&LP, RetPair.first); 1870 DAG.setRoot(RetPair.second); 1871} 1872 1873/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1874/// small case ranges). 1875bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1876 CaseRecVector& WorkList, 1877 const Value* SV, 1878 MachineBasicBlock *Default, 1879 MachineBasicBlock *SwitchBB) { 1880 Case& BackCase = *(CR.Range.second-1); 1881 1882 // Size is the number of Cases represented by this range. 1883 size_t Size = CR.Range.second - CR.Range.first; 1884 if (Size > 3) 1885 return false; 1886 1887 // Get the MachineFunction which holds the current MBB. This is used when 1888 // inserting any additional MBBs necessary to represent the switch. 1889 MachineFunction *CurMF = FuncInfo.MF; 1890 1891 // Figure out which block is immediately after the current one. 1892 MachineBasicBlock *NextBlock = 0; 1893 MachineFunction::iterator BBI = CR.CaseBB; 1894 1895 if (++BBI != FuncInfo.MF->end()) 1896 NextBlock = BBI; 1897 1898 // If any two of the cases has the same destination, and if one value 1899 // is the same as the other, but has one bit unset that the other has set, 1900 // use bit manipulation to do two compares at once. For example: 1901 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1902 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1903 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1904 if (Size == 2 && CR.CaseBB == SwitchBB) { 1905 Case &Small = *CR.Range.first; 1906 Case &Big = *(CR.Range.second-1); 1907 1908 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1909 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1910 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1911 1912 // Check that there is only one bit different. 1913 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1914 (SmallValue | BigValue) == BigValue) { 1915 // Isolate the common bit. 1916 APInt CommonBit = BigValue & ~SmallValue; 1917 assert((SmallValue | CommonBit) == BigValue && 1918 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1919 1920 SDValue CondLHS = getValue(SV); 1921 EVT VT = CondLHS.getValueType(); 1922 DebugLoc DL = getCurDebugLoc(); 1923 1924 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1925 DAG.getConstant(CommonBit, VT)); 1926 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1927 Or, DAG.getConstant(BigValue, VT), 1928 ISD::SETEQ); 1929 1930 // Update successor info. 1931 addSuccessorWithWeight(SwitchBB, Small.BB); 1932 addSuccessorWithWeight(SwitchBB, Default); 1933 1934 // Insert the true branch. 1935 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1936 getControlRoot(), Cond, 1937 DAG.getBasicBlock(Small.BB)); 1938 1939 // Insert the false branch. 1940 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1941 DAG.getBasicBlock(Default)); 1942 1943 DAG.setRoot(BrCond); 1944 return true; 1945 } 1946 } 1947 } 1948 1949 // Rearrange the case blocks so that the last one falls through if possible. 1950 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1951 // The last case block won't fall through into 'NextBlock' if we emit the 1952 // branches in this order. See if rearranging a case value would help. 1953 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1954 if (I->BB == NextBlock) { 1955 std::swap(*I, BackCase); 1956 break; 1957 } 1958 } 1959 } 1960 1961 // Create a CaseBlock record representing a conditional branch to 1962 // the Case's target mbb if the value being switched on SV is equal 1963 // to C. 1964 MachineBasicBlock *CurBlock = CR.CaseBB; 1965 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1966 MachineBasicBlock *FallThrough; 1967 if (I != E-1) { 1968 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1969 CurMF->insert(BBI, FallThrough); 1970 1971 // Put SV in a virtual register to make it available from the new blocks. 1972 ExportFromCurrentBlock(SV); 1973 } else { 1974 // If the last case doesn't match, go to the default block. 1975 FallThrough = Default; 1976 } 1977 1978 const Value *RHS, *LHS, *MHS; 1979 ISD::CondCode CC; 1980 if (I->High == I->Low) { 1981 // This is just small small case range :) containing exactly 1 case 1982 CC = ISD::SETEQ; 1983 LHS = SV; RHS = I->High; MHS = NULL; 1984 } else { 1985 CC = ISD::SETLE; 1986 LHS = I->Low; MHS = SV; RHS = I->High; 1987 } 1988 1989 uint32_t ExtraWeight = I->ExtraWeight; 1990 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 1991 /* me */ CurBlock, 1992 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 1993 1994 // If emitting the first comparison, just call visitSwitchCase to emit the 1995 // code into the current block. Otherwise, push the CaseBlock onto the 1996 // vector to be later processed by SDISel, and insert the node's MBB 1997 // before the next MBB. 1998 if (CurBlock == SwitchBB) 1999 visitSwitchCase(CB, SwitchBB); 2000 else 2001 SwitchCases.push_back(CB); 2002 2003 CurBlock = FallThrough; 2004 } 2005 2006 return true; 2007} 2008 2009static inline bool areJTsAllowed(const TargetLowering &TLI) { 2010 return !TLI.getTargetMachine().Options.DisableJumpTables && 2011 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2012 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2013} 2014 2015static APInt ComputeRange(const APInt &First, const APInt &Last) { 2016 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2017 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 2018 return (LastExt - FirstExt + 1ULL); 2019} 2020 2021/// handleJTSwitchCase - Emit jumptable for current switch case range 2022bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2023 CaseRecVector &WorkList, 2024 const Value *SV, 2025 MachineBasicBlock *Default, 2026 MachineBasicBlock *SwitchBB) { 2027 Case& FrontCase = *CR.Range.first; 2028 Case& BackCase = *(CR.Range.second-1); 2029 2030 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2031 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2032 2033 APInt TSize(First.getBitWidth(), 0); 2034 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2035 TSize += I->size(); 2036 2037 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2038 return false; 2039 2040 APInt Range = ComputeRange(First, Last); 2041 // The density is TSize / Range. Require at least 40%. 2042 // It should not be possible for IntTSize to saturate for sane code, but make 2043 // sure we handle Range saturation correctly. 2044 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2045 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2046 if (IntTSize * 10 < IntRange * 4) 2047 return false; 2048 2049 DEBUG(dbgs() << "Lowering jump table\n" 2050 << "First entry: " << First << ". Last entry: " << Last << '\n' 2051 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2052 2053 // Get the MachineFunction which holds the current MBB. This is used when 2054 // inserting any additional MBBs necessary to represent the switch. 2055 MachineFunction *CurMF = FuncInfo.MF; 2056 2057 // Figure out which block is immediately after the current one. 2058 MachineFunction::iterator BBI = CR.CaseBB; 2059 ++BBI; 2060 2061 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2062 2063 // Create a new basic block to hold the code for loading the address 2064 // of the jump table, and jumping to it. Update successor information; 2065 // we will either branch to the default case for the switch, or the jump 2066 // table. 2067 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2068 CurMF->insert(BBI, JumpTableBB); 2069 2070 addSuccessorWithWeight(CR.CaseBB, Default); 2071 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2072 2073 // Build a vector of destination BBs, corresponding to each target 2074 // of the jump table. If the value of the jump table slot corresponds to 2075 // a case statement, push the case's BB onto the vector, otherwise, push 2076 // the default BB. 2077 std::vector<MachineBasicBlock*> DestBBs; 2078 APInt TEI = First; 2079 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2080 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2081 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2082 2083 if (Low.sle(TEI) && TEI.sle(High)) { 2084 DestBBs.push_back(I->BB); 2085 if (TEI==High) 2086 ++I; 2087 } else { 2088 DestBBs.push_back(Default); 2089 } 2090 } 2091 2092 // Update successor info. Add one edge to each unique successor. 2093 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2094 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2095 E = DestBBs.end(); I != E; ++I) { 2096 if (!SuccsHandled[(*I)->getNumber()]) { 2097 SuccsHandled[(*I)->getNumber()] = true; 2098 addSuccessorWithWeight(JumpTableBB, *I); 2099 } 2100 } 2101 2102 // Create a jump table index for this jump table. 2103 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2104 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2105 ->createJumpTableIndex(DestBBs); 2106 2107 // Set the jump table information so that we can codegen it as a second 2108 // MachineBasicBlock 2109 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2110 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2111 if (CR.CaseBB == SwitchBB) 2112 visitJumpTableHeader(JT, JTH, SwitchBB); 2113 2114 JTCases.push_back(JumpTableBlock(JTH, JT)); 2115 return true; 2116} 2117 2118/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2119/// 2 subtrees. 2120bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2121 CaseRecVector& WorkList, 2122 const Value* SV, 2123 MachineBasicBlock *Default, 2124 MachineBasicBlock *SwitchBB) { 2125 // Get the MachineFunction which holds the current MBB. This is used when 2126 // inserting any additional MBBs necessary to represent the switch. 2127 MachineFunction *CurMF = FuncInfo.MF; 2128 2129 // Figure out which block is immediately after the current one. 2130 MachineFunction::iterator BBI = CR.CaseBB; 2131 ++BBI; 2132 2133 Case& FrontCase = *CR.Range.first; 2134 Case& BackCase = *(CR.Range.second-1); 2135 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2136 2137 // Size is the number of Cases represented by this range. 2138 unsigned Size = CR.Range.second - CR.Range.first; 2139 2140 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2141 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2142 double FMetric = 0; 2143 CaseItr Pivot = CR.Range.first + Size/2; 2144 2145 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2146 // (heuristically) allow us to emit JumpTable's later. 2147 APInt TSize(First.getBitWidth(), 0); 2148 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2149 I!=E; ++I) 2150 TSize += I->size(); 2151 2152 APInt LSize = FrontCase.size(); 2153 APInt RSize = TSize-LSize; 2154 DEBUG(dbgs() << "Selecting best pivot: \n" 2155 << "First: " << First << ", Last: " << Last <<'\n' 2156 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2157 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2158 J!=E; ++I, ++J) { 2159 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2160 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2161 APInt Range = ComputeRange(LEnd, RBegin); 2162 assert((Range - 2ULL).isNonNegative() && 2163 "Invalid case distance"); 2164 // Use volatile double here to avoid excess precision issues on some hosts, 2165 // e.g. that use 80-bit X87 registers. 2166 volatile double LDensity = 2167 (double)LSize.roundToDouble() / 2168 (LEnd - First + 1ULL).roundToDouble(); 2169 volatile double RDensity = 2170 (double)RSize.roundToDouble() / 2171 (Last - RBegin + 1ULL).roundToDouble(); 2172 double Metric = Range.logBase2()*(LDensity+RDensity); 2173 // Should always split in some non-trivial place 2174 DEBUG(dbgs() <<"=>Step\n" 2175 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2176 << "LDensity: " << LDensity 2177 << ", RDensity: " << RDensity << '\n' 2178 << "Metric: " << Metric << '\n'); 2179 if (FMetric < Metric) { 2180 Pivot = J; 2181 FMetric = Metric; 2182 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2183 } 2184 2185 LSize += J->size(); 2186 RSize -= J->size(); 2187 } 2188 if (areJTsAllowed(TLI)) { 2189 // If our case is dense we *really* should handle it earlier! 2190 assert((FMetric > 0) && "Should handle dense range earlier!"); 2191 } else { 2192 Pivot = CR.Range.first + Size/2; 2193 } 2194 2195 CaseRange LHSR(CR.Range.first, Pivot); 2196 CaseRange RHSR(Pivot, CR.Range.second); 2197 Constant *C = Pivot->Low; 2198 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2199 2200 // We know that we branch to the LHS if the Value being switched on is 2201 // less than the Pivot value, C. We use this to optimize our binary 2202 // tree a bit, by recognizing that if SV is greater than or equal to the 2203 // LHS's Case Value, and that Case Value is exactly one less than the 2204 // Pivot's Value, then we can branch directly to the LHS's Target, 2205 // rather than creating a leaf node for it. 2206 if ((LHSR.second - LHSR.first) == 1 && 2207 LHSR.first->High == CR.GE && 2208 cast<ConstantInt>(C)->getValue() == 2209 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2210 TrueBB = LHSR.first->BB; 2211 } else { 2212 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2213 CurMF->insert(BBI, TrueBB); 2214 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2215 2216 // Put SV in a virtual register to make it available from the new blocks. 2217 ExportFromCurrentBlock(SV); 2218 } 2219 2220 // Similar to the optimization above, if the Value being switched on is 2221 // known to be less than the Constant CR.LT, and the current Case Value 2222 // is CR.LT - 1, then we can branch directly to the target block for 2223 // the current Case Value, rather than emitting a RHS leaf node for it. 2224 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2225 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2226 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2227 FalseBB = RHSR.first->BB; 2228 } else { 2229 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2230 CurMF->insert(BBI, FalseBB); 2231 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2232 2233 // Put SV in a virtual register to make it available from the new blocks. 2234 ExportFromCurrentBlock(SV); 2235 } 2236 2237 // Create a CaseBlock record representing a conditional branch to 2238 // the LHS node if the value being switched on SV is less than C. 2239 // Otherwise, branch to LHS. 2240 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2241 2242 if (CR.CaseBB == SwitchBB) 2243 visitSwitchCase(CB, SwitchBB); 2244 else 2245 SwitchCases.push_back(CB); 2246 2247 return true; 2248} 2249 2250/// handleBitTestsSwitchCase - if current case range has few destination and 2251/// range span less, than machine word bitwidth, encode case range into series 2252/// of masks and emit bit tests with these masks. 2253bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2254 CaseRecVector& WorkList, 2255 const Value* SV, 2256 MachineBasicBlock* Default, 2257 MachineBasicBlock *SwitchBB){ 2258 EVT PTy = TLI.getPointerTy(); 2259 unsigned IntPtrBits = PTy.getSizeInBits(); 2260 2261 Case& FrontCase = *CR.Range.first; 2262 Case& BackCase = *(CR.Range.second-1); 2263 2264 // Get the MachineFunction which holds the current MBB. This is used when 2265 // inserting any additional MBBs necessary to represent the switch. 2266 MachineFunction *CurMF = FuncInfo.MF; 2267 2268 // If target does not have legal shift left, do not emit bit tests at all. 2269 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2270 return false; 2271 2272 size_t numCmps = 0; 2273 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2274 I!=E; ++I) { 2275 // Single case counts one, case range - two. 2276 numCmps += (I->Low == I->High ? 1 : 2); 2277 } 2278 2279 // Count unique destinations 2280 SmallSet<MachineBasicBlock*, 4> Dests; 2281 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2282 Dests.insert(I->BB); 2283 if (Dests.size() > 3) 2284 // Don't bother the code below, if there are too much unique destinations 2285 return false; 2286 } 2287 DEBUG(dbgs() << "Total number of unique destinations: " 2288 << Dests.size() << '\n' 2289 << "Total number of comparisons: " << numCmps << '\n'); 2290 2291 // Compute span of values. 2292 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2293 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2294 APInt cmpRange = maxValue - minValue; 2295 2296 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2297 << "Low bound: " << minValue << '\n' 2298 << "High bound: " << maxValue << '\n'); 2299 2300 if (cmpRange.uge(IntPtrBits) || 2301 (!(Dests.size() == 1 && numCmps >= 3) && 2302 !(Dests.size() == 2 && numCmps >= 5) && 2303 !(Dests.size() >= 3 && numCmps >= 6))) 2304 return false; 2305 2306 DEBUG(dbgs() << "Emitting bit tests\n"); 2307 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2308 2309 // Optimize the case where all the case values fit in a 2310 // word without having to subtract minValue. In this case, 2311 // we can optimize away the subtraction. 2312 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2313 cmpRange = maxValue; 2314 } else { 2315 lowBound = minValue; 2316 } 2317 2318 CaseBitsVector CasesBits; 2319 unsigned i, count = 0; 2320 2321 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2322 MachineBasicBlock* Dest = I->BB; 2323 for (i = 0; i < count; ++i) 2324 if (Dest == CasesBits[i].BB) 2325 break; 2326 2327 if (i == count) { 2328 assert((count < 3) && "Too much destinations to test!"); 2329 CasesBits.push_back(CaseBits(0, Dest, 0)); 2330 count++; 2331 } 2332 2333 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2334 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2335 2336 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2337 uint64_t hi = (highValue - lowBound).getZExtValue(); 2338 2339 for (uint64_t j = lo; j <= hi; j++) { 2340 CasesBits[i].Mask |= 1ULL << j; 2341 CasesBits[i].Bits++; 2342 } 2343 2344 } 2345 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2346 2347 BitTestInfo BTC; 2348 2349 // Figure out which block is immediately after the current one. 2350 MachineFunction::iterator BBI = CR.CaseBB; 2351 ++BBI; 2352 2353 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2354 2355 DEBUG(dbgs() << "Cases:\n"); 2356 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2357 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2358 << ", Bits: " << CasesBits[i].Bits 2359 << ", BB: " << CasesBits[i].BB << '\n'); 2360 2361 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2362 CurMF->insert(BBI, CaseBB); 2363 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2364 CaseBB, 2365 CasesBits[i].BB)); 2366 2367 // Put SV in a virtual register to make it available from the new blocks. 2368 ExportFromCurrentBlock(SV); 2369 } 2370 2371 BitTestBlock BTB(lowBound, cmpRange, SV, 2372 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2373 CR.CaseBB, Default, BTC); 2374 2375 if (CR.CaseBB == SwitchBB) 2376 visitBitTestHeader(BTB, SwitchBB); 2377 2378 BitTestCases.push_back(BTB); 2379 2380 return true; 2381} 2382 2383/// Clusterify - Transform simple list of Cases into list of CaseRange's 2384size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2385 const SwitchInst& SI) { 2386 size_t numCmps = 0; 2387 2388 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2389 // Start with "simple" cases 2390 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2391 BasicBlock *SuccBB = SI.getSuccessor(i); 2392 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2393 2394 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0; 2395 2396 Cases.push_back(Case(SI.getSuccessorValue(i), 2397 SI.getSuccessorValue(i), 2398 SMBB, ExtraWeight)); 2399 } 2400 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2401 2402 // Merge case into clusters 2403 if (Cases.size() >= 2) 2404 // Must recompute end() each iteration because it may be 2405 // invalidated by erase if we hold on to it 2406 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2407 J != Cases.end(); ) { 2408 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2409 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2410 MachineBasicBlock* nextBB = J->BB; 2411 MachineBasicBlock* currentBB = I->BB; 2412 2413 // If the two neighboring cases go to the same destination, merge them 2414 // into a single case. 2415 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2416 I->High = J->High; 2417 J = Cases.erase(J); 2418 2419 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) { 2420 uint32_t CurWeight = currentBB->getBasicBlock() ? 2421 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16; 2422 uint32_t NextWeight = nextBB->getBasicBlock() ? 2423 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16; 2424 2425 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(), 2426 CurWeight + NextWeight); 2427 } 2428 } else { 2429 I = J++; 2430 } 2431 } 2432 2433 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2434 if (I->Low != I->High) 2435 // A range counts double, since it requires two compares. 2436 ++numCmps; 2437 } 2438 2439 return numCmps; 2440} 2441 2442void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2443 MachineBasicBlock *Last) { 2444 // Update JTCases. 2445 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2446 if (JTCases[i].first.HeaderBB == First) 2447 JTCases[i].first.HeaderBB = Last; 2448 2449 // Update BitTestCases. 2450 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2451 if (BitTestCases[i].Parent == First) 2452 BitTestCases[i].Parent = Last; 2453} 2454 2455void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2456 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2457 2458 // Figure out which block is immediately after the current one. 2459 MachineBasicBlock *NextBlock = 0; 2460 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2461 2462 // If there is only the default destination, branch to it if it is not the 2463 // next basic block. Otherwise, just fall through. 2464 if (SI.getNumCases() == 1) { 2465 // Update machine-CFG edges. 2466 2467 // If this is not a fall-through branch, emit the branch. 2468 SwitchMBB->addSuccessor(Default); 2469 if (Default != NextBlock) 2470 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2471 MVT::Other, getControlRoot(), 2472 DAG.getBasicBlock(Default))); 2473 2474 return; 2475 } 2476 2477 // If there are any non-default case statements, create a vector of Cases 2478 // representing each one, and sort the vector so that we can efficiently 2479 // create a binary search tree from them. 2480 CaseVector Cases; 2481 size_t numCmps = Clusterify(Cases, SI); 2482 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2483 << ". Total compares: " << numCmps << '\n'); 2484 (void)numCmps; 2485 2486 // Get the Value to be switched on and default basic blocks, which will be 2487 // inserted into CaseBlock records, representing basic blocks in the binary 2488 // search tree. 2489 const Value *SV = SI.getCondition(); 2490 2491 // Push the initial CaseRec onto the worklist 2492 CaseRecVector WorkList; 2493 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2494 CaseRange(Cases.begin(),Cases.end()))); 2495 2496 while (!WorkList.empty()) { 2497 // Grab a record representing a case range to process off the worklist 2498 CaseRec CR = WorkList.back(); 2499 WorkList.pop_back(); 2500 2501 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2502 continue; 2503 2504 // If the range has few cases (two or less) emit a series of specific 2505 // tests. 2506 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2507 continue; 2508 2509 // If the switch has more than 5 blocks, and at least 40% dense, and the 2510 // target supports indirect branches, then emit a jump table rather than 2511 // lowering the switch to a binary tree of conditional branches. 2512 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2513 continue; 2514 2515 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2516 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2517 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2518 } 2519} 2520 2521void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2522 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2523 2524 // Update machine-CFG edges with unique successors. 2525 SmallVector<BasicBlock*, 32> succs; 2526 succs.reserve(I.getNumSuccessors()); 2527 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2528 succs.push_back(I.getSuccessor(i)); 2529 array_pod_sort(succs.begin(), succs.end()); 2530 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2531 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2532 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2533 addSuccessorWithWeight(IndirectBrMBB, Succ); 2534 } 2535 2536 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2537 MVT::Other, getControlRoot(), 2538 getValue(I.getAddress()))); 2539} 2540 2541void SelectionDAGBuilder::visitFSub(const User &I) { 2542 // -0.0 - X --> fneg 2543 Type *Ty = I.getType(); 2544 if (isa<Constant>(I.getOperand(0)) && 2545 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2546 SDValue Op2 = getValue(I.getOperand(1)); 2547 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2548 Op2.getValueType(), Op2)); 2549 return; 2550 } 2551 2552 visitBinary(I, ISD::FSUB); 2553} 2554 2555void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2556 SDValue Op1 = getValue(I.getOperand(0)); 2557 SDValue Op2 = getValue(I.getOperand(1)); 2558 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2559 Op1.getValueType(), Op1, Op2)); 2560} 2561 2562void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2563 SDValue Op1 = getValue(I.getOperand(0)); 2564 SDValue Op2 = getValue(I.getOperand(1)); 2565 2566 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2567 2568 // Coerce the shift amount to the right type if we can. 2569 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2570 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2571 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2572 DebugLoc DL = getCurDebugLoc(); 2573 2574 // If the operand is smaller than the shift count type, promote it. 2575 if (ShiftSize > Op2Size) 2576 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2577 2578 // If the operand is larger than the shift count type but the shift 2579 // count type has enough bits to represent any shift value, truncate 2580 // it now. This is a common case and it exposes the truncate to 2581 // optimization early. 2582 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2583 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2584 // Otherwise we'll need to temporarily settle for some other convenient 2585 // type. Type legalization will make adjustments once the shiftee is split. 2586 else 2587 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2588 } 2589 2590 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2591 Op1.getValueType(), Op1, Op2)); 2592} 2593 2594void SelectionDAGBuilder::visitSDiv(const User &I) { 2595 SDValue Op1 = getValue(I.getOperand(0)); 2596 SDValue Op2 = getValue(I.getOperand(1)); 2597 2598 // Turn exact SDivs into multiplications. 2599 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2600 // exact bit. 2601 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2602 !isa<ConstantSDNode>(Op1) && 2603 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2604 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2605 else 2606 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2607 Op1, Op2)); 2608} 2609 2610void SelectionDAGBuilder::visitICmp(const User &I) { 2611 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2612 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2613 predicate = IC->getPredicate(); 2614 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2615 predicate = ICmpInst::Predicate(IC->getPredicate()); 2616 SDValue Op1 = getValue(I.getOperand(0)); 2617 SDValue Op2 = getValue(I.getOperand(1)); 2618 ISD::CondCode Opcode = getICmpCondCode(predicate); 2619 2620 EVT DestVT = TLI.getValueType(I.getType()); 2621 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2622} 2623 2624void SelectionDAGBuilder::visitFCmp(const User &I) { 2625 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2626 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2627 predicate = FC->getPredicate(); 2628 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2629 predicate = FCmpInst::Predicate(FC->getPredicate()); 2630 SDValue Op1 = getValue(I.getOperand(0)); 2631 SDValue Op2 = getValue(I.getOperand(1)); 2632 ISD::CondCode Condition = getFCmpCondCode(predicate); 2633 if (TM.Options.NoNaNsFPMath) 2634 Condition = getFCmpCodeWithoutNaN(Condition); 2635 EVT DestVT = TLI.getValueType(I.getType()); 2636 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2637} 2638 2639void SelectionDAGBuilder::visitSelect(const User &I) { 2640 SmallVector<EVT, 4> ValueVTs; 2641 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2642 unsigned NumValues = ValueVTs.size(); 2643 if (NumValues == 0) return; 2644 2645 SmallVector<SDValue, 4> Values(NumValues); 2646 SDValue Cond = getValue(I.getOperand(0)); 2647 SDValue TrueVal = getValue(I.getOperand(1)); 2648 SDValue FalseVal = getValue(I.getOperand(2)); 2649 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2650 ISD::VSELECT : ISD::SELECT; 2651 2652 for (unsigned i = 0; i != NumValues; ++i) 2653 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2654 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2655 Cond, 2656 SDValue(TrueVal.getNode(), 2657 TrueVal.getResNo() + i), 2658 SDValue(FalseVal.getNode(), 2659 FalseVal.getResNo() + i)); 2660 2661 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2662 DAG.getVTList(&ValueVTs[0], NumValues), 2663 &Values[0], NumValues)); 2664} 2665 2666void SelectionDAGBuilder::visitTrunc(const User &I) { 2667 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2668 SDValue N = getValue(I.getOperand(0)); 2669 EVT DestVT = TLI.getValueType(I.getType()); 2670 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2671} 2672 2673void SelectionDAGBuilder::visitZExt(const User &I) { 2674 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2675 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2676 SDValue N = getValue(I.getOperand(0)); 2677 EVT DestVT = TLI.getValueType(I.getType()); 2678 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2679} 2680 2681void SelectionDAGBuilder::visitSExt(const User &I) { 2682 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2683 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2684 SDValue N = getValue(I.getOperand(0)); 2685 EVT DestVT = TLI.getValueType(I.getType()); 2686 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2687} 2688 2689void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2690 // FPTrunc is never a no-op cast, no need to check 2691 SDValue N = getValue(I.getOperand(0)); 2692 EVT DestVT = TLI.getValueType(I.getType()); 2693 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2694 DestVT, N, 2695 DAG.getTargetConstant(0, TLI.getPointerTy()))); 2696} 2697 2698void SelectionDAGBuilder::visitFPExt(const User &I){ 2699 // FPExt is never a no-op cast, no need to check 2700 SDValue N = getValue(I.getOperand(0)); 2701 EVT DestVT = TLI.getValueType(I.getType()); 2702 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2703} 2704 2705void SelectionDAGBuilder::visitFPToUI(const User &I) { 2706 // FPToUI is never a no-op cast, no need to check 2707 SDValue N = getValue(I.getOperand(0)); 2708 EVT DestVT = TLI.getValueType(I.getType()); 2709 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2710} 2711 2712void SelectionDAGBuilder::visitFPToSI(const User &I) { 2713 // FPToSI is never a no-op cast, no need to check 2714 SDValue N = getValue(I.getOperand(0)); 2715 EVT DestVT = TLI.getValueType(I.getType()); 2716 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2717} 2718 2719void SelectionDAGBuilder::visitUIToFP(const User &I) { 2720 // UIToFP is never a no-op cast, no need to check 2721 SDValue N = getValue(I.getOperand(0)); 2722 EVT DestVT = TLI.getValueType(I.getType()); 2723 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2724} 2725 2726void SelectionDAGBuilder::visitSIToFP(const User &I){ 2727 // SIToFP is never a no-op cast, no need to check 2728 SDValue N = getValue(I.getOperand(0)); 2729 EVT DestVT = TLI.getValueType(I.getType()); 2730 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2731} 2732 2733void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2734 // What to do depends on the size of the integer and the size of the pointer. 2735 // We can either truncate, zero extend, or no-op, accordingly. 2736 SDValue N = getValue(I.getOperand(0)); 2737 EVT DestVT = TLI.getValueType(I.getType()); 2738 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2739} 2740 2741void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2742 // What to do depends on the size of the integer and the size of the pointer. 2743 // We can either truncate, zero extend, or no-op, accordingly. 2744 SDValue N = getValue(I.getOperand(0)); 2745 EVT DestVT = TLI.getValueType(I.getType()); 2746 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2747} 2748 2749void SelectionDAGBuilder::visitBitCast(const User &I) { 2750 SDValue N = getValue(I.getOperand(0)); 2751 EVT DestVT = TLI.getValueType(I.getType()); 2752 2753 // BitCast assures us that source and destination are the same size so this is 2754 // either a BITCAST or a no-op. 2755 if (DestVT != N.getValueType()) 2756 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2757 DestVT, N)); // convert types. 2758 else 2759 setValue(&I, N); // noop cast. 2760} 2761 2762void SelectionDAGBuilder::visitInsertElement(const User &I) { 2763 SDValue InVec = getValue(I.getOperand(0)); 2764 SDValue InVal = getValue(I.getOperand(1)); 2765 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2766 TLI.getPointerTy(), 2767 getValue(I.getOperand(2))); 2768 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2769 TLI.getValueType(I.getType()), 2770 InVec, InVal, InIdx)); 2771} 2772 2773void SelectionDAGBuilder::visitExtractElement(const User &I) { 2774 SDValue InVec = getValue(I.getOperand(0)); 2775 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2776 TLI.getPointerTy(), 2777 getValue(I.getOperand(1))); 2778 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2779 TLI.getValueType(I.getType()), InVec, InIdx)); 2780} 2781 2782// Utility for visitShuffleVector - Return true if every element in Mask, 2783// begining // from position Pos and ending in Pos+Size, falls within the 2784// specified sequential range [L, L+Pos). or is undef. 2785static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2786 int Pos, int Size, int Low) { 2787 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2788 if (Mask[i] >= 0 && Mask[i] != Low) 2789 return false; 2790 return true; 2791} 2792 2793void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2794 SmallVector<int, 8> Mask; 2795 SDValue Src1 = getValue(I.getOperand(0)); 2796 SDValue Src2 = getValue(I.getOperand(1)); 2797 2798 // Convert the ConstantVector mask operand into an array of ints, with -1 2799 // representing undef values. 2800 SmallVector<Constant*, 8> MaskElts; 2801 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2802 unsigned MaskNumElts = MaskElts.size(); 2803 for (unsigned i = 0; i != MaskNumElts; ++i) { 2804 if (isa<UndefValue>(MaskElts[i])) 2805 Mask.push_back(-1); 2806 else 2807 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2808 } 2809 2810 EVT VT = TLI.getValueType(I.getType()); 2811 EVT SrcVT = Src1.getValueType(); 2812 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2813 2814 if (SrcNumElts == MaskNumElts) { 2815 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2816 &Mask[0])); 2817 return; 2818 } 2819 2820 // Normalize the shuffle vector since mask and vector length don't match. 2821 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2822 // Mask is longer than the source vectors and is a multiple of the source 2823 // vectors. We can use concatenate vector to make the mask and vectors 2824 // lengths match. 2825 if (SrcNumElts*2 == MaskNumElts) { 2826 // First check for Src1 in low and Src2 in high 2827 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 2828 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 2829 // The shuffle is concatenating two vectors together. 2830 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2831 VT, Src1, Src2)); 2832 return; 2833 } 2834 // Then check for Src2 in low and Src1 in high 2835 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 2836 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 2837 // The shuffle is concatenating two vectors together. 2838 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2839 VT, Src2, Src1)); 2840 return; 2841 } 2842 } 2843 2844 // Pad both vectors with undefs to make them the same length as the mask. 2845 unsigned NumConcat = MaskNumElts / SrcNumElts; 2846 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2847 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2848 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2849 2850 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2851 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2852 MOps1[0] = Src1; 2853 MOps2[0] = Src2; 2854 2855 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2856 getCurDebugLoc(), VT, 2857 &MOps1[0], NumConcat); 2858 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2859 getCurDebugLoc(), VT, 2860 &MOps2[0], NumConcat); 2861 2862 // Readjust mask for new input vector length. 2863 SmallVector<int, 8> MappedOps; 2864 for (unsigned i = 0; i != MaskNumElts; ++i) { 2865 int Idx = Mask[i]; 2866 if (Idx < (int)SrcNumElts) 2867 MappedOps.push_back(Idx); 2868 else 2869 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2870 } 2871 2872 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2873 &MappedOps[0])); 2874 return; 2875 } 2876 2877 if (SrcNumElts > MaskNumElts) { 2878 // Analyze the access pattern of the vector to see if we can extract 2879 // two subvectors and do the shuffle. The analysis is done by calculating 2880 // the range of elements the mask access on both vectors. 2881 int MinRange[2] = { static_cast<int>(SrcNumElts+1), 2882 static_cast<int>(SrcNumElts+1)}; 2883 int MaxRange[2] = {-1, -1}; 2884 2885 for (unsigned i = 0; i != MaskNumElts; ++i) { 2886 int Idx = Mask[i]; 2887 int Input = 0; 2888 if (Idx < 0) 2889 continue; 2890 2891 if (Idx >= (int)SrcNumElts) { 2892 Input = 1; 2893 Idx -= SrcNumElts; 2894 } 2895 if (Idx > MaxRange[Input]) 2896 MaxRange[Input] = Idx; 2897 if (Idx < MinRange[Input]) 2898 MinRange[Input] = Idx; 2899 } 2900 2901 // Check if the access is smaller than the vector size and can we find 2902 // a reasonable extract index. 2903 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2904 // Extract. 2905 int StartIdx[2]; // StartIdx to extract from 2906 for (int Input=0; Input < 2; ++Input) { 2907 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2908 RangeUse[Input] = 0; // Unused 2909 StartIdx[Input] = 0; 2910 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2911 // Fits within range but we should see if we can find a good 2912 // start index that is a multiple of the mask length. 2913 if (MaxRange[Input] < (int)MaskNumElts) { 2914 RangeUse[Input] = 1; // Extract from beginning of the vector 2915 StartIdx[Input] = 0; 2916 } else { 2917 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2918 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2919 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2920 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2921 } 2922 } 2923 } 2924 2925 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2926 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2927 return; 2928 } 2929 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2930 // Extract appropriate subvector and generate a vector shuffle 2931 for (int Input=0; Input < 2; ++Input) { 2932 SDValue &Src = Input == 0 ? Src1 : Src2; 2933 if (RangeUse[Input] == 0) 2934 Src = DAG.getUNDEF(VT); 2935 else 2936 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2937 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2938 } 2939 2940 // Calculate new mask. 2941 SmallVector<int, 8> MappedOps; 2942 for (unsigned i = 0; i != MaskNumElts; ++i) { 2943 int Idx = Mask[i]; 2944 if (Idx < 0) 2945 MappedOps.push_back(Idx); 2946 else if (Idx < (int)SrcNumElts) 2947 MappedOps.push_back(Idx - StartIdx[0]); 2948 else 2949 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2950 } 2951 2952 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2953 &MappedOps[0])); 2954 return; 2955 } 2956 } 2957 2958 // We can't use either concat vectors or extract subvectors so fall back to 2959 // replacing the shuffle with extract and build vector. 2960 // to insert and build vector. 2961 EVT EltVT = VT.getVectorElementType(); 2962 EVT PtrVT = TLI.getPointerTy(); 2963 SmallVector<SDValue,8> Ops; 2964 for (unsigned i = 0; i != MaskNumElts; ++i) { 2965 if (Mask[i] < 0) { 2966 Ops.push_back(DAG.getUNDEF(EltVT)); 2967 } else { 2968 int Idx = Mask[i]; 2969 SDValue Res; 2970 2971 if (Idx < (int)SrcNumElts) 2972 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2973 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2974 else 2975 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2976 EltVT, Src2, 2977 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2978 2979 Ops.push_back(Res); 2980 } 2981 } 2982 2983 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2984 VT, &Ops[0], Ops.size())); 2985} 2986 2987void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2988 const Value *Op0 = I.getOperand(0); 2989 const Value *Op1 = I.getOperand(1); 2990 Type *AggTy = I.getType(); 2991 Type *ValTy = Op1->getType(); 2992 bool IntoUndef = isa<UndefValue>(Op0); 2993 bool FromUndef = isa<UndefValue>(Op1); 2994 2995 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2996 2997 SmallVector<EVT, 4> AggValueVTs; 2998 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2999 SmallVector<EVT, 4> ValValueVTs; 3000 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3001 3002 unsigned NumAggValues = AggValueVTs.size(); 3003 unsigned NumValValues = ValValueVTs.size(); 3004 SmallVector<SDValue, 4> Values(NumAggValues); 3005 3006 SDValue Agg = getValue(Op0); 3007 unsigned i = 0; 3008 // Copy the beginning value(s) from the original aggregate. 3009 for (; i != LinearIndex; ++i) 3010 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3011 SDValue(Agg.getNode(), Agg.getResNo() + i); 3012 // Copy values from the inserted value(s). 3013 if (NumValValues) { 3014 SDValue Val = getValue(Op1); 3015 for (; i != LinearIndex + NumValValues; ++i) 3016 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3017 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3018 } 3019 // Copy remaining value(s) from the original aggregate. 3020 for (; i != NumAggValues; ++i) 3021 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3022 SDValue(Agg.getNode(), Agg.getResNo() + i); 3023 3024 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3025 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3026 &Values[0], NumAggValues)); 3027} 3028 3029void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3030 const Value *Op0 = I.getOperand(0); 3031 Type *AggTy = Op0->getType(); 3032 Type *ValTy = I.getType(); 3033 bool OutOfUndef = isa<UndefValue>(Op0); 3034 3035 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3036 3037 SmallVector<EVT, 4> ValValueVTs; 3038 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3039 3040 unsigned NumValValues = ValValueVTs.size(); 3041 3042 // Ignore a extractvalue that produces an empty object 3043 if (!NumValValues) { 3044 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3045 return; 3046 } 3047 3048 SmallVector<SDValue, 4> Values(NumValValues); 3049 3050 SDValue Agg = getValue(Op0); 3051 // Copy out the selected value(s). 3052 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3053 Values[i - LinearIndex] = 3054 OutOfUndef ? 3055 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3056 SDValue(Agg.getNode(), Agg.getResNo() + i); 3057 3058 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3059 DAG.getVTList(&ValValueVTs[0], NumValValues), 3060 &Values[0], NumValValues)); 3061} 3062 3063void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3064 SDValue N = getValue(I.getOperand(0)); 3065 Type *Ty = I.getOperand(0)->getType(); 3066 3067 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3068 OI != E; ++OI) { 3069 const Value *Idx = *OI; 3070 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3071 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3072 if (Field) { 3073 // N = N + Offset 3074 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3075 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3076 DAG.getIntPtrConstant(Offset)); 3077 } 3078 3079 Ty = StTy->getElementType(Field); 3080 } else { 3081 Ty = cast<SequentialType>(Ty)->getElementType(); 3082 3083 // If this is a constant subscript, handle it quickly. 3084 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3085 if (CI->isZero()) continue; 3086 uint64_t Offs = 3087 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3088 SDValue OffsVal; 3089 EVT PTy = TLI.getPointerTy(); 3090 unsigned PtrBits = PTy.getSizeInBits(); 3091 if (PtrBits < 64) 3092 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3093 TLI.getPointerTy(), 3094 DAG.getConstant(Offs, MVT::i64)); 3095 else 3096 OffsVal = DAG.getIntPtrConstant(Offs); 3097 3098 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3099 OffsVal); 3100 continue; 3101 } 3102 3103 // N = N + Idx * ElementSize; 3104 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3105 TD->getTypeAllocSize(Ty)); 3106 SDValue IdxN = getValue(Idx); 3107 3108 // If the index is smaller or larger than intptr_t, truncate or extend 3109 // it. 3110 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3111 3112 // If this is a multiply by a power of two, turn it into a shl 3113 // immediately. This is a very common case. 3114 if (ElementSize != 1) { 3115 if (ElementSize.isPowerOf2()) { 3116 unsigned Amt = ElementSize.logBase2(); 3117 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3118 N.getValueType(), IdxN, 3119 DAG.getConstant(Amt, IdxN.getValueType())); 3120 } else { 3121 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3122 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3123 N.getValueType(), IdxN, Scale); 3124 } 3125 } 3126 3127 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3128 N.getValueType(), N, IdxN); 3129 } 3130 } 3131 3132 setValue(&I, N); 3133} 3134 3135void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3136 // If this is a fixed sized alloca in the entry block of the function, 3137 // allocate it statically on the stack. 3138 if (FuncInfo.StaticAllocaMap.count(&I)) 3139 return; // getValue will auto-populate this. 3140 3141 Type *Ty = I.getAllocatedType(); 3142 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3143 unsigned Align = 3144 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3145 I.getAlignment()); 3146 3147 SDValue AllocSize = getValue(I.getArraySize()); 3148 3149 EVT IntPtr = TLI.getPointerTy(); 3150 if (AllocSize.getValueType() != IntPtr) 3151 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3152 3153 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3154 AllocSize, 3155 DAG.getConstant(TySize, IntPtr)); 3156 3157 // Handle alignment. If the requested alignment is less than or equal to 3158 // the stack alignment, ignore it. If the size is greater than or equal to 3159 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3160 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3161 if (Align <= StackAlign) 3162 Align = 0; 3163 3164 // Round the size of the allocation up to the stack alignment size 3165 // by add SA-1 to the size. 3166 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3167 AllocSize.getValueType(), AllocSize, 3168 DAG.getIntPtrConstant(StackAlign-1)); 3169 3170 // Mask out the low bits for alignment purposes. 3171 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3172 AllocSize.getValueType(), AllocSize, 3173 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3174 3175 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3176 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3177 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3178 VTs, Ops, 3); 3179 setValue(&I, DSA); 3180 DAG.setRoot(DSA.getValue(1)); 3181 3182 // Inform the Frame Information that we have just allocated a variable-sized 3183 // object. 3184 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3185} 3186 3187void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3188 if (I.isAtomic()) 3189 return visitAtomicLoad(I); 3190 3191 const Value *SV = I.getOperand(0); 3192 SDValue Ptr = getValue(SV); 3193 3194 Type *Ty = I.getType(); 3195 3196 bool isVolatile = I.isVolatile(); 3197 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3198 bool isInvariant = I.getMetadata("invariant.load") != 0; 3199 unsigned Alignment = I.getAlignment(); 3200 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3201 3202 SmallVector<EVT, 4> ValueVTs; 3203 SmallVector<uint64_t, 4> Offsets; 3204 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3205 unsigned NumValues = ValueVTs.size(); 3206 if (NumValues == 0) 3207 return; 3208 3209 SDValue Root; 3210 bool ConstantMemory = false; 3211 if (I.isVolatile() || NumValues > MaxParallelChains) 3212 // Serialize volatile loads with other side effects. 3213 Root = getRoot(); 3214 else if (AA->pointsToConstantMemory( 3215 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3216 // Do not serialize (non-volatile) loads of constant memory with anything. 3217 Root = DAG.getEntryNode(); 3218 ConstantMemory = true; 3219 } else { 3220 // Do not serialize non-volatile loads against each other. 3221 Root = DAG.getRoot(); 3222 } 3223 3224 SmallVector<SDValue, 4> Values(NumValues); 3225 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3226 NumValues)); 3227 EVT PtrVT = Ptr.getValueType(); 3228 unsigned ChainI = 0; 3229 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3230 // Serializing loads here may result in excessive register pressure, and 3231 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3232 // could recover a bit by hoisting nodes upward in the chain by recognizing 3233 // they are side-effect free or do not alias. The optimizer should really 3234 // avoid this case by converting large object/array copies to llvm.memcpy 3235 // (MaxParallelChains should always remain as failsafe). 3236 if (ChainI == MaxParallelChains) { 3237 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3238 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3239 MVT::Other, &Chains[0], ChainI); 3240 Root = Chain; 3241 ChainI = 0; 3242 } 3243 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3244 PtrVT, Ptr, 3245 DAG.getConstant(Offsets[i], PtrVT)); 3246 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3247 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3248 isNonTemporal, isInvariant, Alignment, TBAAInfo); 3249 3250 Values[i] = L; 3251 Chains[ChainI] = L.getValue(1); 3252 } 3253 3254 if (!ConstantMemory) { 3255 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3256 MVT::Other, &Chains[0], ChainI); 3257 if (isVolatile) 3258 DAG.setRoot(Chain); 3259 else 3260 PendingLoads.push_back(Chain); 3261 } 3262 3263 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3264 DAG.getVTList(&ValueVTs[0], NumValues), 3265 &Values[0], NumValues)); 3266} 3267 3268void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3269 if (I.isAtomic()) 3270 return visitAtomicStore(I); 3271 3272 const Value *SrcV = I.getOperand(0); 3273 const Value *PtrV = I.getOperand(1); 3274 3275 SmallVector<EVT, 4> ValueVTs; 3276 SmallVector<uint64_t, 4> Offsets; 3277 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3278 unsigned NumValues = ValueVTs.size(); 3279 if (NumValues == 0) 3280 return; 3281 3282 // Get the lowered operands. Note that we do this after 3283 // checking if NumResults is zero, because with zero results 3284 // the operands won't have values in the map. 3285 SDValue Src = getValue(SrcV); 3286 SDValue Ptr = getValue(PtrV); 3287 3288 SDValue Root = getRoot(); 3289 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3290 NumValues)); 3291 EVT PtrVT = Ptr.getValueType(); 3292 bool isVolatile = I.isVolatile(); 3293 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3294 unsigned Alignment = I.getAlignment(); 3295 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3296 3297 unsigned ChainI = 0; 3298 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3299 // See visitLoad comments. 3300 if (ChainI == MaxParallelChains) { 3301 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3302 MVT::Other, &Chains[0], ChainI); 3303 Root = Chain; 3304 ChainI = 0; 3305 } 3306 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3307 DAG.getConstant(Offsets[i], PtrVT)); 3308 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3309 SDValue(Src.getNode(), Src.getResNo() + i), 3310 Add, MachinePointerInfo(PtrV, Offsets[i]), 3311 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3312 Chains[ChainI] = St; 3313 } 3314 3315 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3316 MVT::Other, &Chains[0], ChainI); 3317 ++SDNodeOrder; 3318 AssignOrderingToNode(StoreNode.getNode()); 3319 DAG.setRoot(StoreNode); 3320} 3321 3322static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3323 SynchronizationScope Scope, 3324 bool Before, DebugLoc dl, 3325 SelectionDAG &DAG, 3326 const TargetLowering &TLI) { 3327 // Fence, if necessary 3328 if (Before) { 3329 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3330 Order = Release; 3331 else if (Order == Acquire || Order == Monotonic) 3332 return Chain; 3333 } else { 3334 if (Order == AcquireRelease) 3335 Order = Acquire; 3336 else if (Order == Release || Order == Monotonic) 3337 return Chain; 3338 } 3339 SDValue Ops[3]; 3340 Ops[0] = Chain; 3341 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3342 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3343 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3344} 3345 3346void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3347 DebugLoc dl = getCurDebugLoc(); 3348 AtomicOrdering Order = I.getOrdering(); 3349 SynchronizationScope Scope = I.getSynchScope(); 3350 3351 SDValue InChain = getRoot(); 3352 3353 if (TLI.getInsertFencesForAtomic()) 3354 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3355 DAG, TLI); 3356 3357 SDValue L = 3358 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3359 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3360 InChain, 3361 getValue(I.getPointerOperand()), 3362 getValue(I.getCompareOperand()), 3363 getValue(I.getNewValOperand()), 3364 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3365 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3366 Scope); 3367 3368 SDValue OutChain = L.getValue(1); 3369 3370 if (TLI.getInsertFencesForAtomic()) 3371 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3372 DAG, TLI); 3373 3374 setValue(&I, L); 3375 DAG.setRoot(OutChain); 3376} 3377 3378void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3379 DebugLoc dl = getCurDebugLoc(); 3380 ISD::NodeType NT; 3381 switch (I.getOperation()) { 3382 default: llvm_unreachable("Unknown atomicrmw operation"); return; 3383 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3384 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3385 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3386 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3387 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3388 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3389 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3390 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3391 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3392 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3393 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3394 } 3395 AtomicOrdering Order = I.getOrdering(); 3396 SynchronizationScope Scope = I.getSynchScope(); 3397 3398 SDValue InChain = getRoot(); 3399 3400 if (TLI.getInsertFencesForAtomic()) 3401 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3402 DAG, TLI); 3403 3404 SDValue L = 3405 DAG.getAtomic(NT, dl, 3406 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3407 InChain, 3408 getValue(I.getPointerOperand()), 3409 getValue(I.getValOperand()), 3410 I.getPointerOperand(), 0 /* Alignment */, 3411 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3412 Scope); 3413 3414 SDValue OutChain = L.getValue(1); 3415 3416 if (TLI.getInsertFencesForAtomic()) 3417 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3418 DAG, TLI); 3419 3420 setValue(&I, L); 3421 DAG.setRoot(OutChain); 3422} 3423 3424void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3425 DebugLoc dl = getCurDebugLoc(); 3426 SDValue Ops[3]; 3427 Ops[0] = getRoot(); 3428 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3429 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3430 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3431} 3432 3433void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3434 DebugLoc dl = getCurDebugLoc(); 3435 AtomicOrdering Order = I.getOrdering(); 3436 SynchronizationScope Scope = I.getSynchScope(); 3437 3438 SDValue InChain = getRoot(); 3439 3440 EVT VT = EVT::getEVT(I.getType()); 3441 3442 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3443 report_fatal_error("Cannot generate unaligned atomic load"); 3444 3445 SDValue L = 3446 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3447 getValue(I.getPointerOperand()), 3448 I.getPointerOperand(), I.getAlignment(), 3449 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3450 Scope); 3451 3452 SDValue OutChain = L.getValue(1); 3453 3454 if (TLI.getInsertFencesForAtomic()) 3455 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3456 DAG, TLI); 3457 3458 setValue(&I, L); 3459 DAG.setRoot(OutChain); 3460} 3461 3462void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3463 DebugLoc dl = getCurDebugLoc(); 3464 3465 AtomicOrdering Order = I.getOrdering(); 3466 SynchronizationScope Scope = I.getSynchScope(); 3467 3468 SDValue InChain = getRoot(); 3469 3470 EVT VT = EVT::getEVT(I.getValueOperand()->getType()); 3471 3472 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3473 report_fatal_error("Cannot generate unaligned atomic store"); 3474 3475 if (TLI.getInsertFencesForAtomic()) 3476 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3477 DAG, TLI); 3478 3479 SDValue OutChain = 3480 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3481 InChain, 3482 getValue(I.getPointerOperand()), 3483 getValue(I.getValueOperand()), 3484 I.getPointerOperand(), I.getAlignment(), 3485 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3486 Scope); 3487 3488 if (TLI.getInsertFencesForAtomic()) 3489 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3490 DAG, TLI); 3491 3492 DAG.setRoot(OutChain); 3493} 3494 3495/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3496/// node. 3497void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3498 unsigned Intrinsic) { 3499 bool HasChain = !I.doesNotAccessMemory(); 3500 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3501 3502 // Build the operand list. 3503 SmallVector<SDValue, 8> Ops; 3504 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3505 if (OnlyLoad) { 3506 // We don't need to serialize loads against other loads. 3507 Ops.push_back(DAG.getRoot()); 3508 } else { 3509 Ops.push_back(getRoot()); 3510 } 3511 } 3512 3513 // Info is set by getTgtMemInstrinsic 3514 TargetLowering::IntrinsicInfo Info; 3515 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3516 3517 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3518 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3519 Info.opc == ISD::INTRINSIC_W_CHAIN) 3520 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy())); 3521 3522 // Add all operands of the call to the operand list. 3523 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3524 SDValue Op = getValue(I.getArgOperand(i)); 3525 Ops.push_back(Op); 3526 } 3527 3528 SmallVector<EVT, 4> ValueVTs; 3529 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3530 3531 if (HasChain) 3532 ValueVTs.push_back(MVT::Other); 3533 3534 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3535 3536 // Create the node. 3537 SDValue Result; 3538 if (IsTgtIntrinsic) { 3539 // This is target intrinsic that touches memory 3540 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3541 VTs, &Ops[0], Ops.size(), 3542 Info.memVT, 3543 MachinePointerInfo(Info.ptrVal, Info.offset), 3544 Info.align, Info.vol, 3545 Info.readMem, Info.writeMem); 3546 } else if (!HasChain) { 3547 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3548 VTs, &Ops[0], Ops.size()); 3549 } else if (!I.getType()->isVoidTy()) { 3550 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3551 VTs, &Ops[0], Ops.size()); 3552 } else { 3553 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3554 VTs, &Ops[0], Ops.size()); 3555 } 3556 3557 if (HasChain) { 3558 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3559 if (OnlyLoad) 3560 PendingLoads.push_back(Chain); 3561 else 3562 DAG.setRoot(Chain); 3563 } 3564 3565 if (!I.getType()->isVoidTy()) { 3566 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3567 EVT VT = TLI.getValueType(PTy); 3568 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3569 } 3570 3571 setValue(&I, Result); 3572 } 3573} 3574 3575/// GetSignificand - Get the significand and build it into a floating-point 3576/// number with exponent of 1: 3577/// 3578/// Op = (Op & 0x007fffff) | 0x3f800000; 3579/// 3580/// where Op is the hexidecimal representation of floating point value. 3581static SDValue 3582GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3583 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3584 DAG.getConstant(0x007fffff, MVT::i32)); 3585 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3586 DAG.getConstant(0x3f800000, MVT::i32)); 3587 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3588} 3589 3590/// GetExponent - Get the exponent: 3591/// 3592/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3593/// 3594/// where Op is the hexidecimal representation of floating point value. 3595static SDValue 3596GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3597 DebugLoc dl) { 3598 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3599 DAG.getConstant(0x7f800000, MVT::i32)); 3600 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3601 DAG.getConstant(23, TLI.getPointerTy())); 3602 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3603 DAG.getConstant(127, MVT::i32)); 3604 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3605} 3606 3607/// getF32Constant - Get 32-bit floating point constant. 3608static SDValue 3609getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3610 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3611} 3612 3613// implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3614const char * 3615SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3616 SDValue Op1 = getValue(I.getArgOperand(0)); 3617 SDValue Op2 = getValue(I.getArgOperand(1)); 3618 3619 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3620 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3621 return 0; 3622} 3623 3624/// visitExp - Lower an exp intrinsic. Handles the special sequences for 3625/// limited-precision mode. 3626void 3627SelectionDAGBuilder::visitExp(const CallInst &I) { 3628 SDValue result; 3629 DebugLoc dl = getCurDebugLoc(); 3630 3631 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3632 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3633 SDValue Op = getValue(I.getArgOperand(0)); 3634 3635 // Put the exponent in the right bit position for later addition to the 3636 // final result: 3637 // 3638 // #define LOG2OFe 1.4426950f 3639 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3640 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3641 getF32Constant(DAG, 0x3fb8aa3b)); 3642 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3643 3644 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3645 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3646 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3647 3648 // IntegerPartOfX <<= 23; 3649 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3650 DAG.getConstant(23, TLI.getPointerTy())); 3651 3652 if (LimitFloatPrecision <= 6) { 3653 // For floating-point precision of 6: 3654 // 3655 // TwoToFractionalPartOfX = 3656 // 0.997535578f + 3657 // (0.735607626f + 0.252464424f * x) * x; 3658 // 3659 // error 0.0144103317, which is 6 bits 3660 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3661 getF32Constant(DAG, 0x3e814304)); 3662 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3663 getF32Constant(DAG, 0x3f3c50c8)); 3664 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3665 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3666 getF32Constant(DAG, 0x3f7f5e7e)); 3667 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3668 3669 // Add the exponent into the result in integer domain. 3670 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3671 TwoToFracPartOfX, IntegerPartOfX); 3672 3673 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3674 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3675 // For floating-point precision of 12: 3676 // 3677 // TwoToFractionalPartOfX = 3678 // 0.999892986f + 3679 // (0.696457318f + 3680 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3681 // 3682 // 0.000107046256 error, which is 13 to 14 bits 3683 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3684 getF32Constant(DAG, 0x3da235e3)); 3685 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3686 getF32Constant(DAG, 0x3e65b8f3)); 3687 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3688 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3689 getF32Constant(DAG, 0x3f324b07)); 3690 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3691 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3692 getF32Constant(DAG, 0x3f7ff8fd)); 3693 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3694 3695 // Add the exponent into the result in integer domain. 3696 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3697 TwoToFracPartOfX, IntegerPartOfX); 3698 3699 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3700 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3701 // For floating-point precision of 18: 3702 // 3703 // TwoToFractionalPartOfX = 3704 // 0.999999982f + 3705 // (0.693148872f + 3706 // (0.240227044f + 3707 // (0.554906021e-1f + 3708 // (0.961591928e-2f + 3709 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3710 // 3711 // error 2.47208000*10^(-7), which is better than 18 bits 3712 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3713 getF32Constant(DAG, 0x3924b03e)); 3714 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3715 getF32Constant(DAG, 0x3ab24b87)); 3716 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3717 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3718 getF32Constant(DAG, 0x3c1d8c17)); 3719 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3720 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3721 getF32Constant(DAG, 0x3d634a1d)); 3722 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3723 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3724 getF32Constant(DAG, 0x3e75fe14)); 3725 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3726 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3727 getF32Constant(DAG, 0x3f317234)); 3728 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3729 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3730 getF32Constant(DAG, 0x3f800000)); 3731 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3732 MVT::i32, t13); 3733 3734 // Add the exponent into the result in integer domain. 3735 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3736 TwoToFracPartOfX, IntegerPartOfX); 3737 3738 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3739 } 3740 } else { 3741 // No special expansion. 3742 result = DAG.getNode(ISD::FEXP, dl, 3743 getValue(I.getArgOperand(0)).getValueType(), 3744 getValue(I.getArgOperand(0))); 3745 } 3746 3747 setValue(&I, result); 3748} 3749 3750/// visitLog - Lower a log intrinsic. Handles the special sequences for 3751/// limited-precision mode. 3752void 3753SelectionDAGBuilder::visitLog(const CallInst &I) { 3754 SDValue result; 3755 DebugLoc dl = getCurDebugLoc(); 3756 3757 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3758 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3759 SDValue Op = getValue(I.getArgOperand(0)); 3760 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3761 3762 // Scale the exponent by log(2) [0.69314718f]. 3763 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3764 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3765 getF32Constant(DAG, 0x3f317218)); 3766 3767 // Get the significand and build it into a floating-point number with 3768 // exponent of 1. 3769 SDValue X = GetSignificand(DAG, Op1, dl); 3770 3771 if (LimitFloatPrecision <= 6) { 3772 // For floating-point precision of 6: 3773 // 3774 // LogofMantissa = 3775 // -1.1609546f + 3776 // (1.4034025f - 0.23903021f * x) * x; 3777 // 3778 // error 0.0034276066, which is better than 8 bits 3779 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3780 getF32Constant(DAG, 0xbe74c456)); 3781 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3782 getF32Constant(DAG, 0x3fb3a2b1)); 3783 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3784 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3785 getF32Constant(DAG, 0x3f949a29)); 3786 3787 result = DAG.getNode(ISD::FADD, dl, 3788 MVT::f32, LogOfExponent, LogOfMantissa); 3789 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3790 // For floating-point precision of 12: 3791 // 3792 // LogOfMantissa = 3793 // -1.7417939f + 3794 // (2.8212026f + 3795 // (-1.4699568f + 3796 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3797 // 3798 // error 0.000061011436, which is 14 bits 3799 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3800 getF32Constant(DAG, 0xbd67b6d6)); 3801 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3802 getF32Constant(DAG, 0x3ee4f4b8)); 3803 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3804 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3805 getF32Constant(DAG, 0x3fbc278b)); 3806 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3807 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3808 getF32Constant(DAG, 0x40348e95)); 3809 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3810 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3811 getF32Constant(DAG, 0x3fdef31a)); 3812 3813 result = DAG.getNode(ISD::FADD, dl, 3814 MVT::f32, LogOfExponent, LogOfMantissa); 3815 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3816 // For floating-point precision of 18: 3817 // 3818 // LogOfMantissa = 3819 // -2.1072184f + 3820 // (4.2372794f + 3821 // (-3.7029485f + 3822 // (2.2781945f + 3823 // (-0.87823314f + 3824 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3825 // 3826 // error 0.0000023660568, which is better than 18 bits 3827 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3828 getF32Constant(DAG, 0xbc91e5ac)); 3829 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3830 getF32Constant(DAG, 0x3e4350aa)); 3831 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3832 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3833 getF32Constant(DAG, 0x3f60d3e3)); 3834 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3835 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3836 getF32Constant(DAG, 0x4011cdf0)); 3837 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3838 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3839 getF32Constant(DAG, 0x406cfd1c)); 3840 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3841 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3842 getF32Constant(DAG, 0x408797cb)); 3843 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3844 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3845 getF32Constant(DAG, 0x4006dcab)); 3846 3847 result = DAG.getNode(ISD::FADD, dl, 3848 MVT::f32, LogOfExponent, LogOfMantissa); 3849 } 3850 } else { 3851 // No special expansion. 3852 result = DAG.getNode(ISD::FLOG, dl, 3853 getValue(I.getArgOperand(0)).getValueType(), 3854 getValue(I.getArgOperand(0))); 3855 } 3856 3857 setValue(&I, result); 3858} 3859 3860/// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3861/// limited-precision mode. 3862void 3863SelectionDAGBuilder::visitLog2(const CallInst &I) { 3864 SDValue result; 3865 DebugLoc dl = getCurDebugLoc(); 3866 3867 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3868 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3869 SDValue Op = getValue(I.getArgOperand(0)); 3870 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3871 3872 // Get the exponent. 3873 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3874 3875 // Get the significand and build it into a floating-point number with 3876 // exponent of 1. 3877 SDValue X = GetSignificand(DAG, Op1, dl); 3878 3879 // Different possible minimax approximations of significand in 3880 // floating-point for various degrees of accuracy over [1,2]. 3881 if (LimitFloatPrecision <= 6) { 3882 // For floating-point precision of 6: 3883 // 3884 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3885 // 3886 // error 0.0049451742, which is more than 7 bits 3887 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3888 getF32Constant(DAG, 0xbeb08fe0)); 3889 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3890 getF32Constant(DAG, 0x40019463)); 3891 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3892 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3893 getF32Constant(DAG, 0x3fd6633d)); 3894 3895 result = DAG.getNode(ISD::FADD, dl, 3896 MVT::f32, LogOfExponent, Log2ofMantissa); 3897 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3898 // For floating-point precision of 12: 3899 // 3900 // Log2ofMantissa = 3901 // -2.51285454f + 3902 // (4.07009056f + 3903 // (-2.12067489f + 3904 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3905 // 3906 // error 0.0000876136000, which is better than 13 bits 3907 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3908 getF32Constant(DAG, 0xbda7262e)); 3909 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3910 getF32Constant(DAG, 0x3f25280b)); 3911 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3912 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3913 getF32Constant(DAG, 0x4007b923)); 3914 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3915 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3916 getF32Constant(DAG, 0x40823e2f)); 3917 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3918 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3919 getF32Constant(DAG, 0x4020d29c)); 3920 3921 result = DAG.getNode(ISD::FADD, dl, 3922 MVT::f32, LogOfExponent, Log2ofMantissa); 3923 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3924 // For floating-point precision of 18: 3925 // 3926 // Log2ofMantissa = 3927 // -3.0400495f + 3928 // (6.1129976f + 3929 // (-5.3420409f + 3930 // (3.2865683f + 3931 // (-1.2669343f + 3932 // (0.27515199f - 3933 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3934 // 3935 // error 0.0000018516, which is better than 18 bits 3936 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3937 getF32Constant(DAG, 0xbcd2769e)); 3938 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3939 getF32Constant(DAG, 0x3e8ce0b9)); 3940 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3941 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3942 getF32Constant(DAG, 0x3fa22ae7)); 3943 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3944 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3945 getF32Constant(DAG, 0x40525723)); 3946 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3947 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3948 getF32Constant(DAG, 0x40aaf200)); 3949 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3950 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3951 getF32Constant(DAG, 0x40c39dad)); 3952 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3953 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3954 getF32Constant(DAG, 0x4042902c)); 3955 3956 result = DAG.getNode(ISD::FADD, dl, 3957 MVT::f32, LogOfExponent, Log2ofMantissa); 3958 } 3959 } else { 3960 // No special expansion. 3961 result = DAG.getNode(ISD::FLOG2, dl, 3962 getValue(I.getArgOperand(0)).getValueType(), 3963 getValue(I.getArgOperand(0))); 3964 } 3965 3966 setValue(&I, result); 3967} 3968 3969/// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3970/// limited-precision mode. 3971void 3972SelectionDAGBuilder::visitLog10(const CallInst &I) { 3973 SDValue result; 3974 DebugLoc dl = getCurDebugLoc(); 3975 3976 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3977 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3978 SDValue Op = getValue(I.getArgOperand(0)); 3979 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3980 3981 // Scale the exponent by log10(2) [0.30102999f]. 3982 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3983 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3984 getF32Constant(DAG, 0x3e9a209a)); 3985 3986 // Get the significand and build it into a floating-point number with 3987 // exponent of 1. 3988 SDValue X = GetSignificand(DAG, Op1, dl); 3989 3990 if (LimitFloatPrecision <= 6) { 3991 // For floating-point precision of 6: 3992 // 3993 // Log10ofMantissa = 3994 // -0.50419619f + 3995 // (0.60948995f - 0.10380950f * x) * x; 3996 // 3997 // error 0.0014886165, which is 6 bits 3998 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3999 getF32Constant(DAG, 0xbdd49a13)); 4000 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4001 getF32Constant(DAG, 0x3f1c0789)); 4002 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4003 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4004 getF32Constant(DAG, 0x3f011300)); 4005 4006 result = DAG.getNode(ISD::FADD, dl, 4007 MVT::f32, LogOfExponent, Log10ofMantissa); 4008 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4009 // For floating-point precision of 12: 4010 // 4011 // Log10ofMantissa = 4012 // -0.64831180f + 4013 // (0.91751397f + 4014 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4015 // 4016 // error 0.00019228036, which is better than 12 bits 4017 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4018 getF32Constant(DAG, 0x3d431f31)); 4019 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4020 getF32Constant(DAG, 0x3ea21fb2)); 4021 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4022 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4023 getF32Constant(DAG, 0x3f6ae232)); 4024 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4025 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4026 getF32Constant(DAG, 0x3f25f7c3)); 4027 4028 result = DAG.getNode(ISD::FADD, dl, 4029 MVT::f32, LogOfExponent, Log10ofMantissa); 4030 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4031 // For floating-point precision of 18: 4032 // 4033 // Log10ofMantissa = 4034 // -0.84299375f + 4035 // (1.5327582f + 4036 // (-1.0688956f + 4037 // (0.49102474f + 4038 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4039 // 4040 // error 0.0000037995730, which is better than 18 bits 4041 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4042 getF32Constant(DAG, 0x3c5d51ce)); 4043 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4044 getF32Constant(DAG, 0x3e00685a)); 4045 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4046 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4047 getF32Constant(DAG, 0x3efb6798)); 4048 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4049 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4050 getF32Constant(DAG, 0x3f88d192)); 4051 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4052 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4053 getF32Constant(DAG, 0x3fc4316c)); 4054 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4055 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4056 getF32Constant(DAG, 0x3f57ce70)); 4057 4058 result = DAG.getNode(ISD::FADD, dl, 4059 MVT::f32, LogOfExponent, Log10ofMantissa); 4060 } 4061 } else { 4062 // No special expansion. 4063 result = DAG.getNode(ISD::FLOG10, dl, 4064 getValue(I.getArgOperand(0)).getValueType(), 4065 getValue(I.getArgOperand(0))); 4066 } 4067 4068 setValue(&I, result); 4069} 4070 4071/// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4072/// limited-precision mode. 4073void 4074SelectionDAGBuilder::visitExp2(const CallInst &I) { 4075 SDValue result; 4076 DebugLoc dl = getCurDebugLoc(); 4077 4078 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4079 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4080 SDValue Op = getValue(I.getArgOperand(0)); 4081 4082 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4083 4084 // FractionalPartOfX = x - (float)IntegerPartOfX; 4085 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4086 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4087 4088 // IntegerPartOfX <<= 23; 4089 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4090 DAG.getConstant(23, TLI.getPointerTy())); 4091 4092 if (LimitFloatPrecision <= 6) { 4093 // For floating-point precision of 6: 4094 // 4095 // TwoToFractionalPartOfX = 4096 // 0.997535578f + 4097 // (0.735607626f + 0.252464424f * x) * x; 4098 // 4099 // error 0.0144103317, which is 6 bits 4100 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4101 getF32Constant(DAG, 0x3e814304)); 4102 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4103 getF32Constant(DAG, 0x3f3c50c8)); 4104 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4105 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4106 getF32Constant(DAG, 0x3f7f5e7e)); 4107 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4108 SDValue TwoToFractionalPartOfX = 4109 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4110 4111 result = DAG.getNode(ISD::BITCAST, dl, 4112 MVT::f32, TwoToFractionalPartOfX); 4113 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4114 // For floating-point precision of 12: 4115 // 4116 // TwoToFractionalPartOfX = 4117 // 0.999892986f + 4118 // (0.696457318f + 4119 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4120 // 4121 // error 0.000107046256, which is 13 to 14 bits 4122 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4123 getF32Constant(DAG, 0x3da235e3)); 4124 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4125 getF32Constant(DAG, 0x3e65b8f3)); 4126 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4127 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4128 getF32Constant(DAG, 0x3f324b07)); 4129 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4130 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4131 getF32Constant(DAG, 0x3f7ff8fd)); 4132 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4133 SDValue TwoToFractionalPartOfX = 4134 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4135 4136 result = DAG.getNode(ISD::BITCAST, dl, 4137 MVT::f32, TwoToFractionalPartOfX); 4138 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4139 // For floating-point precision of 18: 4140 // 4141 // TwoToFractionalPartOfX = 4142 // 0.999999982f + 4143 // (0.693148872f + 4144 // (0.240227044f + 4145 // (0.554906021e-1f + 4146 // (0.961591928e-2f + 4147 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4148 // error 2.47208000*10^(-7), which is better than 18 bits 4149 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4150 getF32Constant(DAG, 0x3924b03e)); 4151 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4152 getF32Constant(DAG, 0x3ab24b87)); 4153 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4154 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4155 getF32Constant(DAG, 0x3c1d8c17)); 4156 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4157 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4158 getF32Constant(DAG, 0x3d634a1d)); 4159 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4160 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4161 getF32Constant(DAG, 0x3e75fe14)); 4162 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4163 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4164 getF32Constant(DAG, 0x3f317234)); 4165 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4166 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4167 getF32Constant(DAG, 0x3f800000)); 4168 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4169 SDValue TwoToFractionalPartOfX = 4170 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4171 4172 result = DAG.getNode(ISD::BITCAST, dl, 4173 MVT::f32, TwoToFractionalPartOfX); 4174 } 4175 } else { 4176 // No special expansion. 4177 result = DAG.getNode(ISD::FEXP2, dl, 4178 getValue(I.getArgOperand(0)).getValueType(), 4179 getValue(I.getArgOperand(0))); 4180 } 4181 4182 setValue(&I, result); 4183} 4184 4185/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4186/// limited-precision mode with x == 10.0f. 4187void 4188SelectionDAGBuilder::visitPow(const CallInst &I) { 4189 SDValue result; 4190 const Value *Val = I.getArgOperand(0); 4191 DebugLoc dl = getCurDebugLoc(); 4192 bool IsExp10 = false; 4193 4194 if (getValue(Val).getValueType() == MVT::f32 && 4195 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4196 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4197 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4198 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4199 APFloat Ten(10.0f); 4200 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4201 } 4202 } 4203 } 4204 4205 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4206 SDValue Op = getValue(I.getArgOperand(1)); 4207 4208 // Put the exponent in the right bit position for later addition to the 4209 // final result: 4210 // 4211 // #define LOG2OF10 3.3219281f 4212 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4213 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4214 getF32Constant(DAG, 0x40549a78)); 4215 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4216 4217 // FractionalPartOfX = x - (float)IntegerPartOfX; 4218 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4219 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4220 4221 // IntegerPartOfX <<= 23; 4222 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4223 DAG.getConstant(23, TLI.getPointerTy())); 4224 4225 if (LimitFloatPrecision <= 6) { 4226 // For floating-point precision of 6: 4227 // 4228 // twoToFractionalPartOfX = 4229 // 0.997535578f + 4230 // (0.735607626f + 0.252464424f * x) * x; 4231 // 4232 // error 0.0144103317, which is 6 bits 4233 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4234 getF32Constant(DAG, 0x3e814304)); 4235 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4236 getF32Constant(DAG, 0x3f3c50c8)); 4237 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4238 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4239 getF32Constant(DAG, 0x3f7f5e7e)); 4240 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4241 SDValue TwoToFractionalPartOfX = 4242 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4243 4244 result = DAG.getNode(ISD::BITCAST, dl, 4245 MVT::f32, TwoToFractionalPartOfX); 4246 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4247 // For floating-point precision of 12: 4248 // 4249 // TwoToFractionalPartOfX = 4250 // 0.999892986f + 4251 // (0.696457318f + 4252 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4253 // 4254 // error 0.000107046256, which is 13 to 14 bits 4255 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4256 getF32Constant(DAG, 0x3da235e3)); 4257 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4258 getF32Constant(DAG, 0x3e65b8f3)); 4259 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4260 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4261 getF32Constant(DAG, 0x3f324b07)); 4262 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4263 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4264 getF32Constant(DAG, 0x3f7ff8fd)); 4265 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4266 SDValue TwoToFractionalPartOfX = 4267 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4268 4269 result = DAG.getNode(ISD::BITCAST, dl, 4270 MVT::f32, TwoToFractionalPartOfX); 4271 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4272 // For floating-point precision of 18: 4273 // 4274 // TwoToFractionalPartOfX = 4275 // 0.999999982f + 4276 // (0.693148872f + 4277 // (0.240227044f + 4278 // (0.554906021e-1f + 4279 // (0.961591928e-2f + 4280 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4281 // error 2.47208000*10^(-7), which is better than 18 bits 4282 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4283 getF32Constant(DAG, 0x3924b03e)); 4284 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4285 getF32Constant(DAG, 0x3ab24b87)); 4286 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4287 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4288 getF32Constant(DAG, 0x3c1d8c17)); 4289 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4290 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4291 getF32Constant(DAG, 0x3d634a1d)); 4292 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4293 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4294 getF32Constant(DAG, 0x3e75fe14)); 4295 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4296 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4297 getF32Constant(DAG, 0x3f317234)); 4298 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4299 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4300 getF32Constant(DAG, 0x3f800000)); 4301 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4302 SDValue TwoToFractionalPartOfX = 4303 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4304 4305 result = DAG.getNode(ISD::BITCAST, dl, 4306 MVT::f32, TwoToFractionalPartOfX); 4307 } 4308 } else { 4309 // No special expansion. 4310 result = DAG.getNode(ISD::FPOW, dl, 4311 getValue(I.getArgOperand(0)).getValueType(), 4312 getValue(I.getArgOperand(0)), 4313 getValue(I.getArgOperand(1))); 4314 } 4315 4316 setValue(&I, result); 4317} 4318 4319 4320/// ExpandPowI - Expand a llvm.powi intrinsic. 4321static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4322 SelectionDAG &DAG) { 4323 // If RHS is a constant, we can expand this out to a multiplication tree, 4324 // otherwise we end up lowering to a call to __powidf2 (for example). When 4325 // optimizing for size, we only want to do this if the expansion would produce 4326 // a small number of multiplies, otherwise we do the full expansion. 4327 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4328 // Get the exponent as a positive value. 4329 unsigned Val = RHSC->getSExtValue(); 4330 if ((int)Val < 0) Val = -Val; 4331 4332 // powi(x, 0) -> 1.0 4333 if (Val == 0) 4334 return DAG.getConstantFP(1.0, LHS.getValueType()); 4335 4336 const Function *F = DAG.getMachineFunction().getFunction(); 4337 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4338 // If optimizing for size, don't insert too many multiplies. This 4339 // inserts up to 5 multiplies. 4340 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4341 // We use the simple binary decomposition method to generate the multiply 4342 // sequence. There are more optimal ways to do this (for example, 4343 // powi(x,15) generates one more multiply than it should), but this has 4344 // the benefit of being both really simple and much better than a libcall. 4345 SDValue Res; // Logically starts equal to 1.0 4346 SDValue CurSquare = LHS; 4347 while (Val) { 4348 if (Val & 1) { 4349 if (Res.getNode()) 4350 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4351 else 4352 Res = CurSquare; // 1.0*CurSquare. 4353 } 4354 4355 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4356 CurSquare, CurSquare); 4357 Val >>= 1; 4358 } 4359 4360 // If the original was negative, invert the result, producing 1/(x*x*x). 4361 if (RHSC->getSExtValue() < 0) 4362 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4363 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4364 return Res; 4365 } 4366 } 4367 4368 // Otherwise, expand to a libcall. 4369 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4370} 4371 4372// getTruncatedArgReg - Find underlying register used for an truncated 4373// argument. 4374static unsigned getTruncatedArgReg(const SDValue &N) { 4375 if (N.getOpcode() != ISD::TRUNCATE) 4376 return 0; 4377 4378 const SDValue &Ext = N.getOperand(0); 4379 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4380 const SDValue &CFR = Ext.getOperand(0); 4381 if (CFR.getOpcode() == ISD::CopyFromReg) 4382 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4383 else 4384 if (CFR.getOpcode() == ISD::TRUNCATE) 4385 return getTruncatedArgReg(CFR); 4386 } 4387 return 0; 4388} 4389 4390/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4391/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4392/// At the end of instruction selection, they will be inserted to the entry BB. 4393bool 4394SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4395 int64_t Offset, 4396 const SDValue &N) { 4397 const Argument *Arg = dyn_cast<Argument>(V); 4398 if (!Arg) 4399 return false; 4400 4401 MachineFunction &MF = DAG.getMachineFunction(); 4402 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4403 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4404 4405 // Ignore inlined function arguments here. 4406 DIVariable DV(Variable); 4407 if (DV.isInlinedFnArgument(MF.getFunction())) 4408 return false; 4409 4410 unsigned Reg = 0; 4411 // Some arguments' frame index is recorded during argument lowering. 4412 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4413 if (Offset) 4414 Reg = TRI->getFrameRegister(MF); 4415 4416 if (!Reg && N.getNode()) { 4417 if (N.getOpcode() == ISD::CopyFromReg) 4418 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4419 else 4420 Reg = getTruncatedArgReg(N); 4421 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4422 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4423 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4424 if (PR) 4425 Reg = PR; 4426 } 4427 } 4428 4429 if (!Reg) { 4430 // Check if ValueMap has reg number. 4431 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4432 if (VMI != FuncInfo.ValueMap.end()) 4433 Reg = VMI->second; 4434 } 4435 4436 if (!Reg && N.getNode()) { 4437 // Check if frame index is available. 4438 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4439 if (FrameIndexSDNode *FINode = 4440 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4441 Reg = TRI->getFrameRegister(MF); 4442 Offset = FINode->getIndex(); 4443 } 4444 } 4445 4446 if (!Reg) 4447 return false; 4448 4449 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4450 TII->get(TargetOpcode::DBG_VALUE)) 4451 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4452 FuncInfo.ArgDbgValues.push_back(&*MIB); 4453 return true; 4454} 4455 4456// VisualStudio defines setjmp as _setjmp 4457#if defined(_MSC_VER) && defined(setjmp) && \ 4458 !defined(setjmp_undefined_for_msvc) 4459# pragma push_macro("setjmp") 4460# undef setjmp 4461# define setjmp_undefined_for_msvc 4462#endif 4463 4464/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4465/// we want to emit this as a call to a named external function, return the name 4466/// otherwise lower it and return null. 4467const char * 4468SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4469 DebugLoc dl = getCurDebugLoc(); 4470 SDValue Res; 4471 4472 switch (Intrinsic) { 4473 default: 4474 // By default, turn this into a target intrinsic node. 4475 visitTargetIntrinsic(I, Intrinsic); 4476 return 0; 4477 case Intrinsic::vastart: visitVAStart(I); return 0; 4478 case Intrinsic::vaend: visitVAEnd(I); return 0; 4479 case Intrinsic::vacopy: visitVACopy(I); return 0; 4480 case Intrinsic::returnaddress: 4481 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4482 getValue(I.getArgOperand(0)))); 4483 return 0; 4484 case Intrinsic::frameaddress: 4485 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4486 getValue(I.getArgOperand(0)))); 4487 return 0; 4488 case Intrinsic::setjmp: 4489 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4490 case Intrinsic::longjmp: 4491 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4492 case Intrinsic::memcpy: { 4493 // Assert for address < 256 since we support only user defined address 4494 // spaces. 4495 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4496 < 256 && 4497 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4498 < 256 && 4499 "Unknown address space"); 4500 SDValue Op1 = getValue(I.getArgOperand(0)); 4501 SDValue Op2 = getValue(I.getArgOperand(1)); 4502 SDValue Op3 = getValue(I.getArgOperand(2)); 4503 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4504 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4505 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4506 MachinePointerInfo(I.getArgOperand(0)), 4507 MachinePointerInfo(I.getArgOperand(1)))); 4508 return 0; 4509 } 4510 case Intrinsic::memset: { 4511 // Assert for address < 256 since we support only user defined address 4512 // spaces. 4513 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4514 < 256 && 4515 "Unknown address space"); 4516 SDValue Op1 = getValue(I.getArgOperand(0)); 4517 SDValue Op2 = getValue(I.getArgOperand(1)); 4518 SDValue Op3 = getValue(I.getArgOperand(2)); 4519 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4520 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4521 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4522 MachinePointerInfo(I.getArgOperand(0)))); 4523 return 0; 4524 } 4525 case Intrinsic::memmove: { 4526 // Assert for address < 256 since we support only user defined address 4527 // spaces. 4528 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4529 < 256 && 4530 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4531 < 256 && 4532 "Unknown address space"); 4533 SDValue Op1 = getValue(I.getArgOperand(0)); 4534 SDValue Op2 = getValue(I.getArgOperand(1)); 4535 SDValue Op3 = getValue(I.getArgOperand(2)); 4536 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4537 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4538 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4539 MachinePointerInfo(I.getArgOperand(0)), 4540 MachinePointerInfo(I.getArgOperand(1)))); 4541 return 0; 4542 } 4543 case Intrinsic::dbg_declare: { 4544 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4545 MDNode *Variable = DI.getVariable(); 4546 const Value *Address = DI.getAddress(); 4547 if (!Address || !DIVariable(Variable).Verify()) 4548 return 0; 4549 4550 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4551 // but do not always have a corresponding SDNode built. The SDNodeOrder 4552 // absolute, but not relative, values are different depending on whether 4553 // debug info exists. 4554 ++SDNodeOrder; 4555 4556 // Check if address has undef value. 4557 if (isa<UndefValue>(Address) || 4558 (Address->use_empty() && !isa<Argument>(Address))) { 4559 DEBUG(dbgs() << "Dropping debug info for " << DI); 4560 return 0; 4561 } 4562 4563 SDValue &N = NodeMap[Address]; 4564 if (!N.getNode() && isa<Argument>(Address)) 4565 // Check unused arguments map. 4566 N = UnusedArgNodeMap[Address]; 4567 SDDbgValue *SDV; 4568 if (N.getNode()) { 4569 // Parameters are handled specially. 4570 bool isParameter = 4571 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4572 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4573 Address = BCI->getOperand(0); 4574 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4575 4576 if (isParameter && !AI) { 4577 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4578 if (FINode) 4579 // Byval parameter. We have a frame index at this point. 4580 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4581 0, dl, SDNodeOrder); 4582 else { 4583 // Address is an argument, so try to emit its dbg value using 4584 // virtual register info from the FuncInfo.ValueMap. 4585 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4586 return 0; 4587 } 4588 } else if (AI) 4589 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4590 0, dl, SDNodeOrder); 4591 else { 4592 // Can't do anything with other non-AI cases yet. 4593 DEBUG(dbgs() << "Dropping debug info for " << DI); 4594 return 0; 4595 } 4596 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4597 } else { 4598 // If Address is an argument then try to emit its dbg value using 4599 // virtual register info from the FuncInfo.ValueMap. 4600 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4601 // If variable is pinned by a alloca in dominating bb then 4602 // use StaticAllocaMap. 4603 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4604 if (AI->getParent() != DI.getParent()) { 4605 DenseMap<const AllocaInst*, int>::iterator SI = 4606 FuncInfo.StaticAllocaMap.find(AI); 4607 if (SI != FuncInfo.StaticAllocaMap.end()) { 4608 SDV = DAG.getDbgValue(Variable, SI->second, 4609 0, dl, SDNodeOrder); 4610 DAG.AddDbgValue(SDV, 0, false); 4611 return 0; 4612 } 4613 } 4614 } 4615 DEBUG(dbgs() << "Dropping debug info for " << DI); 4616 } 4617 } 4618 return 0; 4619 } 4620 case Intrinsic::dbg_value: { 4621 const DbgValueInst &DI = cast<DbgValueInst>(I); 4622 if (!DIVariable(DI.getVariable()).Verify()) 4623 return 0; 4624 4625 MDNode *Variable = DI.getVariable(); 4626 uint64_t Offset = DI.getOffset(); 4627 const Value *V = DI.getValue(); 4628 if (!V) 4629 return 0; 4630 4631 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4632 // but do not always have a corresponding SDNode built. The SDNodeOrder 4633 // absolute, but not relative, values are different depending on whether 4634 // debug info exists. 4635 ++SDNodeOrder; 4636 SDDbgValue *SDV; 4637 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4638 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4639 DAG.AddDbgValue(SDV, 0, false); 4640 } else { 4641 // Do not use getValue() in here; we don't want to generate code at 4642 // this point if it hasn't been done yet. 4643 SDValue N = NodeMap[V]; 4644 if (!N.getNode() && isa<Argument>(V)) 4645 // Check unused arguments map. 4646 N = UnusedArgNodeMap[V]; 4647 if (N.getNode()) { 4648 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4649 SDV = DAG.getDbgValue(Variable, N.getNode(), 4650 N.getResNo(), Offset, dl, SDNodeOrder); 4651 DAG.AddDbgValue(SDV, N.getNode(), false); 4652 } 4653 } else if (!V->use_empty() ) { 4654 // Do not call getValue(V) yet, as we don't want to generate code. 4655 // Remember it for later. 4656 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4657 DanglingDebugInfoMap[V] = DDI; 4658 } else { 4659 // We may expand this to cover more cases. One case where we have no 4660 // data available is an unreferenced parameter. 4661 DEBUG(dbgs() << "Dropping debug info for " << DI); 4662 } 4663 } 4664 4665 // Build a debug info table entry. 4666 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4667 V = BCI->getOperand(0); 4668 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4669 // Don't handle byval struct arguments or VLAs, for example. 4670 if (!AI) 4671 return 0; 4672 DenseMap<const AllocaInst*, int>::iterator SI = 4673 FuncInfo.StaticAllocaMap.find(AI); 4674 if (SI == FuncInfo.StaticAllocaMap.end()) 4675 return 0; // VLAs. 4676 int FI = SI->second; 4677 4678 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4679 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4680 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4681 return 0; 4682 } 4683 case Intrinsic::eh_exception: { 4684 // Insert the EXCEPTIONADDR instruction. 4685 assert(FuncInfo.MBB->isLandingPad() && 4686 "Call to eh.exception not in landing pad!"); 4687 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4688 SDValue Ops[1]; 4689 Ops[0] = DAG.getRoot(); 4690 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4691 setValue(&I, Op); 4692 DAG.setRoot(Op.getValue(1)); 4693 return 0; 4694 } 4695 4696 case Intrinsic::eh_selector: { 4697 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4698 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4699 if (CallMBB->isLandingPad()) 4700 AddCatchInfo(I, &MMI, CallMBB); 4701 else { 4702#ifndef NDEBUG 4703 FuncInfo.CatchInfoLost.insert(&I); 4704#endif 4705 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4706 unsigned Reg = TLI.getExceptionSelectorRegister(); 4707 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4708 } 4709 4710 // Insert the EHSELECTION instruction. 4711 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4712 SDValue Ops[2]; 4713 Ops[0] = getValue(I.getArgOperand(0)); 4714 Ops[1] = getRoot(); 4715 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4716 DAG.setRoot(Op.getValue(1)); 4717 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4718 return 0; 4719 } 4720 4721 case Intrinsic::eh_typeid_for: { 4722 // Find the type id for the given typeinfo. 4723 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4724 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4725 Res = DAG.getConstant(TypeID, MVT::i32); 4726 setValue(&I, Res); 4727 return 0; 4728 } 4729 4730 case Intrinsic::eh_return_i32: 4731 case Intrinsic::eh_return_i64: 4732 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4733 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4734 MVT::Other, 4735 getControlRoot(), 4736 getValue(I.getArgOperand(0)), 4737 getValue(I.getArgOperand(1)))); 4738 return 0; 4739 case Intrinsic::eh_unwind_init: 4740 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4741 return 0; 4742 case Intrinsic::eh_dwarf_cfa: { 4743 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4744 TLI.getPointerTy()); 4745 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4746 TLI.getPointerTy(), 4747 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4748 TLI.getPointerTy()), 4749 CfaArg); 4750 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4751 TLI.getPointerTy(), 4752 DAG.getConstant(0, TLI.getPointerTy())); 4753 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4754 FA, Offset)); 4755 return 0; 4756 } 4757 case Intrinsic::eh_sjlj_callsite: { 4758 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4759 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4760 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4761 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4762 4763 MMI.setCurrentCallSite(CI->getZExtValue()); 4764 return 0; 4765 } 4766 case Intrinsic::eh_sjlj_functioncontext: { 4767 // Get and store the index of the function context. 4768 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4769 AllocaInst *FnCtx = 4770 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4771 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4772 MFI->setFunctionContextIndex(FI); 4773 return 0; 4774 } 4775 case Intrinsic::eh_sjlj_setjmp: { 4776 SDValue Ops[2]; 4777 Ops[0] = getRoot(); 4778 Ops[1] = getValue(I.getArgOperand(0)); 4779 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4780 DAG.getVTList(MVT::i32, MVT::Other), 4781 Ops, 2); 4782 setValue(&I, Op.getValue(0)); 4783 DAG.setRoot(Op.getValue(1)); 4784 return 0; 4785 } 4786 case Intrinsic::eh_sjlj_longjmp: { 4787 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4788 getRoot(), getValue(I.getArgOperand(0)))); 4789 return 0; 4790 } 4791 4792 case Intrinsic::x86_mmx_pslli_w: 4793 case Intrinsic::x86_mmx_pslli_d: 4794 case Intrinsic::x86_mmx_pslli_q: 4795 case Intrinsic::x86_mmx_psrli_w: 4796 case Intrinsic::x86_mmx_psrli_d: 4797 case Intrinsic::x86_mmx_psrli_q: 4798 case Intrinsic::x86_mmx_psrai_w: 4799 case Intrinsic::x86_mmx_psrai_d: { 4800 SDValue ShAmt = getValue(I.getArgOperand(1)); 4801 if (isa<ConstantSDNode>(ShAmt)) { 4802 visitTargetIntrinsic(I, Intrinsic); 4803 return 0; 4804 } 4805 unsigned NewIntrinsic = 0; 4806 EVT ShAmtVT = MVT::v2i32; 4807 switch (Intrinsic) { 4808 case Intrinsic::x86_mmx_pslli_w: 4809 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4810 break; 4811 case Intrinsic::x86_mmx_pslli_d: 4812 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4813 break; 4814 case Intrinsic::x86_mmx_pslli_q: 4815 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4816 break; 4817 case Intrinsic::x86_mmx_psrli_w: 4818 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4819 break; 4820 case Intrinsic::x86_mmx_psrli_d: 4821 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4822 break; 4823 case Intrinsic::x86_mmx_psrli_q: 4824 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4825 break; 4826 case Intrinsic::x86_mmx_psrai_w: 4827 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4828 break; 4829 case Intrinsic::x86_mmx_psrai_d: 4830 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4831 break; 4832 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4833 } 4834 4835 // The vector shift intrinsics with scalars uses 32b shift amounts but 4836 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4837 // to be zero. 4838 // We must do this early because v2i32 is not a legal type. 4839 DebugLoc dl = getCurDebugLoc(); 4840 SDValue ShOps[2]; 4841 ShOps[0] = ShAmt; 4842 ShOps[1] = DAG.getConstant(0, MVT::i32); 4843 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4844 EVT DestVT = TLI.getValueType(I.getType()); 4845 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4846 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4847 DAG.getConstant(NewIntrinsic, MVT::i32), 4848 getValue(I.getArgOperand(0)), ShAmt); 4849 setValue(&I, Res); 4850 return 0; 4851 } 4852 case Intrinsic::convertff: 4853 case Intrinsic::convertfsi: 4854 case Intrinsic::convertfui: 4855 case Intrinsic::convertsif: 4856 case Intrinsic::convertuif: 4857 case Intrinsic::convertss: 4858 case Intrinsic::convertsu: 4859 case Intrinsic::convertus: 4860 case Intrinsic::convertuu: { 4861 ISD::CvtCode Code = ISD::CVT_INVALID; 4862 switch (Intrinsic) { 4863 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4864 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4865 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4866 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4867 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4868 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4869 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4870 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4871 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4872 } 4873 EVT DestVT = TLI.getValueType(I.getType()); 4874 const Value *Op1 = I.getArgOperand(0); 4875 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4876 DAG.getValueType(DestVT), 4877 DAG.getValueType(getValue(Op1).getValueType()), 4878 getValue(I.getArgOperand(1)), 4879 getValue(I.getArgOperand(2)), 4880 Code); 4881 setValue(&I, Res); 4882 return 0; 4883 } 4884 case Intrinsic::sqrt: 4885 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4886 getValue(I.getArgOperand(0)).getValueType(), 4887 getValue(I.getArgOperand(0)))); 4888 return 0; 4889 case Intrinsic::powi: 4890 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4891 getValue(I.getArgOperand(1)), DAG)); 4892 return 0; 4893 case Intrinsic::sin: 4894 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4895 getValue(I.getArgOperand(0)).getValueType(), 4896 getValue(I.getArgOperand(0)))); 4897 return 0; 4898 case Intrinsic::cos: 4899 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4900 getValue(I.getArgOperand(0)).getValueType(), 4901 getValue(I.getArgOperand(0)))); 4902 return 0; 4903 case Intrinsic::log: 4904 visitLog(I); 4905 return 0; 4906 case Intrinsic::log2: 4907 visitLog2(I); 4908 return 0; 4909 case Intrinsic::log10: 4910 visitLog10(I); 4911 return 0; 4912 case Intrinsic::exp: 4913 visitExp(I); 4914 return 0; 4915 case Intrinsic::exp2: 4916 visitExp2(I); 4917 return 0; 4918 case Intrinsic::pow: 4919 visitPow(I); 4920 return 0; 4921 case Intrinsic::fma: 4922 setValue(&I, DAG.getNode(ISD::FMA, dl, 4923 getValue(I.getArgOperand(0)).getValueType(), 4924 getValue(I.getArgOperand(0)), 4925 getValue(I.getArgOperand(1)), 4926 getValue(I.getArgOperand(2)))); 4927 return 0; 4928 case Intrinsic::convert_to_fp16: 4929 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4930 MVT::i16, getValue(I.getArgOperand(0)))); 4931 return 0; 4932 case Intrinsic::convert_from_fp16: 4933 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4934 MVT::f32, getValue(I.getArgOperand(0)))); 4935 return 0; 4936 case Intrinsic::pcmarker: { 4937 SDValue Tmp = getValue(I.getArgOperand(0)); 4938 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4939 return 0; 4940 } 4941 case Intrinsic::readcyclecounter: { 4942 SDValue Op = getRoot(); 4943 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4944 DAG.getVTList(MVT::i64, MVT::Other), 4945 &Op, 1); 4946 setValue(&I, Res); 4947 DAG.setRoot(Res.getValue(1)); 4948 return 0; 4949 } 4950 case Intrinsic::bswap: 4951 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4952 getValue(I.getArgOperand(0)).getValueType(), 4953 getValue(I.getArgOperand(0)))); 4954 return 0; 4955 case Intrinsic::cttz: { 4956 SDValue Arg = getValue(I.getArgOperand(0)); 4957 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4958 EVT Ty = Arg.getValueType(); 4959 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 4960 dl, Ty, Arg)); 4961 return 0; 4962 } 4963 case Intrinsic::ctlz: { 4964 SDValue Arg = getValue(I.getArgOperand(0)); 4965 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 4966 EVT Ty = Arg.getValueType(); 4967 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 4968 dl, Ty, Arg)); 4969 return 0; 4970 } 4971 case Intrinsic::ctpop: { 4972 SDValue Arg = getValue(I.getArgOperand(0)); 4973 EVT Ty = Arg.getValueType(); 4974 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4975 return 0; 4976 } 4977 case Intrinsic::stacksave: { 4978 SDValue Op = getRoot(); 4979 Res = DAG.getNode(ISD::STACKSAVE, dl, 4980 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4981 setValue(&I, Res); 4982 DAG.setRoot(Res.getValue(1)); 4983 return 0; 4984 } 4985 case Intrinsic::stackrestore: { 4986 Res = getValue(I.getArgOperand(0)); 4987 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4988 return 0; 4989 } 4990 case Intrinsic::stackprotector: { 4991 // Emit code into the DAG to store the stack guard onto the stack. 4992 MachineFunction &MF = DAG.getMachineFunction(); 4993 MachineFrameInfo *MFI = MF.getFrameInfo(); 4994 EVT PtrTy = TLI.getPointerTy(); 4995 4996 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4997 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4998 4999 int FI = FuncInfo.StaticAllocaMap[Slot]; 5000 MFI->setStackProtectorIndex(FI); 5001 5002 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5003 5004 // Store the stack protector onto the stack. 5005 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 5006 MachinePointerInfo::getFixedStack(FI), 5007 true, false, 0); 5008 setValue(&I, Res); 5009 DAG.setRoot(Res); 5010 return 0; 5011 } 5012 case Intrinsic::objectsize: { 5013 // If we don't know by now, we're never going to know. 5014 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5015 5016 assert(CI && "Non-constant type in __builtin_object_size?"); 5017 5018 SDValue Arg = getValue(I.getCalledValue()); 5019 EVT Ty = Arg.getValueType(); 5020 5021 if (CI->isZero()) 5022 Res = DAG.getConstant(-1ULL, Ty); 5023 else 5024 Res = DAG.getConstant(0, Ty); 5025 5026 setValue(&I, Res); 5027 return 0; 5028 } 5029 case Intrinsic::var_annotation: 5030 // Discard annotate attributes 5031 return 0; 5032 5033 case Intrinsic::init_trampoline: { 5034 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5035 5036 SDValue Ops[6]; 5037 Ops[0] = getRoot(); 5038 Ops[1] = getValue(I.getArgOperand(0)); 5039 Ops[2] = getValue(I.getArgOperand(1)); 5040 Ops[3] = getValue(I.getArgOperand(2)); 5041 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5042 Ops[5] = DAG.getSrcValue(F); 5043 5044 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5045 5046 DAG.setRoot(Res); 5047 return 0; 5048 } 5049 case Intrinsic::adjust_trampoline: { 5050 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5051 TLI.getPointerTy(), 5052 getValue(I.getArgOperand(0)))); 5053 return 0; 5054 } 5055 case Intrinsic::gcroot: 5056 if (GFI) { 5057 const Value *Alloca = I.getArgOperand(0); 5058 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5059 5060 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5061 GFI->addStackRoot(FI->getIndex(), TypeMap); 5062 } 5063 return 0; 5064 case Intrinsic::gcread: 5065 case Intrinsic::gcwrite: 5066 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5067 return 0; 5068 case Intrinsic::flt_rounds: 5069 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5070 return 0; 5071 5072 case Intrinsic::expect: { 5073 // Just replace __builtin_expect(exp, c) with EXP. 5074 setValue(&I, getValue(I.getArgOperand(0))); 5075 return 0; 5076 } 5077 5078 case Intrinsic::trap: { 5079 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5080 if (TrapFuncName.empty()) { 5081 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5082 return 0; 5083 } 5084 TargetLowering::ArgListTy Args; 5085 std::pair<SDValue, SDValue> Result = 5086 TLI.LowerCallTo(getRoot(), I.getType(), 5087 false, false, false, false, 0, CallingConv::C, 5088 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 5089 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5090 Args, DAG, getCurDebugLoc()); 5091 DAG.setRoot(Result.second); 5092 return 0; 5093 } 5094 case Intrinsic::uadd_with_overflow: 5095 return implVisitAluOverflow(I, ISD::UADDO); 5096 case Intrinsic::sadd_with_overflow: 5097 return implVisitAluOverflow(I, ISD::SADDO); 5098 case Intrinsic::usub_with_overflow: 5099 return implVisitAluOverflow(I, ISD::USUBO); 5100 case Intrinsic::ssub_with_overflow: 5101 return implVisitAluOverflow(I, ISD::SSUBO); 5102 case Intrinsic::umul_with_overflow: 5103 return implVisitAluOverflow(I, ISD::UMULO); 5104 case Intrinsic::smul_with_overflow: 5105 return implVisitAluOverflow(I, ISD::SMULO); 5106 5107 case Intrinsic::prefetch: { 5108 SDValue Ops[5]; 5109 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5110 Ops[0] = getRoot(); 5111 Ops[1] = getValue(I.getArgOperand(0)); 5112 Ops[2] = getValue(I.getArgOperand(1)); 5113 Ops[3] = getValue(I.getArgOperand(2)); 5114 Ops[4] = getValue(I.getArgOperand(3)); 5115 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5116 DAG.getVTList(MVT::Other), 5117 &Ops[0], 5, 5118 EVT::getIntegerVT(*Context, 8), 5119 MachinePointerInfo(I.getArgOperand(0)), 5120 0, /* align */ 5121 false, /* volatile */ 5122 rw==0, /* read */ 5123 rw==1)); /* write */ 5124 return 0; 5125 } 5126 5127 case Intrinsic::invariant_start: 5128 case Intrinsic::lifetime_start: 5129 // Discard region information. 5130 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5131 return 0; 5132 case Intrinsic::invariant_end: 5133 case Intrinsic::lifetime_end: 5134 // Discard region information. 5135 return 0; 5136 } 5137} 5138 5139void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5140 bool isTailCall, 5141 MachineBasicBlock *LandingPad) { 5142 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5143 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5144 Type *RetTy = FTy->getReturnType(); 5145 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5146 MCSymbol *BeginLabel = 0; 5147 5148 TargetLowering::ArgListTy Args; 5149 TargetLowering::ArgListEntry Entry; 5150 Args.reserve(CS.arg_size()); 5151 5152 // Check whether the function can return without sret-demotion. 5153 SmallVector<ISD::OutputArg, 4> Outs; 5154 SmallVector<uint64_t, 4> Offsets; 5155 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5156 Outs, TLI, &Offsets); 5157 5158 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5159 DAG.getMachineFunction(), 5160 FTy->isVarArg(), Outs, 5161 FTy->getContext()); 5162 5163 SDValue DemoteStackSlot; 5164 int DemoteStackIdx = -100; 5165 5166 if (!CanLowerReturn) { 5167 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5168 FTy->getReturnType()); 5169 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5170 FTy->getReturnType()); 5171 MachineFunction &MF = DAG.getMachineFunction(); 5172 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5173 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5174 5175 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5176 Entry.Node = DemoteStackSlot; 5177 Entry.Ty = StackSlotPtrType; 5178 Entry.isSExt = false; 5179 Entry.isZExt = false; 5180 Entry.isInReg = false; 5181 Entry.isSRet = true; 5182 Entry.isNest = false; 5183 Entry.isByVal = false; 5184 Entry.Alignment = Align; 5185 Args.push_back(Entry); 5186 RetTy = Type::getVoidTy(FTy->getContext()); 5187 } 5188 5189 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5190 i != e; ++i) { 5191 const Value *V = *i; 5192 5193 // Skip empty types 5194 if (V->getType()->isEmptyTy()) 5195 continue; 5196 5197 SDValue ArgNode = getValue(V); 5198 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5199 5200 unsigned attrInd = i - CS.arg_begin() + 1; 5201 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5202 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5203 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5204 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5205 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5206 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5207 Entry.Alignment = CS.getParamAlignment(attrInd); 5208 Args.push_back(Entry); 5209 } 5210 5211 if (LandingPad) { 5212 // Insert a label before the invoke call to mark the try range. This can be 5213 // used to detect deletion of the invoke via the MachineModuleInfo. 5214 BeginLabel = MMI.getContext().CreateTempSymbol(); 5215 5216 // For SjLj, keep track of which landing pads go with which invokes 5217 // so as to maintain the ordering of pads in the LSDA. 5218 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5219 if (CallSiteIndex) { 5220 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5221 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5222 5223 // Now that the call site is handled, stop tracking it. 5224 MMI.setCurrentCallSite(0); 5225 } 5226 5227 // Both PendingLoads and PendingExports must be flushed here; 5228 // this call might not return. 5229 (void)getRoot(); 5230 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5231 } 5232 5233 // Check if target-independent constraints permit a tail call here. 5234 // Target-dependent constraints are checked within TLI.LowerCallTo. 5235 if (isTailCall && 5236 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5237 isTailCall = false; 5238 5239 // If there's a possibility that fast-isel has already selected some amount 5240 // of the current basic block, don't emit a tail call. 5241 if (isTailCall && TM.Options.EnableFastISel) 5242 isTailCall = false; 5243 5244 std::pair<SDValue,SDValue> Result = 5245 TLI.LowerCallTo(getRoot(), RetTy, 5246 CS.paramHasAttr(0, Attribute::SExt), 5247 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5248 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5249 CS.getCallingConv(), 5250 isTailCall, 5251 !CS.getInstruction()->use_empty(), 5252 Callee, Args, DAG, getCurDebugLoc()); 5253 assert((isTailCall || Result.second.getNode()) && 5254 "Non-null chain expected with non-tail call!"); 5255 assert((Result.second.getNode() || !Result.first.getNode()) && 5256 "Null value expected with tail call!"); 5257 if (Result.first.getNode()) { 5258 setValue(CS.getInstruction(), Result.first); 5259 } else if (!CanLowerReturn && Result.second.getNode()) { 5260 // The instruction result is the result of loading from the 5261 // hidden sret parameter. 5262 SmallVector<EVT, 1> PVTs; 5263 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5264 5265 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5266 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5267 EVT PtrVT = PVTs[0]; 5268 unsigned NumValues = Outs.size(); 5269 SmallVector<SDValue, 4> Values(NumValues); 5270 SmallVector<SDValue, 4> Chains(NumValues); 5271 5272 for (unsigned i = 0; i < NumValues; ++i) { 5273 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5274 DemoteStackSlot, 5275 DAG.getConstant(Offsets[i], PtrVT)); 5276 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5277 Add, 5278 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5279 false, false, false, 1); 5280 Values[i] = L; 5281 Chains[i] = L.getValue(1); 5282 } 5283 5284 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5285 MVT::Other, &Chains[0], NumValues); 5286 PendingLoads.push_back(Chain); 5287 5288 // Collect the legal value parts into potentially illegal values 5289 // that correspond to the original function's return values. 5290 SmallVector<EVT, 4> RetTys; 5291 RetTy = FTy->getReturnType(); 5292 ComputeValueVTs(TLI, RetTy, RetTys); 5293 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5294 SmallVector<SDValue, 4> ReturnValues; 5295 unsigned CurReg = 0; 5296 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5297 EVT VT = RetTys[I]; 5298 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5299 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5300 5301 SDValue ReturnValue = 5302 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5303 RegisterVT, VT, AssertOp); 5304 ReturnValues.push_back(ReturnValue); 5305 CurReg += NumRegs; 5306 } 5307 5308 setValue(CS.getInstruction(), 5309 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5310 DAG.getVTList(&RetTys[0], RetTys.size()), 5311 &ReturnValues[0], ReturnValues.size())); 5312 } 5313 5314 // Assign order to nodes here. If the call does not produce a result, it won't 5315 // be mapped to a SDNode and visit() will not assign it an order number. 5316 if (!Result.second.getNode()) { 5317 // As a special case, a null chain means that a tail call has been emitted and 5318 // the DAG root is already updated. 5319 HasTailCall = true; 5320 ++SDNodeOrder; 5321 AssignOrderingToNode(DAG.getRoot().getNode()); 5322 } else { 5323 DAG.setRoot(Result.second); 5324 ++SDNodeOrder; 5325 AssignOrderingToNode(Result.second.getNode()); 5326 } 5327 5328 if (LandingPad) { 5329 // Insert a label at the end of the invoke call to mark the try range. This 5330 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5331 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5332 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5333 5334 // Inform MachineModuleInfo of range. 5335 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5336 } 5337} 5338 5339/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5340/// value is equal or not-equal to zero. 5341static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5342 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5343 UI != E; ++UI) { 5344 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5345 if (IC->isEquality()) 5346 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5347 if (C->isNullValue()) 5348 continue; 5349 // Unknown instruction. 5350 return false; 5351 } 5352 return true; 5353} 5354 5355static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5356 Type *LoadTy, 5357 SelectionDAGBuilder &Builder) { 5358 5359 // Check to see if this load can be trivially constant folded, e.g. if the 5360 // input is from a string literal. 5361 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5362 // Cast pointer to the type we really want to load. 5363 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5364 PointerType::getUnqual(LoadTy)); 5365 5366 if (const Constant *LoadCst = 5367 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5368 Builder.TD)) 5369 return Builder.getValue(LoadCst); 5370 } 5371 5372 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5373 // still constant memory, the input chain can be the entry node. 5374 SDValue Root; 5375 bool ConstantMemory = false; 5376 5377 // Do not serialize (non-volatile) loads of constant memory with anything. 5378 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5379 Root = Builder.DAG.getEntryNode(); 5380 ConstantMemory = true; 5381 } else { 5382 // Do not serialize non-volatile loads against each other. 5383 Root = Builder.DAG.getRoot(); 5384 } 5385 5386 SDValue Ptr = Builder.getValue(PtrVal); 5387 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5388 Ptr, MachinePointerInfo(PtrVal), 5389 false /*volatile*/, 5390 false /*nontemporal*/, 5391 false /*isinvariant*/, 1 /* align=1 */); 5392 5393 if (!ConstantMemory) 5394 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5395 return LoadVal; 5396} 5397 5398 5399/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5400/// If so, return true and lower it, otherwise return false and it will be 5401/// lowered like a normal call. 5402bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5403 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5404 if (I.getNumArgOperands() != 3) 5405 return false; 5406 5407 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5408 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5409 !I.getArgOperand(2)->getType()->isIntegerTy() || 5410 !I.getType()->isIntegerTy()) 5411 return false; 5412 5413 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5414 5415 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5416 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5417 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5418 bool ActuallyDoIt = true; 5419 MVT LoadVT; 5420 Type *LoadTy; 5421 switch (Size->getZExtValue()) { 5422 default: 5423 LoadVT = MVT::Other; 5424 LoadTy = 0; 5425 ActuallyDoIt = false; 5426 break; 5427 case 2: 5428 LoadVT = MVT::i16; 5429 LoadTy = Type::getInt16Ty(Size->getContext()); 5430 break; 5431 case 4: 5432 LoadVT = MVT::i32; 5433 LoadTy = Type::getInt32Ty(Size->getContext()); 5434 break; 5435 case 8: 5436 LoadVT = MVT::i64; 5437 LoadTy = Type::getInt64Ty(Size->getContext()); 5438 break; 5439 /* 5440 case 16: 5441 LoadVT = MVT::v4i32; 5442 LoadTy = Type::getInt32Ty(Size->getContext()); 5443 LoadTy = VectorType::get(LoadTy, 4); 5444 break; 5445 */ 5446 } 5447 5448 // This turns into unaligned loads. We only do this if the target natively 5449 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5450 // we'll only produce a small number of byte loads. 5451 5452 // Require that we can find a legal MVT, and only do this if the target 5453 // supports unaligned loads of that type. Expanding into byte loads would 5454 // bloat the code. 5455 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5456 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5457 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5458 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5459 ActuallyDoIt = false; 5460 } 5461 5462 if (ActuallyDoIt) { 5463 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5464 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5465 5466 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5467 ISD::SETNE); 5468 EVT CallVT = TLI.getValueType(I.getType(), true); 5469 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5470 return true; 5471 } 5472 } 5473 5474 5475 return false; 5476} 5477 5478 5479void SelectionDAGBuilder::visitCall(const CallInst &I) { 5480 // Handle inline assembly differently. 5481 if (isa<InlineAsm>(I.getCalledValue())) { 5482 visitInlineAsm(&I); 5483 return; 5484 } 5485 5486 // See if any floating point values are being passed to this function. This is 5487 // used to emit an undefined reference to fltused on Windows. 5488 FunctionType *FT = 5489 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5490 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5491 if (FT->isVarArg() && 5492 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5493 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5494 Type* T = I.getArgOperand(i)->getType(); 5495 for (po_iterator<Type*> i = po_begin(T), e = po_end(T); 5496 i != e; ++i) { 5497 if (!i->isFloatingPointTy()) continue; 5498 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5499 break; 5500 } 5501 } 5502 } 5503 5504 const char *RenameFn = 0; 5505 if (Function *F = I.getCalledFunction()) { 5506 if (F->isDeclaration()) { 5507 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5508 if (unsigned IID = II->getIntrinsicID(F)) { 5509 RenameFn = visitIntrinsicCall(I, IID); 5510 if (!RenameFn) 5511 return; 5512 } 5513 } 5514 if (unsigned IID = F->getIntrinsicID()) { 5515 RenameFn = visitIntrinsicCall(I, IID); 5516 if (!RenameFn) 5517 return; 5518 } 5519 } 5520 5521 // Check for well-known libc/libm calls. If the function is internal, it 5522 // can't be a library call. 5523 if (!F->hasLocalLinkage() && F->hasName()) { 5524 StringRef Name = F->getName(); 5525 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") || 5526 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") || 5527 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) { 5528 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5529 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5530 I.getType() == I.getArgOperand(0)->getType() && 5531 I.getType() == I.getArgOperand(1)->getType()) { 5532 SDValue LHS = getValue(I.getArgOperand(0)); 5533 SDValue RHS = getValue(I.getArgOperand(1)); 5534 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5535 LHS.getValueType(), LHS, RHS)); 5536 return; 5537 } 5538 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") || 5539 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") || 5540 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) { 5541 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5542 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5543 I.getType() == I.getArgOperand(0)->getType()) { 5544 SDValue Tmp = getValue(I.getArgOperand(0)); 5545 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5546 Tmp.getValueType(), Tmp)); 5547 return; 5548 } 5549 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") || 5550 (LibInfo->has(LibFunc::sinf) && Name == "sinf") || 5551 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) { 5552 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5553 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5554 I.getType() == I.getArgOperand(0)->getType() && 5555 I.onlyReadsMemory()) { 5556 SDValue Tmp = getValue(I.getArgOperand(0)); 5557 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5558 Tmp.getValueType(), Tmp)); 5559 return; 5560 } 5561 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") || 5562 (LibInfo->has(LibFunc::cosf) && Name == "cosf") || 5563 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) { 5564 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5565 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5566 I.getType() == I.getArgOperand(0)->getType() && 5567 I.onlyReadsMemory()) { 5568 SDValue Tmp = getValue(I.getArgOperand(0)); 5569 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5570 Tmp.getValueType(), Tmp)); 5571 return; 5572 } 5573 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") || 5574 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") || 5575 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) { 5576 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5577 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5578 I.getType() == I.getArgOperand(0)->getType() && 5579 I.onlyReadsMemory()) { 5580 SDValue Tmp = getValue(I.getArgOperand(0)); 5581 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5582 Tmp.getValueType(), Tmp)); 5583 return; 5584 } 5585 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") || 5586 (LibInfo->has(LibFunc::floorf) && Name == "floorf") || 5587 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) { 5588 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5589 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5590 I.getType() == I.getArgOperand(0)->getType()) { 5591 SDValue Tmp = getValue(I.getArgOperand(0)); 5592 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(), 5593 Tmp.getValueType(), Tmp)); 5594 return; 5595 } 5596 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") || 5597 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") || 5598 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) { 5599 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5600 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5601 I.getType() == I.getArgOperand(0)->getType()) { 5602 SDValue Tmp = getValue(I.getArgOperand(0)); 5603 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(), 5604 Tmp.getValueType(), Tmp)); 5605 return; 5606 } 5607 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") || 5608 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") || 5609 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) { 5610 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5611 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5612 I.getType() == I.getArgOperand(0)->getType()) { 5613 SDValue Tmp = getValue(I.getArgOperand(0)); 5614 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(), 5615 Tmp.getValueType(), Tmp)); 5616 return; 5617 } 5618 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") || 5619 (LibInfo->has(LibFunc::rintf) && Name == "rintf") || 5620 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) { 5621 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5622 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5623 I.getType() == I.getArgOperand(0)->getType()) { 5624 SDValue Tmp = getValue(I.getArgOperand(0)); 5625 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(), 5626 Tmp.getValueType(), Tmp)); 5627 return; 5628 } 5629 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") || 5630 (LibInfo->has(LibFunc::truncf) && Name == "truncf") || 5631 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) { 5632 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5633 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5634 I.getType() == I.getArgOperand(0)->getType()) { 5635 SDValue Tmp = getValue(I.getArgOperand(0)); 5636 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(), 5637 Tmp.getValueType(), Tmp)); 5638 return; 5639 } 5640 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") || 5641 (LibInfo->has(LibFunc::log2f) && Name == "log2f") || 5642 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) { 5643 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5644 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5645 I.getType() == I.getArgOperand(0)->getType()) { 5646 SDValue Tmp = getValue(I.getArgOperand(0)); 5647 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(), 5648 Tmp.getValueType(), Tmp)); 5649 return; 5650 } 5651 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") || 5652 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") || 5653 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) { 5654 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5655 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5656 I.getType() == I.getArgOperand(0)->getType()) { 5657 SDValue Tmp = getValue(I.getArgOperand(0)); 5658 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(), 5659 Tmp.getValueType(), Tmp)); 5660 return; 5661 } 5662 } else if (Name == "memcmp") { 5663 if (visitMemCmpCall(I)) 5664 return; 5665 } 5666 } 5667 } 5668 5669 SDValue Callee; 5670 if (!RenameFn) 5671 Callee = getValue(I.getCalledValue()); 5672 else 5673 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5674 5675 // Check if we can potentially perform a tail call. More detailed checking is 5676 // be done within LowerCallTo, after more information about the call is known. 5677 LowerCallTo(&I, Callee, I.isTailCall()); 5678} 5679 5680namespace { 5681 5682/// AsmOperandInfo - This contains information for each constraint that we are 5683/// lowering. 5684class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5685public: 5686 /// CallOperand - If this is the result output operand or a clobber 5687 /// this is null, otherwise it is the incoming operand to the CallInst. 5688 /// This gets modified as the asm is processed. 5689 SDValue CallOperand; 5690 5691 /// AssignedRegs - If this is a register or register class operand, this 5692 /// contains the set of register corresponding to the operand. 5693 RegsForValue AssignedRegs; 5694 5695 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5696 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5697 } 5698 5699 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5700 /// busy in OutputRegs/InputRegs. 5701 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5702 std::set<unsigned> &OutputRegs, 5703 std::set<unsigned> &InputRegs, 5704 const TargetRegisterInfo &TRI) const { 5705 if (isOutReg) { 5706 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5707 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5708 } 5709 if (isInReg) { 5710 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5711 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5712 } 5713 } 5714 5715 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5716 /// corresponds to. If there is no Value* for this operand, it returns 5717 /// MVT::Other. 5718 EVT getCallOperandValEVT(LLVMContext &Context, 5719 const TargetLowering &TLI, 5720 const TargetData *TD) const { 5721 if (CallOperandVal == 0) return MVT::Other; 5722 5723 if (isa<BasicBlock>(CallOperandVal)) 5724 return TLI.getPointerTy(); 5725 5726 llvm::Type *OpTy = CallOperandVal->getType(); 5727 5728 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5729 // If this is an indirect operand, the operand is a pointer to the 5730 // accessed type. 5731 if (isIndirect) { 5732 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5733 if (!PtrTy) 5734 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5735 OpTy = PtrTy->getElementType(); 5736 } 5737 5738 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5739 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5740 if (STy->getNumElements() == 1) 5741 OpTy = STy->getElementType(0); 5742 5743 // If OpTy is not a single value, it may be a struct/union that we 5744 // can tile with integers. 5745 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5746 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5747 switch (BitSize) { 5748 default: break; 5749 case 1: 5750 case 8: 5751 case 16: 5752 case 32: 5753 case 64: 5754 case 128: 5755 OpTy = IntegerType::get(Context, BitSize); 5756 break; 5757 } 5758 } 5759 5760 return TLI.getValueType(OpTy, true); 5761 } 5762 5763private: 5764 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5765 /// specified set. 5766 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5767 const TargetRegisterInfo &TRI) { 5768 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5769 Regs.insert(Reg); 5770 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5771 for (; *Aliases; ++Aliases) 5772 Regs.insert(*Aliases); 5773 } 5774}; 5775 5776typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5777 5778} // end anonymous namespace 5779 5780/// GetRegistersForValue - Assign registers (virtual or physical) for the 5781/// specified operand. We prefer to assign virtual registers, to allow the 5782/// register allocator to handle the assignment process. However, if the asm 5783/// uses features that we can't model on machineinstrs, we have SDISel do the 5784/// allocation. This produces generally horrible, but correct, code. 5785/// 5786/// OpInfo describes the operand. 5787/// Input and OutputRegs are the set of already allocated physical registers. 5788/// 5789static void GetRegistersForValue(SelectionDAG &DAG, 5790 const TargetLowering &TLI, 5791 DebugLoc DL, 5792 SDISelAsmOperandInfo &OpInfo, 5793 std::set<unsigned> &OutputRegs, 5794 std::set<unsigned> &InputRegs) { 5795 LLVMContext &Context = *DAG.getContext(); 5796 5797 // Compute whether this value requires an input register, an output register, 5798 // or both. 5799 bool isOutReg = false; 5800 bool isInReg = false; 5801 switch (OpInfo.Type) { 5802 case InlineAsm::isOutput: 5803 isOutReg = true; 5804 5805 // If there is an input constraint that matches this, we need to reserve 5806 // the input register so no other inputs allocate to it. 5807 isInReg = OpInfo.hasMatchingInput(); 5808 break; 5809 case InlineAsm::isInput: 5810 isInReg = true; 5811 isOutReg = false; 5812 break; 5813 case InlineAsm::isClobber: 5814 isOutReg = true; 5815 isInReg = true; 5816 break; 5817 } 5818 5819 5820 MachineFunction &MF = DAG.getMachineFunction(); 5821 SmallVector<unsigned, 4> Regs; 5822 5823 // If this is a constraint for a single physreg, or a constraint for a 5824 // register class, find it. 5825 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5826 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5827 OpInfo.ConstraintVT); 5828 5829 unsigned NumRegs = 1; 5830 if (OpInfo.ConstraintVT != MVT::Other) { 5831 // If this is a FP input in an integer register (or visa versa) insert a bit 5832 // cast of the input value. More generally, handle any case where the input 5833 // value disagrees with the register class we plan to stick this in. 5834 if (OpInfo.Type == InlineAsm::isInput && 5835 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5836 // Try to convert to the first EVT that the reg class contains. If the 5837 // types are identical size, use a bitcast to convert (e.g. two differing 5838 // vector types). 5839 EVT RegVT = *PhysReg.second->vt_begin(); 5840 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5841 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5842 RegVT, OpInfo.CallOperand); 5843 OpInfo.ConstraintVT = RegVT; 5844 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5845 // If the input is a FP value and we want it in FP registers, do a 5846 // bitcast to the corresponding integer type. This turns an f64 value 5847 // into i64, which can be passed with two i32 values on a 32-bit 5848 // machine. 5849 RegVT = EVT::getIntegerVT(Context, 5850 OpInfo.ConstraintVT.getSizeInBits()); 5851 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5852 RegVT, OpInfo.CallOperand); 5853 OpInfo.ConstraintVT = RegVT; 5854 } 5855 } 5856 5857 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5858 } 5859 5860 EVT RegVT; 5861 EVT ValueVT = OpInfo.ConstraintVT; 5862 5863 // If this is a constraint for a specific physical register, like {r17}, 5864 // assign it now. 5865 if (unsigned AssignedReg = PhysReg.first) { 5866 const TargetRegisterClass *RC = PhysReg.second; 5867 if (OpInfo.ConstraintVT == MVT::Other) 5868 ValueVT = *RC->vt_begin(); 5869 5870 // Get the actual register value type. This is important, because the user 5871 // may have asked for (e.g.) the AX register in i32 type. We need to 5872 // remember that AX is actually i16 to get the right extension. 5873 RegVT = *RC->vt_begin(); 5874 5875 // This is a explicit reference to a physical register. 5876 Regs.push_back(AssignedReg); 5877 5878 // If this is an expanded reference, add the rest of the regs to Regs. 5879 if (NumRegs != 1) { 5880 TargetRegisterClass::iterator I = RC->begin(); 5881 for (; *I != AssignedReg; ++I) 5882 assert(I != RC->end() && "Didn't find reg!"); 5883 5884 // Already added the first reg. 5885 --NumRegs; ++I; 5886 for (; NumRegs; --NumRegs, ++I) { 5887 assert(I != RC->end() && "Ran out of registers to allocate!"); 5888 Regs.push_back(*I); 5889 } 5890 } 5891 5892 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5893 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5894 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5895 return; 5896 } 5897 5898 // Otherwise, if this was a reference to an LLVM register class, create vregs 5899 // for this reference. 5900 if (const TargetRegisterClass *RC = PhysReg.second) { 5901 RegVT = *RC->vt_begin(); 5902 if (OpInfo.ConstraintVT == MVT::Other) 5903 ValueVT = RegVT; 5904 5905 // Create the appropriate number of virtual registers. 5906 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5907 for (; NumRegs; --NumRegs) 5908 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5909 5910 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5911 return; 5912 } 5913 5914 // Otherwise, we couldn't allocate enough registers for this. 5915} 5916 5917/// visitInlineAsm - Handle a call to an InlineAsm object. 5918/// 5919void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5920 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5921 5922 /// ConstraintOperands - Information about all of the constraints. 5923 SDISelAsmOperandInfoVector ConstraintOperands; 5924 5925 std::set<unsigned> OutputRegs, InputRegs; 5926 5927 TargetLowering::AsmOperandInfoVector 5928 TargetConstraints = TLI.ParseConstraints(CS); 5929 5930 bool hasMemory = false; 5931 5932 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5933 unsigned ResNo = 0; // ResNo - The result number of the next output. 5934 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5935 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5936 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5937 5938 EVT OpVT = MVT::Other; 5939 5940 // Compute the value type for each operand. 5941 switch (OpInfo.Type) { 5942 case InlineAsm::isOutput: 5943 // Indirect outputs just consume an argument. 5944 if (OpInfo.isIndirect) { 5945 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5946 break; 5947 } 5948 5949 // The return value of the call is this value. As such, there is no 5950 // corresponding argument. 5951 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5952 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5953 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5954 } else { 5955 assert(ResNo == 0 && "Asm only has one result!"); 5956 OpVT = TLI.getValueType(CS.getType()); 5957 } 5958 ++ResNo; 5959 break; 5960 case InlineAsm::isInput: 5961 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5962 break; 5963 case InlineAsm::isClobber: 5964 // Nothing to do. 5965 break; 5966 } 5967 5968 // If this is an input or an indirect output, process the call argument. 5969 // BasicBlocks are labels, currently appearing only in asm's. 5970 if (OpInfo.CallOperandVal) { 5971 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5972 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5973 } else { 5974 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5975 } 5976 5977 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5978 } 5979 5980 OpInfo.ConstraintVT = OpVT; 5981 5982 // Indirect operand accesses access memory. 5983 if (OpInfo.isIndirect) 5984 hasMemory = true; 5985 else { 5986 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5987 TargetLowering::ConstraintType 5988 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5989 if (CType == TargetLowering::C_Memory) { 5990 hasMemory = true; 5991 break; 5992 } 5993 } 5994 } 5995 } 5996 5997 SDValue Chain, Flag; 5998 5999 // We won't need to flush pending loads if this asm doesn't touch 6000 // memory and is nonvolatile. 6001 if (hasMemory || IA->hasSideEffects()) 6002 Chain = getRoot(); 6003 else 6004 Chain = DAG.getRoot(); 6005 6006 // Second pass over the constraints: compute which constraint option to use 6007 // and assign registers to constraints that want a specific physreg. 6008 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6009 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6010 6011 // If this is an output operand with a matching input operand, look up the 6012 // matching input. If their types mismatch, e.g. one is an integer, the 6013 // other is floating point, or their sizes are different, flag it as an 6014 // error. 6015 if (OpInfo.hasMatchingInput()) { 6016 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 6017 6018 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 6019 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 6020 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 6021 OpInfo.ConstraintVT); 6022 std::pair<unsigned, const TargetRegisterClass*> InputRC = 6023 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 6024 Input.ConstraintVT); 6025 if ((OpInfo.ConstraintVT.isInteger() != 6026 Input.ConstraintVT.isInteger()) || 6027 (MatchRC.second != InputRC.second)) { 6028 report_fatal_error("Unsupported asm: input constraint" 6029 " with a matching output constraint of" 6030 " incompatible type!"); 6031 } 6032 Input.ConstraintVT = OpInfo.ConstraintVT; 6033 } 6034 } 6035 6036 // Compute the constraint code and ConstraintType to use. 6037 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 6038 6039 // If this is a memory input, and if the operand is not indirect, do what we 6040 // need to to provide an address for the memory input. 6041 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 6042 !OpInfo.isIndirect) { 6043 assert((OpInfo.isMultipleAlternative || 6044 (OpInfo.Type == InlineAsm::isInput)) && 6045 "Can only indirectify direct input operands!"); 6046 6047 // Memory operands really want the address of the value. If we don't have 6048 // an indirect input, put it in the constpool if we can, otherwise spill 6049 // it to a stack slot. 6050 // TODO: This isn't quite right. We need to handle these according to 6051 // the addressing mode that the constraint wants. Also, this may take 6052 // an additional register for the computation and we don't want that 6053 // either. 6054 6055 // If the operand is a float, integer, or vector constant, spill to a 6056 // constant pool entry to get its address. 6057 const Value *OpVal = OpInfo.CallOperandVal; 6058 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 6059 isa<ConstantVector>(OpVal)) { 6060 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 6061 TLI.getPointerTy()); 6062 } else { 6063 // Otherwise, create a stack slot and emit a store to it before the 6064 // asm. 6065 Type *Ty = OpVal->getType(); 6066 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 6067 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 6068 MachineFunction &MF = DAG.getMachineFunction(); 6069 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6070 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 6071 Chain = DAG.getStore(Chain, getCurDebugLoc(), 6072 OpInfo.CallOperand, StackSlot, 6073 MachinePointerInfo::getFixedStack(SSFI), 6074 false, false, 0); 6075 OpInfo.CallOperand = StackSlot; 6076 } 6077 6078 // There is no longer a Value* corresponding to this operand. 6079 OpInfo.CallOperandVal = 0; 6080 6081 // It is now an indirect operand. 6082 OpInfo.isIndirect = true; 6083 } 6084 6085 // If this constraint is for a specific register, allocate it before 6086 // anything else. 6087 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6088 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 6089 InputRegs); 6090 } 6091 6092 // Second pass - Loop over all of the operands, assigning virtual or physregs 6093 // to register class operands. 6094 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6095 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6096 6097 // C_Register operands have already been allocated, Other/Memory don't need 6098 // to be. 6099 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6100 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 6101 InputRegs); 6102 } 6103 6104 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6105 std::vector<SDValue> AsmNodeOperands; 6106 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6107 AsmNodeOperands.push_back( 6108 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6109 TLI.getPointerTy())); 6110 6111 // If we have a !srcloc metadata node associated with it, we want to attach 6112 // this to the ultimately generated inline asm machineinstr. To do this, we 6113 // pass in the third operand as this (potentially null) inline asm MDNode. 6114 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6115 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6116 6117 // Remember the HasSideEffect and AlignStack bits as operand 3. 6118 unsigned ExtraInfo = 0; 6119 if (IA->hasSideEffects()) 6120 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6121 if (IA->isAlignStack()) 6122 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6123 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6124 TLI.getPointerTy())); 6125 6126 // Loop over all of the inputs, copying the operand values into the 6127 // appropriate registers and processing the output regs. 6128 RegsForValue RetValRegs; 6129 6130 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6131 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6132 6133 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6134 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6135 6136 switch (OpInfo.Type) { 6137 case InlineAsm::isOutput: { 6138 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6139 OpInfo.ConstraintType != TargetLowering::C_Register) { 6140 // Memory output, or 'other' output (e.g. 'X' constraint). 6141 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6142 6143 // Add information to the INLINEASM node to know about this output. 6144 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6145 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6146 TLI.getPointerTy())); 6147 AsmNodeOperands.push_back(OpInfo.CallOperand); 6148 break; 6149 } 6150 6151 // Otherwise, this is a register or register class output. 6152 6153 // Copy the output from the appropriate register. Find a register that 6154 // we can use. 6155 if (OpInfo.AssignedRegs.Regs.empty()) { 6156 LLVMContext &Ctx = *DAG.getContext(); 6157 Ctx.emitError(CS.getInstruction(), 6158 "couldn't allocate output register for constraint '" + 6159 Twine(OpInfo.ConstraintCode) + "'"); 6160 break; 6161 } 6162 6163 // If this is an indirect operand, store through the pointer after the 6164 // asm. 6165 if (OpInfo.isIndirect) { 6166 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6167 OpInfo.CallOperandVal)); 6168 } else { 6169 // This is the result value of the call. 6170 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6171 // Concatenate this output onto the outputs list. 6172 RetValRegs.append(OpInfo.AssignedRegs); 6173 } 6174 6175 // Add information to the INLINEASM node to know that this register is 6176 // set. 6177 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6178 InlineAsm::Kind_RegDefEarlyClobber : 6179 InlineAsm::Kind_RegDef, 6180 false, 6181 0, 6182 DAG, 6183 AsmNodeOperands); 6184 break; 6185 } 6186 case InlineAsm::isInput: { 6187 SDValue InOperandVal = OpInfo.CallOperand; 6188 6189 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6190 // If this is required to match an output register we have already set, 6191 // just use its register. 6192 unsigned OperandNo = OpInfo.getMatchedOperand(); 6193 6194 // Scan until we find the definition we already emitted of this operand. 6195 // When we find it, create a RegsForValue operand. 6196 unsigned CurOp = InlineAsm::Op_FirstOperand; 6197 for (; OperandNo; --OperandNo) { 6198 // Advance to the next operand. 6199 unsigned OpFlag = 6200 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6201 assert((InlineAsm::isRegDefKind(OpFlag) || 6202 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6203 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6204 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6205 } 6206 6207 unsigned OpFlag = 6208 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6209 if (InlineAsm::isRegDefKind(OpFlag) || 6210 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6211 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6212 if (OpInfo.isIndirect) { 6213 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6214 LLVMContext &Ctx = *DAG.getContext(); 6215 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6216 " don't know how to handle tied " 6217 "indirect register inputs"); 6218 } 6219 6220 RegsForValue MatchedRegs; 6221 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6222 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6223 MatchedRegs.RegVTs.push_back(RegVT); 6224 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6225 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6226 i != e; ++i) 6227 MatchedRegs.Regs.push_back 6228 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6229 6230 // Use the produced MatchedRegs object to 6231 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6232 Chain, &Flag); 6233 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6234 true, OpInfo.getMatchedOperand(), 6235 DAG, AsmNodeOperands); 6236 break; 6237 } 6238 6239 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6240 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6241 "Unexpected number of operands"); 6242 // Add information to the INLINEASM node to know about this input. 6243 // See InlineAsm.h isUseOperandTiedToDef. 6244 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6245 OpInfo.getMatchedOperand()); 6246 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6247 TLI.getPointerTy())); 6248 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6249 break; 6250 } 6251 6252 // Treat indirect 'X' constraint as memory. 6253 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6254 OpInfo.isIndirect) 6255 OpInfo.ConstraintType = TargetLowering::C_Memory; 6256 6257 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6258 std::vector<SDValue> Ops; 6259 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6260 Ops, DAG); 6261 if (Ops.empty()) { 6262 LLVMContext &Ctx = *DAG.getContext(); 6263 Ctx.emitError(CS.getInstruction(), 6264 "invalid operand for inline asm constraint '" + 6265 Twine(OpInfo.ConstraintCode) + "'"); 6266 break; 6267 } 6268 6269 // Add information to the INLINEASM node to know about this input. 6270 unsigned ResOpType = 6271 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6272 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6273 TLI.getPointerTy())); 6274 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6275 break; 6276 } 6277 6278 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6279 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6280 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6281 "Memory operands expect pointer values"); 6282 6283 // Add information to the INLINEASM node to know about this input. 6284 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6285 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6286 TLI.getPointerTy())); 6287 AsmNodeOperands.push_back(InOperandVal); 6288 break; 6289 } 6290 6291 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6292 OpInfo.ConstraintType == TargetLowering::C_Register) && 6293 "Unknown constraint type!"); 6294 assert(!OpInfo.isIndirect && 6295 "Don't know how to handle indirect register inputs yet!"); 6296 6297 // Copy the input into the appropriate registers. 6298 if (OpInfo.AssignedRegs.Regs.empty()) { 6299 LLVMContext &Ctx = *DAG.getContext(); 6300 Ctx.emitError(CS.getInstruction(), 6301 "couldn't allocate input reg for constraint '" + 6302 Twine(OpInfo.ConstraintCode) + "'"); 6303 break; 6304 } 6305 6306 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6307 Chain, &Flag); 6308 6309 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6310 DAG, AsmNodeOperands); 6311 break; 6312 } 6313 case InlineAsm::isClobber: { 6314 // Add the clobbered value to the operand list, so that the register 6315 // allocator is aware that the physreg got clobbered. 6316 if (!OpInfo.AssignedRegs.Regs.empty()) 6317 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6318 false, 0, DAG, 6319 AsmNodeOperands); 6320 break; 6321 } 6322 } 6323 } 6324 6325 // Finish up input operands. Set the input chain and add the flag last. 6326 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6327 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6328 6329 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6330 DAG.getVTList(MVT::Other, MVT::Glue), 6331 &AsmNodeOperands[0], AsmNodeOperands.size()); 6332 Flag = Chain.getValue(1); 6333 6334 // If this asm returns a register value, copy the result from that register 6335 // and set it as the value of the call. 6336 if (!RetValRegs.Regs.empty()) { 6337 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6338 Chain, &Flag); 6339 6340 // FIXME: Why don't we do this for inline asms with MRVs? 6341 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6342 EVT ResultType = TLI.getValueType(CS.getType()); 6343 6344 // If any of the results of the inline asm is a vector, it may have the 6345 // wrong width/num elts. This can happen for register classes that can 6346 // contain multiple different value types. The preg or vreg allocated may 6347 // not have the same VT as was expected. Convert it to the right type 6348 // with bit_convert. 6349 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6350 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6351 ResultType, Val); 6352 6353 } else if (ResultType != Val.getValueType() && 6354 ResultType.isInteger() && Val.getValueType().isInteger()) { 6355 // If a result value was tied to an input value, the computed result may 6356 // have a wider width than the expected result. Extract the relevant 6357 // portion. 6358 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6359 } 6360 6361 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6362 } 6363 6364 setValue(CS.getInstruction(), Val); 6365 // Don't need to use this as a chain in this case. 6366 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6367 return; 6368 } 6369 6370 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6371 6372 // Process indirect outputs, first output all of the flagged copies out of 6373 // physregs. 6374 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6375 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6376 const Value *Ptr = IndirectStoresToEmit[i].second; 6377 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6378 Chain, &Flag); 6379 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6380 } 6381 6382 // Emit the non-flagged stores from the physregs. 6383 SmallVector<SDValue, 8> OutChains; 6384 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6385 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6386 StoresToEmit[i].first, 6387 getValue(StoresToEmit[i].second), 6388 MachinePointerInfo(StoresToEmit[i].second), 6389 false, false, 0); 6390 OutChains.push_back(Val); 6391 } 6392 6393 if (!OutChains.empty()) 6394 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6395 &OutChains[0], OutChains.size()); 6396 6397 DAG.setRoot(Chain); 6398} 6399 6400void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6401 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6402 MVT::Other, getRoot(), 6403 getValue(I.getArgOperand(0)), 6404 DAG.getSrcValue(I.getArgOperand(0)))); 6405} 6406 6407void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6408 const TargetData &TD = *TLI.getTargetData(); 6409 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6410 getRoot(), getValue(I.getOperand(0)), 6411 DAG.getSrcValue(I.getOperand(0)), 6412 TD.getABITypeAlignment(I.getType())); 6413 setValue(&I, V); 6414 DAG.setRoot(V.getValue(1)); 6415} 6416 6417void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6418 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6419 MVT::Other, getRoot(), 6420 getValue(I.getArgOperand(0)), 6421 DAG.getSrcValue(I.getArgOperand(0)))); 6422} 6423 6424void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6425 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6426 MVT::Other, getRoot(), 6427 getValue(I.getArgOperand(0)), 6428 getValue(I.getArgOperand(1)), 6429 DAG.getSrcValue(I.getArgOperand(0)), 6430 DAG.getSrcValue(I.getArgOperand(1)))); 6431} 6432 6433/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6434/// implementation, which just calls LowerCall. 6435/// FIXME: When all targets are 6436/// migrated to using LowerCall, this hook should be integrated into SDISel. 6437std::pair<SDValue, SDValue> 6438TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6439 bool RetSExt, bool RetZExt, bool isVarArg, 6440 bool isInreg, unsigned NumFixedArgs, 6441 CallingConv::ID CallConv, bool isTailCall, 6442 bool isReturnValueUsed, 6443 SDValue Callee, 6444 ArgListTy &Args, SelectionDAG &DAG, 6445 DebugLoc dl) const { 6446 // Handle all of the outgoing arguments. 6447 SmallVector<ISD::OutputArg, 32> Outs; 6448 SmallVector<SDValue, 32> OutVals; 6449 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6450 SmallVector<EVT, 4> ValueVTs; 6451 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6452 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6453 Value != NumValues; ++Value) { 6454 EVT VT = ValueVTs[Value]; 6455 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6456 SDValue Op = SDValue(Args[i].Node.getNode(), 6457 Args[i].Node.getResNo() + Value); 6458 ISD::ArgFlagsTy Flags; 6459 unsigned OriginalAlignment = 6460 getTargetData()->getABITypeAlignment(ArgTy); 6461 6462 if (Args[i].isZExt) 6463 Flags.setZExt(); 6464 if (Args[i].isSExt) 6465 Flags.setSExt(); 6466 if (Args[i].isInReg) 6467 Flags.setInReg(); 6468 if (Args[i].isSRet) 6469 Flags.setSRet(); 6470 if (Args[i].isByVal) { 6471 Flags.setByVal(); 6472 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6473 Type *ElementTy = Ty->getElementType(); 6474 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6475 // For ByVal, alignment should come from FE. BE will guess if this 6476 // info is not there but there are cases it cannot get right. 6477 unsigned FrameAlign; 6478 if (Args[i].Alignment) 6479 FrameAlign = Args[i].Alignment; 6480 else 6481 FrameAlign = getByValTypeAlignment(ElementTy); 6482 Flags.setByValAlign(FrameAlign); 6483 } 6484 if (Args[i].isNest) 6485 Flags.setNest(); 6486 Flags.setOrigAlign(OriginalAlignment); 6487 6488 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6489 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6490 SmallVector<SDValue, 4> Parts(NumParts); 6491 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6492 6493 if (Args[i].isSExt) 6494 ExtendKind = ISD::SIGN_EXTEND; 6495 else if (Args[i].isZExt) 6496 ExtendKind = ISD::ZERO_EXTEND; 6497 6498 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6499 PartVT, ExtendKind); 6500 6501 for (unsigned j = 0; j != NumParts; ++j) { 6502 // if it isn't first piece, alignment must be 1 6503 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6504 i < NumFixedArgs); 6505 if (NumParts > 1 && j == 0) 6506 MyFlags.Flags.setSplit(); 6507 else if (j != 0) 6508 MyFlags.Flags.setOrigAlign(1); 6509 6510 Outs.push_back(MyFlags); 6511 OutVals.push_back(Parts[j]); 6512 } 6513 } 6514 } 6515 6516 // Handle the incoming return values from the call. 6517 SmallVector<ISD::InputArg, 32> Ins; 6518 SmallVector<EVT, 4> RetTys; 6519 ComputeValueVTs(*this, RetTy, RetTys); 6520 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6521 EVT VT = RetTys[I]; 6522 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6523 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6524 for (unsigned i = 0; i != NumRegs; ++i) { 6525 ISD::InputArg MyFlags; 6526 MyFlags.VT = RegisterVT.getSimpleVT(); 6527 MyFlags.Used = isReturnValueUsed; 6528 if (RetSExt) 6529 MyFlags.Flags.setSExt(); 6530 if (RetZExt) 6531 MyFlags.Flags.setZExt(); 6532 if (isInreg) 6533 MyFlags.Flags.setInReg(); 6534 Ins.push_back(MyFlags); 6535 } 6536 } 6537 6538 SmallVector<SDValue, 4> InVals; 6539 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6540 Outs, OutVals, Ins, dl, DAG, InVals); 6541 6542 // Verify that the target's LowerCall behaved as expected. 6543 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6544 "LowerCall didn't return a valid chain!"); 6545 assert((!isTailCall || InVals.empty()) && 6546 "LowerCall emitted a return value for a tail call!"); 6547 assert((isTailCall || InVals.size() == Ins.size()) && 6548 "LowerCall didn't emit the correct number of values!"); 6549 6550 // For a tail call, the return value is merely live-out and there aren't 6551 // any nodes in the DAG representing it. Return a special value to 6552 // indicate that a tail call has been emitted and no more Instructions 6553 // should be processed in the current block. 6554 if (isTailCall) { 6555 DAG.setRoot(Chain); 6556 return std::make_pair(SDValue(), SDValue()); 6557 } 6558 6559 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6560 assert(InVals[i].getNode() && 6561 "LowerCall emitted a null value!"); 6562 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6563 "LowerCall emitted a value with the wrong type!"); 6564 }); 6565 6566 // Collect the legal value parts into potentially illegal values 6567 // that correspond to the original function's return values. 6568 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6569 if (RetSExt) 6570 AssertOp = ISD::AssertSext; 6571 else if (RetZExt) 6572 AssertOp = ISD::AssertZext; 6573 SmallVector<SDValue, 4> ReturnValues; 6574 unsigned CurReg = 0; 6575 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6576 EVT VT = RetTys[I]; 6577 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6578 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6579 6580 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6581 NumRegs, RegisterVT, VT, 6582 AssertOp)); 6583 CurReg += NumRegs; 6584 } 6585 6586 // For a function returning void, there is no return value. We can't create 6587 // such a node, so we just return a null return value in that case. In 6588 // that case, nothing will actually look at the value. 6589 if (ReturnValues.empty()) 6590 return std::make_pair(SDValue(), Chain); 6591 6592 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6593 DAG.getVTList(&RetTys[0], RetTys.size()), 6594 &ReturnValues[0], ReturnValues.size()); 6595 return std::make_pair(Res, Chain); 6596} 6597 6598void TargetLowering::LowerOperationWrapper(SDNode *N, 6599 SmallVectorImpl<SDValue> &Results, 6600 SelectionDAG &DAG) const { 6601 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6602 if (Res.getNode()) 6603 Results.push_back(Res); 6604} 6605 6606SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6607 llvm_unreachable("LowerOperation not implemented for this target!"); 6608 return SDValue(); 6609} 6610 6611void 6612SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6613 SDValue Op = getNonRegisterValue(V); 6614 assert((Op.getOpcode() != ISD::CopyFromReg || 6615 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6616 "Copy from a reg to the same reg!"); 6617 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6618 6619 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6620 SDValue Chain = DAG.getEntryNode(); 6621 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6622 PendingExports.push_back(Chain); 6623} 6624 6625#include "llvm/CodeGen/SelectionDAGISel.h" 6626 6627/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6628/// entry block, return true. This includes arguments used by switches, since 6629/// the switch may expand into multiple basic blocks. 6630static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 6631 // With FastISel active, we may be splitting blocks, so force creation 6632 // of virtual registers for all non-dead arguments. 6633 if (FastISel) 6634 return A->use_empty(); 6635 6636 const BasicBlock *Entry = A->getParent()->begin(); 6637 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6638 UI != E; ++UI) { 6639 const User *U = *UI; 6640 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6641 return false; // Use not in entry block. 6642 } 6643 return true; 6644} 6645 6646void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6647 // If this is the entry block, emit arguments. 6648 const Function &F = *LLVMBB->getParent(); 6649 SelectionDAG &DAG = SDB->DAG; 6650 DebugLoc dl = SDB->getCurDebugLoc(); 6651 const TargetData *TD = TLI.getTargetData(); 6652 SmallVector<ISD::InputArg, 16> Ins; 6653 6654 // Check whether the function can return without sret-demotion. 6655 SmallVector<ISD::OutputArg, 4> Outs; 6656 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6657 Outs, TLI); 6658 6659 if (!FuncInfo->CanLowerReturn) { 6660 // Put in an sret pointer parameter before all the other parameters. 6661 SmallVector<EVT, 1> ValueVTs; 6662 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6663 6664 // NOTE: Assuming that a pointer will never break down to more than one VT 6665 // or one register. 6666 ISD::ArgFlagsTy Flags; 6667 Flags.setSRet(); 6668 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6669 ISD::InputArg RetArg(Flags, RegisterVT, true); 6670 Ins.push_back(RetArg); 6671 } 6672 6673 // Set up the incoming argument description vector. 6674 unsigned Idx = 1; 6675 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6676 I != E; ++I, ++Idx) { 6677 SmallVector<EVT, 4> ValueVTs; 6678 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6679 bool isArgValueUsed = !I->use_empty(); 6680 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6681 Value != NumValues; ++Value) { 6682 EVT VT = ValueVTs[Value]; 6683 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6684 ISD::ArgFlagsTy Flags; 6685 unsigned OriginalAlignment = 6686 TD->getABITypeAlignment(ArgTy); 6687 6688 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6689 Flags.setZExt(); 6690 if (F.paramHasAttr(Idx, Attribute::SExt)) 6691 Flags.setSExt(); 6692 if (F.paramHasAttr(Idx, Attribute::InReg)) 6693 Flags.setInReg(); 6694 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6695 Flags.setSRet(); 6696 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6697 Flags.setByVal(); 6698 PointerType *Ty = cast<PointerType>(I->getType()); 6699 Type *ElementTy = Ty->getElementType(); 6700 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6701 // For ByVal, alignment should be passed from FE. BE will guess if 6702 // this info is not there but there are cases it cannot get right. 6703 unsigned FrameAlign; 6704 if (F.getParamAlignment(Idx)) 6705 FrameAlign = F.getParamAlignment(Idx); 6706 else 6707 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6708 Flags.setByValAlign(FrameAlign); 6709 } 6710 if (F.paramHasAttr(Idx, Attribute::Nest)) 6711 Flags.setNest(); 6712 Flags.setOrigAlign(OriginalAlignment); 6713 6714 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6715 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6716 for (unsigned i = 0; i != NumRegs; ++i) { 6717 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6718 if (NumRegs > 1 && i == 0) 6719 MyFlags.Flags.setSplit(); 6720 // if it isn't first piece, alignment must be 1 6721 else if (i > 0) 6722 MyFlags.Flags.setOrigAlign(1); 6723 Ins.push_back(MyFlags); 6724 } 6725 } 6726 } 6727 6728 // Call the target to set up the argument values. 6729 SmallVector<SDValue, 8> InVals; 6730 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6731 F.isVarArg(), Ins, 6732 dl, DAG, InVals); 6733 6734 // Verify that the target's LowerFormalArguments behaved as expected. 6735 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6736 "LowerFormalArguments didn't return a valid chain!"); 6737 assert(InVals.size() == Ins.size() && 6738 "LowerFormalArguments didn't emit the correct number of values!"); 6739 DEBUG({ 6740 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6741 assert(InVals[i].getNode() && 6742 "LowerFormalArguments emitted a null value!"); 6743 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6744 "LowerFormalArguments emitted a value with the wrong type!"); 6745 } 6746 }); 6747 6748 // Update the DAG with the new chain value resulting from argument lowering. 6749 DAG.setRoot(NewRoot); 6750 6751 // Set up the argument values. 6752 unsigned i = 0; 6753 Idx = 1; 6754 if (!FuncInfo->CanLowerReturn) { 6755 // Create a virtual register for the sret pointer, and put in a copy 6756 // from the sret argument into it. 6757 SmallVector<EVT, 1> ValueVTs; 6758 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6759 EVT VT = ValueVTs[0]; 6760 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6761 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6762 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6763 RegVT, VT, AssertOp); 6764 6765 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6766 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6767 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6768 FuncInfo->DemoteRegister = SRetReg; 6769 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6770 SRetReg, ArgValue); 6771 DAG.setRoot(NewRoot); 6772 6773 // i indexes lowered arguments. Bump it past the hidden sret argument. 6774 // Idx indexes LLVM arguments. Don't touch it. 6775 ++i; 6776 } 6777 6778 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6779 ++I, ++Idx) { 6780 SmallVector<SDValue, 4> ArgValues; 6781 SmallVector<EVT, 4> ValueVTs; 6782 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6783 unsigned NumValues = ValueVTs.size(); 6784 6785 // If this argument is unused then remember its value. It is used to generate 6786 // debugging information. 6787 if (I->use_empty() && NumValues) 6788 SDB->setUnusedArgValue(I, InVals[i]); 6789 6790 for (unsigned Val = 0; Val != NumValues; ++Val) { 6791 EVT VT = ValueVTs[Val]; 6792 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6793 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6794 6795 if (!I->use_empty()) { 6796 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6797 if (F.paramHasAttr(Idx, Attribute::SExt)) 6798 AssertOp = ISD::AssertSext; 6799 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6800 AssertOp = ISD::AssertZext; 6801 6802 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6803 NumParts, PartVT, VT, 6804 AssertOp)); 6805 } 6806 6807 i += NumParts; 6808 } 6809 6810 // We don't need to do anything else for unused arguments. 6811 if (ArgValues.empty()) 6812 continue; 6813 6814 // Note down frame index. 6815 if (FrameIndexSDNode *FI = 6816 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6817 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6818 6819 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6820 SDB->getCurDebugLoc()); 6821 6822 SDB->setValue(I, Res); 6823 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6824 if (LoadSDNode *LNode = 6825 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6826 if (FrameIndexSDNode *FI = 6827 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6828 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6829 } 6830 6831 // If this argument is live outside of the entry block, insert a copy from 6832 // wherever we got it to the vreg that other BB's will reference it as. 6833 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6834 // If we can, though, try to skip creating an unnecessary vreg. 6835 // FIXME: This isn't very clean... it would be nice to make this more 6836 // general. It's also subtly incompatible with the hacks FastISel 6837 // uses with vregs. 6838 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6839 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6840 FuncInfo->ValueMap[I] = Reg; 6841 continue; 6842 } 6843 } 6844 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 6845 FuncInfo->InitializeRegForValue(I); 6846 SDB->CopyToExportRegsIfNeeded(I); 6847 } 6848 } 6849 6850 assert(i == InVals.size() && "Argument register count mismatch!"); 6851 6852 // Finally, if the target has anything special to do, allow it to do so. 6853 // FIXME: this should insert code into the DAG! 6854 EmitFunctionEntryCode(); 6855} 6856 6857/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6858/// ensure constants are generated when needed. Remember the virtual registers 6859/// that need to be added to the Machine PHI nodes as input. We cannot just 6860/// directly add them, because expansion might result in multiple MBB's for one 6861/// BB. As such, the start of the BB might correspond to a different MBB than 6862/// the end. 6863/// 6864void 6865SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6866 const TerminatorInst *TI = LLVMBB->getTerminator(); 6867 6868 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6869 6870 // Check successor nodes' PHI nodes that expect a constant to be available 6871 // from this block. 6872 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6873 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6874 if (!isa<PHINode>(SuccBB->begin())) continue; 6875 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6876 6877 // If this terminator has multiple identical successors (common for 6878 // switches), only handle each succ once. 6879 if (!SuccsHandled.insert(SuccMBB)) continue; 6880 6881 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6882 6883 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6884 // nodes and Machine PHI nodes, but the incoming operands have not been 6885 // emitted yet. 6886 for (BasicBlock::const_iterator I = SuccBB->begin(); 6887 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6888 // Ignore dead phi's. 6889 if (PN->use_empty()) continue; 6890 6891 // Skip empty types 6892 if (PN->getType()->isEmptyTy()) 6893 continue; 6894 6895 unsigned Reg; 6896 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6897 6898 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6899 unsigned &RegOut = ConstantsOut[C]; 6900 if (RegOut == 0) { 6901 RegOut = FuncInfo.CreateRegs(C->getType()); 6902 CopyValueToVirtualRegister(C, RegOut); 6903 } 6904 Reg = RegOut; 6905 } else { 6906 DenseMap<const Value *, unsigned>::iterator I = 6907 FuncInfo.ValueMap.find(PHIOp); 6908 if (I != FuncInfo.ValueMap.end()) 6909 Reg = I->second; 6910 else { 6911 assert(isa<AllocaInst>(PHIOp) && 6912 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6913 "Didn't codegen value into a register!??"); 6914 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6915 CopyValueToVirtualRegister(PHIOp, Reg); 6916 } 6917 } 6918 6919 // Remember that this register needs to added to the machine PHI node as 6920 // the input for this MBB. 6921 SmallVector<EVT, 4> ValueVTs; 6922 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6923 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6924 EVT VT = ValueVTs[vti]; 6925 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6926 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6927 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6928 Reg += NumRegisters; 6929 } 6930 } 6931 } 6932 ConstantsOut.clear(); 6933} 6934