ARMBaseRegisterInfo.cpp revision 6b97ebe9a32342207b24a5f73ebbf3070ec8d189
1//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseRegisterInfo.h" 15#include "ARM.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMFrameLowering.h" 18#include "ARMMachineFunctionInfo.h" 19#include "ARMSubtarget.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/ADT/BitVector.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/RegisterScavenging.h" 29#include "llvm/CodeGen/VirtRegMap.h" 30#include "llvm/IR/Constants.h" 31#include "llvm/IR/DerivedTypes.h" 32#include "llvm/IR/Function.h" 33#include "llvm/IR/LLVMContext.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/Target/TargetFrameLowering.h" 38#include "llvm/Target/TargetMachine.h" 39#include "llvm/Target/TargetOptions.h" 40 41#define GET_REGINFO_TARGET_DESC 42#include "ARMGenRegisterInfo.inc" 43 44using namespace llvm; 45 46ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti) 47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), 48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 49 BasePtr(ARM::R6) { 50} 51 52const uint16_t* 53ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 54 bool ghcCall = false; 55 56 if (MF) { 57 const Function *F = MF->getFunction(); 58 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); 59 } 60 61 if (ghcCall) 62 return CSR_GHC_SaveList; 63 else 64 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 65 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 66} 67 68const uint32_t* 69ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 70 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 71 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 72} 73 74const uint32_t* 75ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID) const { 76 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 77 ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask; 78 // This should return NULL in the case of any calling convention that does 79 // not use the same register for an i32 first argument and an i32 return 80 // value 81} 82 83const uint32_t* 84ARMBaseRegisterInfo::getNoPreservedMask() const { 85 return CSR_NoRegs_RegMask; 86} 87 88BitVector ARMBaseRegisterInfo:: 89getReservedRegs(const MachineFunction &MF) const { 90 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 91 92 // FIXME: avoid re-calculating this every time. 93 BitVector Reserved(getNumRegs()); 94 Reserved.set(ARM::SP); 95 Reserved.set(ARM::PC); 96 Reserved.set(ARM::FPSCR); 97 Reserved.set(ARM::APSR_NZCV); 98 if (TFI->hasFP(MF)) 99 Reserved.set(FramePtr); 100 if (hasBasePointer(MF)) 101 Reserved.set(BasePtr); 102 // Some targets reserve R9. 103 if (STI.isR9Reserved()) 104 Reserved.set(ARM::R9); 105 // Reserve D16-D31 if the subtarget doesn't support them. 106 if (!STI.hasVFP3() || STI.hasD16()) { 107 assert(ARM::D31 == ARM::D16 + 15); 108 for (unsigned i = 0; i != 16; ++i) 109 Reserved.set(ARM::D16 + i); 110 } 111 const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 112 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 113 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 114 if (Reserved.test(*SI)) Reserved.set(*I); 115 116 return Reserved; 117} 118 119const TargetRegisterClass* 120ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 121 const { 122 const TargetRegisterClass *Super = RC; 123 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 124 do { 125 switch (Super->getID()) { 126 case ARM::GPRRegClassID: 127 case ARM::SPRRegClassID: 128 case ARM::DPRRegClassID: 129 case ARM::QPRRegClassID: 130 case ARM::QQPRRegClassID: 131 case ARM::QQQQPRRegClassID: 132 case ARM::GPRPairRegClassID: 133 return Super; 134 } 135 Super = *I++; 136 } while (Super); 137 return RC; 138} 139 140const TargetRegisterClass * 141ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 142 const { 143 return &ARM::GPRRegClass; 144} 145 146const TargetRegisterClass * 147ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 148 if (RC == &ARM::CCRRegClass) 149 return 0; // Can't copy CCR registers. 150 return RC; 151} 152 153unsigned 154ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 155 MachineFunction &MF) const { 156 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 157 158 switch (RC->getID()) { 159 default: 160 return 0; 161 case ARM::tGPRRegClassID: 162 return TFI->hasFP(MF) ? 4 : 5; 163 case ARM::GPRRegClassID: { 164 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 165 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 166 } 167 case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 168 case ARM::DPRRegClassID: 169 return 32 - 10; 170 } 171} 172 173// Get the other register in a GPRPair. 174static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 175 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 176 if (ARM::GPRPairRegClass.contains(*Supers)) 177 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 178 return 0; 179} 180 181// Resolve the RegPairEven / RegPairOdd register allocator hints. 182void 183ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 184 ArrayRef<MCPhysReg> Order, 185 SmallVectorImpl<MCPhysReg> &Hints, 186 const MachineFunction &MF, 187 const VirtRegMap *VRM) const { 188 const MachineRegisterInfo &MRI = MF.getRegInfo(); 189 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 190 191 unsigned Odd; 192 switch (Hint.first) { 193 case ARMRI::RegPairEven: 194 Odd = 0; 195 break; 196 case ARMRI::RegPairOdd: 197 Odd = 1; 198 break; 199 default: 200 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 201 return; 202 } 203 204 // This register should preferably be even (Odd == 0) or odd (Odd == 1). 205 // Check if the other part of the pair has already been assigned, and provide 206 // the paired register as the first hint. 207 unsigned PairedPhys = 0; 208 if (VRM && VRM->hasPhys(Hint.second)) { 209 PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); 210 if (PairedPhys && MRI.isReserved(PairedPhys)) 211 PairedPhys = 0; 212 } 213 214 // First prefer the paired physreg. 215 if (PairedPhys && 216 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 217 Hints.push_back(PairedPhys); 218 219 // Then prefer even or odd registers. 220 for (unsigned I = 0, E = Order.size(); I != E; ++I) { 221 unsigned Reg = Order[I]; 222 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 223 continue; 224 // Don't provide hints that are paired to a reserved register. 225 unsigned Paired = getPairedGPR(Reg, !Odd, this); 226 if (!Paired || MRI.isReserved(Paired)) 227 continue; 228 Hints.push_back(Reg); 229 } 230} 231 232void 233ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 234 MachineFunction &MF) const { 235 MachineRegisterInfo *MRI = &MF.getRegInfo(); 236 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 237 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 238 Hint.first == (unsigned)ARMRI::RegPairEven) && 239 TargetRegisterInfo::isVirtualRegister(Hint.second)) { 240 // If 'Reg' is one of the even / odd register pair and it's now changed 241 // (e.g. coalesced) into a different register. The other register of the 242 // pair allocation hint must be updated to reflect the relationship 243 // change. 244 unsigned OtherReg = Hint.second; 245 Hint = MRI->getRegAllocationHint(OtherReg); 246 if (Hint.second == Reg) 247 // Make sure the pair has not already divorced. 248 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 249 } 250} 251 252bool 253ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 254 // CortexA9 has a Write-after-write hazard for NEON registers. 255 if (!STI.isLikeA9()) 256 return false; 257 258 switch (RC->getID()) { 259 case ARM::DPRRegClassID: 260 case ARM::DPR_8RegClassID: 261 case ARM::DPR_VFP2RegClassID: 262 case ARM::QPRRegClassID: 263 case ARM::QPR_8RegClassID: 264 case ARM::QPR_VFP2RegClassID: 265 case ARM::SPRRegClassID: 266 case ARM::SPR_8RegClassID: 267 // Avoid reusing S, D, and Q registers. 268 // Don't increase register pressure for QQ and QQQQ. 269 return true; 270 default: 271 return false; 272 } 273} 274 275bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 276 const MachineFrameInfo *MFI = MF.getFrameInfo(); 277 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 278 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 279 280 // When outgoing call frames are so large that we adjust the stack pointer 281 // around the call, we can no longer use the stack pointer to reach the 282 // emergency spill slot. 283 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 284 return true; 285 286 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 287 // negative range for ldr/str (255), and thumb1 is positive offsets only. 288 // It's going to be better to use the SP or Base Pointer instead. When there 289 // are variable sized objects, we can't reference off of the SP, so we 290 // reserve a Base Pointer. 291 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 292 // Conservatively estimate whether the negative offset from the frame 293 // pointer will be sufficient to reach. If a function has a smallish 294 // frame, it's less likely to have lots of spills and callee saved 295 // space, so it's all more likely to be within range of the frame pointer. 296 // If it's wrong, the scavenger will still enable access to work, it just 297 // won't be optimal. 298 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 299 return false; 300 return true; 301 } 302 303 return false; 304} 305 306bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 307 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 308 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 309 // We can't realign the stack if: 310 // 1. Dynamic stack realignment is explicitly disabled, 311 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 312 // 3. There are VLAs in the function and the base pointer is disabled. 313 if (!MF.getTarget().Options.RealignStack) 314 return false; 315 if (AFI->isThumb1OnlyFunction()) 316 return false; 317 // Stack realignment requires a frame pointer. If we already started 318 // register allocation with frame pointer elimination, it is too late now. 319 if (!MRI->canReserveReg(FramePtr)) 320 return false; 321 // We may also need a base pointer if there are dynamic allocas or stack 322 // pointer adjustments around calls. 323 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) 324 return true; 325 // A base pointer is required and allowed. Check that it isn't too late to 326 // reserve it. 327 return MRI->canReserveReg(BasePtr); 328} 329 330bool ARMBaseRegisterInfo:: 331needsStackRealignment(const MachineFunction &MF) const { 332 const MachineFrameInfo *MFI = MF.getFrameInfo(); 333 const Function *F = MF.getFunction(); 334 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 335 bool requiresRealignment = 336 ((MFI->getMaxAlignment() > StackAlign) || 337 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 338 Attribute::StackAlignment)); 339 340 return requiresRealignment && canRealignStack(MF); 341} 342 343bool ARMBaseRegisterInfo:: 344cannotEliminateFrame(const MachineFunction &MF) const { 345 const MachineFrameInfo *MFI = MF.getFrameInfo(); 346 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 347 return true; 348 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 349 || needsStackRealignment(MF); 350} 351 352unsigned 353ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 354 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 355 356 if (TFI->hasFP(MF)) 357 return FramePtr; 358 return ARM::SP; 359} 360 361unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 362 llvm_unreachable("What is the exception register"); 363} 364 365unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 366 llvm_unreachable("What is the exception handler register"); 367} 368 369/// emitLoadConstPool - Emits a load from constpool to materialize the 370/// specified immediate. 371void ARMBaseRegisterInfo:: 372emitLoadConstPool(MachineBasicBlock &MBB, 373 MachineBasicBlock::iterator &MBBI, 374 DebugLoc dl, 375 unsigned DestReg, unsigned SubIdx, int Val, 376 ARMCC::CondCodes Pred, 377 unsigned PredReg, unsigned MIFlags) const { 378 MachineFunction &MF = *MBB.getParent(); 379 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 380 MachineConstantPool *ConstantPool = MF.getConstantPool(); 381 const Constant *C = 382 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 383 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 384 385 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 386 .addReg(DestReg, getDefRegState(true), SubIdx) 387 .addConstantPoolIndex(Idx) 388 .addImm(0).addImm(Pred).addReg(PredReg) 389 .setMIFlags(MIFlags); 390} 391 392bool ARMBaseRegisterInfo:: 393requiresRegisterScavenging(const MachineFunction &MF) const { 394 return true; 395} 396 397bool ARMBaseRegisterInfo:: 398trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 399 return true; 400} 401 402bool ARMBaseRegisterInfo:: 403requiresFrameIndexScavenging(const MachineFunction &MF) const { 404 return true; 405} 406 407bool ARMBaseRegisterInfo:: 408requiresVirtualBaseRegisters(const MachineFunction &MF) const { 409 return true; 410} 411 412int64_t ARMBaseRegisterInfo:: 413getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 414 const MCInstrDesc &Desc = MI->getDesc(); 415 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 416 int64_t InstrOffs = 0; 417 int Scale = 1; 418 unsigned ImmIdx = 0; 419 switch (AddrMode) { 420 case ARMII::AddrModeT2_i8: 421 case ARMII::AddrModeT2_i12: 422 case ARMII::AddrMode_i12: 423 InstrOffs = MI->getOperand(Idx+1).getImm(); 424 Scale = 1; 425 break; 426 case ARMII::AddrMode5: { 427 // VFP address mode. 428 const MachineOperand &OffOp = MI->getOperand(Idx+1); 429 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 430 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 431 InstrOffs = -InstrOffs; 432 Scale = 4; 433 break; 434 } 435 case ARMII::AddrMode2: { 436 ImmIdx = Idx+2; 437 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 438 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 439 InstrOffs = -InstrOffs; 440 break; 441 } 442 case ARMII::AddrMode3: { 443 ImmIdx = Idx+2; 444 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 445 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 446 InstrOffs = -InstrOffs; 447 break; 448 } 449 case ARMII::AddrModeT1_s: { 450 ImmIdx = Idx+1; 451 InstrOffs = MI->getOperand(ImmIdx).getImm(); 452 Scale = 4; 453 break; 454 } 455 default: 456 llvm_unreachable("Unsupported addressing mode!"); 457 } 458 459 return InstrOffs * Scale; 460} 461 462/// needsFrameBaseReg - Returns true if the instruction's frame index 463/// reference would be better served by a base register other than FP 464/// or SP. Used by LocalStackFrameAllocation to determine which frame index 465/// references it should create new base registers for. 466bool ARMBaseRegisterInfo:: 467needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 468 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 469 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 470 } 471 472 // It's the load/store FI references that cause issues, as it can be difficult 473 // to materialize the offset if it won't fit in the literal field. Estimate 474 // based on the size of the local frame and some conservative assumptions 475 // about the rest of the stack frame (note, this is pre-regalloc, so 476 // we don't know everything for certain yet) whether this offset is likely 477 // to be out of range of the immediate. Return true if so. 478 479 // We only generate virtual base registers for loads and stores, so 480 // return false for everything else. 481 unsigned Opc = MI->getOpcode(); 482 switch (Opc) { 483 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 484 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 485 case ARM::t2LDRi12: case ARM::t2LDRi8: 486 case ARM::t2STRi12: case ARM::t2STRi8: 487 case ARM::VLDRS: case ARM::VLDRD: 488 case ARM::VSTRS: case ARM::VSTRD: 489 case ARM::tSTRspi: case ARM::tLDRspi: 490 break; 491 default: 492 return false; 493 } 494 495 // Without a virtual base register, if the function has variable sized 496 // objects, all fixed-size local references will be via the frame pointer, 497 // Approximate the offset and see if it's legal for the instruction. 498 // Note that the incoming offset is based on the SP value at function entry, 499 // so it'll be negative. 500 MachineFunction &MF = *MI->getParent()->getParent(); 501 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 502 MachineFrameInfo *MFI = MF.getFrameInfo(); 503 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 504 505 // Estimate an offset from the frame pointer. 506 // Conservatively assume all callee-saved registers get pushed. R4-R6 507 // will be earlier than the FP, so we ignore those. 508 // R7, LR 509 int64_t FPOffset = Offset - 8; 510 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 511 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 512 FPOffset -= 80; 513 // Estimate an offset from the stack pointer. 514 // The incoming offset is relating to the SP at the start of the function, 515 // but when we access the local it'll be relative to the SP after local 516 // allocation, so adjust our SP-relative offset by that allocation size. 517 Offset = -Offset; 518 Offset += MFI->getLocalFrameSize(); 519 // Assume that we'll have at least some spill slots allocated. 520 // FIXME: This is a total SWAG number. We should run some statistics 521 // and pick a real one. 522 Offset += 128; // 128 bytes of spill slots 523 524 // If there is a frame pointer, try using it. 525 // The FP is only available if there is no dynamic realignment. We 526 // don't know for sure yet whether we'll need that, so we guess based 527 // on whether there are any local variables that would trigger it. 528 unsigned StackAlign = TFI->getStackAlignment(); 529 if (TFI->hasFP(MF) && 530 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 531 if (isFrameOffsetLegal(MI, FPOffset)) 532 return false; 533 } 534 // If we can reference via the stack pointer, try that. 535 // FIXME: This (and the code that resolves the references) can be improved 536 // to only disallow SP relative references in the live range of 537 // the VLA(s). In practice, it's unclear how much difference that 538 // would make, but it may be worth doing. 539 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 540 return false; 541 542 // The offset likely isn't legal, we want to allocate a virtual base register. 543 return true; 544} 545 546/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 547/// be a pointer to FrameIdx at the beginning of the basic block. 548void ARMBaseRegisterInfo:: 549materializeFrameBaseRegister(MachineBasicBlock *MBB, 550 unsigned BaseReg, int FrameIdx, 551 int64_t Offset) const { 552 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 553 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 554 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 555 556 MachineBasicBlock::iterator Ins = MBB->begin(); 557 DebugLoc DL; // Defaults to "unknown" 558 if (Ins != MBB->end()) 559 DL = Ins->getDebugLoc(); 560 561 const MachineFunction &MF = *MBB->getParent(); 562 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 563 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 564 const MCInstrDesc &MCID = TII.get(ADDriOpc); 565 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 566 567 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) 568 .addFrameIndex(FrameIdx).addImm(Offset)); 569 570 if (!AFI->isThumb1OnlyFunction()) 571 AddDefaultCC(MIB); 572} 573 574void 575ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 576 unsigned BaseReg, int64_t Offset) const { 577 MachineInstr &MI = *I; 578 MachineBasicBlock &MBB = *MI.getParent(); 579 MachineFunction &MF = *MBB.getParent(); 580 const ARMBaseInstrInfo &TII = 581 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 582 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 583 int Off = Offset; // ARM doesn't need the general 64-bit offsets 584 unsigned i = 0; 585 586 assert(!AFI->isThumb1OnlyFunction() && 587 "This resolveFrameIndex does not support Thumb1!"); 588 589 while (!MI.getOperand(i).isFI()) { 590 ++i; 591 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 592 } 593 bool Done = false; 594 if (!AFI->isThumbFunction()) 595 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 596 else { 597 assert(AFI->isThumb2Function()); 598 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 599 } 600 assert (Done && "Unable to resolve frame index!"); 601 (void)Done; 602} 603 604bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 605 int64_t Offset) const { 606 const MCInstrDesc &Desc = MI->getDesc(); 607 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 608 unsigned i = 0; 609 610 while (!MI->getOperand(i).isFI()) { 611 ++i; 612 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 613 } 614 615 // AddrMode4 and AddrMode6 cannot handle any offset. 616 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 617 return Offset == 0; 618 619 unsigned NumBits = 0; 620 unsigned Scale = 1; 621 bool isSigned = true; 622 switch (AddrMode) { 623 case ARMII::AddrModeT2_i8: 624 case ARMII::AddrModeT2_i12: 625 // i8 supports only negative, and i12 supports only positive, so 626 // based on Offset sign, consider the appropriate instruction 627 Scale = 1; 628 if (Offset < 0) { 629 NumBits = 8; 630 Offset = -Offset; 631 } else { 632 NumBits = 12; 633 } 634 break; 635 case ARMII::AddrMode5: 636 // VFP address mode. 637 NumBits = 8; 638 Scale = 4; 639 break; 640 case ARMII::AddrMode_i12: 641 case ARMII::AddrMode2: 642 NumBits = 12; 643 break; 644 case ARMII::AddrMode3: 645 NumBits = 8; 646 break; 647 case ARMII::AddrModeT1_s: 648 NumBits = 5; 649 Scale = 4; 650 isSigned = false; 651 break; 652 default: 653 llvm_unreachable("Unsupported addressing mode!"); 654 } 655 656 Offset += getFrameIndexInstrOffset(MI, i); 657 // Make sure the offset is encodable for instructions that scale the 658 // immediate. 659 if ((Offset & (Scale-1)) != 0) 660 return false; 661 662 if (isSigned && Offset < 0) 663 Offset = -Offset; 664 665 unsigned Mask = (1 << NumBits) - 1; 666 if ((unsigned)Offset <= Mask * Scale) 667 return true; 668 669 return false; 670} 671 672void 673ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 674 int SPAdj, unsigned FIOperandNum, 675 RegScavenger *RS) const { 676 MachineInstr &MI = *II; 677 MachineBasicBlock &MBB = *MI.getParent(); 678 MachineFunction &MF = *MBB.getParent(); 679 const ARMBaseInstrInfo &TII = 680 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 681 const ARMFrameLowering *TFI = 682 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 683 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 684 assert(!AFI->isThumb1OnlyFunction() && 685 "This eliminateFrameIndex does not support Thumb1!"); 686 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 687 unsigned FrameReg; 688 689 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 690 691 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 692 // call frame setup/destroy instructions have already been eliminated. That 693 // means the stack pointer cannot be used to access the emergency spill slot 694 // when !hasReservedCallFrame(). 695#ifndef NDEBUG 696 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 697 assert(TFI->hasReservedCallFrame(MF) && 698 "Cannot use SP to access the emergency spill slot in " 699 "functions without a reserved call frame"); 700 assert(!MF.getFrameInfo()->hasVarSizedObjects() && 701 "Cannot use SP to access the emergency spill slot in " 702 "functions with variable sized frame objects"); 703 } 704#endif // NDEBUG 705 706 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); 707 708 // Modify MI as necessary to handle as much of 'Offset' as possible 709 bool Done = false; 710 if (!AFI->isThumbFunction()) 711 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 712 else { 713 assert(AFI->isThumb2Function()); 714 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 715 } 716 if (Done) 717 return; 718 719 // If we get here, the immediate doesn't fit into the instruction. We folded 720 // as much as possible above, handle the rest, providing a register that is 721 // SP+LargeImm. 722 assert((Offset || 723 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 724 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 725 "This code isn't needed if offset already handled!"); 726 727 unsigned ScratchReg = 0; 728 int PIdx = MI.findFirstPredOperandIdx(); 729 ARMCC::CondCodes Pred = (PIdx == -1) 730 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 731 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 732 if (Offset == 0) 733 // Must be addrmode4/6. 734 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 735 else { 736 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 737 if (!AFI->isThumbFunction()) 738 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 739 Offset, Pred, PredReg, TII); 740 else { 741 assert(AFI->isThumb2Function()); 742 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 743 Offset, Pred, PredReg, TII); 744 } 745 // Update the original instruction to use the scratch register. 746 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 747 } 748} 749