ARMBaseRegisterInfo.cpp revision 7bde2971330d8d64d6650d002db9c1ce77f4e4d4
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMAddressingModes.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMBaseRegisterInfo.h" 18#include "ARMInstrInfo.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMSubtarget.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/LLVMContext.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineLocation.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/RegisterScavenging.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetFrameInfo.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/BitVector.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/Support/CommandLine.h" 41using namespace llvm; 42 43static cl::opt<bool> 44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true), 45 cl::desc("Reuse repeated frame index values")); 46 47unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, 48 bool *isSPVFP) { 49 if (isSPVFP) 50 *isSPVFP = false; 51 52 using namespace ARM; 53 switch (RegEnum) { 54 default: 55 llvm_unreachable("Unknown ARM register!"); 56 case R0: case D0: case Q0: return 0; 57 case R1: case D1: case Q1: return 1; 58 case R2: case D2: case Q2: return 2; 59 case R3: case D3: case Q3: return 3; 60 case R4: case D4: case Q4: return 4; 61 case R5: case D5: case Q5: return 5; 62 case R6: case D6: case Q6: return 6; 63 case R7: case D7: case Q7: return 7; 64 case R8: case D8: case Q8: return 8; 65 case R9: case D9: case Q9: return 9; 66 case R10: case D10: case Q10: return 10; 67 case R11: case D11: case Q11: return 11; 68 case R12: case D12: case Q12: return 12; 69 case SP: case D13: case Q13: return 13; 70 case LR: case D14: case Q14: return 14; 71 case PC: case D15: case Q15: return 15; 72 73 case D16: return 16; 74 case D17: return 17; 75 case D18: return 18; 76 case D19: return 19; 77 case D20: return 20; 78 case D21: return 21; 79 case D22: return 22; 80 case D23: return 23; 81 case D24: return 24; 82 case D25: return 25; 83 case D26: return 27; 84 case D27: return 27; 85 case D28: return 28; 86 case D29: return 29; 87 case D30: return 30; 88 case D31: return 31; 89 90 case S0: case S1: case S2: case S3: 91 case S4: case S5: case S6: case S7: 92 case S8: case S9: case S10: case S11: 93 case S12: case S13: case S14: case S15: 94 case S16: case S17: case S18: case S19: 95 case S20: case S21: case S22: case S23: 96 case S24: case S25: case S26: case S27: 97 case S28: case S29: case S30: case S31: { 98 if (isSPVFP) 99 *isSPVFP = true; 100 switch (RegEnum) { 101 default: return 0; // Avoid compile time warning. 102 case S0: return 0; 103 case S1: return 1; 104 case S2: return 2; 105 case S3: return 3; 106 case S4: return 4; 107 case S5: return 5; 108 case S6: return 6; 109 case S7: return 7; 110 case S8: return 8; 111 case S9: return 9; 112 case S10: return 10; 113 case S11: return 11; 114 case S12: return 12; 115 case S13: return 13; 116 case S14: return 14; 117 case S15: return 15; 118 case S16: return 16; 119 case S17: return 17; 120 case S18: return 18; 121 case S19: return 19; 122 case S20: return 20; 123 case S21: return 21; 124 case S22: return 22; 125 case S23: return 23; 126 case S24: return 24; 127 case S25: return 25; 128 case S26: return 26; 129 case S27: return 27; 130 case S28: return 28; 131 case S29: return 29; 132 case S30: return 30; 133 case S31: return 31; 134 } 135 } 136 } 137} 138 139ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 140 const ARMSubtarget &sti) 141 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 142 TII(tii), STI(sti), 143 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 144} 145 146const unsigned* 147ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 148 static const unsigned CalleeSavedRegs[] = { 149 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 150 ARM::R7, ARM::R6, ARM::R5, ARM::R4, 151 152 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 153 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 154 0 155 }; 156 157 static const unsigned DarwinCalleeSavedRegs[] = { 158 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 159 // register. 160 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 161 ARM::R11, ARM::R10, ARM::R8, 162 163 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 164 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 165 0 166 }; 167 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 168} 169 170const TargetRegisterClass* const * 171ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 172 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 173 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 174 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 175 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 176 177 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 178 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 179 0 180 }; 181 182 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { 183 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 184 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass, 185 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass, 186 187 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 188 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 189 0 190 }; 191 192 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = { 193 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 194 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 195 &ARM::GPRRegClass, &ARM::GPRRegClass, 196 197 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 198 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 199 0 200 }; 201 202 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={ 203 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass, 204 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass, 205 &ARM::GPRRegClass, &ARM::GPRRegClass, 206 207 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 208 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 209 0 210 }; 211 212 if (STI.isThumb1Only()) { 213 return STI.isTargetDarwin() 214 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses; 215 } 216 return STI.isTargetDarwin() 217 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses; 218} 219 220BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 221 // FIXME: avoid re-calculating this everytime. 222 BitVector Reserved(getNumRegs()); 223 Reserved.set(ARM::SP); 224 Reserved.set(ARM::PC); 225 if (STI.isTargetDarwin() || hasFP(MF)) 226 Reserved.set(FramePtr); 227 // Some targets reserve R9. 228 if (STI.isR9Reserved()) 229 Reserved.set(ARM::R9); 230 return Reserved; 231} 232 233bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 234 unsigned Reg) const { 235 switch (Reg) { 236 default: break; 237 case ARM::SP: 238 case ARM::PC: 239 return true; 240 case ARM::R7: 241 case ARM::R11: 242 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 243 return true; 244 break; 245 case ARM::R9: 246 return STI.isR9Reserved(); 247 } 248 249 return false; 250} 251 252const TargetRegisterClass * 253ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 254 const TargetRegisterClass *B, 255 unsigned SubIdx) const { 256 switch (SubIdx) { 257 default: return 0; 258 case 1: 259 case 2: 260 case 3: 261 case 4: 262 // S sub-registers. 263 if (A->getSize() == 8) { 264 if (B == &ARM::SPR_8RegClass) 265 return &ARM::DPR_8RegClass; 266 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!"); 267 if (A == &ARM::DPR_8RegClass) 268 return A; 269 return &ARM::DPR_VFP2RegClass; 270 } 271 272 assert(A->getSize() == 16 && "Expecting a Q register class!"); 273 if (B == &ARM::SPR_8RegClass) 274 return &ARM::QPR_8RegClass; 275 return &ARM::QPR_VFP2RegClass; 276 case 5: 277 case 6: 278 // D sub-registers. 279 if (B == &ARM::DPR_VFP2RegClass) 280 return &ARM::QPR_VFP2RegClass; 281 if (B == &ARM::DPR_8RegClass) 282 return &ARM::QPR_8RegClass; 283 return A; 284 } 285 return 0; 286} 287 288const TargetRegisterClass * 289ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { 290 return ARM::GPRRegisterClass; 291} 292 293/// getAllocationOrder - Returns the register allocation order for a specified 294/// register class in the form of a pair of TargetRegisterClass iterators. 295std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 296ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, 297 unsigned HintType, unsigned HintReg, 298 const MachineFunction &MF) const { 299 // Alternative register allocation orders when favoring even / odd registers 300 // of register pairs. 301 302 // No FP, R9 is available. 303 static const unsigned GPREven1[] = { 304 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 305 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 306 ARM::R9, ARM::R11 307 }; 308 static const unsigned GPROdd1[] = { 309 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 310 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 311 ARM::R8, ARM::R10 312 }; 313 314 // FP is R7, R9 is available. 315 static const unsigned GPREven2[] = { 316 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 317 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 318 ARM::R9, ARM::R11 319 }; 320 static const unsigned GPROdd2[] = { 321 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 322 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 323 ARM::R8, ARM::R10 324 }; 325 326 // FP is R11, R9 is available. 327 static const unsigned GPREven3[] = { 328 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 329 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 330 ARM::R9 331 }; 332 static const unsigned GPROdd3[] = { 333 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 334 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 335 ARM::R8 336 }; 337 338 // No FP, R9 is not available. 339 static const unsigned GPREven4[] = { 340 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 341 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 342 ARM::R11 343 }; 344 static const unsigned GPROdd4[] = { 345 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 346 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 347 ARM::R10 348 }; 349 350 // FP is R7, R9 is not available. 351 static const unsigned GPREven5[] = { 352 ARM::R0, ARM::R2, ARM::R4, ARM::R10, 353 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 354 ARM::R11 355 }; 356 static const unsigned GPROdd5[] = { 357 ARM::R1, ARM::R3, ARM::R5, ARM::R11, 358 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 359 ARM::R10 360 }; 361 362 // FP is R11, R9 is not available. 363 static const unsigned GPREven6[] = { 364 ARM::R0, ARM::R2, ARM::R4, ARM::R6, 365 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 366 }; 367 static const unsigned GPROdd6[] = { 368 ARM::R1, ARM::R3, ARM::R5, ARM::R7, 369 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 370 }; 371 372 373 if (HintType == ARMRI::RegPairEven) { 374 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 375 // It's no longer possible to fulfill this hint. Return the default 376 // allocation order. 377 return std::make_pair(RC->allocation_order_begin(MF), 378 RC->allocation_order_end(MF)); 379 380 if (!STI.isTargetDarwin() && !hasFP(MF)) { 381 if (!STI.isR9Reserved()) 382 return std::make_pair(GPREven1, 383 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); 384 else 385 return std::make_pair(GPREven4, 386 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); 387 } else if (FramePtr == ARM::R7) { 388 if (!STI.isR9Reserved()) 389 return std::make_pair(GPREven2, 390 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); 391 else 392 return std::make_pair(GPREven5, 393 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); 394 } else { // FramePtr == ARM::R11 395 if (!STI.isR9Reserved()) 396 return std::make_pair(GPREven3, 397 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); 398 else 399 return std::make_pair(GPREven6, 400 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); 401 } 402 } else if (HintType == ARMRI::RegPairOdd) { 403 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 404 // It's no longer possible to fulfill this hint. Return the default 405 // allocation order. 406 return std::make_pair(RC->allocation_order_begin(MF), 407 RC->allocation_order_end(MF)); 408 409 if (!STI.isTargetDarwin() && !hasFP(MF)) { 410 if (!STI.isR9Reserved()) 411 return std::make_pair(GPROdd1, 412 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); 413 else 414 return std::make_pair(GPROdd4, 415 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); 416 } else if (FramePtr == ARM::R7) { 417 if (!STI.isR9Reserved()) 418 return std::make_pair(GPROdd2, 419 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); 420 else 421 return std::make_pair(GPROdd5, 422 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); 423 } else { // FramePtr == ARM::R11 424 if (!STI.isR9Reserved()) 425 return std::make_pair(GPROdd3, 426 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); 427 else 428 return std::make_pair(GPROdd6, 429 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); 430 } 431 } 432 return std::make_pair(RC->allocation_order_begin(MF), 433 RC->allocation_order_end(MF)); 434} 435 436/// ResolveRegAllocHint - Resolves the specified register allocation hint 437/// to a physical register. Returns the physical register if it is successful. 438unsigned 439ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 440 const MachineFunction &MF) const { 441 if (Reg == 0 || !isPhysicalRegister(Reg)) 442 return 0; 443 if (Type == 0) 444 return Reg; 445 else if (Type == (unsigned)ARMRI::RegPairOdd) 446 // Odd register. 447 return getRegisterPairOdd(Reg, MF); 448 else if (Type == (unsigned)ARMRI::RegPairEven) 449 // Even register. 450 return getRegisterPairEven(Reg, MF); 451 return 0; 452} 453 454void 455ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 456 MachineFunction &MF) const { 457 MachineRegisterInfo *MRI = &MF.getRegInfo(); 458 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 459 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 460 Hint.first == (unsigned)ARMRI::RegPairEven) && 461 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { 462 // If 'Reg' is one of the even / odd register pair and it's now changed 463 // (e.g. coalesced) into a different register. The other register of the 464 // pair allocation hint must be updated to reflect the relationship 465 // change. 466 unsigned OtherReg = Hint.second; 467 Hint = MRI->getRegAllocationHint(OtherReg); 468 if (Hint.second == Reg) 469 // Make sure the pair has not already divorced. 470 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 471 } 472} 473 474static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) { 475 unsigned MaxAlign = 0; 476 477 for (int i = FFI->getObjectIndexBegin(), 478 e = FFI->getObjectIndexEnd(); i != e; ++i) { 479 if (FFI->isDeadObjectIndex(i)) 480 continue; 481 482 unsigned Align = FFI->getObjectAlignment(i); 483 MaxAlign = std::max(MaxAlign, Align); 484 } 485 486 return MaxAlign; 487} 488 489/// hasFP - Return true if the specified function should have a dedicated frame 490/// pointer register. This is true if the function has variable sized allocas 491/// or if frame pointer elimination is disabled. 492/// 493bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { 494 const MachineFrameInfo *MFI = MF.getFrameInfo(); 495 return (NoFramePointerElim || 496 needsStackRealignment(MF) || 497 MFI->hasVarSizedObjects() || 498 MFI->isFrameAddressTaken()); 499} 500 501bool ARMBaseRegisterInfo:: 502needsStackRealignment(const MachineFunction &MF) const { 503 const MachineFrameInfo *MFI = MF.getFrameInfo(); 504 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 505 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 506 return (RealignStack && 507 !AFI->isThumb1OnlyFunction() && 508 (MFI->getMaxAlignment() > StackAlign) && 509 !MFI->hasVarSizedObjects()); 510} 511 512bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const { 513 const MachineFrameInfo *MFI = MF.getFrameInfo(); 514 if (NoFramePointerElim && MFI->hasCalls()) 515 return true; 516 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 517 || needsStackRealignment(MF); 518} 519 520/// estimateStackSize - Estimate and return the size of the frame. 521static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 522 const MachineFrameInfo *FFI = MF.getFrameInfo(); 523 int Offset = 0; 524 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 525 int FixedOff = -FFI->getObjectOffset(i); 526 if (FixedOff > Offset) Offset = FixedOff; 527 } 528 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 529 if (FFI->isDeadObjectIndex(i)) 530 continue; 531 Offset += FFI->getObjectSize(i); 532 unsigned Align = FFI->getObjectAlignment(i); 533 // Adjust to alignment boundary 534 Offset = (Offset+Align-1)/Align*Align; 535 } 536 return (unsigned)Offset; 537} 538 539/// estimateRSStackSizeLimit - Look at each instruction that references stack 540/// frames and return the stack size limit beyond which some of these 541/// instructions will require scratch register during their expansion later. 542unsigned 543ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const { 544 unsigned Limit = (1 << 12) - 1; 545 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 546 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 547 I != E; ++I) { 548 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 549 if (!I->getOperand(i).isFI()) continue; 550 551 const TargetInstrDesc &Desc = TII.get(I->getOpcode()); 552 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 553 if (AddrMode == ARMII::AddrMode3 || 554 AddrMode == ARMII::AddrModeT2_i8) 555 return (1 << 8) - 1; 556 557 if (AddrMode == ARMII::AddrMode5 || 558 AddrMode == ARMII::AddrModeT2_i8s4) 559 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 560 561 if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF)) 562 // When the stack offset is negative, we will end up using 563 // the i8 instructions instead. 564 return (1 << 8) - 1; 565 break; // At most one FI per instruction 566 } 567 } 568 } 569 570 return Limit; 571} 572 573void 574ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 575 RegScavenger *RS) const { 576 // This tells PEI to spill the FP as if it is any other callee-save register 577 // to take advantage the eliminateFrameIndex machinery. This also ensures it 578 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 579 // to combine multiple loads / stores. 580 bool CanEliminateFrame = true; 581 bool CS1Spilled = false; 582 bool LRSpilled = false; 583 unsigned NumGPRSpills = 0; 584 SmallVector<unsigned, 4> UnspilledCS1GPRs; 585 SmallVector<unsigned, 4> UnspilledCS2GPRs; 586 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 587 588 MachineFrameInfo *MFI = MF.getFrameInfo(); 589 590 // Calculate and set max stack object alignment early, so we can decide 591 // whether we will need stack realignment (and thus FP). 592 if (RealignStack) { 593 unsigned MaxAlign = std::max(MFI->getMaxAlignment(), 594 calculateMaxStackAlignment(MFI)); 595 MFI->setMaxAlignment(MaxAlign); 596 } 597 598 // Don't spill FP if the frame can be eliminated. This is determined 599 // by scanning the callee-save registers to see if any is used. 600 const unsigned *CSRegs = getCalleeSavedRegs(); 601 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 602 for (unsigned i = 0; CSRegs[i]; ++i) { 603 unsigned Reg = CSRegs[i]; 604 bool Spilled = false; 605 if (MF.getRegInfo().isPhysRegUsed(Reg)) { 606 AFI->setCSRegisterIsSpilled(Reg); 607 Spilled = true; 608 CanEliminateFrame = false; 609 } else { 610 // Check alias registers too. 611 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 612 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 613 Spilled = true; 614 CanEliminateFrame = false; 615 } 616 } 617 } 618 619 if (CSRegClasses[i] == ARM::GPRRegisterClass || 620 CSRegClasses[i] == ARM::tGPRRegisterClass) { 621 if (Spilled) { 622 NumGPRSpills++; 623 624 if (!STI.isTargetDarwin()) { 625 if (Reg == ARM::LR) 626 LRSpilled = true; 627 CS1Spilled = true; 628 continue; 629 } 630 631 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 632 switch (Reg) { 633 case ARM::LR: 634 LRSpilled = true; 635 // Fallthrough 636 case ARM::R4: 637 case ARM::R5: 638 case ARM::R6: 639 case ARM::R7: 640 CS1Spilled = true; 641 break; 642 default: 643 break; 644 } 645 } else { 646 if (!STI.isTargetDarwin()) { 647 UnspilledCS1GPRs.push_back(Reg); 648 continue; 649 } 650 651 switch (Reg) { 652 case ARM::R4: 653 case ARM::R5: 654 case ARM::R6: 655 case ARM::R7: 656 case ARM::LR: 657 UnspilledCS1GPRs.push_back(Reg); 658 break; 659 default: 660 UnspilledCS2GPRs.push_back(Reg); 661 break; 662 } 663 } 664 } 665 } 666 667 bool ForceLRSpill = false; 668 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 669 unsigned FnSize = TII.GetFunctionSizeInBytes(MF); 670 // Force LR to be spilled if the Thumb function size is > 2048. This enables 671 // use of BL to implement far jump. If it turns out that it's not needed 672 // then the branch fix up path will undo it. 673 if (FnSize >= (1 << 11)) { 674 CanEliminateFrame = false; 675 ForceLRSpill = true; 676 } 677 } 678 679 bool ExtraCSSpill = false; 680 if (!CanEliminateFrame || cannotEliminateFrame(MF)) { 681 AFI->setHasStackFrame(true); 682 683 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 684 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 685 if (!LRSpilled && CS1Spilled) { 686 MF.getRegInfo().setPhysRegUsed(ARM::LR); 687 AFI->setCSRegisterIsSpilled(ARM::LR); 688 NumGPRSpills++; 689 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 690 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 691 ForceLRSpill = false; 692 ExtraCSSpill = true; 693 } 694 695 // Darwin ABI requires FP to point to the stack slot that contains the 696 // previous FP. 697 if (STI.isTargetDarwin() || hasFP(MF)) { 698 MF.getRegInfo().setPhysRegUsed(FramePtr); 699 NumGPRSpills++; 700 } 701 702 // If stack and double are 8-byte aligned and we are spilling an odd number 703 // of GPRs. Spill one extra callee save GPR so we won't have to pad between 704 // the integer and double callee save areas. 705 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 706 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 707 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 708 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 709 unsigned Reg = UnspilledCS1GPRs[i]; 710 // Don't spill high register if the function is thumb1 711 if (!AFI->isThumb1OnlyFunction() || 712 isARMLowRegister(Reg) || Reg == ARM::LR) { 713 MF.getRegInfo().setPhysRegUsed(Reg); 714 AFI->setCSRegisterIsSpilled(Reg); 715 if (!isReservedReg(MF, Reg)) 716 ExtraCSSpill = true; 717 break; 718 } 719 } 720 } else if (!UnspilledCS2GPRs.empty() && 721 !AFI->isThumb1OnlyFunction()) { 722 unsigned Reg = UnspilledCS2GPRs.front(); 723 MF.getRegInfo().setPhysRegUsed(Reg); 724 AFI->setCSRegisterIsSpilled(Reg); 725 if (!isReservedReg(MF, Reg)) 726 ExtraCSSpill = true; 727 } 728 } 729 730 // Estimate if we might need to scavenge a register at some point in order 731 // to materialize a stack offset. If so, either spill one additional 732 // callee-saved register or reserve a special spill slot to facilitate 733 // register scavenging. Thumb1 needs a spill slot for stack pointer 734 // adjustments also, even when the frame itself is small. 735 if (RS && !ExtraCSSpill) { 736 MachineFrameInfo *MFI = MF.getFrameInfo(); 737 // If any of the stack slot references may be out of range of an 738 // immediate offset, make sure a register (or a spill slot) is 739 // available for the register scavenger. Note that if we're indexing 740 // off the frame pointer, the effective stack size is 4 bytes larger 741 // since the FP points to the stack slot of the previous FP. 742 if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0) 743 >= estimateRSStackSizeLimit(MF)) { 744 // If any non-reserved CS register isn't spilled, just spill one or two 745 // extra. That should take care of it! 746 unsigned NumExtras = TargetAlign / 4; 747 SmallVector<unsigned, 2> Extras; 748 while (NumExtras && !UnspilledCS1GPRs.empty()) { 749 unsigned Reg = UnspilledCS1GPRs.back(); 750 UnspilledCS1GPRs.pop_back(); 751 if (!isReservedReg(MF, Reg)) { 752 Extras.push_back(Reg); 753 NumExtras--; 754 } 755 } 756 // For non-Thumb1 functions, also check for hi-reg CS registers 757 if (!AFI->isThumb1OnlyFunction()) { 758 while (NumExtras && !UnspilledCS2GPRs.empty()) { 759 unsigned Reg = UnspilledCS2GPRs.back(); 760 UnspilledCS2GPRs.pop_back(); 761 if (!isReservedReg(MF, Reg)) { 762 Extras.push_back(Reg); 763 NumExtras--; 764 } 765 } 766 } 767 if (Extras.size() && NumExtras == 0) { 768 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 769 MF.getRegInfo().setPhysRegUsed(Extras[i]); 770 AFI->setCSRegisterIsSpilled(Extras[i]); 771 } 772 } else if (!AFI->isThumb1OnlyFunction()) { 773 // note: Thumb1 functions spill to R12, not the stack. 774 // Reserve a slot closest to SP or frame pointer. 775 const TargetRegisterClass *RC = ARM::GPRRegisterClass; 776 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 777 RC->getAlignment(), 778 false)); 779 } 780 } 781 } 782 } 783 784 if (ForceLRSpill) { 785 MF.getRegInfo().setPhysRegUsed(ARM::LR); 786 AFI->setCSRegisterIsSpilled(ARM::LR); 787 AFI->setLRIsSpilledForFarJump(true); 788 } 789} 790 791unsigned ARMBaseRegisterInfo::getRARegister() const { 792 return ARM::LR; 793} 794 795unsigned 796ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 797 if (STI.isTargetDarwin() || hasFP(MF)) 798 return FramePtr; 799 return ARM::SP; 800} 801 802unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 803 llvm_unreachable("What is the exception register"); 804 return 0; 805} 806 807unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 808 llvm_unreachable("What is the exception handler register"); 809 return 0; 810} 811 812int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 813 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 814} 815 816unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 817 const MachineFunction &MF) const { 818 switch (Reg) { 819 default: break; 820 // Return 0 if either register of the pair is a special register. 821 // So no R12, etc. 822 case ARM::R1: 823 return ARM::R0; 824 case ARM::R3: 825 return ARM::R2; 826 case ARM::R5: 827 return ARM::R4; 828 case ARM::R7: 829 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; 830 case ARM::R9: 831 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 832 case ARM::R11: 833 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 834 835 case ARM::S1: 836 return ARM::S0; 837 case ARM::S3: 838 return ARM::S2; 839 case ARM::S5: 840 return ARM::S4; 841 case ARM::S7: 842 return ARM::S6; 843 case ARM::S9: 844 return ARM::S8; 845 case ARM::S11: 846 return ARM::S10; 847 case ARM::S13: 848 return ARM::S12; 849 case ARM::S15: 850 return ARM::S14; 851 case ARM::S17: 852 return ARM::S16; 853 case ARM::S19: 854 return ARM::S18; 855 case ARM::S21: 856 return ARM::S20; 857 case ARM::S23: 858 return ARM::S22; 859 case ARM::S25: 860 return ARM::S24; 861 case ARM::S27: 862 return ARM::S26; 863 case ARM::S29: 864 return ARM::S28; 865 case ARM::S31: 866 return ARM::S30; 867 868 case ARM::D1: 869 return ARM::D0; 870 case ARM::D3: 871 return ARM::D2; 872 case ARM::D5: 873 return ARM::D4; 874 case ARM::D7: 875 return ARM::D6; 876 case ARM::D9: 877 return ARM::D8; 878 case ARM::D11: 879 return ARM::D10; 880 case ARM::D13: 881 return ARM::D12; 882 case ARM::D15: 883 return ARM::D14; 884 case ARM::D17: 885 return ARM::D16; 886 case ARM::D19: 887 return ARM::D18; 888 case ARM::D21: 889 return ARM::D20; 890 case ARM::D23: 891 return ARM::D22; 892 case ARM::D25: 893 return ARM::D24; 894 case ARM::D27: 895 return ARM::D26; 896 case ARM::D29: 897 return ARM::D28; 898 case ARM::D31: 899 return ARM::D30; 900 } 901 902 return 0; 903} 904 905unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 906 const MachineFunction &MF) const { 907 switch (Reg) { 908 default: break; 909 // Return 0 if either register of the pair is a special register. 910 // So no R12, etc. 911 case ARM::R0: 912 return ARM::R1; 913 case ARM::R2: 914 return ARM::R3; 915 case ARM::R4: 916 return ARM::R5; 917 case ARM::R6: 918 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; 919 case ARM::R8: 920 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 921 case ARM::R10: 922 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 923 924 case ARM::S0: 925 return ARM::S1; 926 case ARM::S2: 927 return ARM::S3; 928 case ARM::S4: 929 return ARM::S5; 930 case ARM::S6: 931 return ARM::S7; 932 case ARM::S8: 933 return ARM::S9; 934 case ARM::S10: 935 return ARM::S11; 936 case ARM::S12: 937 return ARM::S13; 938 case ARM::S14: 939 return ARM::S15; 940 case ARM::S16: 941 return ARM::S17; 942 case ARM::S18: 943 return ARM::S19; 944 case ARM::S20: 945 return ARM::S21; 946 case ARM::S22: 947 return ARM::S23; 948 case ARM::S24: 949 return ARM::S25; 950 case ARM::S26: 951 return ARM::S27; 952 case ARM::S28: 953 return ARM::S29; 954 case ARM::S30: 955 return ARM::S31; 956 957 case ARM::D0: 958 return ARM::D1; 959 case ARM::D2: 960 return ARM::D3; 961 case ARM::D4: 962 return ARM::D5; 963 case ARM::D6: 964 return ARM::D7; 965 case ARM::D8: 966 return ARM::D9; 967 case ARM::D10: 968 return ARM::D11; 969 case ARM::D12: 970 return ARM::D13; 971 case ARM::D14: 972 return ARM::D15; 973 case ARM::D16: 974 return ARM::D17; 975 case ARM::D18: 976 return ARM::D19; 977 case ARM::D20: 978 return ARM::D21; 979 case ARM::D22: 980 return ARM::D23; 981 case ARM::D24: 982 return ARM::D25; 983 case ARM::D26: 984 return ARM::D27; 985 case ARM::D28: 986 return ARM::D29; 987 case ARM::D30: 988 return ARM::D31; 989 } 990 991 return 0; 992} 993 994/// emitLoadConstPool - Emits a load from constpool to materialize the 995/// specified immediate. 996void ARMBaseRegisterInfo:: 997emitLoadConstPool(MachineBasicBlock &MBB, 998 MachineBasicBlock::iterator &MBBI, 999 DebugLoc dl, 1000 unsigned DestReg, unsigned SubIdx, int Val, 1001 ARMCC::CondCodes Pred, 1002 unsigned PredReg) const { 1003 MachineFunction &MF = *MBB.getParent(); 1004 MachineConstantPool *ConstantPool = MF.getConstantPool(); 1005 Constant *C = 1006 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 1007 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 1008 1009 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 1010 .addReg(DestReg, getDefRegState(true), SubIdx) 1011 .addConstantPoolIndex(Idx) 1012 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 1013} 1014 1015bool ARMBaseRegisterInfo:: 1016requiresRegisterScavenging(const MachineFunction &MF) const { 1017 return true; 1018} 1019 1020bool ARMBaseRegisterInfo:: 1021requiresFrameIndexScavenging(const MachineFunction &MF) const { 1022 return true; 1023} 1024 1025// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 1026// not required, we reserve argument space for call sites in the function 1027// immediately on entry to the current function. This eliminates the need for 1028// add/sub sp brackets around call sites. Returns true if the call frame is 1029// included as part of the stack frame. 1030bool ARMBaseRegisterInfo:: 1031hasReservedCallFrame(MachineFunction &MF) const { 1032 const MachineFrameInfo *FFI = MF.getFrameInfo(); 1033 unsigned CFSize = FFI->getMaxCallFrameSize(); 1034 // It's not always a good idea to include the call frame as part of the 1035 // stack frame. ARM (especially Thumb) has small immediate offset to 1036 // address the stack frame. So a large call frame can cause poor codegen 1037 // and may even makes it impossible to scavenge a register. 1038 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 1039 return false; 1040 1041 return !MF.getFrameInfo()->hasVarSizedObjects(); 1042} 1043 1044static void 1045emitSPUpdate(bool isARM, 1046 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 1047 DebugLoc dl, const ARMBaseInstrInfo &TII, 1048 int NumBytes, 1049 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 1050 if (isARM) 1051 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 1052 Pred, PredReg, TII); 1053 else 1054 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 1055 Pred, PredReg, TII); 1056} 1057 1058 1059void ARMBaseRegisterInfo:: 1060eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1061 MachineBasicBlock::iterator I) const { 1062 if (!hasReservedCallFrame(MF)) { 1063 // If we have alloca, convert as follows: 1064 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 1065 // ADJCALLSTACKUP -> add, sp, sp, amount 1066 MachineInstr *Old = I; 1067 DebugLoc dl = Old->getDebugLoc(); 1068 unsigned Amount = Old->getOperand(0).getImm(); 1069 if (Amount != 0) { 1070 // We need to keep the stack aligned properly. To do this, we round the 1071 // amount of space needed for the outgoing arguments up to the next 1072 // alignment boundary. 1073 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1074 Amount = (Amount+Align-1)/Align*Align; 1075 1076 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1077 assert(!AFI->isThumb1OnlyFunction() && 1078 "This eliminateCallFramePseudoInstr does not suppor Thumb1!"); 1079 bool isARM = !AFI->isThumbFunction(); 1080 1081 // Replace the pseudo instruction with a new instruction... 1082 unsigned Opc = Old->getOpcode(); 1083 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm(); 1084 // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN? 1085 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 1086 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1087 unsigned PredReg = Old->getOperand(2).getReg(); 1088 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 1089 } else { 1090 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1091 unsigned PredReg = Old->getOperand(3).getReg(); 1092 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 1093 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 1094 } 1095 } 1096 } 1097 MBB.erase(I); 1098} 1099 1100unsigned 1101ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1102 int SPAdj, int *Value, 1103 RegScavenger *RS) const { 1104 unsigned i = 0; 1105 MachineInstr &MI = *II; 1106 MachineBasicBlock &MBB = *MI.getParent(); 1107 MachineFunction &MF = *MBB.getParent(); 1108 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1109 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1110 assert(!AFI->isThumb1OnlyFunction() && 1111 "This eliminateFrameIndex does not support Thumb1!"); 1112 1113 while (!MI.getOperand(i).isFI()) { 1114 ++i; 1115 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 1116 } 1117 1118 unsigned FrameReg = ARM::SP; 1119 int FrameIndex = MI.getOperand(i).getIndex(); 1120 int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj; 1121 bool isFixed = MFI->isFixedObjectIndex(FrameIndex); 1122 1123 // When doing dynamic stack realignment, all of these need to change(?) 1124 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 1125 Offset -= AFI->getGPRCalleeSavedArea1Offset(); 1126 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 1127 Offset -= AFI->getGPRCalleeSavedArea2Offset(); 1128 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 1129 Offset -= AFI->getDPRCalleeSavedAreaOffset(); 1130 else if (needsStackRealignment(MF)) { 1131 // When dynamically realigning the stack, use the frame pointer for 1132 // parameters, and the stack pointer for locals. 1133 assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 1134 if (isFixed) { 1135 FrameReg = getFrameRegister(MF); 1136 Offset -= AFI->getFramePtrSpillOffset(); 1137 // When referencing from the frame pointer, stack pointer adjustments 1138 // don't matter. 1139 SPAdj = 0; 1140 } 1141 } else if (hasFP(MF) && AFI->hasStackFrame()) { 1142 assert(SPAdj == 0 && "Unexpected stack offset!"); 1143 if (isFixed || MFI->hasVarSizedObjects()) { 1144 // Use frame pointer to reference fixed objects unless this is a 1145 // frameless function. 1146 FrameReg = getFrameRegister(MF); 1147 Offset -= AFI->getFramePtrSpillOffset(); 1148 } else if (AFI->isThumb2Function()) { 1149 // In Thumb2 mode, the negative offset is very limited. 1150 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 1151 if (FPOffset >= -255 && FPOffset < 0) { 1152 FrameReg = getFrameRegister(MF); 1153 Offset = FPOffset; 1154 } 1155 } 1156 } 1157 1158 // Modify MI as necessary to handle as much of 'Offset' as possible 1159 bool Done = false; 1160 if (!AFI->isThumbFunction()) 1161 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 1162 else { 1163 assert(AFI->isThumb2Function()); 1164 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 1165 } 1166 if (Done) 1167 return 0; 1168 1169 // If we get here, the immediate doesn't fit into the instruction. We folded 1170 // as much as possible above, handle the rest, providing a register that is 1171 // SP+LargeImm. 1172 assert((Offset || 1173 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 1174 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 1175 "This code isn't needed if offset already handled!"); 1176 1177 unsigned ScratchReg = 0; 1178 int PIdx = MI.findFirstPredOperandIdx(); 1179 ARMCC::CondCodes Pred = (PIdx == -1) 1180 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1181 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1182 if (Offset == 0) 1183 // Must be addrmode4/6. 1184 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 1185 else { 1186 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); 1187 if (Value) *Value = Offset; 1188 if (!AFI->isThumbFunction()) 1189 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1190 Offset, Pred, PredReg, TII); 1191 else { 1192 assert(AFI->isThumb2Function()); 1193 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1194 Offset, Pred, PredReg, TII); 1195 } 1196 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1197 if (!ReuseFrameIndexVals) 1198 ScratchReg = 0; 1199 } 1200 return ScratchReg; 1201} 1202 1203/// Move iterator past the next bunch of callee save load / store ops for 1204/// the particular spill area (1: integer area 1, 2: integer area 2, 1205/// 3: fp area, 0: don't care). 1206static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1207 MachineBasicBlock::iterator &MBBI, 1208 int Opc1, int Opc2, unsigned Area, 1209 const ARMSubtarget &STI) { 1210 while (MBBI != MBB.end() && 1211 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && 1212 MBBI->getOperand(1).isFI()) { 1213 if (Area != 0) { 1214 bool Done = false; 1215 unsigned Category = 0; 1216 switch (MBBI->getOperand(0).getReg()) { 1217 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1218 case ARM::LR: 1219 Category = 1; 1220 break; 1221 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1222 Category = STI.isTargetDarwin() ? 2 : 1; 1223 break; 1224 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1225 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1226 Category = 3; 1227 break; 1228 default: 1229 Done = true; 1230 break; 1231 } 1232 if (Done || Category != Area) 1233 break; 1234 } 1235 1236 ++MBBI; 1237 } 1238} 1239 1240void ARMBaseRegisterInfo:: 1241emitPrologue(MachineFunction &MF) const { 1242 MachineBasicBlock &MBB = MF.front(); 1243 MachineBasicBlock::iterator MBBI = MBB.begin(); 1244 MachineFrameInfo *MFI = MF.getFrameInfo(); 1245 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1246 assert(!AFI->isThumb1OnlyFunction() && 1247 "This emitPrologue does not suppor Thumb1!"); 1248 bool isARM = !AFI->isThumbFunction(); 1249 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1250 unsigned NumBytes = MFI->getStackSize(); 1251 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1252 DebugLoc dl = (MBBI != MBB.end() ? 1253 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); 1254 1255 // Determine the sizes of each callee-save spill areas and record which frame 1256 // belongs to which callee-save spill areas. 1257 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1258 int FramePtrSpillFI = 0; 1259 1260 // Allocate the vararg register save area. This is not counted in NumBytes. 1261 if (VARegSaveSize) 1262 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); 1263 1264 if (!AFI->hasStackFrame()) { 1265 if (NumBytes != 0) 1266 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1267 return; 1268 } 1269 1270 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1271 unsigned Reg = CSI[i].getReg(); 1272 int FI = CSI[i].getFrameIdx(); 1273 switch (Reg) { 1274 case ARM::R4: 1275 case ARM::R5: 1276 case ARM::R6: 1277 case ARM::R7: 1278 case ARM::LR: 1279 if (Reg == FramePtr) 1280 FramePtrSpillFI = FI; 1281 AFI->addGPRCalleeSavedArea1Frame(FI); 1282 GPRCS1Size += 4; 1283 break; 1284 case ARM::R8: 1285 case ARM::R9: 1286 case ARM::R10: 1287 case ARM::R11: 1288 if (Reg == FramePtr) 1289 FramePtrSpillFI = FI; 1290 if (STI.isTargetDarwin()) { 1291 AFI->addGPRCalleeSavedArea2Frame(FI); 1292 GPRCS2Size += 4; 1293 } else { 1294 AFI->addGPRCalleeSavedArea1Frame(FI); 1295 GPRCS1Size += 4; 1296 } 1297 break; 1298 default: 1299 AFI->addDPRCalleeSavedAreaFrame(FI); 1300 DPRCSSize += 8; 1301 } 1302 } 1303 1304 // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1305 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); 1306 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); 1307 1308 // Set FP to point to the stack slot that contains the previous FP. 1309 // For Darwin, FP is R7, which has now been stored in spill area 1. 1310 // Otherwise, if this is not Darwin, all the callee-saved registers go 1311 // into spill area 1, including the FP in R11. In either case, it is 1312 // now safe to emit this assignment. 1313 if (STI.isTargetDarwin() || hasFP(MF)) { 1314 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 1315 MachineInstrBuilder MIB = 1316 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 1317 .addFrameIndex(FramePtrSpillFI).addImm(0); 1318 AddDefaultCC(AddDefaultPred(MIB)); 1319 } 1320 1321 // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1322 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); 1323 1324 // Build the new SUBri to adjust SP for FP callee-save spill area. 1325 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); 1326 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); 1327 1328 // Determine starting offsets of spill areas. 1329 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1330 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1331 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1332 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1333 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1334 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1335 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1336 1337 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI); 1338 NumBytes = DPRCSOffset; 1339 if (NumBytes) { 1340 // Adjust SP after all the callee-save spills. 1341 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1342 } 1343 1344 if (STI.isTargetELF() && hasFP(MF)) { 1345 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1346 AFI->getFramePtrSpillOffset()); 1347 } 1348 1349 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1350 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1351 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1352 1353 // If we need dynamic stack realignment, do it here. 1354 if (needsStackRealignment(MF)) { 1355 unsigned Opc; 1356 unsigned MaxAlign = MFI->getMaxAlignment(); 1357 assert (!AFI->isThumb1OnlyFunction()); 1358 Opc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri; 1359 1360 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), ARM::SP) 1361 .addReg(ARM::SP, RegState::Kill) 1362 .addImm(MaxAlign-1))); 1363 } 1364} 1365 1366static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1367 for (unsigned i = 0; CSRegs[i]; ++i) 1368 if (Reg == CSRegs[i]) 1369 return true; 1370 return false; 1371} 1372 1373static bool isCSRestore(MachineInstr *MI, 1374 const ARMBaseInstrInfo &TII, 1375 const unsigned *CSRegs) { 1376 return ((MI->getOpcode() == (int)ARM::VLDRD || 1377 MI->getOpcode() == (int)ARM::LDR || 1378 MI->getOpcode() == (int)ARM::t2LDRi12) && 1379 MI->getOperand(1).isFI() && 1380 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1381} 1382 1383void ARMBaseRegisterInfo:: 1384emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { 1385 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1386 assert(MBBI->getDesc().isReturn() && 1387 "Can only insert epilog into returning blocks"); 1388 DebugLoc dl = MBBI->getDebugLoc(); 1389 MachineFrameInfo *MFI = MF.getFrameInfo(); 1390 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1391 assert(!AFI->isThumb1OnlyFunction() && 1392 "This emitEpilogue does not suppor Thumb1!"); 1393 bool isARM = !AFI->isThumbFunction(); 1394 1395 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1396 int NumBytes = (int)MFI->getStackSize(); 1397 1398 if (!AFI->hasStackFrame()) { 1399 if (NumBytes != 0) 1400 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1401 } else { 1402 // Unwind MBBI to point to first LDR / VLDRD. 1403 const unsigned *CSRegs = getCalleeSavedRegs(); 1404 if (MBBI != MBB.begin()) { 1405 do 1406 --MBBI; 1407 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 1408 if (!isCSRestore(MBBI, TII, CSRegs)) 1409 ++MBBI; 1410 } 1411 1412 // Move SP to start of FP callee save spill area. 1413 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1414 AFI->getGPRCalleeSavedArea2Size() + 1415 AFI->getDPRCalleeSavedAreaSize()); 1416 1417 // Darwin ABI requires FP to point to the stack slot that contains the 1418 // previous FP. 1419 bool HasFP = hasFP(MF); 1420 if ((STI.isTargetDarwin() && NumBytes) || HasFP) { 1421 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1422 // Reset SP based on frame pointer only if the stack frame extends beyond 1423 // frame pointer stack slot or target is ELF and the function has FP. 1424 if (HasFP || 1425 AFI->getGPRCalleeSavedArea2Size() || 1426 AFI->getDPRCalleeSavedAreaSize() || 1427 AFI->getDPRCalleeSavedAreaOffset()) { 1428 if (NumBytes) { 1429 if (isARM) 1430 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1431 ARMCC::AL, 0, TII); 1432 else 1433 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1434 ARMCC::AL, 0, TII); 1435 } else { 1436 // Thumb2 or ARM. 1437 if (isARM) 1438 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 1439 .addReg(FramePtr) 1440 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1441 else 1442 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) 1443 .addReg(FramePtr); 1444 } 1445 } 1446 } else if (NumBytes) 1447 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1448 1449 // Move SP to start of integer callee save spill area 2. 1450 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI); 1451 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); 1452 1453 // Move SP to start of integer callee save spill area 1. 1454 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); 1455 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); 1456 1457 // Move SP to SP upon entry to the function. 1458 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); 1459 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); 1460 } 1461 1462 if (VARegSaveSize) 1463 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 1464} 1465 1466namespace { 1467 struct MaximalStackAlignmentCalculator : public MachineFunctionPass { 1468 static char ID; 1469 MaximalStackAlignmentCalculator() : MachineFunctionPass(&ID) {} 1470 1471 virtual bool runOnMachineFunction(MachineFunction &MF) { 1472 MachineFrameInfo *FFI = MF.getFrameInfo(); 1473 MachineRegisterInfo &RI = MF.getRegInfo(); 1474 1475 // Calculate max stack alignment of all already allocated stack objects. 1476 unsigned MaxAlign = calculateMaxStackAlignment(FFI); 1477 1478 // Be over-conservative: scan over all vreg defs and find, whether vector 1479 // registers are used. If yes - there is probability, that vector register 1480 // will be spilled and thus stack needs to be aligned properly. 1481 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister; 1482 RegNum < RI.getLastVirtReg(); ++RegNum) 1483 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment()); 1484 1485 if (FFI->getMaxAlignment() == MaxAlign) 1486 return false; 1487 1488 FFI->setMaxAlignment(MaxAlign); 1489 return true; 1490 } 1491 1492 virtual const char *getPassName() const { 1493 return "ARM Stack Required Alignment Auto-Detector"; 1494 } 1495 1496 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 1497 AU.setPreservesCFG(); 1498 MachineFunctionPass::getAnalysisUsage(AU); 1499 } 1500 }; 1501 1502 char MaximalStackAlignmentCalculator::ID = 0; 1503} 1504 1505FunctionPass* 1506llvm::createARMMaxStackAlignmentCalculatorPass() { 1507 return new MaximalStackAlignmentCalculator(); 1508} 1509 1510#include "ARMGenRegisterInfo.inc" 1511