ARMBaseRegisterInfo.cpp revision 7e831db1d4f5dc51ca6526739cf41e59895c5c20 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/raw_ostream.h"
34#include "llvm/Target/TargetFrameInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/ADT/BitVector.h"
38#include "llvm/ADT/SmallVector.h"
39using namespace llvm;
40
41unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
42                                                   bool *isSPVFP) {
43  if (isSPVFP)
44    *isSPVFP = false;
45
46  using namespace ARM;
47  switch (RegEnum) {
48  default:
49    llvm_unreachable("Unknown ARM register!");
50  case R0:  case D0:  case Q0:  return 0;
51  case R1:  case D1:  case Q1:  return 1;
52  case R2:  case D2:  case Q2:  return 2;
53  case R3:  case D3:  case Q3:  return 3;
54  case R4:  case D4:  case Q4:  return 4;
55  case R5:  case D5:  case Q5:  return 5;
56  case R6:  case D6:  case Q6:  return 6;
57  case R7:  case D7:  case Q7:  return 7;
58  case R8:  case D8:  case Q8:  return 8;
59  case R9:  case D9:  case Q9:  return 9;
60  case R10: case D10: case Q10: return 10;
61  case R11: case D11: case Q11: return 11;
62  case R12: case D12: case Q12: return 12;
63  case SP:  case D13: case Q13: return 13;
64  case LR:  case D14: case Q14: return 14;
65  case PC:  case D15: case Q15: return 15;
66
67  case D16: return 16;
68  case D17: return 17;
69  case D18: return 18;
70  case D19: return 19;
71  case D20: return 20;
72  case D21: return 21;
73  case D22: return 22;
74  case D23: return 23;
75  case D24: return 24;
76  case D25: return 25;
77  case D26: return 27;
78  case D27: return 27;
79  case D28: return 28;
80  case D29: return 29;
81  case D30: return 30;
82  case D31: return 31;
83
84  case S0: case S1: case S2: case S3:
85  case S4: case S5: case S6: case S7:
86  case S8: case S9: case S10: case S11:
87  case S12: case S13: case S14: case S15:
88  case S16: case S17: case S18: case S19:
89  case S20: case S21: case S22: case S23:
90  case S24: case S25: case S26: case S27:
91  case S28: case S29: case S30: case S31: {
92    if (isSPVFP)
93      *isSPVFP = true;
94    switch (RegEnum) {
95    default: return 0; // Avoid compile time warning.
96    case S0: return 0;
97    case S1: return 1;
98    case S2: return 2;
99    case S3: return 3;
100    case S4: return 4;
101    case S5: return 5;
102    case S6: return 6;
103    case S7: return 7;
104    case S8: return 8;
105    case S9: return 9;
106    case S10: return 10;
107    case S11: return 11;
108    case S12: return 12;
109    case S13: return 13;
110    case S14: return 14;
111    case S15: return 15;
112    case S16: return 16;
113    case S17: return 17;
114    case S18: return 18;
115    case S19: return 19;
116    case S20: return 20;
117    case S21: return 21;
118    case S22: return 22;
119    case S23: return 23;
120    case S24: return 24;
121    case S25: return 25;
122    case S26: return 26;
123    case S27: return 27;
124    case S28: return 28;
125    case S29: return 29;
126    case S30: return 30;
127    case S31: return 31;
128    }
129  }
130  }
131}
132
133ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
134                                         const ARMSubtarget &sti)
135  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
136    TII(tii), STI(sti),
137    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
138}
139
140const unsigned*
141ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
142  static const unsigned CalleeSavedRegs[] = {
143    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
144    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
145
146    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
147    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
148    0
149  };
150
151  static const unsigned DarwinCalleeSavedRegs[] = {
152    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
153    // register.
154    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
155    ARM::R11, ARM::R10, ARM::R8,
156
157    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
158    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
159    0
160  };
161  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
162}
163
164const TargetRegisterClass* const *
165ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
166  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
167    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
168    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
169    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
170
171    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
172    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
173    0
174  };
175
176  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
177    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
178    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
179    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
180
181    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
182    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
183    0
184  };
185
186  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
187    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
188    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
189    &ARM::GPRRegClass, &ARM::GPRRegClass,
190
191    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
192    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
193    0
194  };
195
196  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
197    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
198    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
199    &ARM::GPRRegClass,  &ARM::GPRRegClass,
200
201    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
202    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
203    0
204  };
205
206  if (STI.isThumb1Only()) {
207    return STI.isTargetDarwin()
208      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
209  }
210  return STI.isTargetDarwin()
211    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
212}
213
214BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
215  // FIXME: avoid re-calculating this everytime.
216  BitVector Reserved(getNumRegs());
217  Reserved.set(ARM::SP);
218  Reserved.set(ARM::PC);
219  if (STI.isTargetDarwin() || hasFP(MF))
220    Reserved.set(FramePtr);
221  // Some targets reserve R9.
222  if (STI.isR9Reserved())
223    Reserved.set(ARM::R9);
224  return Reserved;
225}
226
227bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
228                                        unsigned Reg) const {
229  switch (Reg) {
230  default: break;
231  case ARM::SP:
232  case ARM::PC:
233    return true;
234  case ARM::R7:
235  case ARM::R11:
236    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
237      return true;
238    break;
239  case ARM::R9:
240    return STI.isR9Reserved();
241  }
242
243  return false;
244}
245
246const TargetRegisterClass *
247ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
248  return ARM::GPRRegisterClass;
249}
250
251/// getAllocationOrder - Returns the register allocation order for a specified
252/// register class in the form of a pair of TargetRegisterClass iterators.
253std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
254ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
255                                        unsigned HintType, unsigned HintReg,
256                                        const MachineFunction &MF) const {
257  // Alternative register allocation orders when favoring even / odd registers
258  // of register pairs.
259
260  // No FP, R9 is available.
261  static const unsigned GPREven1[] = {
262    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
263    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
264    ARM::R9, ARM::R11
265  };
266  static const unsigned GPROdd1[] = {
267    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
268    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
269    ARM::R8, ARM::R10
270  };
271
272  // FP is R7, R9 is available.
273  static const unsigned GPREven2[] = {
274    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
275    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
276    ARM::R9, ARM::R11
277  };
278  static const unsigned GPROdd2[] = {
279    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
280    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
281    ARM::R8, ARM::R10
282  };
283
284  // FP is R11, R9 is available.
285  static const unsigned GPREven3[] = {
286    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
287    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
288    ARM::R9
289  };
290  static const unsigned GPROdd3[] = {
291    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
292    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
293    ARM::R8
294  };
295
296  // No FP, R9 is not available.
297  static const unsigned GPREven4[] = {
298    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
299    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
300    ARM::R11
301  };
302  static const unsigned GPROdd4[] = {
303    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
304    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
305    ARM::R10
306  };
307
308  // FP is R7, R9 is not available.
309  static const unsigned GPREven5[] = {
310    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
311    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
312    ARM::R11
313  };
314  static const unsigned GPROdd5[] = {
315    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
316    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
317    ARM::R10
318  };
319
320  // FP is R11, R9 is not available.
321  static const unsigned GPREven6[] = {
322    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
323    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
324  };
325  static const unsigned GPROdd6[] = {
326    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
327    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
328  };
329
330
331  if (HintType == ARMRI::RegPairEven) {
332    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
333      // It's no longer possible to fulfill this hint. Return the default
334      // allocation order.
335      return std::make_pair(RC->allocation_order_begin(MF),
336                            RC->allocation_order_end(MF));
337
338    if (!STI.isTargetDarwin() && !hasFP(MF)) {
339      if (!STI.isR9Reserved())
340        return std::make_pair(GPREven1,
341                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
342      else
343        return std::make_pair(GPREven4,
344                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
345    } else if (FramePtr == ARM::R7) {
346      if (!STI.isR9Reserved())
347        return std::make_pair(GPREven2,
348                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
349      else
350        return std::make_pair(GPREven5,
351                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
352    } else { // FramePtr == ARM::R11
353      if (!STI.isR9Reserved())
354        return std::make_pair(GPREven3,
355                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
356      else
357        return std::make_pair(GPREven6,
358                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
359    }
360  } else if (HintType == ARMRI::RegPairOdd) {
361    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
362      // It's no longer possible to fulfill this hint. Return the default
363      // allocation order.
364      return std::make_pair(RC->allocation_order_begin(MF),
365                            RC->allocation_order_end(MF));
366
367    if (!STI.isTargetDarwin() && !hasFP(MF)) {
368      if (!STI.isR9Reserved())
369        return std::make_pair(GPROdd1,
370                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
371      else
372        return std::make_pair(GPROdd4,
373                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
374    } else if (FramePtr == ARM::R7) {
375      if (!STI.isR9Reserved())
376        return std::make_pair(GPROdd2,
377                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
378      else
379        return std::make_pair(GPROdd5,
380                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
381    } else { // FramePtr == ARM::R11
382      if (!STI.isR9Reserved())
383        return std::make_pair(GPROdd3,
384                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
385      else
386        return std::make_pair(GPROdd6,
387                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
388    }
389  }
390  return std::make_pair(RC->allocation_order_begin(MF),
391                        RC->allocation_order_end(MF));
392}
393
394/// ResolveRegAllocHint - Resolves the specified register allocation hint
395/// to a physical register. Returns the physical register if it is successful.
396unsigned
397ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
398                                         const MachineFunction &MF) const {
399  if (Reg == 0 || !isPhysicalRegister(Reg))
400    return 0;
401  if (Type == 0)
402    return Reg;
403  else if (Type == (unsigned)ARMRI::RegPairOdd)
404    // Odd register.
405    return getRegisterPairOdd(Reg, MF);
406  else if (Type == (unsigned)ARMRI::RegPairEven)
407    // Even register.
408    return getRegisterPairEven(Reg, MF);
409  return 0;
410}
411
412void
413ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
414                                        MachineFunction &MF) const {
415  MachineRegisterInfo *MRI = &MF.getRegInfo();
416  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
417  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
418       Hint.first == (unsigned)ARMRI::RegPairEven) &&
419      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
420    // If 'Reg' is one of the even / odd register pair and it's now changed
421    // (e.g. coalesced) into a different register. The other register of the
422    // pair allocation hint must be updated to reflect the relationship
423    // change.
424    unsigned OtherReg = Hint.second;
425    Hint = MRI->getRegAllocationHint(OtherReg);
426    if (Hint.second == Reg)
427      // Make sure the pair has not already divorced.
428      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
429  }
430}
431
432/// hasFP - Return true if the specified function should have a dedicated frame
433/// pointer register.  This is true if the function has variable sized allocas
434/// or if frame pointer elimination is disabled.
435///
436bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
437  const MachineFrameInfo *MFI = MF.getFrameInfo();
438  return (NoFramePointerElim ||
439          MFI->hasVarSizedObjects() ||
440          MFI->isFrameAddressTaken());
441}
442
443bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
444  const MachineFrameInfo *MFI = MF.getFrameInfo();
445  if (NoFramePointerElim && MFI->hasCalls())
446    return true;
447  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
448}
449
450/// estimateStackSize - Estimate and return the size of the frame.
451static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
452  const MachineFrameInfo *FFI = MF.getFrameInfo();
453  int Offset = 0;
454  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
455    int FixedOff = -FFI->getObjectOffset(i);
456    if (FixedOff > Offset) Offset = FixedOff;
457  }
458  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
459    if (FFI->isDeadObjectIndex(i))
460      continue;
461    Offset += FFI->getObjectSize(i);
462    unsigned Align = FFI->getObjectAlignment(i);
463    // Adjust to alignment boundary
464    Offset = (Offset+Align-1)/Align*Align;
465  }
466  return (unsigned)Offset;
467}
468
469/// estimateRSStackSizeLimit - Look at each instruction that references stack
470/// frames and return the stack size limit beyond which some of these
471/// instructions will require scratch register during their expansion later.
472unsigned
473ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
474  unsigned Limit = (1 << 12) - 1;
475  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
476    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
477         I != E; ++I) {
478      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
479        if (!I->getOperand(i).isFI()) continue;
480
481        const TargetInstrDesc &Desc = TII.get(I->getOpcode());
482        unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
483        if (AddrMode == ARMII::AddrMode3 ||
484            AddrMode == ARMII::AddrModeT2_i8)
485          return (1 << 8) - 1;
486
487        if (AddrMode == ARMII::AddrMode5 ||
488            AddrMode == ARMII::AddrModeT2_i8s4)
489          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
490
491        if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF))
492          // When the stack offset is negative, we will end up using
493          // the i8 instructions instead.
494          return (1 << 8) - 1;
495        break; // At most one FI per instruction
496      }
497    }
498  }
499
500  return Limit;
501}
502
503void
504ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
505                                                          RegScavenger *RS) const {
506  // This tells PEI to spill the FP as if it is any other callee-save register
507  // to take advantage the eliminateFrameIndex machinery. This also ensures it
508  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
509  // to combine multiple loads / stores.
510  bool CanEliminateFrame = true;
511  bool CS1Spilled = false;
512  bool LRSpilled = false;
513  unsigned NumGPRSpills = 0;
514  SmallVector<unsigned, 4> UnspilledCS1GPRs;
515  SmallVector<unsigned, 4> UnspilledCS2GPRs;
516  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
517
518  // Don't spill FP if the frame can be eliminated. This is determined
519  // by scanning the callee-save registers to see if any is used.
520  const unsigned *CSRegs = getCalleeSavedRegs();
521  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
522  for (unsigned i = 0; CSRegs[i]; ++i) {
523    unsigned Reg = CSRegs[i];
524    bool Spilled = false;
525    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
526      AFI->setCSRegisterIsSpilled(Reg);
527      Spilled = true;
528      CanEliminateFrame = false;
529    } else {
530      // Check alias registers too.
531      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
532        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
533          Spilled = true;
534          CanEliminateFrame = false;
535        }
536      }
537    }
538
539    if (CSRegClasses[i] == ARM::GPRRegisterClass ||
540        CSRegClasses[i] == ARM::tGPRRegisterClass) {
541      if (Spilled) {
542        NumGPRSpills++;
543
544        if (!STI.isTargetDarwin()) {
545          if (Reg == ARM::LR)
546            LRSpilled = true;
547          CS1Spilled = true;
548          continue;
549        }
550
551        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
552        switch (Reg) {
553        case ARM::LR:
554          LRSpilled = true;
555          // Fallthrough
556        case ARM::R4:
557        case ARM::R5:
558        case ARM::R6:
559        case ARM::R7:
560          CS1Spilled = true;
561          break;
562        default:
563          break;
564        }
565      } else {
566        if (!STI.isTargetDarwin()) {
567          UnspilledCS1GPRs.push_back(Reg);
568          continue;
569        }
570
571        switch (Reg) {
572        case ARM::R4:
573        case ARM::R5:
574        case ARM::R6:
575        case ARM::R7:
576        case ARM::LR:
577          UnspilledCS1GPRs.push_back(Reg);
578          break;
579        default:
580          UnspilledCS2GPRs.push_back(Reg);
581          break;
582        }
583      }
584    }
585  }
586
587  bool ForceLRSpill = false;
588  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
589    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
590    // Force LR to be spilled if the Thumb function size is > 2048. This enables
591    // use of BL to implement far jump. If it turns out that it's not needed
592    // then the branch fix up path will undo it.
593    if (FnSize >= (1 << 11)) {
594      CanEliminateFrame = false;
595      ForceLRSpill = true;
596    }
597  }
598
599  bool ExtraCSSpill = false;
600  if (!CanEliminateFrame || cannotEliminateFrame(MF)) {
601    AFI->setHasStackFrame(true);
602
603    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
604    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
605    if (!LRSpilled && CS1Spilled) {
606      MF.getRegInfo().setPhysRegUsed(ARM::LR);
607      AFI->setCSRegisterIsSpilled(ARM::LR);
608      NumGPRSpills++;
609      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
610                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
611      ForceLRSpill = false;
612      ExtraCSSpill = true;
613    }
614
615    // Darwin ABI requires FP to point to the stack slot that contains the
616    // previous FP.
617    if (STI.isTargetDarwin() || hasFP(MF)) {
618      MF.getRegInfo().setPhysRegUsed(FramePtr);
619      NumGPRSpills++;
620    }
621
622    // If stack and double are 8-byte aligned and we are spilling an odd number
623    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
624    // the integer and double callee save areas.
625    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
626    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
627      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
628        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
629          unsigned Reg = UnspilledCS1GPRs[i];
630          // Don't spill high register if the function is thumb1
631          if (!AFI->isThumb1OnlyFunction() ||
632              isARMLowRegister(Reg) || Reg == ARM::LR) {
633            MF.getRegInfo().setPhysRegUsed(Reg);
634            AFI->setCSRegisterIsSpilled(Reg);
635            if (!isReservedReg(MF, Reg))
636              ExtraCSSpill = true;
637            break;
638          }
639        }
640      } else if (!UnspilledCS2GPRs.empty() &&
641                 !AFI->isThumb1OnlyFunction()) {
642        unsigned Reg = UnspilledCS2GPRs.front();
643        MF.getRegInfo().setPhysRegUsed(Reg);
644        AFI->setCSRegisterIsSpilled(Reg);
645        if (!isReservedReg(MF, Reg))
646          ExtraCSSpill = true;
647      }
648    }
649
650    // Estimate if we might need to scavenge a register at some point in order
651    // to materialize a stack offset. If so, either spill one additional
652    // callee-saved register or reserve a special spill slot to facilitate
653    // register scavenging. Thumb1 needs a spill slot for stack pointer
654    // adjustments also, even when the frame itself is small.
655    if (RS && !ExtraCSSpill) {
656      MachineFrameInfo  *MFI = MF.getFrameInfo();
657      // If any of the stack slot references may be out of range of an
658      // immediate offset, make sure a register (or a spill slot) is
659      // available for the register scavenger. Note that if we're indexing
660      // off the frame pointer, the effective stack size is 4 bytes larger
661      // since the FP points to the stack slot of the previous FP.
662      if (estimateStackSize(MF, MFI) + (hasFP(MF) ? 4 : 0)
663          >= estimateRSStackSizeLimit(MF)) {
664        // If any non-reserved CS register isn't spilled, just spill one or two
665        // extra. That should take care of it!
666        unsigned NumExtras = TargetAlign / 4;
667        SmallVector<unsigned, 2> Extras;
668        while (NumExtras && !UnspilledCS1GPRs.empty()) {
669          unsigned Reg = UnspilledCS1GPRs.back();
670          UnspilledCS1GPRs.pop_back();
671          if (!isReservedReg(MF, Reg)) {
672            Extras.push_back(Reg);
673            NumExtras--;
674          }
675        }
676        // For non-Thumb1 functions, also check for hi-reg CS registers
677        if (!AFI->isThumb1OnlyFunction()) {
678          while (NumExtras && !UnspilledCS2GPRs.empty()) {
679            unsigned Reg = UnspilledCS2GPRs.back();
680            UnspilledCS2GPRs.pop_back();
681            if (!isReservedReg(MF, Reg)) {
682              Extras.push_back(Reg);
683              NumExtras--;
684            }
685          }
686        }
687        if (Extras.size() && NumExtras == 0) {
688          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
689            MF.getRegInfo().setPhysRegUsed(Extras[i]);
690            AFI->setCSRegisterIsSpilled(Extras[i]);
691          }
692        } else if (!AFI->isThumb1OnlyFunction()) {
693          // note: Thumb1 functions spill to R12, not the stack.
694          // Reserve a slot closest to SP or frame pointer.
695          const TargetRegisterClass *RC = ARM::GPRRegisterClass;
696          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
697                                                           RC->getAlignment()));
698        }
699      }
700    }
701  }
702
703  if (ForceLRSpill) {
704    MF.getRegInfo().setPhysRegUsed(ARM::LR);
705    AFI->setCSRegisterIsSpilled(ARM::LR);
706    AFI->setLRIsSpilledForFarJump(true);
707  }
708}
709
710unsigned ARMBaseRegisterInfo::getRARegister() const {
711  return ARM::LR;
712}
713
714unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
715  if (STI.isTargetDarwin() || hasFP(MF))
716    return FramePtr;
717  return ARM::SP;
718}
719
720unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
721  llvm_unreachable("What is the exception register");
722  return 0;
723}
724
725unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
726  llvm_unreachable("What is the exception handler register");
727  return 0;
728}
729
730int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
731  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
732}
733
734unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
735                                               const MachineFunction &MF) const {
736  switch (Reg) {
737  default: break;
738  // Return 0 if either register of the pair is a special register.
739  // So no R12, etc.
740  case ARM::R1:
741    return ARM::R0;
742  case ARM::R3:
743    return ARM::R2;
744  case ARM::R5:
745    return ARM::R4;
746  case ARM::R7:
747    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
748  case ARM::R9:
749    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
750  case ARM::R11:
751    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
752
753  case ARM::S1:
754    return ARM::S0;
755  case ARM::S3:
756    return ARM::S2;
757  case ARM::S5:
758    return ARM::S4;
759  case ARM::S7:
760    return ARM::S6;
761  case ARM::S9:
762    return ARM::S8;
763  case ARM::S11:
764    return ARM::S10;
765  case ARM::S13:
766    return ARM::S12;
767  case ARM::S15:
768    return ARM::S14;
769  case ARM::S17:
770    return ARM::S16;
771  case ARM::S19:
772    return ARM::S18;
773  case ARM::S21:
774    return ARM::S20;
775  case ARM::S23:
776    return ARM::S22;
777  case ARM::S25:
778    return ARM::S24;
779  case ARM::S27:
780    return ARM::S26;
781  case ARM::S29:
782    return ARM::S28;
783  case ARM::S31:
784    return ARM::S30;
785
786  case ARM::D1:
787    return ARM::D0;
788  case ARM::D3:
789    return ARM::D2;
790  case ARM::D5:
791    return ARM::D4;
792  case ARM::D7:
793    return ARM::D6;
794  case ARM::D9:
795    return ARM::D8;
796  case ARM::D11:
797    return ARM::D10;
798  case ARM::D13:
799    return ARM::D12;
800  case ARM::D15:
801    return ARM::D14;
802  case ARM::D17:
803    return ARM::D16;
804  case ARM::D19:
805    return ARM::D18;
806  case ARM::D21:
807    return ARM::D20;
808  case ARM::D23:
809    return ARM::D22;
810  case ARM::D25:
811    return ARM::D24;
812  case ARM::D27:
813    return ARM::D26;
814  case ARM::D29:
815    return ARM::D28;
816  case ARM::D31:
817    return ARM::D30;
818  }
819
820  return 0;
821}
822
823unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
824                                             const MachineFunction &MF) const {
825  switch (Reg) {
826  default: break;
827  // Return 0 if either register of the pair is a special register.
828  // So no R12, etc.
829  case ARM::R0:
830    return ARM::R1;
831  case ARM::R2:
832    return ARM::R3;
833  case ARM::R4:
834    return ARM::R5;
835  case ARM::R6:
836    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
837  case ARM::R8:
838    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
839  case ARM::R10:
840    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
841
842  case ARM::S0:
843    return ARM::S1;
844  case ARM::S2:
845    return ARM::S3;
846  case ARM::S4:
847    return ARM::S5;
848  case ARM::S6:
849    return ARM::S7;
850  case ARM::S8:
851    return ARM::S9;
852  case ARM::S10:
853    return ARM::S11;
854  case ARM::S12:
855    return ARM::S13;
856  case ARM::S14:
857    return ARM::S15;
858  case ARM::S16:
859    return ARM::S17;
860  case ARM::S18:
861    return ARM::S19;
862  case ARM::S20:
863    return ARM::S21;
864  case ARM::S22:
865    return ARM::S23;
866  case ARM::S24:
867    return ARM::S25;
868  case ARM::S26:
869    return ARM::S27;
870  case ARM::S28:
871    return ARM::S29;
872  case ARM::S30:
873    return ARM::S31;
874
875  case ARM::D0:
876    return ARM::D1;
877  case ARM::D2:
878    return ARM::D3;
879  case ARM::D4:
880    return ARM::D5;
881  case ARM::D6:
882    return ARM::D7;
883  case ARM::D8:
884    return ARM::D9;
885  case ARM::D10:
886    return ARM::D11;
887  case ARM::D12:
888    return ARM::D13;
889  case ARM::D14:
890    return ARM::D15;
891  case ARM::D16:
892    return ARM::D17;
893  case ARM::D18:
894    return ARM::D19;
895  case ARM::D20:
896    return ARM::D21;
897  case ARM::D22:
898    return ARM::D23;
899  case ARM::D24:
900    return ARM::D25;
901  case ARM::D26:
902    return ARM::D27;
903  case ARM::D28:
904    return ARM::D29;
905  case ARM::D30:
906    return ARM::D31;
907  }
908
909  return 0;
910}
911
912/// emitLoadConstPool - Emits a load from constpool to materialize the
913/// specified immediate.
914void ARMBaseRegisterInfo::
915emitLoadConstPool(MachineBasicBlock &MBB,
916                  MachineBasicBlock::iterator &MBBI,
917                  DebugLoc dl,
918                  unsigned DestReg, unsigned SubIdx, int Val,
919                  ARMCC::CondCodes Pred,
920                  unsigned PredReg) const {
921  MachineFunction &MF = *MBB.getParent();
922  MachineConstantPool *ConstantPool = MF.getConstantPool();
923  Constant *C =
924        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
925  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
926
927  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
928    .addReg(DestReg, getDefRegState(true), SubIdx)
929    .addConstantPoolIndex(Idx)
930    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
931}
932
933bool ARMBaseRegisterInfo::
934requiresRegisterScavenging(const MachineFunction &MF) const {
935  return true;
936}
937bool ARMBaseRegisterInfo::
938requiresFrameIndexScavenging(const MachineFunction &MF) const {
939  return true;
940}
941
942// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
943// not required, we reserve argument space for call sites in the function
944// immediately on entry to the current function. This eliminates the need for
945// add/sub sp brackets around call sites. Returns true if the call frame is
946// included as part of the stack frame.
947bool ARMBaseRegisterInfo::
948hasReservedCallFrame(MachineFunction &MF) const {
949  const MachineFrameInfo *FFI = MF.getFrameInfo();
950  unsigned CFSize = FFI->getMaxCallFrameSize();
951  // It's not always a good idea to include the call frame as part of the
952  // stack frame. ARM (especially Thumb) has small immediate offset to
953  // address the stack frame. So a large call frame can cause poor codegen
954  // and may even makes it impossible to scavenge a register.
955  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
956    return false;
957
958  return !MF.getFrameInfo()->hasVarSizedObjects();
959}
960
961static void
962emitSPUpdate(bool isARM,
963             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
964             DebugLoc dl, const ARMBaseInstrInfo &TII,
965             int NumBytes,
966             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
967  if (isARM)
968    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
969                            Pred, PredReg, TII);
970  else
971    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
972                           Pred, PredReg, TII);
973}
974
975
976void ARMBaseRegisterInfo::
977eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
978                              MachineBasicBlock::iterator I) const {
979  if (!hasReservedCallFrame(MF)) {
980    // If we have alloca, convert as follows:
981    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
982    // ADJCALLSTACKUP   -> add, sp, sp, amount
983    MachineInstr *Old = I;
984    DebugLoc dl = Old->getDebugLoc();
985    unsigned Amount = Old->getOperand(0).getImm();
986    if (Amount != 0) {
987      // We need to keep the stack aligned properly.  To do this, we round the
988      // amount of space needed for the outgoing arguments up to the next
989      // alignment boundary.
990      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
991      Amount = (Amount+Align-1)/Align*Align;
992
993      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
994      assert(!AFI->isThumb1OnlyFunction() &&
995             "This eliminateCallFramePseudoInstr does not suppor Thumb1!");
996      bool isARM = !AFI->isThumbFunction();
997
998      // Replace the pseudo instruction with a new instruction...
999      unsigned Opc = Old->getOpcode();
1000      ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
1001      // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN?
1002      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1003        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1004        unsigned PredReg = Old->getOperand(2).getReg();
1005        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1006      } else {
1007        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1008        unsigned PredReg = Old->getOperand(3).getReg();
1009        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1010        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1011      }
1012    }
1013  }
1014  MBB.erase(I);
1015}
1016
1017unsigned
1018ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1019                                         int SPAdj, int *Value,
1020                                         RegScavenger *RS) const {
1021  unsigned i = 0;
1022  MachineInstr &MI = *II;
1023  MachineBasicBlock &MBB = *MI.getParent();
1024  MachineFunction &MF = *MBB.getParent();
1025  const MachineFrameInfo *MFI = MF.getFrameInfo();
1026  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1027  assert(!AFI->isThumb1OnlyFunction() &&
1028         "This eliminateFrameIndex does not support Thumb1!");
1029
1030  while (!MI.getOperand(i).isFI()) {
1031    ++i;
1032    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1033  }
1034
1035  unsigned FrameReg = ARM::SP;
1036  int FrameIndex = MI.getOperand(i).getIndex();
1037  int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj;
1038
1039  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1040    Offset -= AFI->getGPRCalleeSavedArea1Offset();
1041  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1042    Offset -= AFI->getGPRCalleeSavedArea2Offset();
1043  else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1044    Offset -= AFI->getDPRCalleeSavedAreaOffset();
1045  else if (hasFP(MF) && AFI->hasStackFrame()) {
1046    assert(SPAdj == 0 && "Unexpected stack offset!");
1047    // Use frame pointer to reference fixed objects unless this is a
1048    // frameless function,
1049    FrameReg = getFrameRegister(MF);
1050    Offset -= AFI->getFramePtrSpillOffset();
1051  }
1052
1053  // modify MI as necessary to handle as much of 'Offset' as possible
1054  bool Done = false;
1055  if (!AFI->isThumbFunction())
1056    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1057  else {
1058    assert(AFI->isThumb2Function());
1059    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1060  }
1061  if (Done)
1062    return 0;
1063
1064  // If we get here, the immediate doesn't fit into the instruction.  We folded
1065  // as much as possible above, handle the rest, providing a register that is
1066  // SP+LargeImm.
1067  assert((Offset ||
1068          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) &&
1069         "This code isn't needed if offset already handled!");
1070
1071  unsigned ScratchReg = 0;
1072  int PIdx = MI.findFirstPredOperandIdx();
1073  ARMCC::CondCodes Pred = (PIdx == -1)
1074    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1075  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1076  if (Offset == 0)
1077    // Must be addrmode4.
1078    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1079  else {
1080    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1081    *Value = Offset;
1082    if (!AFI->isThumbFunction())
1083      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1084                              Offset, Pred, PredReg, TII);
1085    else {
1086      assert(AFI->isThumb2Function());
1087      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1088                             Offset, Pred, PredReg, TII);
1089    }
1090    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1091  }
1092  return ScratchReg;
1093}
1094
1095/// Move iterator pass the next bunch of callee save load / store ops for
1096/// the particular spill area (1: integer area 1, 2: integer area 2,
1097/// 3: fp area, 0: don't care).
1098static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1099                                   MachineBasicBlock::iterator &MBBI,
1100                                   int Opc1, int Opc2, unsigned Area,
1101                                   const ARMSubtarget &STI) {
1102  while (MBBI != MBB.end() &&
1103         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1104         MBBI->getOperand(1).isFI()) {
1105    if (Area != 0) {
1106      bool Done = false;
1107      unsigned Category = 0;
1108      switch (MBBI->getOperand(0).getReg()) {
1109      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1110      case ARM::LR:
1111        Category = 1;
1112        break;
1113      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1114        Category = STI.isTargetDarwin() ? 2 : 1;
1115        break;
1116      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1117      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1118        Category = 3;
1119        break;
1120      default:
1121        Done = true;
1122        break;
1123      }
1124      if (Done || Category != Area)
1125        break;
1126    }
1127
1128    ++MBBI;
1129  }
1130}
1131
1132void ARMBaseRegisterInfo::
1133emitPrologue(MachineFunction &MF) const {
1134  MachineBasicBlock &MBB = MF.front();
1135  MachineBasicBlock::iterator MBBI = MBB.begin();
1136  MachineFrameInfo  *MFI = MF.getFrameInfo();
1137  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1138  assert(!AFI->isThumb1OnlyFunction() &&
1139         "This emitPrologue does not suppor Thumb1!");
1140  bool isARM = !AFI->isThumbFunction();
1141  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1142  unsigned NumBytes = MFI->getStackSize();
1143  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1144  DebugLoc dl = (MBBI != MBB.end() ?
1145                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1146
1147  // Determine the sizes of each callee-save spill areas and record which frame
1148  // belongs to which callee-save spill areas.
1149  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1150  int FramePtrSpillFI = 0;
1151
1152  // Allocate the vararg register save area. This is not counted in NumBytes.
1153  if (VARegSaveSize)
1154    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1155
1156  if (!AFI->hasStackFrame()) {
1157    if (NumBytes != 0)
1158      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1159    return;
1160  }
1161
1162  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1163    unsigned Reg = CSI[i].getReg();
1164    int FI = CSI[i].getFrameIdx();
1165    switch (Reg) {
1166    case ARM::R4:
1167    case ARM::R5:
1168    case ARM::R6:
1169    case ARM::R7:
1170    case ARM::LR:
1171      if (Reg == FramePtr)
1172        FramePtrSpillFI = FI;
1173      AFI->addGPRCalleeSavedArea1Frame(FI);
1174      GPRCS1Size += 4;
1175      break;
1176    case ARM::R8:
1177    case ARM::R9:
1178    case ARM::R10:
1179    case ARM::R11:
1180      if (Reg == FramePtr)
1181        FramePtrSpillFI = FI;
1182      if (STI.isTargetDarwin()) {
1183        AFI->addGPRCalleeSavedArea2Frame(FI);
1184        GPRCS2Size += 4;
1185      } else {
1186        AFI->addGPRCalleeSavedArea1Frame(FI);
1187        GPRCS1Size += 4;
1188      }
1189      break;
1190    default:
1191      AFI->addDPRCalleeSavedAreaFrame(FI);
1192      DPRCSSize += 8;
1193    }
1194  }
1195
1196  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1197  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1198  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1199
1200  // Set FP to point to the stack slot that contains the previous FP.
1201  // For Darwin, FP is R7, which has now been stored in spill area 1.
1202  // Otherwise, if this is not Darwin, all the callee-saved registers go
1203  // into spill area 1, including the FP in R11.  In either case, it is
1204  // now safe to emit this assignment.
1205  if (STI.isTargetDarwin() || hasFP(MF)) {
1206    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1207    MachineInstrBuilder MIB =
1208      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1209      .addFrameIndex(FramePtrSpillFI).addImm(0);
1210    AddDefaultCC(AddDefaultPred(MIB));
1211  }
1212
1213  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1214  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1215
1216  // Build the new SUBri to adjust SP for FP callee-save spill area.
1217  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1218  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1219
1220  // Determine starting offsets of spill areas.
1221  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1222  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1223  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1224  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1225  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1226  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1227  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1228
1229  NumBytes = DPRCSOffset;
1230  if (NumBytes) {
1231    // Insert it after all the callee-save spills.
1232    movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI);
1233    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1234  }
1235
1236  if (STI.isTargetELF() && hasFP(MF)) {
1237    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1238                             AFI->getFramePtrSpillOffset());
1239  }
1240
1241  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1242  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1243  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1244}
1245
1246static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1247  for (unsigned i = 0; CSRegs[i]; ++i)
1248    if (Reg == CSRegs[i])
1249      return true;
1250  return false;
1251}
1252
1253static bool isCSRestore(MachineInstr *MI,
1254                        const ARMBaseInstrInfo &TII,
1255                        const unsigned *CSRegs) {
1256  return ((MI->getOpcode() == (int)ARM::FLDD ||
1257           MI->getOpcode() == (int)ARM::LDR ||
1258           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1259          MI->getOperand(1).isFI() &&
1260          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1261}
1262
1263void ARMBaseRegisterInfo::
1264emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1265  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1266  assert(MBBI->getDesc().isReturn() &&
1267         "Can only insert epilog into returning blocks");
1268  DebugLoc dl = MBBI->getDebugLoc();
1269  MachineFrameInfo *MFI = MF.getFrameInfo();
1270  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1271  assert(!AFI->isThumb1OnlyFunction() &&
1272         "This emitEpilogue does not suppor Thumb1!");
1273  bool isARM = !AFI->isThumbFunction();
1274
1275  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1276  int NumBytes = (int)MFI->getStackSize();
1277
1278  if (!AFI->hasStackFrame()) {
1279    if (NumBytes != 0)
1280      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1281  } else {
1282    // Unwind MBBI to point to first LDR / FLDD.
1283    const unsigned *CSRegs = getCalleeSavedRegs();
1284    if (MBBI != MBB.begin()) {
1285      do
1286        --MBBI;
1287      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1288      if (!isCSRestore(MBBI, TII, CSRegs))
1289        ++MBBI;
1290    }
1291
1292    // Move SP to start of FP callee save spill area.
1293    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1294                 AFI->getGPRCalleeSavedArea2Size() +
1295                 AFI->getDPRCalleeSavedAreaSize());
1296
1297    // Darwin ABI requires FP to point to the stack slot that contains the
1298    // previous FP.
1299    bool HasFP = hasFP(MF);
1300    if ((STI.isTargetDarwin() && NumBytes) || HasFP) {
1301      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1302      // Reset SP based on frame pointer only if the stack frame extends beyond
1303      // frame pointer stack slot or target is ELF and the function has FP.
1304      if (HasFP ||
1305          AFI->getGPRCalleeSavedArea2Size() ||
1306          AFI->getDPRCalleeSavedAreaSize()  ||
1307          AFI->getDPRCalleeSavedAreaOffset()) {
1308        if (NumBytes) {
1309          if (isARM)
1310            emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1311                                    ARMCC::AL, 0, TII);
1312          else
1313            emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1314                                    ARMCC::AL, 0, TII);
1315        } else {
1316          // Thumb2 or ARM.
1317          if (isARM)
1318            BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1319              .addReg(FramePtr)
1320              .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1321          else
1322            BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1323              .addReg(FramePtr);
1324        }
1325      }
1326    } else if (NumBytes)
1327      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1328
1329    // Move SP to start of integer callee save spill area 2.
1330    movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI);
1331    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1332
1333    // Move SP to start of integer callee save spill area 1.
1334    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1335    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1336
1337    // Move SP to SP upon entry to the function.
1338    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1339    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1340  }
1341
1342  if (VARegSaveSize)
1343    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1344}
1345
1346#include "ARMGenRegisterInfo.inc"
1347