ARMBaseRegisterInfo.cpp revision 8295d99bff6f8e3dfdfdaf1871cb72adab423f20
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMAddressingModes.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMBaseRegisterInfo.h" 18#include "ARMInstrInfo.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMSubtarget.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/LLVMContext.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineLocation.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/RegisterScavenging.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetFrameInfo.h" 35#include "llvm/Target/TargetMachine.h" 36#include "llvm/Target/TargetOptions.h" 37#include "llvm/ADT/BitVector.h" 38#include "llvm/ADT/SmallVector.h" 39using namespace llvm; 40 41unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, 42 bool *isSPVFP) { 43 if (isSPVFP) 44 *isSPVFP = false; 45 46 using namespace ARM; 47 switch (RegEnum) { 48 default: 49 llvm_unreachable("Unknown ARM register!"); 50 case R0: case D0: case Q0: return 0; 51 case R1: case D1: case Q1: return 1; 52 case R2: case D2: case Q2: return 2; 53 case R3: case D3: case Q3: return 3; 54 case R4: case D4: case Q4: return 4; 55 case R5: case D5: case Q5: return 5; 56 case R6: case D6: case Q6: return 6; 57 case R7: case D7: case Q7: return 7; 58 case R8: case D8: case Q8: return 8; 59 case R9: case D9: case Q9: return 9; 60 case R10: case D10: case Q10: return 10; 61 case R11: case D11: case Q11: return 11; 62 case R12: case D12: case Q12: return 12; 63 case SP: case D13: case Q13: return 13; 64 case LR: case D14: case Q14: return 14; 65 case PC: case D15: case Q15: return 15; 66 67 case D16: return 16; 68 case D17: return 17; 69 case D18: return 18; 70 case D19: return 19; 71 case D20: return 20; 72 case D21: return 21; 73 case D22: return 22; 74 case D23: return 23; 75 case D24: return 24; 76 case D25: return 25; 77 case D26: return 27; 78 case D27: return 27; 79 case D28: return 28; 80 case D29: return 29; 81 case D30: return 30; 82 case D31: return 31; 83 84 case S0: case S1: case S2: case S3: 85 case S4: case S5: case S6: case S7: 86 case S8: case S9: case S10: case S11: 87 case S12: case S13: case S14: case S15: 88 case S16: case S17: case S18: case S19: 89 case S20: case S21: case S22: case S23: 90 case S24: case S25: case S26: case S27: 91 case S28: case S29: case S30: case S31: { 92 if (isSPVFP) 93 *isSPVFP = true; 94 switch (RegEnum) { 95 default: return 0; // Avoid compile time warning. 96 case S0: return 0; 97 case S1: return 1; 98 case S2: return 2; 99 case S3: return 3; 100 case S4: return 4; 101 case S5: return 5; 102 case S6: return 6; 103 case S7: return 7; 104 case S8: return 8; 105 case S9: return 9; 106 case S10: return 10; 107 case S11: return 11; 108 case S12: return 12; 109 case S13: return 13; 110 case S14: return 14; 111 case S15: return 15; 112 case S16: return 16; 113 case S17: return 17; 114 case S18: return 18; 115 case S19: return 19; 116 case S20: return 20; 117 case S21: return 21; 118 case S22: return 22; 119 case S23: return 23; 120 case S24: return 24; 121 case S25: return 25; 122 case S26: return 26; 123 case S27: return 27; 124 case S28: return 28; 125 case S29: return 29; 126 case S30: return 30; 127 case S31: return 31; 128 } 129 } 130 } 131} 132 133ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 134 const ARMSubtarget &sti) 135 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 136 TII(tii), STI(sti), 137 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 138} 139 140unsigned ARMBaseRegisterInfo:: 141getOpcode(int Op) const { 142 return TII.getOpcode((ARMII::Op)Op); 143} 144 145const unsigned* 146ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 147 static const unsigned CalleeSavedRegs[] = { 148 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 149 ARM::R7, ARM::R6, ARM::R5, ARM::R4, 150 151 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 152 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 153 0 154 }; 155 156 static const unsigned DarwinCalleeSavedRegs[] = { 157 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 158 // register. 159 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 160 ARM::R11, ARM::R10, ARM::R8, 161 162 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 163 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 164 0 165 }; 166 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 167} 168 169const TargetRegisterClass* const * 170ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 171 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 172 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 173 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 174 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 175 176 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 177 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 178 0 179 }; 180 181 static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { 182 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 183 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass, 184 &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass, 185 186 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 187 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 188 0 189 }; 190 191 static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = { 192 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 193 &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, 194 &ARM::GPRRegClass, &ARM::GPRRegClass, 195 196 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 197 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 198 0 199 }; 200 201 static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={ 202 &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass, 203 &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass, 204 &ARM::GPRRegClass, &ARM::GPRRegClass, 205 206 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 207 &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, 208 0 209 }; 210 211 if (STI.isThumb1Only()) { 212 return STI.isTargetDarwin() 213 ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses; 214 } 215 return STI.isTargetDarwin() 216 ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses; 217} 218 219BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 220 // FIXME: avoid re-calculating this everytime. 221 BitVector Reserved(getNumRegs()); 222 Reserved.set(ARM::SP); 223 Reserved.set(ARM::PC); 224 if (STI.isTargetDarwin() || hasFP(MF)) 225 Reserved.set(FramePtr); 226 // Some targets reserve R9. 227 if (STI.isR9Reserved()) 228 Reserved.set(ARM::R9); 229 return Reserved; 230} 231 232bool 233ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { 234 switch (Reg) { 235 default: break; 236 case ARM::SP: 237 case ARM::PC: 238 return true; 239 case ARM::R7: 240 case ARM::R11: 241 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 242 return true; 243 break; 244 case ARM::R9: 245 return STI.isR9Reserved(); 246 } 247 248 return false; 249} 250 251const TargetRegisterClass *ARMBaseRegisterInfo::getPointerRegClass() const { 252 return &ARM::GPRRegClass; 253} 254 255/// getAllocationOrder - Returns the register allocation order for a specified 256/// register class in the form of a pair of TargetRegisterClass iterators. 257std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 258ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, 259 unsigned HintType, unsigned HintReg, 260 const MachineFunction &MF) const { 261 // Alternative register allocation orders when favoring even / odd registers 262 // of register pairs. 263 264 // No FP, R9 is available. 265 static const unsigned GPREven1[] = { 266 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 267 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 268 ARM::R9, ARM::R11 269 }; 270 static const unsigned GPROdd1[] = { 271 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 272 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 273 ARM::R8, ARM::R10 274 }; 275 276 // FP is R7, R9 is available. 277 static const unsigned GPREven2[] = { 278 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 279 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 280 ARM::R9, ARM::R11 281 }; 282 static const unsigned GPROdd2[] = { 283 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 284 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 285 ARM::R8, ARM::R10 286 }; 287 288 // FP is R11, R9 is available. 289 static const unsigned GPREven3[] = { 290 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 291 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 292 ARM::R9 293 }; 294 static const unsigned GPROdd3[] = { 295 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 296 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 297 ARM::R8 298 }; 299 300 // No FP, R9 is not available. 301 static const unsigned GPREven4[] = { 302 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 303 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 304 ARM::R11 305 }; 306 static const unsigned GPROdd4[] = { 307 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 308 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 309 ARM::R10 310 }; 311 312 // FP is R7, R9 is not available. 313 static const unsigned GPREven5[] = { 314 ARM::R0, ARM::R2, ARM::R4, ARM::R10, 315 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 316 ARM::R11 317 }; 318 static const unsigned GPROdd5[] = { 319 ARM::R1, ARM::R3, ARM::R5, ARM::R11, 320 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 321 ARM::R10 322 }; 323 324 // FP is R11, R9 is not available. 325 static const unsigned GPREven6[] = { 326 ARM::R0, ARM::R2, ARM::R4, ARM::R6, 327 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 328 }; 329 static const unsigned GPROdd6[] = { 330 ARM::R1, ARM::R3, ARM::R5, ARM::R7, 331 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 332 }; 333 334 335 if (HintType == ARMRI::RegPairEven) { 336 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 337 // It's no longer possible to fulfill this hint. Return the default 338 // allocation order. 339 return std::make_pair(RC->allocation_order_begin(MF), 340 RC->allocation_order_end(MF)); 341 342 if (!STI.isTargetDarwin() && !hasFP(MF)) { 343 if (!STI.isR9Reserved()) 344 return std::make_pair(GPREven1, 345 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); 346 else 347 return std::make_pair(GPREven4, 348 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); 349 } else if (FramePtr == ARM::R7) { 350 if (!STI.isR9Reserved()) 351 return std::make_pair(GPREven2, 352 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); 353 else 354 return std::make_pair(GPREven5, 355 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); 356 } else { // FramePtr == ARM::R11 357 if (!STI.isR9Reserved()) 358 return std::make_pair(GPREven3, 359 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); 360 else 361 return std::make_pair(GPREven6, 362 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); 363 } 364 } else if (HintType == ARMRI::RegPairOdd) { 365 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 366 // It's no longer possible to fulfill this hint. Return the default 367 // allocation order. 368 return std::make_pair(RC->allocation_order_begin(MF), 369 RC->allocation_order_end(MF)); 370 371 if (!STI.isTargetDarwin() && !hasFP(MF)) { 372 if (!STI.isR9Reserved()) 373 return std::make_pair(GPROdd1, 374 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); 375 else 376 return std::make_pair(GPROdd4, 377 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); 378 } else if (FramePtr == ARM::R7) { 379 if (!STI.isR9Reserved()) 380 return std::make_pair(GPROdd2, 381 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); 382 else 383 return std::make_pair(GPROdd5, 384 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); 385 } else { // FramePtr == ARM::R11 386 if (!STI.isR9Reserved()) 387 return std::make_pair(GPROdd3, 388 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); 389 else 390 return std::make_pair(GPROdd6, 391 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); 392 } 393 } 394 return std::make_pair(RC->allocation_order_begin(MF), 395 RC->allocation_order_end(MF)); 396} 397 398/// ResolveRegAllocHint - Resolves the specified register allocation hint 399/// to a physical register. Returns the physical register if it is successful. 400unsigned 401ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 402 const MachineFunction &MF) const { 403 if (Reg == 0 || !isPhysicalRegister(Reg)) 404 return 0; 405 if (Type == 0) 406 return Reg; 407 else if (Type == (unsigned)ARMRI::RegPairOdd) 408 // Odd register. 409 return getRegisterPairOdd(Reg, MF); 410 else if (Type == (unsigned)ARMRI::RegPairEven) 411 // Even register. 412 return getRegisterPairEven(Reg, MF); 413 return 0; 414} 415 416void 417ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 418 MachineFunction &MF) const { 419 MachineRegisterInfo *MRI = &MF.getRegInfo(); 420 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 421 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 422 Hint.first == (unsigned)ARMRI::RegPairEven) && 423 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { 424 // If 'Reg' is one of the even / odd register pair and it's now changed 425 // (e.g. coalesced) into a different register. The other register of the 426 // pair allocation hint must be updated to reflect the relationship 427 // change. 428 unsigned OtherReg = Hint.second; 429 Hint = MRI->getRegAllocationHint(OtherReg); 430 if (Hint.second == Reg) 431 // Make sure the pair has not already divorced. 432 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 433 } 434} 435 436/// hasFP - Return true if the specified function should have a dedicated frame 437/// pointer register. This is true if the function has variable sized allocas 438/// or if frame pointer elimination is disabled. 439/// 440bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { 441 const MachineFrameInfo *MFI = MF.getFrameInfo(); 442 return (NoFramePointerElim || 443 MFI->hasVarSizedObjects() || 444 MFI->isFrameAddressTaken()); 445} 446 447static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 448 const MachineFrameInfo *FFI = MF.getFrameInfo(); 449 int Offset = 0; 450 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 451 int FixedOff = -FFI->getObjectOffset(i); 452 if (FixedOff > Offset) Offset = FixedOff; 453 } 454 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 455 if (FFI->isDeadObjectIndex(i)) 456 continue; 457 Offset += FFI->getObjectSize(i); 458 unsigned Align = FFI->getObjectAlignment(i); 459 // Adjust to alignment boundary 460 Offset = (Offset+Align-1)/Align*Align; 461 } 462 return (unsigned)Offset; 463} 464 465void 466ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 467 RegScavenger *RS) const { 468 // This tells PEI to spill the FP as if it is any other callee-save register 469 // to take advantage the eliminateFrameIndex machinery. This also ensures it 470 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 471 // to combine multiple loads / stores. 472 bool CanEliminateFrame = true; 473 bool CS1Spilled = false; 474 bool LRSpilled = false; 475 unsigned NumGPRSpills = 0; 476 SmallVector<unsigned, 4> UnspilledCS1GPRs; 477 SmallVector<unsigned, 4> UnspilledCS2GPRs; 478 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 479 480 // Don't spill FP if the frame can be eliminated. This is determined 481 // by scanning the callee-save registers to see if any is used. 482 const unsigned *CSRegs = getCalleeSavedRegs(); 483 const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 484 for (unsigned i = 0; CSRegs[i]; ++i) { 485 unsigned Reg = CSRegs[i]; 486 bool Spilled = false; 487 if (MF.getRegInfo().isPhysRegUsed(Reg)) { 488 AFI->setCSRegisterIsSpilled(Reg); 489 Spilled = true; 490 CanEliminateFrame = false; 491 } else { 492 // Check alias registers too. 493 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 494 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 495 Spilled = true; 496 CanEliminateFrame = false; 497 } 498 } 499 } 500 501 if (CSRegClasses[i] == &ARM::GPRRegClass) { 502 if (Spilled) { 503 NumGPRSpills++; 504 505 if (!STI.isTargetDarwin()) { 506 if (Reg == ARM::LR) 507 LRSpilled = true; 508 CS1Spilled = true; 509 continue; 510 } 511 512 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 513 switch (Reg) { 514 case ARM::LR: 515 LRSpilled = true; 516 // Fallthrough 517 case ARM::R4: 518 case ARM::R5: 519 case ARM::R6: 520 case ARM::R7: 521 CS1Spilled = true; 522 break; 523 default: 524 break; 525 } 526 } else { 527 if (!STI.isTargetDarwin()) { 528 UnspilledCS1GPRs.push_back(Reg); 529 continue; 530 } 531 532 switch (Reg) { 533 case ARM::R4: 534 case ARM::R5: 535 case ARM::R6: 536 case ARM::R7: 537 case ARM::LR: 538 UnspilledCS1GPRs.push_back(Reg); 539 break; 540 default: 541 UnspilledCS2GPRs.push_back(Reg); 542 break; 543 } 544 } 545 } 546 } 547 548 bool ForceLRSpill = false; 549 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 550 unsigned FnSize = TII.GetFunctionSizeInBytes(MF); 551 // Force LR to be spilled if the Thumb function size is > 2048. This enables 552 // use of BL to implement far jump. If it turns out that it's not needed 553 // then the branch fix up path will undo it. 554 if (FnSize >= (1 << 11)) { 555 CanEliminateFrame = false; 556 ForceLRSpill = true; 557 } 558 } 559 560 bool ExtraCSSpill = false; 561 if (!CanEliminateFrame || hasFP(MF)) { 562 AFI->setHasStackFrame(true); 563 564 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 565 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 566 if (!LRSpilled && CS1Spilled) { 567 MF.getRegInfo().setPhysRegUsed(ARM::LR); 568 AFI->setCSRegisterIsSpilled(ARM::LR); 569 NumGPRSpills++; 570 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 571 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 572 ForceLRSpill = false; 573 ExtraCSSpill = true; 574 } 575 576 // Darwin ABI requires FP to point to the stack slot that contains the 577 // previous FP. 578 if (STI.isTargetDarwin() || hasFP(MF)) { 579 MF.getRegInfo().setPhysRegUsed(FramePtr); 580 NumGPRSpills++; 581 } 582 583 // If stack and double are 8-byte aligned and we are spilling an odd number 584 // of GPRs. Spill one extra callee save GPR so we won't have to pad between 585 // the integer and double callee save areas. 586 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 587 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 588 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 589 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 590 unsigned Reg = UnspilledCS1GPRs[i]; 591 // Don't spill high register if the function is thumb1 592 if (!AFI->isThumb1OnlyFunction() || 593 isARMLowRegister(Reg) || Reg == ARM::LR) { 594 MF.getRegInfo().setPhysRegUsed(Reg); 595 AFI->setCSRegisterIsSpilled(Reg); 596 if (!isReservedReg(MF, Reg)) 597 ExtraCSSpill = true; 598 break; 599 } 600 } 601 } else if (!UnspilledCS2GPRs.empty() && 602 !AFI->isThumb1OnlyFunction()) { 603 unsigned Reg = UnspilledCS2GPRs.front(); 604 MF.getRegInfo().setPhysRegUsed(Reg); 605 AFI->setCSRegisterIsSpilled(Reg); 606 if (!isReservedReg(MF, Reg)) 607 ExtraCSSpill = true; 608 } 609 } 610 611 // Estimate if we might need to scavenge a register at some point in order 612 // to materialize a stack offset. If so, either spill one additional 613 // callee-saved register or reserve a special spill slot to facilitate 614 // register scavenging. 615 if (RS && !ExtraCSSpill && !AFI->isThumb1OnlyFunction()) { 616 MachineFrameInfo *MFI = MF.getFrameInfo(); 617 unsigned Size = estimateStackSize(MF, MFI); 618 unsigned Limit = (1 << 12) - 1; 619 for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) 620 for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) { 621 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) 622 if (I->getOperand(i).isFI()) { 623 unsigned Opcode = I->getOpcode(); 624 const TargetInstrDesc &Desc = TII.get(Opcode); 625 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 626 if (AddrMode == ARMII::AddrMode3) { 627 Limit = (1 << 8) - 1; 628 goto DoneEstimating; 629 } else if (AddrMode == ARMII::AddrMode5) { 630 unsigned ThisLimit = ((1 << 8) - 1) * 4; 631 if (ThisLimit < Limit) 632 Limit = ThisLimit; 633 } 634 } 635 } 636 DoneEstimating: 637 if (Size >= Limit) { 638 // If any non-reserved CS register isn't spilled, just spill one or two 639 // extra. That should take care of it! 640 unsigned NumExtras = TargetAlign / 4; 641 SmallVector<unsigned, 2> Extras; 642 while (NumExtras && !UnspilledCS1GPRs.empty()) { 643 unsigned Reg = UnspilledCS1GPRs.back(); 644 UnspilledCS1GPRs.pop_back(); 645 if (!isReservedReg(MF, Reg)) { 646 Extras.push_back(Reg); 647 NumExtras--; 648 } 649 } 650 while (NumExtras && !UnspilledCS2GPRs.empty()) { 651 unsigned Reg = UnspilledCS2GPRs.back(); 652 UnspilledCS2GPRs.pop_back(); 653 if (!isReservedReg(MF, Reg)) { 654 Extras.push_back(Reg); 655 NumExtras--; 656 } 657 } 658 if (Extras.size() && NumExtras == 0) { 659 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 660 MF.getRegInfo().setPhysRegUsed(Extras[i]); 661 AFI->setCSRegisterIsSpilled(Extras[i]); 662 } 663 } else { 664 // Reserve a slot closest to SP or frame pointer. 665 const TargetRegisterClass *RC = &ARM::GPRRegClass; 666 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 667 RC->getAlignment())); 668 } 669 } 670 } 671 } 672 673 if (ForceLRSpill) { 674 MF.getRegInfo().setPhysRegUsed(ARM::LR); 675 AFI->setCSRegisterIsSpilled(ARM::LR); 676 AFI->setLRIsSpilledForFarJump(true); 677 } 678} 679 680unsigned ARMBaseRegisterInfo::getRARegister() const { 681 return ARM::LR; 682} 683 684unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const { 685 if (STI.isTargetDarwin() || hasFP(MF)) 686 return FramePtr; 687 return ARM::SP; 688} 689 690unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 691 llvm_unreachable("What is the exception register"); 692 return 0; 693} 694 695unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 696 llvm_unreachable("What is the exception handler register"); 697 return 0; 698} 699 700int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 701 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 702} 703 704unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 705 const MachineFunction &MF) const { 706 switch (Reg) { 707 default: break; 708 // Return 0 if either register of the pair is a special register. 709 // So no R12, etc. 710 case ARM::R1: 711 return ARM::R0; 712 case ARM::R3: 713 // FIXME! 714 return STI.isThumb1Only() ? 0 : ARM::R2; 715 case ARM::R5: 716 return ARM::R4; 717 case ARM::R7: 718 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; 719 case ARM::R9: 720 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 721 case ARM::R11: 722 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 723 724 case ARM::S1: 725 return ARM::S0; 726 case ARM::S3: 727 return ARM::S2; 728 case ARM::S5: 729 return ARM::S4; 730 case ARM::S7: 731 return ARM::S6; 732 case ARM::S9: 733 return ARM::S8; 734 case ARM::S11: 735 return ARM::S10; 736 case ARM::S13: 737 return ARM::S12; 738 case ARM::S15: 739 return ARM::S14; 740 case ARM::S17: 741 return ARM::S16; 742 case ARM::S19: 743 return ARM::S18; 744 case ARM::S21: 745 return ARM::S20; 746 case ARM::S23: 747 return ARM::S22; 748 case ARM::S25: 749 return ARM::S24; 750 case ARM::S27: 751 return ARM::S26; 752 case ARM::S29: 753 return ARM::S28; 754 case ARM::S31: 755 return ARM::S30; 756 757 case ARM::D1: 758 return ARM::D0; 759 case ARM::D3: 760 return ARM::D2; 761 case ARM::D5: 762 return ARM::D4; 763 case ARM::D7: 764 return ARM::D6; 765 case ARM::D9: 766 return ARM::D8; 767 case ARM::D11: 768 return ARM::D10; 769 case ARM::D13: 770 return ARM::D12; 771 case ARM::D15: 772 return ARM::D14; 773 case ARM::D17: 774 return ARM::D16; 775 case ARM::D19: 776 return ARM::D18; 777 case ARM::D21: 778 return ARM::D20; 779 case ARM::D23: 780 return ARM::D22; 781 case ARM::D25: 782 return ARM::D24; 783 case ARM::D27: 784 return ARM::D26; 785 case ARM::D29: 786 return ARM::D28; 787 case ARM::D31: 788 return ARM::D30; 789 } 790 791 return 0; 792} 793 794unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 795 const MachineFunction &MF) const { 796 switch (Reg) { 797 default: break; 798 // Return 0 if either register of the pair is a special register. 799 // So no R12, etc. 800 case ARM::R0: 801 return ARM::R1; 802 case ARM::R2: 803 // FIXME! 804 return STI.isThumb1Only() ? 0 : ARM::R3; 805 case ARM::R4: 806 return ARM::R5; 807 case ARM::R6: 808 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; 809 case ARM::R8: 810 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 811 case ARM::R10: 812 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 813 814 case ARM::S0: 815 return ARM::S1; 816 case ARM::S2: 817 return ARM::S3; 818 case ARM::S4: 819 return ARM::S5; 820 case ARM::S6: 821 return ARM::S7; 822 case ARM::S8: 823 return ARM::S9; 824 case ARM::S10: 825 return ARM::S11; 826 case ARM::S12: 827 return ARM::S13; 828 case ARM::S14: 829 return ARM::S15; 830 case ARM::S16: 831 return ARM::S17; 832 case ARM::S18: 833 return ARM::S19; 834 case ARM::S20: 835 return ARM::S21; 836 case ARM::S22: 837 return ARM::S23; 838 case ARM::S24: 839 return ARM::S25; 840 case ARM::S26: 841 return ARM::S27; 842 case ARM::S28: 843 return ARM::S29; 844 case ARM::S30: 845 return ARM::S31; 846 847 case ARM::D0: 848 return ARM::D1; 849 case ARM::D2: 850 return ARM::D3; 851 case ARM::D4: 852 return ARM::D5; 853 case ARM::D6: 854 return ARM::D7; 855 case ARM::D8: 856 return ARM::D9; 857 case ARM::D10: 858 return ARM::D11; 859 case ARM::D12: 860 return ARM::D13; 861 case ARM::D14: 862 return ARM::D15; 863 case ARM::D16: 864 return ARM::D17; 865 case ARM::D18: 866 return ARM::D19; 867 case ARM::D20: 868 return ARM::D21; 869 case ARM::D22: 870 return ARM::D23; 871 case ARM::D24: 872 return ARM::D25; 873 case ARM::D26: 874 return ARM::D27; 875 case ARM::D28: 876 return ARM::D29; 877 case ARM::D30: 878 return ARM::D31; 879 } 880 881 return 0; 882} 883 884// FIXME: Dup in ARMBaseInstrInfo.cpp 885static inline 886const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 887 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 888} 889 890static inline 891const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 892 return MIB.addReg(0); 893} 894 895/// emitLoadConstPool - Emits a load from constpool to materialize the 896/// specified immediate. 897void ARMBaseRegisterInfo:: 898emitLoadConstPool(MachineBasicBlock &MBB, 899 MachineBasicBlock::iterator &MBBI, 900 DebugLoc dl, 901 unsigned DestReg, unsigned SubIdx, int Val, 902 ARMCC::CondCodes Pred, 903 unsigned PredReg) const { 904 MachineFunction &MF = *MBB.getParent(); 905 MachineConstantPool *ConstantPool = MF.getConstantPool(); 906 Constant *C = 907 MF.getFunction()->getContext().getConstantInt(Type::Int32Ty, Val); 908 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 909 910 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 911 .addReg(DestReg, getDefRegState(true), SubIdx) 912 .addConstantPoolIndex(Idx) 913 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 914} 915 916bool ARMBaseRegisterInfo:: 917requiresRegisterScavenging(const MachineFunction &MF) const { 918 return true; 919} 920 921// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 922// not required, we reserve argument space for call sites in the function 923// immediately on entry to the current function. This eliminates the need for 924// add/sub sp brackets around call sites. Returns true if the call frame is 925// included as part of the stack frame. 926bool ARMBaseRegisterInfo:: 927hasReservedCallFrame(MachineFunction &MF) const { 928 const MachineFrameInfo *FFI = MF.getFrameInfo(); 929 unsigned CFSize = FFI->getMaxCallFrameSize(); 930 // It's not always a good idea to include the call frame as part of the 931 // stack frame. ARM (especially Thumb) has small immediate offset to 932 // address the stack frame. So a large call frame can cause poor codegen 933 // and may even makes it impossible to scavenge a register. 934 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 935 return false; 936 937 return !MF.getFrameInfo()->hasVarSizedObjects(); 938} 939 940/// emitARMRegPlusImmediate - Emits a series of instructions to materialize 941/// a destreg = basereg + immediate in ARM code. 942static 943void emitARMRegPlusImmediate(MachineBasicBlock &MBB, 944 MachineBasicBlock::iterator &MBBI, 945 unsigned DestReg, unsigned BaseReg, int NumBytes, 946 ARMCC::CondCodes Pred, unsigned PredReg, 947 const ARMBaseInstrInfo &TII, 948 DebugLoc dl) { 949 bool isSub = NumBytes < 0; 950 if (isSub) NumBytes = -NumBytes; 951 952 while (NumBytes) { 953 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); 954 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); 955 assert(ThisVal && "Didn't extract field correctly"); 956 957 // We will handle these bits from offset, clear them. 958 NumBytes &= ~ThisVal; 959 960 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); 961 962 // Build the new ADD / SUB. 963 BuildMI(MBB, MBBI, dl, TII.get(TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri)), DestReg) 964 .addReg(BaseReg, RegState::Kill).addImm(ThisVal) 965 .addImm((unsigned)Pred).addReg(PredReg).addReg(0); 966 BaseReg = DestReg; 967 } 968} 969 970static void 971emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 972 const ARMBaseInstrInfo &TII, DebugLoc dl, 973 int NumBytes, 974 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 975 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, 976 Pred, PredReg, TII, dl); 977} 978 979void ARMBaseRegisterInfo:: 980eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 981 MachineBasicBlock::iterator I) const { 982 if (!hasReservedCallFrame(MF)) { 983 // If we have alloca, convert as follows: 984 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 985 // ADJCALLSTACKUP -> add, sp, sp, amount 986 MachineInstr *Old = I; 987 DebugLoc dl = Old->getDebugLoc(); 988 unsigned Amount = Old->getOperand(0).getImm(); 989 if (Amount != 0) { 990 // We need to keep the stack aligned properly. To do this, we round the 991 // amount of space needed for the outgoing arguments up to the next 992 // alignment boundary. 993 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 994 Amount = (Amount+Align-1)/Align*Align; 995 996 // Replace the pseudo instruction with a new instruction... 997 unsigned Opc = Old->getOpcode(); 998 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm(); 999 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 1000 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1001 unsigned PredReg = Old->getOperand(2).getReg(); 1002 emitSPUpdate(MBB, I, TII, dl, -Amount, Pred, PredReg); 1003 } else { 1004 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1005 unsigned PredReg = Old->getOperand(3).getReg(); 1006 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 1007 emitSPUpdate(MBB, I, TII, dl, Amount, Pred, PredReg); 1008 } 1009 } 1010 } 1011 MBB.erase(I); 1012} 1013 1014/// findScratchRegister - Find a 'free' ARM register. If register scavenger 1015/// is not being used, R12 is available. Otherwise, try for a call-clobbered 1016/// register first and then a spilled callee-saved register if that fails. 1017static 1018unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 1019 ARMFunctionInfo *AFI) { 1020 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12; 1021 assert (!AFI->isThumb1OnlyFunction()); 1022 if (Reg == 0) 1023 // Try a already spilled CS register. 1024 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters()); 1025 1026 return Reg; 1027} 1028 1029void ARMBaseRegisterInfo:: 1030eliminateFrameIndex(MachineBasicBlock::iterator II, 1031 int SPAdj, RegScavenger *RS) const{ 1032 unsigned i = 0; 1033 MachineInstr &MI = *II; 1034 MachineBasicBlock &MBB = *MI.getParent(); 1035 MachineFunction &MF = *MBB.getParent(); 1036 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1037 DebugLoc dl = MI.getDebugLoc(); 1038 1039 while (!MI.getOperand(i).isFI()) { 1040 ++i; 1041 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 1042 } 1043 1044 unsigned FrameReg = ARM::SP; 1045 int FrameIndex = MI.getOperand(i).getIndex(); 1046 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + 1047 MF.getFrameInfo()->getStackSize() + SPAdj; 1048 1049 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 1050 Offset -= AFI->getGPRCalleeSavedArea1Offset(); 1051 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 1052 Offset -= AFI->getGPRCalleeSavedArea2Offset(); 1053 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 1054 Offset -= AFI->getDPRCalleeSavedAreaOffset(); 1055 else if (hasFP(MF)) { 1056 assert(SPAdj == 0 && "Unexpected"); 1057 // There is alloca()'s in this function, must reference off the frame 1058 // pointer instead. 1059 FrameReg = getFrameRegister(MF); 1060 Offset -= AFI->getFramePtrSpillOffset(); 1061 } 1062 1063 unsigned Opcode = MI.getOpcode(); 1064 const TargetInstrDesc &Desc = MI.getDesc(); 1065 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 1066 bool isSub = false; 1067 1068 // Memory operands in inline assembly always use AddrMode2. 1069 if (Opcode == ARM::INLINEASM) 1070 AddrMode = ARMII::AddrMode2; 1071 1072 if (Opcode == getOpcode(ARMII::ADDri)) { 1073 Offset += MI.getOperand(i+1).getImm(); 1074 if (Offset == 0) { 1075 // Turn it into a move. 1076 MI.setDesc(TII.get(getOpcode(ARMII::MOVr))); 1077 MI.getOperand(i).ChangeToRegister(FrameReg, false); 1078 MI.RemoveOperand(i+1); 1079 return; 1080 } else if (Offset < 0) { 1081 Offset = -Offset; 1082 isSub = true; 1083 MI.setDesc(TII.get(getOpcode(ARMII::SUBri))); 1084 } 1085 1086 // Common case: small offset, fits into instruction. 1087 if (ARM_AM::getSOImmVal(Offset) != -1) { 1088 // Replace the FrameIndex with sp / fp 1089 MI.getOperand(i).ChangeToRegister(FrameReg, false); 1090 MI.getOperand(i+1).ChangeToImmediate(Offset); 1091 return; 1092 } 1093 1094 // Otherwise, we fallback to common code below to form the imm offset with 1095 // a sequence of ADDri instructions. First though, pull as much of the imm 1096 // into this ADDri as possible. 1097 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); 1098 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); 1099 1100 // We will handle these bits from offset, clear them. 1101 Offset &= ~ThisImmVal; 1102 1103 // Get the properly encoded SOImmVal field. 1104 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && 1105 "Bit extraction didn't work?"); 1106 MI.getOperand(i+1).ChangeToImmediate(ThisImmVal); 1107 } else { 1108 unsigned ImmIdx = 0; 1109 int InstrOffs = 0; 1110 unsigned NumBits = 0; 1111 unsigned Scale = 1; 1112 switch (AddrMode) { 1113 case ARMII::AddrMode2: { 1114 ImmIdx = i+2; 1115 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); 1116 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1117 InstrOffs *= -1; 1118 NumBits = 12; 1119 break; 1120 } 1121 case ARMII::AddrMode3: { 1122 ImmIdx = i+2; 1123 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); 1124 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1125 InstrOffs *= -1; 1126 NumBits = 8; 1127 break; 1128 } 1129 case ARMII::AddrMode5: { 1130 ImmIdx = i+1; 1131 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); 1132 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) 1133 InstrOffs *= -1; 1134 NumBits = 8; 1135 Scale = 4; 1136 break; 1137 } 1138 case ARMII::AddrModeT2_i12: { 1139 ImmIdx = i+1; 1140 InstrOffs = MI.getOperand(ImmIdx).getImm(); 1141 NumBits = 12; 1142 break; 1143 } 1144 case ARMII::AddrModeT2_i8: { 1145 ImmIdx = i+1; 1146 InstrOffs = MI.getOperand(ImmIdx).getImm(); 1147 NumBits = 8; 1148 break; 1149 } 1150 case ARMII::AddrModeT2_so: { 1151 ImmIdx = i+2; 1152 InstrOffs = MI.getOperand(ImmIdx).getImm(); 1153 break; 1154 } 1155 default: 1156 llvm_unreachable("Unsupported addressing mode!"); 1157 break; 1158 } 1159 1160 Offset += InstrOffs * Scale; 1161 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 1162 if (Offset < 0) { 1163 Offset = -Offset; 1164 isSub = true; 1165 } 1166 1167 // Common case: small offset, fits into instruction. 1168 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 1169 int ImmedOffset = Offset / Scale; 1170 unsigned Mask = (1 << NumBits) - 1; 1171 if ((unsigned)Offset <= Mask * Scale) { 1172 // Replace the FrameIndex with sp 1173 MI.getOperand(i).ChangeToRegister(FrameReg, false); 1174 if (isSub) 1175 ImmedOffset |= 1 << NumBits; 1176 ImmOp.ChangeToImmediate(ImmedOffset); 1177 return; 1178 } 1179 1180 // Otherwise, it didn't fit. Pull in what we can to simplify the immed. 1181 ImmedOffset = ImmedOffset & Mask; 1182 if (isSub) 1183 ImmedOffset |= 1 << NumBits; 1184 ImmOp.ChangeToImmediate(ImmedOffset); 1185 Offset &= ~(Mask*Scale); 1186 } 1187 1188 // If we get here, the immediate doesn't fit into the instruction. We folded 1189 // as much as possible above, handle the rest, providing a register that is 1190 // SP+LargeImm. 1191 assert(Offset && "This code isn't needed if offset already handled!"); 1192 1193 // Insert a set of r12 with the full address: r12 = sp + offset 1194 // If the offset we have is too large to fit into the instruction, we need 1195 // to form it with a series of ADDri's. Do this by taking 8-bit chunks 1196 // out of 'Offset'. 1197 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); 1198 if (ScratchReg == 0) 1199 // No register is "free". Scavenge a register. 1200 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); 1201 int PIdx = MI.findFirstPredOperandIdx(); 1202 ARMCC::CondCodes Pred = (PIdx == -1) 1203 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1204 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1205 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, 1206 isSub ? -Offset : Offset, Pred, PredReg, TII, dl); 1207 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1208} 1209 1210/// Move iterator pass the next bunch of callee save load / store ops for 1211/// the particular spill area (1: integer area 1, 2: integer area 2, 1212/// 3: fp area, 0: don't care). 1213static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1214 MachineBasicBlock::iterator &MBBI, 1215 int Opc, unsigned Area, 1216 const ARMSubtarget &STI) { 1217 while (MBBI != MBB.end() && 1218 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) { 1219 if (Area != 0) { 1220 bool Done = false; 1221 unsigned Category = 0; 1222 switch (MBBI->getOperand(0).getReg()) { 1223 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1224 case ARM::LR: 1225 Category = 1; 1226 break; 1227 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1228 Category = STI.isTargetDarwin() ? 2 : 1; 1229 break; 1230 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1231 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1232 Category = 3; 1233 break; 1234 default: 1235 Done = true; 1236 break; 1237 } 1238 if (Done || Category != Area) 1239 break; 1240 } 1241 1242 ++MBBI; 1243 } 1244} 1245 1246void ARMBaseRegisterInfo:: 1247emitPrologue(MachineFunction &MF) const { 1248 MachineBasicBlock &MBB = MF.front(); 1249 MachineBasicBlock::iterator MBBI = MBB.begin(); 1250 MachineFrameInfo *MFI = MF.getFrameInfo(); 1251 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1252 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1253 unsigned NumBytes = MFI->getStackSize(); 1254 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1255 DebugLoc dl = (MBBI != MBB.end() ? 1256 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); 1257 1258 // Determine the sizes of each callee-save spill areas and record which frame 1259 // belongs to which callee-save spill areas. 1260 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1261 int FramePtrSpillFI = 0; 1262 1263 if (VARegSaveSize) 1264 emitSPUpdate(MBB, MBBI, TII, dl, -VARegSaveSize); 1265 1266 if (!AFI->hasStackFrame()) { 1267 if (NumBytes != 0) 1268 emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes); 1269 return; 1270 } 1271 1272 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1273 unsigned Reg = CSI[i].getReg(); 1274 int FI = CSI[i].getFrameIdx(); 1275 switch (Reg) { 1276 case ARM::R4: 1277 case ARM::R5: 1278 case ARM::R6: 1279 case ARM::R7: 1280 case ARM::LR: 1281 if (Reg == FramePtr) 1282 FramePtrSpillFI = FI; 1283 AFI->addGPRCalleeSavedArea1Frame(FI); 1284 GPRCS1Size += 4; 1285 break; 1286 case ARM::R8: 1287 case ARM::R9: 1288 case ARM::R10: 1289 case ARM::R11: 1290 if (Reg == FramePtr) 1291 FramePtrSpillFI = FI; 1292 if (STI.isTargetDarwin()) { 1293 AFI->addGPRCalleeSavedArea2Frame(FI); 1294 GPRCS2Size += 4; 1295 } else { 1296 AFI->addGPRCalleeSavedArea1Frame(FI); 1297 GPRCS1Size += 4; 1298 } 1299 break; 1300 default: 1301 AFI->addDPRCalleeSavedAreaFrame(FI); 1302 DPRCSSize += 8; 1303 } 1304 } 1305 1306 // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1307 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size); 1308 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 1, STI); 1309 1310 // Darwin ABI requires FP to point to the stack slot that contains the 1311 // previous FP. 1312 if (STI.isTargetDarwin() || hasFP(MF)) { 1313 MachineInstrBuilder MIB = 1314 BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::ADDri)), FramePtr) 1315 .addFrameIndex(FramePtrSpillFI).addImm(0); 1316 AddDefaultCC(AddDefaultPred(MIB)); 1317 } 1318 1319 // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1320 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size); 1321 1322 // Build the new SUBri to adjust SP for FP callee-save spill area. 1323 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 2, STI); 1324 emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize); 1325 1326 // Determine starting offsets of spill areas. 1327 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1328 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1329 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1330 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1331 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1332 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1333 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1334 1335 NumBytes = DPRCSOffset; 1336 if (NumBytes) { 1337 // Insert it after all the callee-save spills. 1338 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FSTD), 3, STI); 1339 emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes); 1340 } 1341 1342 if (STI.isTargetELF() && hasFP(MF)) { 1343 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1344 AFI->getFramePtrSpillOffset()); 1345 } 1346 1347 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1348 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1349 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1350} 1351 1352static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1353 for (unsigned i = 0; CSRegs[i]; ++i) 1354 if (Reg == CSRegs[i]) 1355 return true; 1356 return false; 1357} 1358 1359static bool isCSRestore(MachineInstr *MI, 1360 const ARMBaseInstrInfo &TII, 1361 const unsigned *CSRegs) { 1362 return ((MI->getOpcode() == (int)TII.getOpcode(ARMII::FLDD) || 1363 MI->getOpcode() == (int)TII.getOpcode(ARMII::LDR)) && 1364 MI->getOperand(1).isFI() && 1365 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1366} 1367 1368void ARMBaseRegisterInfo:: 1369emitEpilogue(MachineFunction &MF, 1370 MachineBasicBlock &MBB) const { 1371 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1372 assert(MBBI->getOpcode() == (int)getOpcode(ARMII::BX_RET) && 1373 "Can only insert epilog into returning blocks"); 1374 DebugLoc dl = MBBI->getDebugLoc(); 1375 MachineFrameInfo *MFI = MF.getFrameInfo(); 1376 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1377 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1378 int NumBytes = (int)MFI->getStackSize(); 1379 1380 if (!AFI->hasStackFrame()) { 1381 if (NumBytes != 0) 1382 emitSPUpdate(MBB, MBBI, TII, dl, NumBytes); 1383 } else { 1384 // Unwind MBBI to point to first LDR / FLDD. 1385 const unsigned *CSRegs = getCalleeSavedRegs(); 1386 if (MBBI != MBB.begin()) { 1387 do 1388 --MBBI; 1389 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 1390 if (!isCSRestore(MBBI, TII, CSRegs)) 1391 ++MBBI; 1392 } 1393 1394 // Move SP to start of FP callee save spill area. 1395 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1396 AFI->getGPRCalleeSavedArea2Size() + 1397 AFI->getDPRCalleeSavedAreaSize()); 1398 1399 // Darwin ABI requires FP to point to the stack slot that contains the 1400 // previous FP. 1401 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) { 1402 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1403 // Reset SP based on frame pointer only if the stack frame extends beyond 1404 // frame pointer stack slot or target is ELF and the function has FP. 1405 if (AFI->getGPRCalleeSavedArea2Size() || 1406 AFI->getDPRCalleeSavedAreaSize() || 1407 AFI->getDPRCalleeSavedAreaOffset()|| 1408 hasFP(MF)) { 1409 if (NumBytes) 1410 BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::SUBri)), ARM::SP).addReg(FramePtr) 1411 .addImm(NumBytes) 1412 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1413 else 1414 BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::MOVr)), ARM::SP).addReg(FramePtr) 1415 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1416 } 1417 } else if (NumBytes) { 1418 emitSPUpdate(MBB, MBBI, TII, dl, NumBytes); 1419 } 1420 1421 // Move SP to start of integer callee save spill area 2. 1422 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FLDD), 3, STI); 1423 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize()); 1424 1425 // Move SP to start of integer callee save spill area 1. 1426 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 2, STI); 1427 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size()); 1428 1429 // Move SP to SP upon entry to the function. 1430 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 1, STI); 1431 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size()); 1432 } 1433 1434 if (VARegSaveSize) 1435 emitSPUpdate(MBB, MBBI, TII, dl, VARegSaveSize); 1436 1437} 1438 1439#include "ARMGenRegisterInfo.inc" 1440