ARMBaseRegisterInfo.cpp revision 831737d329a727f53a1fb0572f7b7a8127208881
1//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseRegisterInfo.h" 15#include "ARM.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMFrameLowering.h" 18#include "ARMMachineFunctionInfo.h" 19#include "ARMSubtarget.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/ADT/BitVector.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/RegisterScavenging.h" 29#include "llvm/CodeGen/VirtRegMap.h" 30#include "llvm/Constants.h" 31#include "llvm/DerivedTypes.h" 32#include "llvm/Function.h" 33#include "llvm/LLVMContext.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/Target/TargetFrameLowering.h" 38#include "llvm/Target/TargetMachine.h" 39#include "llvm/Target/TargetOptions.h" 40 41#define GET_REGINFO_TARGET_DESC 42#include "ARMGenRegisterInfo.inc" 43 44using namespace llvm; 45 46ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 47 const ARMSubtarget &sti) 48 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), TII(tii), STI(sti), 49 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 50 BasePtr(ARM::R6) { 51} 52 53const uint16_t* 54ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 55 bool ghcCall = false; 56 57 if (MF) { 58 const Function *F = MF->getFunction(); 59 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); 60 } 61 62 if (ghcCall) { 63 return CSR_GHC_SaveList; 64 } 65 else { 66 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 67 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 68 } 69} 70 71const uint32_t* 72ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 73 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 74 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 75} 76 77const uint32_t* 78ARMBaseRegisterInfo::getNoPreservedMask() const { 79 return CSR_NoRegs_RegMask; 80} 81 82BitVector ARMBaseRegisterInfo:: 83getReservedRegs(const MachineFunction &MF) const { 84 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 85 86 // FIXME: avoid re-calculating this every time. 87 BitVector Reserved(getNumRegs()); 88 Reserved.set(ARM::SP); 89 Reserved.set(ARM::PC); 90 Reserved.set(ARM::FPSCR); 91 if (TFI->hasFP(MF)) 92 Reserved.set(FramePtr); 93 if (hasBasePointer(MF)) 94 Reserved.set(BasePtr); 95 // Some targets reserve R9. 96 if (STI.isR9Reserved()) 97 Reserved.set(ARM::R9); 98 // Reserve D16-D31 if the subtarget doesn't support them. 99 if (!STI.hasVFP3() || STI.hasD16()) { 100 assert(ARM::D31 == ARM::D16 + 15); 101 for (unsigned i = 0; i != 16; ++i) 102 Reserved.set(ARM::D16 + i); 103 } 104 const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 105 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 106 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 107 if (Reserved.test(*SI)) Reserved.set(*I); 108 109 return Reserved; 110} 111 112const TargetRegisterClass* 113ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 114 const { 115 const TargetRegisterClass *Super = RC; 116 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 117 do { 118 switch (Super->getID()) { 119 case ARM::GPRRegClassID: 120 case ARM::SPRRegClassID: 121 case ARM::DPRRegClassID: 122 case ARM::QPRRegClassID: 123 case ARM::QQPRRegClassID: 124 case ARM::QQQQPRRegClassID: 125 case ARM::GPRPairRegClassID: 126 return Super; 127 } 128 Super = *I++; 129 } while (Super); 130 return RC; 131} 132 133const TargetRegisterClass * 134ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 135 const { 136 return &ARM::GPRRegClass; 137} 138 139const TargetRegisterClass * 140ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 141 if (RC == &ARM::CCRRegClass) 142 return 0; // Can't copy CCR registers. 143 return RC; 144} 145 146unsigned 147ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 148 MachineFunction &MF) const { 149 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 150 151 switch (RC->getID()) { 152 default: 153 return 0; 154 case ARM::tGPRRegClassID: 155 return TFI->hasFP(MF) ? 4 : 5; 156 case ARM::GPRRegClassID: { 157 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 158 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 159 } 160 case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 161 case ARM::DPRRegClassID: 162 return 32 - 10; 163 } 164} 165 166// Get the other register in a GPRPair. 167static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 168 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 169 if (ARM::GPRPairRegClass.contains(*Supers)) 170 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 171 return 0; 172} 173 174// Resolve the RegPairEven / RegPairOdd register allocator hints. 175void 176ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 177 ArrayRef<MCPhysReg> Order, 178 SmallVectorImpl<MCPhysReg> &Hints, 179 const MachineFunction &MF, 180 const VirtRegMap *VRM) const { 181 const MachineRegisterInfo &MRI = MF.getRegInfo(); 182 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 183 184 unsigned Odd; 185 switch (Hint.first) { 186 case ARMRI::RegPairEven: 187 Odd = 0; 188 break; 189 case ARMRI::RegPairOdd: 190 Odd = 1; 191 break; 192 default: 193 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 194 return; 195 } 196 197 // This register should preferably be even (Odd == 0) or odd (Odd == 1). 198 // Check if the other part of the pair has already been assigned, and provide 199 // the paired register as the first hint. 200 unsigned PairedPhys = 0; 201 if (VRM && VRM->hasPhys(Hint.second)) { 202 PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); 203 if (PairedPhys && MRI.isReserved(PairedPhys)) 204 PairedPhys = 0; 205 } 206 207 // First prefer the paired physreg. 208 if (PairedPhys) 209 Hints.push_back(PairedPhys); 210 211 // Then prefer even or odd registers. 212 for (unsigned I = 0, E = Order.size(); I != E; ++I) { 213 unsigned Reg = Order[I]; 214 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 215 continue; 216 // Don't provide hints that are paired to a reserved register. 217 unsigned Paired = getPairedGPR(Reg, !Odd, this); 218 if (!Paired || MRI.isReserved(Paired)) 219 continue; 220 Hints.push_back(Reg); 221 } 222} 223 224void 225ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 226 MachineFunction &MF) const { 227 MachineRegisterInfo *MRI = &MF.getRegInfo(); 228 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 229 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 230 Hint.first == (unsigned)ARMRI::RegPairEven) && 231 TargetRegisterInfo::isVirtualRegister(Hint.second)) { 232 // If 'Reg' is one of the even / odd register pair and it's now changed 233 // (e.g. coalesced) into a different register. The other register of the 234 // pair allocation hint must be updated to reflect the relationship 235 // change. 236 unsigned OtherReg = Hint.second; 237 Hint = MRI->getRegAllocationHint(OtherReg); 238 if (Hint.second == Reg) 239 // Make sure the pair has not already divorced. 240 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 241 } 242} 243 244bool 245ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 246 // CortexA9 has a Write-after-write hazard for NEON registers. 247 if (!STI.isLikeA9()) 248 return false; 249 250 switch (RC->getID()) { 251 case ARM::DPRRegClassID: 252 case ARM::DPR_8RegClassID: 253 case ARM::DPR_VFP2RegClassID: 254 case ARM::QPRRegClassID: 255 case ARM::QPR_8RegClassID: 256 case ARM::QPR_VFP2RegClassID: 257 case ARM::SPRRegClassID: 258 case ARM::SPR_8RegClassID: 259 // Avoid reusing S, D, and Q registers. 260 // Don't increase register pressure for QQ and QQQQ. 261 return true; 262 default: 263 return false; 264 } 265} 266 267bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 268 const MachineFrameInfo *MFI = MF.getFrameInfo(); 269 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 270 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 271 272 // When outgoing call frames are so large that we adjust the stack pointer 273 // around the call, we can no longer use the stack pointer to reach the 274 // emergency spill slot. 275 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 276 return true; 277 278 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 279 // negative range for ldr/str (255), and thumb1 is positive offsets only. 280 // It's going to be better to use the SP or Base Pointer instead. When there 281 // are variable sized objects, we can't reference off of the SP, so we 282 // reserve a Base Pointer. 283 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 284 // Conservatively estimate whether the negative offset from the frame 285 // pointer will be sufficient to reach. If a function has a smallish 286 // frame, it's less likely to have lots of spills and callee saved 287 // space, so it's all more likely to be within range of the frame pointer. 288 // If it's wrong, the scavenger will still enable access to work, it just 289 // won't be optimal. 290 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 291 return false; 292 return true; 293 } 294 295 return false; 296} 297 298bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 299 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 300 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 301 // We can't realign the stack if: 302 // 1. Dynamic stack realignment is explicitly disabled, 303 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 304 // 3. There are VLAs in the function and the base pointer is disabled. 305 if (!MF.getTarget().Options.RealignStack) 306 return false; 307 if (AFI->isThumb1OnlyFunction()) 308 return false; 309 // Stack realignment requires a frame pointer. If we already started 310 // register allocation with frame pointer elimination, it is too late now. 311 if (!MRI->canReserveReg(FramePtr)) 312 return false; 313 // We may also need a base pointer if there are dynamic allocas or stack 314 // pointer adjustments around calls. 315 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) 316 return true; 317 // A base pointer is required and allowed. Check that it isn't too late to 318 // reserve it. 319 return MRI->canReserveReg(BasePtr); 320} 321 322bool ARMBaseRegisterInfo:: 323needsStackRealignment(const MachineFunction &MF) const { 324 const MachineFrameInfo *MFI = MF.getFrameInfo(); 325 const Function *F = MF.getFunction(); 326 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 327 bool requiresRealignment = 328 ((MFI->getMaxAlignment() > StackAlign) || 329 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 330 Attribute::StackAlignment)); 331 332 return requiresRealignment && canRealignStack(MF); 333} 334 335bool ARMBaseRegisterInfo:: 336cannotEliminateFrame(const MachineFunction &MF) const { 337 const MachineFrameInfo *MFI = MF.getFrameInfo(); 338 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 339 return true; 340 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 341 || needsStackRealignment(MF); 342} 343 344unsigned 345ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 346 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 347 348 if (TFI->hasFP(MF)) 349 return FramePtr; 350 return ARM::SP; 351} 352 353unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 354 llvm_unreachable("What is the exception register"); 355} 356 357unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 358 llvm_unreachable("What is the exception handler register"); 359} 360 361/// emitLoadConstPool - Emits a load from constpool to materialize the 362/// specified immediate. 363void ARMBaseRegisterInfo:: 364emitLoadConstPool(MachineBasicBlock &MBB, 365 MachineBasicBlock::iterator &MBBI, 366 DebugLoc dl, 367 unsigned DestReg, unsigned SubIdx, int Val, 368 ARMCC::CondCodes Pred, 369 unsigned PredReg, unsigned MIFlags) const { 370 MachineFunction &MF = *MBB.getParent(); 371 MachineConstantPool *ConstantPool = MF.getConstantPool(); 372 const Constant *C = 373 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 374 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 375 376 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 377 .addReg(DestReg, getDefRegState(true), SubIdx) 378 .addConstantPoolIndex(Idx) 379 .addImm(0).addImm(Pred).addReg(PredReg) 380 .setMIFlags(MIFlags); 381} 382 383bool ARMBaseRegisterInfo:: 384requiresRegisterScavenging(const MachineFunction &MF) const { 385 return true; 386} 387 388bool ARMBaseRegisterInfo:: 389trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 390 return true; 391} 392 393bool ARMBaseRegisterInfo:: 394requiresFrameIndexScavenging(const MachineFunction &MF) const { 395 return true; 396} 397 398bool ARMBaseRegisterInfo:: 399requiresVirtualBaseRegisters(const MachineFunction &MF) const { 400 return true; 401} 402 403static void 404emitSPUpdate(bool isARM, 405 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 406 DebugLoc dl, const ARMBaseInstrInfo &TII, 407 int NumBytes, 408 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 409 if (isARM) 410 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 411 Pred, PredReg, TII); 412 else 413 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 414 Pred, PredReg, TII); 415} 416 417 418void ARMBaseRegisterInfo:: 419eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 420 MachineBasicBlock::iterator I) const { 421 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 422 if (!TFI->hasReservedCallFrame(MF)) { 423 // If we have alloca, convert as follows: 424 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 425 // ADJCALLSTACKUP -> add, sp, sp, amount 426 MachineInstr *Old = I; 427 DebugLoc dl = Old->getDebugLoc(); 428 unsigned Amount = Old->getOperand(0).getImm(); 429 if (Amount != 0) { 430 // We need to keep the stack aligned properly. To do this, we round the 431 // amount of space needed for the outgoing arguments up to the next 432 // alignment boundary. 433 unsigned Align = TFI->getStackAlignment(); 434 Amount = (Amount+Align-1)/Align*Align; 435 436 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 437 assert(!AFI->isThumb1OnlyFunction() && 438 "This eliminateCallFramePseudoInstr does not support Thumb1!"); 439 bool isARM = !AFI->isThumbFunction(); 440 441 // Replace the pseudo instruction with a new instruction... 442 unsigned Opc = Old->getOpcode(); 443 int PIdx = Old->findFirstPredOperandIdx(); 444 ARMCC::CondCodes Pred = (PIdx == -1) 445 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 446 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 447 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 448 unsigned PredReg = Old->getOperand(2).getReg(); 449 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 450 } else { 451 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 452 unsigned PredReg = Old->getOperand(3).getReg(); 453 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 454 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 455 } 456 } 457 } 458 MBB.erase(I); 459} 460 461int64_t ARMBaseRegisterInfo:: 462getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 463 const MCInstrDesc &Desc = MI->getDesc(); 464 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 465 int64_t InstrOffs = 0; 466 int Scale = 1; 467 unsigned ImmIdx = 0; 468 switch (AddrMode) { 469 case ARMII::AddrModeT2_i8: 470 case ARMII::AddrModeT2_i12: 471 case ARMII::AddrMode_i12: 472 InstrOffs = MI->getOperand(Idx+1).getImm(); 473 Scale = 1; 474 break; 475 case ARMII::AddrMode5: { 476 // VFP address mode. 477 const MachineOperand &OffOp = MI->getOperand(Idx+1); 478 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 479 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 480 InstrOffs = -InstrOffs; 481 Scale = 4; 482 break; 483 } 484 case ARMII::AddrMode2: { 485 ImmIdx = Idx+2; 486 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 487 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 488 InstrOffs = -InstrOffs; 489 break; 490 } 491 case ARMII::AddrMode3: { 492 ImmIdx = Idx+2; 493 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 494 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 495 InstrOffs = -InstrOffs; 496 break; 497 } 498 case ARMII::AddrModeT1_s: { 499 ImmIdx = Idx+1; 500 InstrOffs = MI->getOperand(ImmIdx).getImm(); 501 Scale = 4; 502 break; 503 } 504 default: 505 llvm_unreachable("Unsupported addressing mode!"); 506 } 507 508 return InstrOffs * Scale; 509} 510 511/// needsFrameBaseReg - Returns true if the instruction's frame index 512/// reference would be better served by a base register other than FP 513/// or SP. Used by LocalStackFrameAllocation to determine which frame index 514/// references it should create new base registers for. 515bool ARMBaseRegisterInfo:: 516needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 517 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 518 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 519 } 520 521 // It's the load/store FI references that cause issues, as it can be difficult 522 // to materialize the offset if it won't fit in the literal field. Estimate 523 // based on the size of the local frame and some conservative assumptions 524 // about the rest of the stack frame (note, this is pre-regalloc, so 525 // we don't know everything for certain yet) whether this offset is likely 526 // to be out of range of the immediate. Return true if so. 527 528 // We only generate virtual base registers for loads and stores, so 529 // return false for everything else. 530 unsigned Opc = MI->getOpcode(); 531 switch (Opc) { 532 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 533 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 534 case ARM::t2LDRi12: case ARM::t2LDRi8: 535 case ARM::t2STRi12: case ARM::t2STRi8: 536 case ARM::VLDRS: case ARM::VLDRD: 537 case ARM::VSTRS: case ARM::VSTRD: 538 case ARM::tSTRspi: case ARM::tLDRspi: 539 break; 540 default: 541 return false; 542 } 543 544 // Without a virtual base register, if the function has variable sized 545 // objects, all fixed-size local references will be via the frame pointer, 546 // Approximate the offset and see if it's legal for the instruction. 547 // Note that the incoming offset is based on the SP value at function entry, 548 // so it'll be negative. 549 MachineFunction &MF = *MI->getParent()->getParent(); 550 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 551 MachineFrameInfo *MFI = MF.getFrameInfo(); 552 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 553 554 // Estimate an offset from the frame pointer. 555 // Conservatively assume all callee-saved registers get pushed. R4-R6 556 // will be earlier than the FP, so we ignore those. 557 // R7, LR 558 int64_t FPOffset = Offset - 8; 559 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 560 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 561 FPOffset -= 80; 562 // Estimate an offset from the stack pointer. 563 // The incoming offset is relating to the SP at the start of the function, 564 // but when we access the local it'll be relative to the SP after local 565 // allocation, so adjust our SP-relative offset by that allocation size. 566 Offset = -Offset; 567 Offset += MFI->getLocalFrameSize(); 568 // Assume that we'll have at least some spill slots allocated. 569 // FIXME: This is a total SWAG number. We should run some statistics 570 // and pick a real one. 571 Offset += 128; // 128 bytes of spill slots 572 573 // If there is a frame pointer, try using it. 574 // The FP is only available if there is no dynamic realignment. We 575 // don't know for sure yet whether we'll need that, so we guess based 576 // on whether there are any local variables that would trigger it. 577 unsigned StackAlign = TFI->getStackAlignment(); 578 if (TFI->hasFP(MF) && 579 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 580 if (isFrameOffsetLegal(MI, FPOffset)) 581 return false; 582 } 583 // If we can reference via the stack pointer, try that. 584 // FIXME: This (and the code that resolves the references) can be improved 585 // to only disallow SP relative references in the live range of 586 // the VLA(s). In practice, it's unclear how much difference that 587 // would make, but it may be worth doing. 588 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 589 return false; 590 591 // The offset likely isn't legal, we want to allocate a virtual base register. 592 return true; 593} 594 595/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 596/// be a pointer to FrameIdx at the beginning of the basic block. 597void ARMBaseRegisterInfo:: 598materializeFrameBaseRegister(MachineBasicBlock *MBB, 599 unsigned BaseReg, int FrameIdx, 600 int64_t Offset) const { 601 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 602 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 603 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 604 605 MachineBasicBlock::iterator Ins = MBB->begin(); 606 DebugLoc DL; // Defaults to "unknown" 607 if (Ins != MBB->end()) 608 DL = Ins->getDebugLoc(); 609 610 const MCInstrDesc &MCID = TII.get(ADDriOpc); 611 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 612 const MachineFunction &MF = *MBB->getParent(); 613 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 614 615 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) 616 .addFrameIndex(FrameIdx).addImm(Offset)); 617 618 if (!AFI->isThumb1OnlyFunction()) 619 AddDefaultCC(MIB); 620} 621 622void 623ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 624 unsigned BaseReg, int64_t Offset) const { 625 MachineInstr &MI = *I; 626 MachineBasicBlock &MBB = *MI.getParent(); 627 MachineFunction &MF = *MBB.getParent(); 628 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 629 int Off = Offset; // ARM doesn't need the general 64-bit offsets 630 unsigned i = 0; 631 632 assert(!AFI->isThumb1OnlyFunction() && 633 "This resolveFrameIndex does not support Thumb1!"); 634 635 while (!MI.getOperand(i).isFI()) { 636 ++i; 637 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 638 } 639 bool Done = false; 640 if (!AFI->isThumbFunction()) 641 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 642 else { 643 assert(AFI->isThumb2Function()); 644 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 645 } 646 assert (Done && "Unable to resolve frame index!"); 647 (void)Done; 648} 649 650bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 651 int64_t Offset) const { 652 const MCInstrDesc &Desc = MI->getDesc(); 653 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 654 unsigned i = 0; 655 656 while (!MI->getOperand(i).isFI()) { 657 ++i; 658 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 659 } 660 661 // AddrMode4 and AddrMode6 cannot handle any offset. 662 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 663 return Offset == 0; 664 665 unsigned NumBits = 0; 666 unsigned Scale = 1; 667 bool isSigned = true; 668 switch (AddrMode) { 669 case ARMII::AddrModeT2_i8: 670 case ARMII::AddrModeT2_i12: 671 // i8 supports only negative, and i12 supports only positive, so 672 // based on Offset sign, consider the appropriate instruction 673 Scale = 1; 674 if (Offset < 0) { 675 NumBits = 8; 676 Offset = -Offset; 677 } else { 678 NumBits = 12; 679 } 680 break; 681 case ARMII::AddrMode5: 682 // VFP address mode. 683 NumBits = 8; 684 Scale = 4; 685 break; 686 case ARMII::AddrMode_i12: 687 case ARMII::AddrMode2: 688 NumBits = 12; 689 break; 690 case ARMII::AddrMode3: 691 NumBits = 8; 692 break; 693 case ARMII::AddrModeT1_s: 694 NumBits = 5; 695 Scale = 4; 696 isSigned = false; 697 break; 698 default: 699 llvm_unreachable("Unsupported addressing mode!"); 700 } 701 702 Offset += getFrameIndexInstrOffset(MI, i); 703 // Make sure the offset is encodable for instructions that scale the 704 // immediate. 705 if ((Offset & (Scale-1)) != 0) 706 return false; 707 708 if (isSigned && Offset < 0) 709 Offset = -Offset; 710 711 unsigned Mask = (1 << NumBits) - 1; 712 if ((unsigned)Offset <= Mask * Scale) 713 return true; 714 715 return false; 716} 717 718void 719ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 720 int SPAdj, RegScavenger *RS) const { 721 unsigned i = 0; 722 MachineInstr &MI = *II; 723 MachineBasicBlock &MBB = *MI.getParent(); 724 MachineFunction &MF = *MBB.getParent(); 725 const ARMFrameLowering *TFI = 726 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 727 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 728 assert(!AFI->isThumb1OnlyFunction() && 729 "This eliminateFrameIndex does not support Thumb1!"); 730 731 while (!MI.getOperand(i).isFI()) { 732 ++i; 733 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 734 } 735 736 int FrameIndex = MI.getOperand(i).getIndex(); 737 unsigned FrameReg; 738 739 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 740 741 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 742 // call frame setup/destroy instructions have already been eliminated. That 743 // means the stack pointer cannot be used to access the emergency spill slot 744 // when !hasReservedCallFrame(). 745#ifndef NDEBUG 746 if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){ 747 assert(TFI->hasReservedCallFrame(MF) && 748 "Cannot use SP to access the emergency spill slot in " 749 "functions without a reserved call frame"); 750 assert(!MF.getFrameInfo()->hasVarSizedObjects() && 751 "Cannot use SP to access the emergency spill slot in " 752 "functions with variable sized frame objects"); 753 } 754#endif // NDEBUG 755 756 // Special handling of dbg_value instructions. 757 if (MI.isDebugValue()) { 758 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); 759 MI.getOperand(i+1).ChangeToImmediate(Offset); 760 return; 761 } 762 763 // Modify MI as necessary to handle as much of 'Offset' as possible 764 bool Done = false; 765 if (!AFI->isThumbFunction()) 766 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 767 else { 768 assert(AFI->isThumb2Function()); 769 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 770 } 771 if (Done) 772 return; 773 774 // If we get here, the immediate doesn't fit into the instruction. We folded 775 // as much as possible above, handle the rest, providing a register that is 776 // SP+LargeImm. 777 assert((Offset || 778 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 779 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 780 "This code isn't needed if offset already handled!"); 781 782 unsigned ScratchReg = 0; 783 int PIdx = MI.findFirstPredOperandIdx(); 784 ARMCC::CondCodes Pred = (PIdx == -1) 785 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 786 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 787 if (Offset == 0) 788 // Must be addrmode4/6. 789 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 790 else { 791 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 792 if (!AFI->isThumbFunction()) 793 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 794 Offset, Pred, PredReg, TII); 795 else { 796 assert(AFI->isThumb2Function()); 797 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 798 Offset, Pred, PredReg, TII); 799 } 800 // Update the original instruction to use the scratch register. 801 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 802 } 803} 804