ARMBaseRegisterInfo.cpp revision b1f994af589af28dead4826d2e58a0138105e452 
1//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMBaseRegisterInfo.h"
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMFrameLowering.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMSubtarget.h"
20#include "MCTargetDesc/ARMAddressingModes.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/RegisterScavenging.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/raw_ostream.h"
34#include "llvm/Target/TargetFrameLowering.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37#include "llvm/ADT/BitVector.h"
38#include "llvm/ADT/SmallVector.h"
39#include "llvm/Support/CommandLine.h"
40
41#define GET_REGINFO_TARGET_DESC
42#include "ARMGenRegisterInfo.inc"
43
44using namespace llvm;
45
46static cl::opt<bool>
47ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
48          cl::desc("Force use of virtual base registers for stack load/store"));
49static cl::opt<bool>
50EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
51          cl::desc("Enable pre-regalloc stack frame index allocation"));
52static cl::opt<bool>
53EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
54          cl::desc("Enable use of a base pointer for complex stack frames"));
55
56ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
57                                         const ARMSubtarget &sti)
58  : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
59    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
60    BasePtr(ARM::R6) {
61}
62
63const uint16_t*
64ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
65  bool ghcCall = false;
66
67  if (MF) {
68    const Function *F = MF->getFunction();
69    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
70  }
71
72  if (ghcCall) {
73      return CSR_GHC_SaveList;
74  }
75  else {
76  return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
77    ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
78  }
79}
80
81const uint32_t*
82ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
83  return (STI.isTargetIOS() && !STI.isAAPCS_ABI())
84    ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
85}
86
87BitVector ARMBaseRegisterInfo::
88getReservedRegs(const MachineFunction &MF) const {
89  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
90
91  // FIXME: avoid re-calculating this every time.
92  BitVector Reserved(getNumRegs());
93  Reserved.set(ARM::SP);
94  Reserved.set(ARM::PC);
95  Reserved.set(ARM::FPSCR);
96  if (TFI->hasFP(MF))
97    Reserved.set(FramePtr);
98  if (hasBasePointer(MF))
99    Reserved.set(BasePtr);
100  // Some targets reserve R9.
101  if (STI.isR9Reserved())
102    Reserved.set(ARM::R9);
103  // Reserve D16-D31 if the subtarget doesn't support them.
104  if (!STI.hasVFP3() || STI.hasD16()) {
105    assert(ARM::D31 == ARM::D16 + 15);
106    for (unsigned i = 0; i != 16; ++i)
107      Reserved.set(ARM::D16 + i);
108  }
109  const TargetRegisterClass *RC  = &ARM::GPRPairRegClass;
110  for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
111    for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
112      if (Reserved.test(*SI)) Reserved.set(*I);
113
114  return Reserved;
115}
116
117const TargetRegisterClass*
118ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
119                                                                         const {
120  const TargetRegisterClass *Super = RC;
121  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
122  do {
123    switch (Super->getID()) {
124    case ARM::GPRRegClassID:
125    case ARM::SPRRegClassID:
126    case ARM::DPRRegClassID:
127    case ARM::QPRRegClassID:
128    case ARM::QQPRRegClassID:
129    case ARM::QQQQPRRegClassID:
130    case ARM::GPRPairRegClassID:
131      return Super;
132    }
133    Super = *I++;
134  } while (Super);
135  return RC;
136}
137
138const TargetRegisterClass *
139ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
140                                                                         const {
141  return &ARM::GPRRegClass;
142}
143
144const TargetRegisterClass *
145ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
146  if (RC == &ARM::CCRRegClass)
147    return 0;  // Can't copy CCR registers.
148  return RC;
149}
150
151unsigned
152ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
153                                         MachineFunction &MF) const {
154  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
155
156  switch (RC->getID()) {
157  default:
158    return 0;
159  case ARM::tGPRRegClassID:
160    return TFI->hasFP(MF) ? 4 : 5;
161  case ARM::GPRRegClassID: {
162    unsigned FP = TFI->hasFP(MF) ? 1 : 0;
163    return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
164  }
165  case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
166  case ARM::DPRRegClassID:
167    return 32 - 10;
168  }
169}
170
171/// getRawAllocationOrder - Returns the register allocation order for a
172/// specified register class with a target-dependent hint.
173ArrayRef<uint16_t>
174ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
175                                           unsigned HintType, unsigned HintReg,
176                                           const MachineFunction &MF) const {
177  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
178  // Alternative register allocation orders when favoring even / odd registers
179  // of register pairs.
180
181  // No FP, R9 is available.
182  static const uint16_t GPREven1[] = {
183    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
184    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
185    ARM::R9, ARM::R11
186  };
187  static const uint16_t GPROdd1[] = {
188    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
189    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
190    ARM::R8, ARM::R10
191  };
192
193  // FP is R7, R9 is available.
194  static const uint16_t GPREven2[] = {
195    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
196    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
197    ARM::R9, ARM::R11
198  };
199  static const uint16_t GPROdd2[] = {
200    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
201    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
202    ARM::R8, ARM::R10
203  };
204
205  // FP is R11, R9 is available.
206  static const uint16_t GPREven3[] = {
207    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
208    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
209    ARM::R9
210  };
211  static const uint16_t GPROdd3[] = {
212    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
213    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
214    ARM::R8
215  };
216
217  // No FP, R9 is not available.
218  static const uint16_t GPREven4[] = {
219    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
220    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
221    ARM::R11
222  };
223  static const uint16_t GPROdd4[] = {
224    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
225    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
226    ARM::R10
227  };
228
229  // FP is R7, R9 is not available.
230  static const uint16_t GPREven5[] = {
231    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
232    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
233    ARM::R11
234  };
235  static const uint16_t GPROdd5[] = {
236    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
237    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
238    ARM::R10
239  };
240
241  // FP is R11, R9 is not available.
242  static const uint16_t GPREven6[] = {
243    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
244    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
245  };
246  static const uint16_t GPROdd6[] = {
247    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
248    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
249  };
250
251  // We only support even/odd hints for GPR and rGPR.
252  if (RC != &ARM::GPRRegClass && RC != &ARM::rGPRRegClass)
253    return RC->getRawAllocationOrder(MF);
254
255  if (HintType == ARMRI::RegPairEven) {
256    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
257      // It's no longer possible to fulfill this hint. Return the default
258      // allocation order.
259      return RC->getRawAllocationOrder(MF);
260
261    if (!TFI->hasFP(MF)) {
262      if (!STI.isR9Reserved())
263        return makeArrayRef(GPREven1);
264      else
265        return makeArrayRef(GPREven4);
266    } else if (FramePtr == ARM::R7) {
267      if (!STI.isR9Reserved())
268        return makeArrayRef(GPREven2);
269      else
270        return makeArrayRef(GPREven5);
271    } else { // FramePtr == ARM::R11
272      if (!STI.isR9Reserved())
273        return makeArrayRef(GPREven3);
274      else
275        return makeArrayRef(GPREven6);
276    }
277  } else if (HintType == ARMRI::RegPairOdd) {
278    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
279      // It's no longer possible to fulfill this hint. Return the default
280      // allocation order.
281      return RC->getRawAllocationOrder(MF);
282
283    if (!TFI->hasFP(MF)) {
284      if (!STI.isR9Reserved())
285        return makeArrayRef(GPROdd1);
286      else
287        return makeArrayRef(GPROdd4);
288    } else if (FramePtr == ARM::R7) {
289      if (!STI.isR9Reserved())
290        return makeArrayRef(GPROdd2);
291      else
292        return makeArrayRef(GPROdd5);
293    } else { // FramePtr == ARM::R11
294      if (!STI.isR9Reserved())
295        return makeArrayRef(GPROdd3);
296      else
297        return makeArrayRef(GPROdd6);
298    }
299  }
300  return RC->getRawAllocationOrder(MF);
301}
302
303/// ResolveRegAllocHint - Resolves the specified register allocation hint
304/// to a physical register. Returns the physical register if it is successful.
305unsigned
306ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
307                                         const MachineFunction &MF) const {
308  if (Reg == 0 || !isPhysicalRegister(Reg))
309    return 0;
310  if (Type == 0)
311    return Reg;
312  else if (Type == (unsigned)ARMRI::RegPairOdd)
313    // Odd register.
314    return getRegisterPairOdd(Reg, MF);
315  else if (Type == (unsigned)ARMRI::RegPairEven)
316    // Even register.
317    return getRegisterPairEven(Reg, MF);
318  return 0;
319}
320
321void
322ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
323                                        MachineFunction &MF) const {
324  MachineRegisterInfo *MRI = &MF.getRegInfo();
325  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
326  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
327       Hint.first == (unsigned)ARMRI::RegPairEven) &&
328      TargetRegisterInfo::isVirtualRegister(Hint.second)) {
329    // If 'Reg' is one of the even / odd register pair and it's now changed
330    // (e.g. coalesced) into a different register. The other register of the
331    // pair allocation hint must be updated to reflect the relationship
332    // change.
333    unsigned OtherReg = Hint.second;
334    Hint = MRI->getRegAllocationHint(OtherReg);
335    if (Hint.second == Reg)
336      // Make sure the pair has not already divorced.
337      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
338  }
339}
340
341bool
342ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
343  // CortexA9 has a Write-after-write hazard for NEON registers.
344  if (!STI.isLikeA9())
345    return false;
346
347  switch (RC->getID()) {
348  case ARM::DPRRegClassID:
349  case ARM::DPR_8RegClassID:
350  case ARM::DPR_VFP2RegClassID:
351  case ARM::QPRRegClassID:
352  case ARM::QPR_8RegClassID:
353  case ARM::QPR_VFP2RegClassID:
354  case ARM::SPRRegClassID:
355  case ARM::SPR_8RegClassID:
356    // Avoid reusing S, D, and Q registers.
357    // Don't increase register pressure for QQ and QQQQ.
358    return true;
359  default:
360    return false;
361  }
362}
363
364bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
365  const MachineFrameInfo *MFI = MF.getFrameInfo();
366  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
367  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
368
369  if (!EnableBasePointer)
370    return false;
371
372  // When outgoing call frames are so large that we adjust the stack pointer
373  // around the call, we can no longer use the stack pointer to reach the
374  // emergency spill slot.
375  if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
376    return true;
377
378  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
379  // negative range for ldr/str (255), and thumb1 is positive offsets only.
380  // It's going to be better to use the SP or Base Pointer instead. When there
381  // are variable sized objects, we can't reference off of the SP, so we
382  // reserve a Base Pointer.
383  if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
384    // Conservatively estimate whether the negative offset from the frame
385    // pointer will be sufficient to reach. If a function has a smallish
386    // frame, it's less likely to have lots of spills and callee saved
387    // space, so it's all more likely to be within range of the frame pointer.
388    // If it's wrong, the scavenger will still enable access to work, it just
389    // won't be optimal.
390    if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
391      return false;
392    return true;
393  }
394
395  return false;
396}
397
398bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
399  const MachineRegisterInfo *MRI = &MF.getRegInfo();
400  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
401  // We can't realign the stack if:
402  // 1. Dynamic stack realignment is explicitly disabled,
403  // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
404  // 3. There are VLAs in the function and the base pointer is disabled.
405  if (!MF.getTarget().Options.RealignStack)
406    return false;
407  if (AFI->isThumb1OnlyFunction())
408    return false;
409  // Stack realignment requires a frame pointer.  If we already started
410  // register allocation with frame pointer elimination, it is too late now.
411  if (!MRI->canReserveReg(FramePtr))
412    return false;
413  // We may also need a base pointer if there are dynamic allocas or stack
414  // pointer adjustments around calls.
415  if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF))
416    return true;
417  if (!EnableBasePointer)
418    return false;
419  // A base pointer is required and allowed.  Check that it isn't too late to
420  // reserve it.
421  return MRI->canReserveReg(BasePtr);
422}
423
424bool ARMBaseRegisterInfo::
425needsStackRealignment(const MachineFunction &MF) const {
426  const MachineFrameInfo *MFI = MF.getFrameInfo();
427  const Function *F = MF.getFunction();
428  unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
429  bool requiresRealignment =
430    ((MFI->getMaxAlignment() > StackAlign) ||
431     F->getFnAttributes().hasAttribute(Attributes::StackAlignment));
432
433  return requiresRealignment && canRealignStack(MF);
434}
435
436bool ARMBaseRegisterInfo::
437cannotEliminateFrame(const MachineFunction &MF) const {
438  const MachineFrameInfo *MFI = MF.getFrameInfo();
439  if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
440    return true;
441  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
442    || needsStackRealignment(MF);
443}
444
445unsigned
446ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
447  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
448
449  if (TFI->hasFP(MF))
450    return FramePtr;
451  return ARM::SP;
452}
453
454unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
455  llvm_unreachable("What is the exception register");
456}
457
458unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
459  llvm_unreachable("What is the exception handler register");
460}
461
462unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
463                                              const MachineFunction &MF) const {
464  const MachineRegisterInfo &MRI = MF.getRegInfo();
465  switch (Reg) {
466  default: break;
467  // Return 0 if either register of the pair is a special register.
468  // So no R12, etc.
469  case ARM::R1: return ARM::R0;
470  case ARM::R3: return ARM::R2;
471  case ARM::R5: return ARM::R4;
472  case ARM::R7:
473    return (MRI.isReserved(ARM::R7) || MRI.isReserved(ARM::R6))
474      ? 0 : ARM::R6;
475  case ARM::R9: return MRI.isReserved(ARM::R9)  ? 0 :ARM::R8;
476  case ARM::R11: return MRI.isReserved(ARM::R11) ? 0 : ARM::R10;
477
478  case ARM::S1: return ARM::S0;
479  case ARM::S3: return ARM::S2;
480  case ARM::S5: return ARM::S4;
481  case ARM::S7: return ARM::S6;
482  case ARM::S9: return ARM::S8;
483  case ARM::S11: return ARM::S10;
484  case ARM::S13: return ARM::S12;
485  case ARM::S15: return ARM::S14;
486  case ARM::S17: return ARM::S16;
487  case ARM::S19: return ARM::S18;
488  case ARM::S21: return ARM::S20;
489  case ARM::S23: return ARM::S22;
490  case ARM::S25: return ARM::S24;
491  case ARM::S27: return ARM::S26;
492  case ARM::S29: return ARM::S28;
493  case ARM::S31: return ARM::S30;
494
495  case ARM::D1: return ARM::D0;
496  case ARM::D3: return ARM::D2;
497  case ARM::D5: return ARM::D4;
498  case ARM::D7: return ARM::D6;
499  case ARM::D9: return ARM::D8;
500  case ARM::D11: return ARM::D10;
501  case ARM::D13: return ARM::D12;
502  case ARM::D15: return ARM::D14;
503  case ARM::D17: return ARM::D16;
504  case ARM::D19: return ARM::D18;
505  case ARM::D21: return ARM::D20;
506  case ARM::D23: return ARM::D22;
507  case ARM::D25: return ARM::D24;
508  case ARM::D27: return ARM::D26;
509  case ARM::D29: return ARM::D28;
510  case ARM::D31: return ARM::D30;
511  }
512
513  return 0;
514}
515
516unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
517                                             const MachineFunction &MF) const {
518  const MachineRegisterInfo &MRI = MF.getRegInfo();
519  switch (Reg) {
520  default: break;
521  // Return 0 if either register of the pair is a special register.
522  // So no R12, etc.
523  case ARM::R0: return ARM::R1;
524  case ARM::R2: return ARM::R3;
525  case ARM::R4: return ARM::R5;
526  case ARM::R6:
527    return (MRI.isReserved(ARM::R7) || MRI.isReserved(ARM::R6))
528      ? 0 : ARM::R7;
529  case ARM::R8: return MRI.isReserved(ARM::R9)  ? 0 :ARM::R9;
530  case ARM::R10: return MRI.isReserved(ARM::R11) ? 0 : ARM::R11;
531
532  case ARM::S0: return ARM::S1;
533  case ARM::S2: return ARM::S3;
534  case ARM::S4: return ARM::S5;
535  case ARM::S6: return ARM::S7;
536  case ARM::S8: return ARM::S9;
537  case ARM::S10: return ARM::S11;
538  case ARM::S12: return ARM::S13;
539  case ARM::S14: return ARM::S15;
540  case ARM::S16: return ARM::S17;
541  case ARM::S18: return ARM::S19;
542  case ARM::S20: return ARM::S21;
543  case ARM::S22: return ARM::S23;
544  case ARM::S24: return ARM::S25;
545  case ARM::S26: return ARM::S27;
546  case ARM::S28: return ARM::S29;
547  case ARM::S30: return ARM::S31;
548
549  case ARM::D0: return ARM::D1;
550  case ARM::D2: return ARM::D3;
551  case ARM::D4: return ARM::D5;
552  case ARM::D6: return ARM::D7;
553  case ARM::D8: return ARM::D9;
554  case ARM::D10: return ARM::D11;
555  case ARM::D12: return ARM::D13;
556  case ARM::D14: return ARM::D15;
557  case ARM::D16: return ARM::D17;
558  case ARM::D18: return ARM::D19;
559  case ARM::D20: return ARM::D21;
560  case ARM::D22: return ARM::D23;
561  case ARM::D24: return ARM::D25;
562  case ARM::D26: return ARM::D27;
563  case ARM::D28: return ARM::D29;
564  case ARM::D30: return ARM::D31;
565  }
566
567  return 0;
568}
569
570/// emitLoadConstPool - Emits a load from constpool to materialize the
571/// specified immediate.
572void ARMBaseRegisterInfo::
573emitLoadConstPool(MachineBasicBlock &MBB,
574                  MachineBasicBlock::iterator &MBBI,
575                  DebugLoc dl,
576                  unsigned DestReg, unsigned SubIdx, int Val,
577                  ARMCC::CondCodes Pred,
578                  unsigned PredReg, unsigned MIFlags) const {
579  MachineFunction &MF = *MBB.getParent();
580  MachineConstantPool *ConstantPool = MF.getConstantPool();
581  const Constant *C =
582        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
583  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
584
585  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
586    .addReg(DestReg, getDefRegState(true), SubIdx)
587    .addConstantPoolIndex(Idx)
588    .addImm(0).addImm(Pred).addReg(PredReg)
589    .setMIFlags(MIFlags);
590}
591
592bool ARMBaseRegisterInfo::
593requiresRegisterScavenging(const MachineFunction &MF) const {
594  return true;
595}
596
597bool ARMBaseRegisterInfo::
598trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
599  return true;
600}
601
602bool ARMBaseRegisterInfo::
603requiresFrameIndexScavenging(const MachineFunction &MF) const {
604  return true;
605}
606
607bool ARMBaseRegisterInfo::
608requiresVirtualBaseRegisters(const MachineFunction &MF) const {
609  return EnableLocalStackAlloc;
610}
611
612static void
613emitSPUpdate(bool isARM,
614             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
615             DebugLoc dl, const ARMBaseInstrInfo &TII,
616             int NumBytes,
617             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
618  if (isARM)
619    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
620                            Pred, PredReg, TII);
621  else
622    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
623                           Pred, PredReg, TII);
624}
625
626
627void ARMBaseRegisterInfo::
628eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
629                              MachineBasicBlock::iterator I) const {
630  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
631  if (!TFI->hasReservedCallFrame(MF)) {
632    // If we have alloca, convert as follows:
633    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
634    // ADJCALLSTACKUP   -> add, sp, sp, amount
635    MachineInstr *Old = I;
636    DebugLoc dl = Old->getDebugLoc();
637    unsigned Amount = Old->getOperand(0).getImm();
638    if (Amount != 0) {
639      // We need to keep the stack aligned properly.  To do this, we round the
640      // amount of space needed for the outgoing arguments up to the next
641      // alignment boundary.
642      unsigned Align = TFI->getStackAlignment();
643      Amount = (Amount+Align-1)/Align*Align;
644
645      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
646      assert(!AFI->isThumb1OnlyFunction() &&
647             "This eliminateCallFramePseudoInstr does not support Thumb1!");
648      bool isARM = !AFI->isThumbFunction();
649
650      // Replace the pseudo instruction with a new instruction...
651      unsigned Opc = Old->getOpcode();
652      int PIdx = Old->findFirstPredOperandIdx();
653      ARMCC::CondCodes Pred = (PIdx == -1)
654        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
655      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
656        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
657        unsigned PredReg = Old->getOperand(2).getReg();
658        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
659      } else {
660        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
661        unsigned PredReg = Old->getOperand(3).getReg();
662        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
663        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
664      }
665    }
666  }
667  MBB.erase(I);
668}
669
670int64_t ARMBaseRegisterInfo::
671getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
672  const MCInstrDesc &Desc = MI->getDesc();
673  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
674  int64_t InstrOffs = 0;
675  int Scale = 1;
676  unsigned ImmIdx = 0;
677  switch (AddrMode) {
678  case ARMII::AddrModeT2_i8:
679  case ARMII::AddrModeT2_i12:
680  case ARMII::AddrMode_i12:
681    InstrOffs = MI->getOperand(Idx+1).getImm();
682    Scale = 1;
683    break;
684  case ARMII::AddrMode5: {
685    // VFP address mode.
686    const MachineOperand &OffOp = MI->getOperand(Idx+1);
687    InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
688    if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
689      InstrOffs = -InstrOffs;
690    Scale = 4;
691    break;
692  }
693  case ARMII::AddrMode2: {
694    ImmIdx = Idx+2;
695    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
696    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
697      InstrOffs = -InstrOffs;
698    break;
699  }
700  case ARMII::AddrMode3: {
701    ImmIdx = Idx+2;
702    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
703    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
704      InstrOffs = -InstrOffs;
705    break;
706  }
707  case ARMII::AddrModeT1_s: {
708    ImmIdx = Idx+1;
709    InstrOffs = MI->getOperand(ImmIdx).getImm();
710    Scale = 4;
711    break;
712  }
713  default:
714    llvm_unreachable("Unsupported addressing mode!");
715  }
716
717  return InstrOffs * Scale;
718}
719
720/// needsFrameBaseReg - Returns true if the instruction's frame index
721/// reference would be better served by a base register other than FP
722/// or SP. Used by LocalStackFrameAllocation to determine which frame index
723/// references it should create new base registers for.
724bool ARMBaseRegisterInfo::
725needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
726  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
727    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
728  }
729
730  // It's the load/store FI references that cause issues, as it can be difficult
731  // to materialize the offset if it won't fit in the literal field. Estimate
732  // based on the size of the local frame and some conservative assumptions
733  // about the rest of the stack frame (note, this is pre-regalloc, so
734  // we don't know everything for certain yet) whether this offset is likely
735  // to be out of range of the immediate. Return true if so.
736
737  // We only generate virtual base registers for loads and stores, so
738  // return false for everything else.
739  unsigned Opc = MI->getOpcode();
740  switch (Opc) {
741  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
742  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
743  case ARM::t2LDRi12: case ARM::t2LDRi8:
744  case ARM::t2STRi12: case ARM::t2STRi8:
745  case ARM::VLDRS: case ARM::VLDRD:
746  case ARM::VSTRS: case ARM::VSTRD:
747  case ARM::tSTRspi: case ARM::tLDRspi:
748    if (ForceAllBaseRegAlloc)
749      return true;
750    break;
751  default:
752    return false;
753  }
754
755  // Without a virtual base register, if the function has variable sized
756  // objects, all fixed-size local references will be via the frame pointer,
757  // Approximate the offset and see if it's legal for the instruction.
758  // Note that the incoming offset is based on the SP value at function entry,
759  // so it'll be negative.
760  MachineFunction &MF = *MI->getParent()->getParent();
761  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
762  MachineFrameInfo *MFI = MF.getFrameInfo();
763  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
764
765  // Estimate an offset from the frame pointer.
766  // Conservatively assume all callee-saved registers get pushed. R4-R6
767  // will be earlier than the FP, so we ignore those.
768  // R7, LR
769  int64_t FPOffset = Offset - 8;
770  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
771  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
772    FPOffset -= 80;
773  // Estimate an offset from the stack pointer.
774  // The incoming offset is relating to the SP at the start of the function,
775  // but when we access the local it'll be relative to the SP after local
776  // allocation, so adjust our SP-relative offset by that allocation size.
777  Offset = -Offset;
778  Offset += MFI->getLocalFrameSize();
779  // Assume that we'll have at least some spill slots allocated.
780  // FIXME: This is a total SWAG number. We should run some statistics
781  //        and pick a real one.
782  Offset += 128; // 128 bytes of spill slots
783
784  // If there is a frame pointer, try using it.
785  // The FP is only available if there is no dynamic realignment. We
786  // don't know for sure yet whether we'll need that, so we guess based
787  // on whether there are any local variables that would trigger it.
788  unsigned StackAlign = TFI->getStackAlignment();
789  if (TFI->hasFP(MF) &&
790      !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
791    if (isFrameOffsetLegal(MI, FPOffset))
792      return false;
793  }
794  // If we can reference via the stack pointer, try that.
795  // FIXME: This (and the code that resolves the references) can be improved
796  //        to only disallow SP relative references in the live range of
797  //        the VLA(s). In practice, it's unclear how much difference that
798  //        would make, but it may be worth doing.
799  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
800    return false;
801
802  // The offset likely isn't legal, we want to allocate a virtual base register.
803  return true;
804}
805
806/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
807/// be a pointer to FrameIdx at the beginning of the basic block.
808void ARMBaseRegisterInfo::
809materializeFrameBaseRegister(MachineBasicBlock *MBB,
810                             unsigned BaseReg, int FrameIdx,
811                             int64_t Offset) const {
812  ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
813  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
814    (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
815
816  MachineBasicBlock::iterator Ins = MBB->begin();
817  DebugLoc DL;                  // Defaults to "unknown"
818  if (Ins != MBB->end())
819    DL = Ins->getDebugLoc();
820
821  const MCInstrDesc &MCID = TII.get(ADDriOpc);
822  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
823  const MachineFunction &MF = *MBB->getParent();
824  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
825
826  MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
827    .addFrameIndex(FrameIdx).addImm(Offset));
828
829  if (!AFI->isThumb1OnlyFunction())
830    AddDefaultCC(MIB);
831}
832
833void
834ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
835                                       unsigned BaseReg, int64_t Offset) const {
836  MachineInstr &MI = *I;
837  MachineBasicBlock &MBB = *MI.getParent();
838  MachineFunction &MF = *MBB.getParent();
839  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
840  int Off = Offset; // ARM doesn't need the general 64-bit offsets
841  unsigned i = 0;
842
843  assert(!AFI->isThumb1OnlyFunction() &&
844         "This resolveFrameIndex does not support Thumb1!");
845
846  while (!MI.getOperand(i).isFI()) {
847    ++i;
848    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
849  }
850  bool Done = false;
851  if (!AFI->isThumbFunction())
852    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
853  else {
854    assert(AFI->isThumb2Function());
855    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
856  }
857  assert (Done && "Unable to resolve frame index!");
858  (void)Done;
859}
860
861bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
862                                             int64_t Offset) const {
863  const MCInstrDesc &Desc = MI->getDesc();
864  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
865  unsigned i = 0;
866
867  while (!MI->getOperand(i).isFI()) {
868    ++i;
869    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
870  }
871
872  // AddrMode4 and AddrMode6 cannot handle any offset.
873  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
874    return Offset == 0;
875
876  unsigned NumBits = 0;
877  unsigned Scale = 1;
878  bool isSigned = true;
879  switch (AddrMode) {
880  case ARMII::AddrModeT2_i8:
881  case ARMII::AddrModeT2_i12:
882    // i8 supports only negative, and i12 supports only positive, so
883    // based on Offset sign, consider the appropriate instruction
884    Scale = 1;
885    if (Offset < 0) {
886      NumBits = 8;
887      Offset = -Offset;
888    } else {
889      NumBits = 12;
890    }
891    break;
892  case ARMII::AddrMode5:
893    // VFP address mode.
894    NumBits = 8;
895    Scale = 4;
896    break;
897  case ARMII::AddrMode_i12:
898  case ARMII::AddrMode2:
899    NumBits = 12;
900    break;
901  case ARMII::AddrMode3:
902    NumBits = 8;
903    break;
904  case ARMII::AddrModeT1_s:
905    NumBits = 5;
906    Scale = 4;
907    isSigned = false;
908    break;
909  default:
910    llvm_unreachable("Unsupported addressing mode!");
911  }
912
913  Offset += getFrameIndexInstrOffset(MI, i);
914  // Make sure the offset is encodable for instructions that scale the
915  // immediate.
916  if ((Offset & (Scale-1)) != 0)
917    return false;
918
919  if (isSigned && Offset < 0)
920    Offset = -Offset;
921
922  unsigned Mask = (1 << NumBits) - 1;
923  if ((unsigned)Offset <= Mask * Scale)
924    return true;
925
926  return false;
927}
928
929void
930ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
931                                         int SPAdj, RegScavenger *RS) const {
932  unsigned i = 0;
933  MachineInstr &MI = *II;
934  MachineBasicBlock &MBB = *MI.getParent();
935  MachineFunction &MF = *MBB.getParent();
936  const ARMFrameLowering *TFI =
937    static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
938  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
939  assert(!AFI->isThumb1OnlyFunction() &&
940         "This eliminateFrameIndex does not support Thumb1!");
941
942  while (!MI.getOperand(i).isFI()) {
943    ++i;
944    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
945  }
946
947  int FrameIndex = MI.getOperand(i).getIndex();
948  unsigned FrameReg;
949
950  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
951
952  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
953  // call frame setup/destroy instructions have already been eliminated.  That
954  // means the stack pointer cannot be used to access the emergency spill slot
955  // when !hasReservedCallFrame().
956#ifndef NDEBUG
957  if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){
958    assert(TFI->hasReservedCallFrame(MF) &&
959           "Cannot use SP to access the emergency spill slot in "
960           "functions without a reserved call frame");
961    assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
962           "Cannot use SP to access the emergency spill slot in "
963           "functions with variable sized frame objects");
964  }
965#endif // NDEBUG
966
967  // Special handling of dbg_value instructions.
968  if (MI.isDebugValue()) {
969    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
970    MI.getOperand(i+1).ChangeToImmediate(Offset);
971    return;
972  }
973
974  // Modify MI as necessary to handle as much of 'Offset' as possible
975  bool Done = false;
976  if (!AFI->isThumbFunction())
977    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
978  else {
979    assert(AFI->isThumb2Function());
980    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
981  }
982  if (Done)
983    return;
984
985  // If we get here, the immediate doesn't fit into the instruction.  We folded
986  // as much as possible above, handle the rest, providing a register that is
987  // SP+LargeImm.
988  assert((Offset ||
989          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
990          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
991         "This code isn't needed if offset already handled!");
992
993  unsigned ScratchReg = 0;
994  int PIdx = MI.findFirstPredOperandIdx();
995  ARMCC::CondCodes Pred = (PIdx == -1)
996    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
997  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
998  if (Offset == 0)
999    // Must be addrmode4/6.
1000    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1001  else {
1002    ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
1003    if (!AFI->isThumbFunction())
1004      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1005                              Offset, Pred, PredReg, TII);
1006    else {
1007      assert(AFI->isThumb2Function());
1008      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1009                             Offset, Pred, PredReg, TII);
1010    }
1011    // Update the original instruction to use the scratch register.
1012    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1013  }
1014}
1015