ARMBaseRegisterInfo.cpp revision c2e08db4e5a8e1b3c253fb07c6eb736dfb66fe59 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMFrameLowering.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "MCTargetDesc/ARMAddressingModes.h"
22#include "llvm/Constants.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
25#include "llvm/LLVMContext.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameLowering.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42#define GET_REGINFO_TARGET_DESC
43#include "ARMGenRegisterInfo.inc"
44
45using namespace llvm;
46
47static cl::opt<bool>
48ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
49          cl::desc("Force use of virtual base registers for stack load/store"));
50static cl::opt<bool>
51EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
52          cl::desc("Enable pre-regalloc stack frame index allocation"));
53static cl::opt<bool>
54EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55          cl::desc("Enable use of a base pointer for complex stack frames"));
56
57ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
58                                         const ARMSubtarget &sti)
59  : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
60    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
61    BasePtr(ARM::R6) {
62}
63
64const unsigned*
65ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
66  return (STI.isTargetIOS()) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
67}
68
69const uint32_t*
70ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
71  return (STI.isTargetIOS()) ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
72}
73
74BitVector ARMBaseRegisterInfo::
75getReservedRegs(const MachineFunction &MF) const {
76  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
77
78  // FIXME: avoid re-calculating this every time.
79  BitVector Reserved(getNumRegs());
80  Reserved.set(ARM::SP);
81  Reserved.set(ARM::PC);
82  if (TFI->hasFP(MF))
83    Reserved.set(FramePtr);
84  if (hasBasePointer(MF))
85    Reserved.set(BasePtr);
86  // Some targets reserve R9.
87  if (STI.isR9Reserved())
88    Reserved.set(ARM::R9);
89  // Reserve D16-D31 if the subtarget doesn't support them.
90  if (!STI.hasVFP3() || STI.hasD16()) {
91    assert(ARM::D31 == ARM::D16 + 15);
92    for (unsigned i = 0; i != 16; ++i)
93      Reserved.set(ARM::D16 + i);
94  }
95  return Reserved;
96}
97
98bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
99                                        unsigned Reg) const {
100  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
101
102  switch (Reg) {
103  default: break;
104  case ARM::SP:
105  case ARM::PC:
106    return true;
107  case ARM::R6:
108    if (hasBasePointer(MF))
109      return true;
110    break;
111  case ARM::R7:
112  case ARM::R11:
113    if (FramePtr == Reg && TFI->hasFP(MF))
114      return true;
115    break;
116  case ARM::R9:
117    return STI.isR9Reserved();
118  }
119
120  return false;
121}
122
123bool
124ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
125                                          SmallVectorImpl<unsigned> &SubIndices,
126                                          unsigned &NewSubIdx) const {
127
128  unsigned Size = RC->getSize() * 8;
129  if (Size < 6)
130    return 0;
131
132  NewSubIdx = 0;  // Whole register.
133  unsigned NumRegs = SubIndices.size();
134  if (NumRegs == 8) {
135    // 8 D registers -> 1 QQQQ register.
136    return (Size == 512 &&
137            SubIndices[0] == ARM::dsub_0 &&
138            SubIndices[1] == ARM::dsub_1 &&
139            SubIndices[2] == ARM::dsub_2 &&
140            SubIndices[3] == ARM::dsub_3 &&
141            SubIndices[4] == ARM::dsub_4 &&
142            SubIndices[5] == ARM::dsub_5 &&
143            SubIndices[6] == ARM::dsub_6 &&
144            SubIndices[7] == ARM::dsub_7);
145  } else if (NumRegs == 4) {
146    if (SubIndices[0] == ARM::qsub_0) {
147      // 4 Q registers -> 1 QQQQ register.
148      return (Size == 512 &&
149              SubIndices[1] == ARM::qsub_1 &&
150              SubIndices[2] == ARM::qsub_2 &&
151              SubIndices[3] == ARM::qsub_3);
152    } else if (SubIndices[0] == ARM::dsub_0) {
153      // 4 D registers -> 1 QQ register.
154      if (Size >= 256 &&
155          SubIndices[1] == ARM::dsub_1 &&
156          SubIndices[2] == ARM::dsub_2 &&
157          SubIndices[3] == ARM::dsub_3) {
158        if (Size == 512)
159          NewSubIdx = ARM::qqsub_0;
160        return true;
161      }
162    } else if (SubIndices[0] == ARM::dsub_4) {
163      // 4 D registers -> 1 QQ register (2nd).
164      if (Size == 512 &&
165          SubIndices[1] == ARM::dsub_5 &&
166          SubIndices[2] == ARM::dsub_6 &&
167          SubIndices[3] == ARM::dsub_7) {
168        NewSubIdx = ARM::qqsub_1;
169        return true;
170      }
171    } else if (SubIndices[0] == ARM::ssub_0) {
172      // 4 S registers -> 1 Q register.
173      if (Size >= 128 &&
174          SubIndices[1] == ARM::ssub_1 &&
175          SubIndices[2] == ARM::ssub_2 &&
176          SubIndices[3] == ARM::ssub_3) {
177        if (Size >= 256)
178          NewSubIdx = ARM::qsub_0;
179        return true;
180      }
181    }
182  } else if (NumRegs == 2) {
183    if (SubIndices[0] == ARM::qsub_0) {
184      // 2 Q registers -> 1 QQ register.
185      if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
186        if (Size == 512)
187          NewSubIdx = ARM::qqsub_0;
188        return true;
189      }
190    } else if (SubIndices[0] == ARM::qsub_2) {
191      // 2 Q registers -> 1 QQ register (2nd).
192      if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
193        NewSubIdx = ARM::qqsub_1;
194        return true;
195      }
196    } else if (SubIndices[0] == ARM::dsub_0) {
197      // 2 D registers -> 1 Q register.
198      if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
199        if (Size >= 256)
200          NewSubIdx = ARM::qsub_0;
201        return true;
202      }
203    } else if (SubIndices[0] == ARM::dsub_2) {
204      // 2 D registers -> 1 Q register (2nd).
205      if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
206        NewSubIdx = ARM::qsub_1;
207        return true;
208      }
209    } else if (SubIndices[0] == ARM::dsub_4) {
210      // 2 D registers -> 1 Q register (3rd).
211      if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
212        NewSubIdx = ARM::qsub_2;
213        return true;
214      }
215    } else if (SubIndices[0] == ARM::dsub_6) {
216      // 2 D registers -> 1 Q register (3rd).
217      if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
218        NewSubIdx = ARM::qsub_3;
219        return true;
220      }
221    } else if (SubIndices[0] == ARM::ssub_0) {
222      // 2 S registers -> 1 D register.
223      if (SubIndices[1] == ARM::ssub_1) {
224        if (Size >= 128)
225          NewSubIdx = ARM::dsub_0;
226        return true;
227      }
228    } else if (SubIndices[0] == ARM::ssub_2) {
229      // 2 S registers -> 1 D register (2nd).
230      if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
231        NewSubIdx = ARM::dsub_1;
232        return true;
233      }
234    }
235  }
236  return false;
237}
238
239const TargetRegisterClass*
240ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
241                                                                         const {
242  const TargetRegisterClass *Super = RC;
243  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
244  do {
245    switch (Super->getID()) {
246    case ARM::GPRRegClassID:
247    case ARM::SPRRegClassID:
248    case ARM::DPRRegClassID:
249    case ARM::QPRRegClassID:
250    case ARM::QQPRRegClassID:
251    case ARM::QQQQPRRegClassID:
252      return Super;
253    }
254    Super = *I++;
255  } while (Super);
256  return RC;
257}
258
259const TargetRegisterClass *
260ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
261  return ARM::GPRRegisterClass;
262}
263
264const TargetRegisterClass *
265ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
266  if (RC == &ARM::CCRRegClass)
267    return 0;  // Can't copy CCR registers.
268  return RC;
269}
270
271unsigned
272ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
273                                         MachineFunction &MF) const {
274  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
275
276  switch (RC->getID()) {
277  default:
278    return 0;
279  case ARM::tGPRRegClassID:
280    return TFI->hasFP(MF) ? 4 : 5;
281  case ARM::GPRRegClassID: {
282    unsigned FP = TFI->hasFP(MF) ? 1 : 0;
283    return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
284  }
285  case ARM::SPRRegClassID:  // Currently not used as 'rep' register class.
286  case ARM::DPRRegClassID:
287    return 32 - 10;
288  }
289}
290
291/// getRawAllocationOrder - Returns the register allocation order for a
292/// specified register class with a target-dependent hint.
293ArrayRef<unsigned>
294ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
295                                           unsigned HintType, unsigned HintReg,
296                                           const MachineFunction &MF) const {
297  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
298  // Alternative register allocation orders when favoring even / odd registers
299  // of register pairs.
300
301  // No FP, R9 is available.
302  static const unsigned GPREven1[] = {
303    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
304    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
305    ARM::R9, ARM::R11
306  };
307  static const unsigned GPROdd1[] = {
308    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
309    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
310    ARM::R8, ARM::R10
311  };
312
313  // FP is R7, R9 is available.
314  static const unsigned GPREven2[] = {
315    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
316    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
317    ARM::R9, ARM::R11
318  };
319  static const unsigned GPROdd2[] = {
320    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
321    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
322    ARM::R8, ARM::R10
323  };
324
325  // FP is R11, R9 is available.
326  static const unsigned GPREven3[] = {
327    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
328    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
329    ARM::R9
330  };
331  static const unsigned GPROdd3[] = {
332    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
333    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
334    ARM::R8
335  };
336
337  // No FP, R9 is not available.
338  static const unsigned GPREven4[] = {
339    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
340    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
341    ARM::R11
342  };
343  static const unsigned GPROdd4[] = {
344    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
345    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
346    ARM::R10
347  };
348
349  // FP is R7, R9 is not available.
350  static const unsigned GPREven5[] = {
351    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
352    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
353    ARM::R11
354  };
355  static const unsigned GPROdd5[] = {
356    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
357    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
358    ARM::R10
359  };
360
361  // FP is R11, R9 is not available.
362  static const unsigned GPREven6[] = {
363    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
364    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
365  };
366  static const unsigned GPROdd6[] = {
367    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
368    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
369  };
370
371  // We only support even/odd hints for GPR and rGPR.
372  if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
373    return RC->getRawAllocationOrder(MF);
374
375  if (HintType == ARMRI::RegPairEven) {
376    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
377      // It's no longer possible to fulfill this hint. Return the default
378      // allocation order.
379      return RC->getRawAllocationOrder(MF);
380
381    if (!TFI->hasFP(MF)) {
382      if (!STI.isR9Reserved())
383        return makeArrayRef(GPREven1);
384      else
385        return makeArrayRef(GPREven4);
386    } else if (FramePtr == ARM::R7) {
387      if (!STI.isR9Reserved())
388        return makeArrayRef(GPREven2);
389      else
390        return makeArrayRef(GPREven5);
391    } else { // FramePtr == ARM::R11
392      if (!STI.isR9Reserved())
393        return makeArrayRef(GPREven3);
394      else
395        return makeArrayRef(GPREven6);
396    }
397  } else if (HintType == ARMRI::RegPairOdd) {
398    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
399      // It's no longer possible to fulfill this hint. Return the default
400      // allocation order.
401      return RC->getRawAllocationOrder(MF);
402
403    if (!TFI->hasFP(MF)) {
404      if (!STI.isR9Reserved())
405        return makeArrayRef(GPROdd1);
406      else
407        return makeArrayRef(GPROdd4);
408    } else if (FramePtr == ARM::R7) {
409      if (!STI.isR9Reserved())
410        return makeArrayRef(GPROdd2);
411      else
412        return makeArrayRef(GPROdd5);
413    } else { // FramePtr == ARM::R11
414      if (!STI.isR9Reserved())
415        return makeArrayRef(GPROdd3);
416      else
417        return makeArrayRef(GPROdd6);
418    }
419  }
420  return RC->getRawAllocationOrder(MF);
421}
422
423/// ResolveRegAllocHint - Resolves the specified register allocation hint
424/// to a physical register. Returns the physical register if it is successful.
425unsigned
426ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
427                                         const MachineFunction &MF) const {
428  if (Reg == 0 || !isPhysicalRegister(Reg))
429    return 0;
430  if (Type == 0)
431    return Reg;
432  else if (Type == (unsigned)ARMRI::RegPairOdd)
433    // Odd register.
434    return getRegisterPairOdd(Reg, MF);
435  else if (Type == (unsigned)ARMRI::RegPairEven)
436    // Even register.
437    return getRegisterPairEven(Reg, MF);
438  return 0;
439}
440
441void
442ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
443                                        MachineFunction &MF) const {
444  MachineRegisterInfo *MRI = &MF.getRegInfo();
445  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
446  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
447       Hint.first == (unsigned)ARMRI::RegPairEven) &&
448      TargetRegisterInfo::isVirtualRegister(Hint.second)) {
449    // If 'Reg' is one of the even / odd register pair and it's now changed
450    // (e.g. coalesced) into a different register. The other register of the
451    // pair allocation hint must be updated to reflect the relationship
452    // change.
453    unsigned OtherReg = Hint.second;
454    Hint = MRI->getRegAllocationHint(OtherReg);
455    if (Hint.second == Reg)
456      // Make sure the pair has not already divorced.
457      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
458  }
459}
460
461bool
462ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
463  // CortexA9 has a Write-after-write hazard for NEON registers.
464  if (!STI.isCortexA9())
465    return false;
466
467  switch (RC->getID()) {
468  case ARM::DPRRegClassID:
469  case ARM::DPR_8RegClassID:
470  case ARM::DPR_VFP2RegClassID:
471  case ARM::QPRRegClassID:
472  case ARM::QPR_8RegClassID:
473  case ARM::QPR_VFP2RegClassID:
474  case ARM::SPRRegClassID:
475  case ARM::SPR_8RegClassID:
476    // Avoid reusing S, D, and Q registers.
477    // Don't increase register pressure for QQ and QQQQ.
478    return true;
479  default:
480    return false;
481  }
482}
483
484bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
485  const MachineFrameInfo *MFI = MF.getFrameInfo();
486  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
487
488  if (!EnableBasePointer)
489    return false;
490
491  if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
492    return true;
493
494  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
495  // negative range for ldr/str (255), and thumb1 is positive offsets only.
496  // It's going to be better to use the SP or Base Pointer instead. When there
497  // are variable sized objects, we can't reference off of the SP, so we
498  // reserve a Base Pointer.
499  if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
500    // Conservatively estimate whether the negative offset from the frame
501    // pointer will be sufficient to reach. If a function has a smallish
502    // frame, it's less likely to have lots of spills and callee saved
503    // space, so it's all more likely to be within range of the frame pointer.
504    // If it's wrong, the scavenger will still enable access to work, it just
505    // won't be optimal.
506    if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
507      return false;
508    return true;
509  }
510
511  return false;
512}
513
514bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
515  const MachineFrameInfo *MFI = MF.getFrameInfo();
516  const MachineRegisterInfo *MRI = &MF.getRegInfo();
517  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
518  // We can't realign the stack if:
519  // 1. Dynamic stack realignment is explicitly disabled,
520  // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
521  // 3. There are VLAs in the function and the base pointer is disabled.
522  if (!MF.getTarget().Options.RealignStack)
523    return false;
524  if (AFI->isThumb1OnlyFunction())
525    return false;
526  // Stack realignment requires a frame pointer.  If we already started
527  // register allocation with frame pointer elimination, it is too late now.
528  if (!MRI->canReserveReg(FramePtr))
529    return false;
530  // We may also need a base pointer if there are dynamic allocas.
531  if (!MFI->hasVarSizedObjects())
532    return true;
533  if (!EnableBasePointer)
534    return false;
535  // A base pointer is required and allowed.  Check that it isn't too late to
536  // reserve it.
537  return MRI->canReserveReg(BasePtr);
538}
539
540bool ARMBaseRegisterInfo::
541needsStackRealignment(const MachineFunction &MF) const {
542  const MachineFrameInfo *MFI = MF.getFrameInfo();
543  const Function *F = MF.getFunction();
544  unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
545  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
546                               F->hasFnAttr(Attribute::StackAlignment));
547
548  return requiresRealignment && canRealignStack(MF);
549}
550
551bool ARMBaseRegisterInfo::
552cannotEliminateFrame(const MachineFunction &MF) const {
553  const MachineFrameInfo *MFI = MF.getFrameInfo();
554  if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack())
555    return true;
556  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
557    || needsStackRealignment(MF);
558}
559
560unsigned
561ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
562  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
563
564  if (TFI->hasFP(MF))
565    return FramePtr;
566  return ARM::SP;
567}
568
569unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
570  llvm_unreachable("What is the exception register");
571}
572
573unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
574  llvm_unreachable("What is the exception handler register");
575}
576
577unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
578                                              const MachineFunction &MF) const {
579  switch (Reg) {
580  default: break;
581  // Return 0 if either register of the pair is a special register.
582  // So no R12, etc.
583  case ARM::R1: return ARM::R0;
584  case ARM::R3: return ARM::R2;
585  case ARM::R5: return ARM::R4;
586  case ARM::R7:
587    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
588      ? 0 : ARM::R6;
589  case ARM::R9: return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
590  case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
591
592  case ARM::S1: return ARM::S0;
593  case ARM::S3: return ARM::S2;
594  case ARM::S5: return ARM::S4;
595  case ARM::S7: return ARM::S6;
596  case ARM::S9: return ARM::S8;
597  case ARM::S11: return ARM::S10;
598  case ARM::S13: return ARM::S12;
599  case ARM::S15: return ARM::S14;
600  case ARM::S17: return ARM::S16;
601  case ARM::S19: return ARM::S18;
602  case ARM::S21: return ARM::S20;
603  case ARM::S23: return ARM::S22;
604  case ARM::S25: return ARM::S24;
605  case ARM::S27: return ARM::S26;
606  case ARM::S29: return ARM::S28;
607  case ARM::S31: return ARM::S30;
608
609  case ARM::D1: return ARM::D0;
610  case ARM::D3: return ARM::D2;
611  case ARM::D5: return ARM::D4;
612  case ARM::D7: return ARM::D6;
613  case ARM::D9: return ARM::D8;
614  case ARM::D11: return ARM::D10;
615  case ARM::D13: return ARM::D12;
616  case ARM::D15: return ARM::D14;
617  case ARM::D17: return ARM::D16;
618  case ARM::D19: return ARM::D18;
619  case ARM::D21: return ARM::D20;
620  case ARM::D23: return ARM::D22;
621  case ARM::D25: return ARM::D24;
622  case ARM::D27: return ARM::D26;
623  case ARM::D29: return ARM::D28;
624  case ARM::D31: return ARM::D30;
625  }
626
627  return 0;
628}
629
630unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
631                                             const MachineFunction &MF) const {
632  switch (Reg) {
633  default: break;
634  // Return 0 if either register of the pair is a special register.
635  // So no R12, etc.
636  case ARM::R0: return ARM::R1;
637  case ARM::R2: return ARM::R3;
638  case ARM::R4: return ARM::R5;
639  case ARM::R6:
640    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
641      ? 0 : ARM::R7;
642  case ARM::R8: return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
643  case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
644
645  case ARM::S0: return ARM::S1;
646  case ARM::S2: return ARM::S3;
647  case ARM::S4: return ARM::S5;
648  case ARM::S6: return ARM::S7;
649  case ARM::S8: return ARM::S9;
650  case ARM::S10: return ARM::S11;
651  case ARM::S12: return ARM::S13;
652  case ARM::S14: return ARM::S15;
653  case ARM::S16: return ARM::S17;
654  case ARM::S18: return ARM::S19;
655  case ARM::S20: return ARM::S21;
656  case ARM::S22: return ARM::S23;
657  case ARM::S24: return ARM::S25;
658  case ARM::S26: return ARM::S27;
659  case ARM::S28: return ARM::S29;
660  case ARM::S30: return ARM::S31;
661
662  case ARM::D0: return ARM::D1;
663  case ARM::D2: return ARM::D3;
664  case ARM::D4: return ARM::D5;
665  case ARM::D6: return ARM::D7;
666  case ARM::D8: return ARM::D9;
667  case ARM::D10: return ARM::D11;
668  case ARM::D12: return ARM::D13;
669  case ARM::D14: return ARM::D15;
670  case ARM::D16: return ARM::D17;
671  case ARM::D18: return ARM::D19;
672  case ARM::D20: return ARM::D21;
673  case ARM::D22: return ARM::D23;
674  case ARM::D24: return ARM::D25;
675  case ARM::D26: return ARM::D27;
676  case ARM::D28: return ARM::D29;
677  case ARM::D30: return ARM::D31;
678  }
679
680  return 0;
681}
682
683/// emitLoadConstPool - Emits a load from constpool to materialize the
684/// specified immediate.
685void ARMBaseRegisterInfo::
686emitLoadConstPool(MachineBasicBlock &MBB,
687                  MachineBasicBlock::iterator &MBBI,
688                  DebugLoc dl,
689                  unsigned DestReg, unsigned SubIdx, int Val,
690                  ARMCC::CondCodes Pred,
691                  unsigned PredReg, unsigned MIFlags) const {
692  MachineFunction &MF = *MBB.getParent();
693  MachineConstantPool *ConstantPool = MF.getConstantPool();
694  const Constant *C =
695        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
696  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
697
698  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
699    .addReg(DestReg, getDefRegState(true), SubIdx)
700    .addConstantPoolIndex(Idx)
701    .addImm(0).addImm(Pred).addReg(PredReg)
702    .setMIFlags(MIFlags);
703}
704
705bool ARMBaseRegisterInfo::
706requiresRegisterScavenging(const MachineFunction &MF) const {
707  return true;
708}
709
710bool ARMBaseRegisterInfo::
711requiresFrameIndexScavenging(const MachineFunction &MF) const {
712  return true;
713}
714
715bool ARMBaseRegisterInfo::
716requiresVirtualBaseRegisters(const MachineFunction &MF) const {
717  return EnableLocalStackAlloc;
718}
719
720static void
721emitSPUpdate(bool isARM,
722             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
723             DebugLoc dl, const ARMBaseInstrInfo &TII,
724             int NumBytes,
725             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
726  if (isARM)
727    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
728                            Pred, PredReg, TII);
729  else
730    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
731                           Pred, PredReg, TII);
732}
733
734
735void ARMBaseRegisterInfo::
736eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
737                              MachineBasicBlock::iterator I) const {
738  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
739  if (!TFI->hasReservedCallFrame(MF)) {
740    // If we have alloca, convert as follows:
741    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
742    // ADJCALLSTACKUP   -> add, sp, sp, amount
743    MachineInstr *Old = I;
744    DebugLoc dl = Old->getDebugLoc();
745    unsigned Amount = Old->getOperand(0).getImm();
746    if (Amount != 0) {
747      // We need to keep the stack aligned properly.  To do this, we round the
748      // amount of space needed for the outgoing arguments up to the next
749      // alignment boundary.
750      unsigned Align = TFI->getStackAlignment();
751      Amount = (Amount+Align-1)/Align*Align;
752
753      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
754      assert(!AFI->isThumb1OnlyFunction() &&
755             "This eliminateCallFramePseudoInstr does not support Thumb1!");
756      bool isARM = !AFI->isThumbFunction();
757
758      // Replace the pseudo instruction with a new instruction...
759      unsigned Opc = Old->getOpcode();
760      int PIdx = Old->findFirstPredOperandIdx();
761      ARMCC::CondCodes Pred = (PIdx == -1)
762        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
763      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
764        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
765        unsigned PredReg = Old->getOperand(2).getReg();
766        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
767      } else {
768        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
769        unsigned PredReg = Old->getOperand(3).getReg();
770        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
771        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
772      }
773    }
774  }
775  MBB.erase(I);
776}
777
778int64_t ARMBaseRegisterInfo::
779getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
780  const MCInstrDesc &Desc = MI->getDesc();
781  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
782  int64_t InstrOffs = 0;;
783  int Scale = 1;
784  unsigned ImmIdx = 0;
785  switch (AddrMode) {
786  case ARMII::AddrModeT2_i8:
787  case ARMII::AddrModeT2_i12:
788  case ARMII::AddrMode_i12:
789    InstrOffs = MI->getOperand(Idx+1).getImm();
790    Scale = 1;
791    break;
792  case ARMII::AddrMode5: {
793    // VFP address mode.
794    const MachineOperand &OffOp = MI->getOperand(Idx+1);
795    InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
796    if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
797      InstrOffs = -InstrOffs;
798    Scale = 4;
799    break;
800  }
801  case ARMII::AddrMode2: {
802    ImmIdx = Idx+2;
803    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
804    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
805      InstrOffs = -InstrOffs;
806    break;
807  }
808  case ARMII::AddrMode3: {
809    ImmIdx = Idx+2;
810    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
811    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
812      InstrOffs = -InstrOffs;
813    break;
814  }
815  case ARMII::AddrModeT1_s: {
816    ImmIdx = Idx+1;
817    InstrOffs = MI->getOperand(ImmIdx).getImm();
818    Scale = 4;
819    break;
820  }
821  default:
822    llvm_unreachable("Unsupported addressing mode!");
823  }
824
825  return InstrOffs * Scale;
826}
827
828/// needsFrameBaseReg - Returns true if the instruction's frame index
829/// reference would be better served by a base register other than FP
830/// or SP. Used by LocalStackFrameAllocation to determine which frame index
831/// references it should create new base registers for.
832bool ARMBaseRegisterInfo::
833needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
834  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
835    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
836  }
837
838  // It's the load/store FI references that cause issues, as it can be difficult
839  // to materialize the offset if it won't fit in the literal field. Estimate
840  // based on the size of the local frame and some conservative assumptions
841  // about the rest of the stack frame (note, this is pre-regalloc, so
842  // we don't know everything for certain yet) whether this offset is likely
843  // to be out of range of the immediate. Return true if so.
844
845  // We only generate virtual base registers for loads and stores, so
846  // return false for everything else.
847  unsigned Opc = MI->getOpcode();
848  switch (Opc) {
849  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
850  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
851  case ARM::t2LDRi12: case ARM::t2LDRi8:
852  case ARM::t2STRi12: case ARM::t2STRi8:
853  case ARM::VLDRS: case ARM::VLDRD:
854  case ARM::VSTRS: case ARM::VSTRD:
855  case ARM::tSTRspi: case ARM::tLDRspi:
856    if (ForceAllBaseRegAlloc)
857      return true;
858    break;
859  default:
860    return false;
861  }
862
863  // Without a virtual base register, if the function has variable sized
864  // objects, all fixed-size local references will be via the frame pointer,
865  // Approximate the offset and see if it's legal for the instruction.
866  // Note that the incoming offset is based on the SP value at function entry,
867  // so it'll be negative.
868  MachineFunction &MF = *MI->getParent()->getParent();
869  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
870  MachineFrameInfo *MFI = MF.getFrameInfo();
871  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
872
873  // Estimate an offset from the frame pointer.
874  // Conservatively assume all callee-saved registers get pushed. R4-R6
875  // will be earlier than the FP, so we ignore those.
876  // R7, LR
877  int64_t FPOffset = Offset - 8;
878  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
879  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
880    FPOffset -= 80;
881  // Estimate an offset from the stack pointer.
882  // The incoming offset is relating to the SP at the start of the function,
883  // but when we access the local it'll be relative to the SP after local
884  // allocation, so adjust our SP-relative offset by that allocation size.
885  Offset = -Offset;
886  Offset += MFI->getLocalFrameSize();
887  // Assume that we'll have at least some spill slots allocated.
888  // FIXME: This is a total SWAG number. We should run some statistics
889  //        and pick a real one.
890  Offset += 128; // 128 bytes of spill slots
891
892  // If there is a frame pointer, try using it.
893  // The FP is only available if there is no dynamic realignment. We
894  // don't know for sure yet whether we'll need that, so we guess based
895  // on whether there are any local variables that would trigger it.
896  unsigned StackAlign = TFI->getStackAlignment();
897  if (TFI->hasFP(MF) &&
898      !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
899    if (isFrameOffsetLegal(MI, FPOffset))
900      return false;
901  }
902  // If we can reference via the stack pointer, try that.
903  // FIXME: This (and the code that resolves the references) can be improved
904  //        to only disallow SP relative references in the live range of
905  //        the VLA(s). In practice, it's unclear how much difference that
906  //        would make, but it may be worth doing.
907  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
908    return false;
909
910  // The offset likely isn't legal, we want to allocate a virtual base register.
911  return true;
912}
913
914/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
915/// be a pointer to FrameIdx at the beginning of the basic block.
916void ARMBaseRegisterInfo::
917materializeFrameBaseRegister(MachineBasicBlock *MBB,
918                             unsigned BaseReg, int FrameIdx,
919                             int64_t Offset) const {
920  ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
921  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
922    (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
923
924  MachineBasicBlock::iterator Ins = MBB->begin();
925  DebugLoc DL;                  // Defaults to "unknown"
926  if (Ins != MBB->end())
927    DL = Ins->getDebugLoc();
928
929  const MCInstrDesc &MCID = TII.get(ADDriOpc);
930  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
931  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this));
932
933  MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
934    .addFrameIndex(FrameIdx).addImm(Offset));
935
936  if (!AFI->isThumb1OnlyFunction())
937    AddDefaultCC(MIB);
938}
939
940void
941ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
942                                       unsigned BaseReg, int64_t Offset) const {
943  MachineInstr &MI = *I;
944  MachineBasicBlock &MBB = *MI.getParent();
945  MachineFunction &MF = *MBB.getParent();
946  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
947  int Off = Offset; // ARM doesn't need the general 64-bit offsets
948  unsigned i = 0;
949
950  assert(!AFI->isThumb1OnlyFunction() &&
951         "This resolveFrameIndex does not support Thumb1!");
952
953  while (!MI.getOperand(i).isFI()) {
954    ++i;
955    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
956  }
957  bool Done = false;
958  if (!AFI->isThumbFunction())
959    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
960  else {
961    assert(AFI->isThumb2Function());
962    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
963  }
964  assert (Done && "Unable to resolve frame index!");
965  (void)Done;
966}
967
968bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
969                                             int64_t Offset) const {
970  const MCInstrDesc &Desc = MI->getDesc();
971  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
972  unsigned i = 0;
973
974  while (!MI->getOperand(i).isFI()) {
975    ++i;
976    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
977  }
978
979  // AddrMode4 and AddrMode6 cannot handle any offset.
980  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
981    return Offset == 0;
982
983  unsigned NumBits = 0;
984  unsigned Scale = 1;
985  bool isSigned = true;
986  switch (AddrMode) {
987  case ARMII::AddrModeT2_i8:
988  case ARMII::AddrModeT2_i12:
989    // i8 supports only negative, and i12 supports only positive, so
990    // based on Offset sign, consider the appropriate instruction
991    Scale = 1;
992    if (Offset < 0) {
993      NumBits = 8;
994      Offset = -Offset;
995    } else {
996      NumBits = 12;
997    }
998    break;
999  case ARMII::AddrMode5:
1000    // VFP address mode.
1001    NumBits = 8;
1002    Scale = 4;
1003    break;
1004  case ARMII::AddrMode_i12:
1005  case ARMII::AddrMode2:
1006    NumBits = 12;
1007    break;
1008  case ARMII::AddrMode3:
1009    NumBits = 8;
1010    break;
1011  case ARMII::AddrModeT1_s:
1012    NumBits = 5;
1013    Scale = 4;
1014    isSigned = false;
1015    break;
1016  default:
1017    llvm_unreachable("Unsupported addressing mode!");
1018  }
1019
1020  Offset += getFrameIndexInstrOffset(MI, i);
1021  // Make sure the offset is encodable for instructions that scale the
1022  // immediate.
1023  if ((Offset & (Scale-1)) != 0)
1024    return false;
1025
1026  if (isSigned && Offset < 0)
1027    Offset = -Offset;
1028
1029  unsigned Mask = (1 << NumBits) - 1;
1030  if ((unsigned)Offset <= Mask * Scale)
1031    return true;
1032
1033  return false;
1034}
1035
1036void
1037ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1038                                         int SPAdj, RegScavenger *RS) const {
1039  unsigned i = 0;
1040  MachineInstr &MI = *II;
1041  MachineBasicBlock &MBB = *MI.getParent();
1042  MachineFunction &MF = *MBB.getParent();
1043  const ARMFrameLowering *TFI =
1044    static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
1045  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1046  assert(!AFI->isThumb1OnlyFunction() &&
1047         "This eliminateFrameIndex does not support Thumb1!");
1048
1049  while (!MI.getOperand(i).isFI()) {
1050    ++i;
1051    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1052  }
1053
1054  int FrameIndex = MI.getOperand(i).getIndex();
1055  unsigned FrameReg;
1056
1057  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1058
1059  // Special handling of dbg_value instructions.
1060  if (MI.isDebugValue()) {
1061    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1062    MI.getOperand(i+1).ChangeToImmediate(Offset);
1063    return;
1064  }
1065
1066  // Modify MI as necessary to handle as much of 'Offset' as possible
1067  bool Done = false;
1068  if (!AFI->isThumbFunction())
1069    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1070  else {
1071    assert(AFI->isThumb2Function());
1072    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1073  }
1074  if (Done)
1075    return;
1076
1077  // If we get here, the immediate doesn't fit into the instruction.  We folded
1078  // as much as possible above, handle the rest, providing a register that is
1079  // SP+LargeImm.
1080  assert((Offset ||
1081          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1082          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1083         "This code isn't needed if offset already handled!");
1084
1085  unsigned ScratchReg = 0;
1086  int PIdx = MI.findFirstPredOperandIdx();
1087  ARMCC::CondCodes Pred = (PIdx == -1)
1088    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1089  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1090  if (Offset == 0)
1091    // Must be addrmode4/6.
1092    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1093  else {
1094    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1095    if (!AFI->isThumbFunction())
1096      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1097                              Offset, Pred, PredReg, TII);
1098    else {
1099      assert(AFI->isThumb2Function());
1100      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1101                             Offset, Pred, PredReg, TII);
1102    }
1103    // Update the original instruction to use the scratch register.
1104    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1105  }
1106}
1107