ARMBaseRegisterInfo.cpp revision dc140c6e7b8350ca51aa1d408c10e25a27826e2c 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42namespace llvm {
43cl::opt<bool>
44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true),
45          cl::desc("Reuse repeated frame index values"));
46}
47
48using namespace llvm;
49
50unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
51                                                   bool *isSPVFP) {
52  if (isSPVFP)
53    *isSPVFP = false;
54
55  using namespace ARM;
56  switch (RegEnum) {
57  default:
58    llvm_unreachable("Unknown ARM register!");
59  case R0:  case D0:  case Q0:  return 0;
60  case R1:  case D1:  case Q1:  return 1;
61  case R2:  case D2:  case Q2:  return 2;
62  case R3:  case D3:  case Q3:  return 3;
63  case R4:  case D4:  case Q4:  return 4;
64  case R5:  case D5:  case Q5:  return 5;
65  case R6:  case D6:  case Q6:  return 6;
66  case R7:  case D7:  case Q7:  return 7;
67  case R8:  case D8:  case Q8:  return 8;
68  case R9:  case D9:  case Q9:  return 9;
69  case R10: case D10: case Q10: return 10;
70  case R11: case D11: case Q11: return 11;
71  case R12: case D12: case Q12: return 12;
72  case SP:  case D13: case Q13: return 13;
73  case LR:  case D14: case Q14: return 14;
74  case PC:  case D15: case Q15: return 15;
75
76  case D16: return 16;
77  case D17: return 17;
78  case D18: return 18;
79  case D19: return 19;
80  case D20: return 20;
81  case D21: return 21;
82  case D22: return 22;
83  case D23: return 23;
84  case D24: return 24;
85  case D25: return 25;
86  case D26: return 26;
87  case D27: return 27;
88  case D28: return 28;
89  case D29: return 29;
90  case D30: return 30;
91  case D31: return 31;
92
93  case S0: case S1: case S2: case S3:
94  case S4: case S5: case S6: case S7:
95  case S8: case S9: case S10: case S11:
96  case S12: case S13: case S14: case S15:
97  case S16: case S17: case S18: case S19:
98  case S20: case S21: case S22: case S23:
99  case S24: case S25: case S26: case S27:
100  case S28: case S29: case S30: case S31: {
101    if (isSPVFP)
102      *isSPVFP = true;
103    switch (RegEnum) {
104    default: return 0; // Avoid compile time warning.
105    case S0: return 0;
106    case S1: return 1;
107    case S2: return 2;
108    case S3: return 3;
109    case S4: return 4;
110    case S5: return 5;
111    case S6: return 6;
112    case S7: return 7;
113    case S8: return 8;
114    case S9: return 9;
115    case S10: return 10;
116    case S11: return 11;
117    case S12: return 12;
118    case S13: return 13;
119    case S14: return 14;
120    case S15: return 15;
121    case S16: return 16;
122    case S17: return 17;
123    case S18: return 18;
124    case S19: return 19;
125    case S20: return 20;
126    case S21: return 21;
127    case S22: return 22;
128    case S23: return 23;
129    case S24: return 24;
130    case S25: return 25;
131    case S26: return 26;
132    case S27: return 27;
133    case S28: return 28;
134    case S29: return 29;
135    case S30: return 30;
136    case S31: return 31;
137    }
138  }
139  }
140}
141
142ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
143                                         const ARMSubtarget &sti)
144  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
145    TII(tii), STI(sti),
146    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
147}
148
149const unsigned*
150ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151  static const unsigned CalleeSavedRegs[] = {
152    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
153    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
154
155    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
156    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
157    0
158  };
159
160  static const unsigned DarwinCalleeSavedRegs[] = {
161    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
162    // register.
163    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
164    ARM::R11, ARM::R10, ARM::R8,
165
166    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
167    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
168    0
169  };
170  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
171}
172
173BitVector ARMBaseRegisterInfo::
174getReservedRegs(const MachineFunction &MF) const {
175  // FIXME: avoid re-calculating this everytime.
176  BitVector Reserved(getNumRegs());
177  Reserved.set(ARM::SP);
178  Reserved.set(ARM::PC);
179  Reserved.set(ARM::FPSCR);
180  if (hasFP(MF))
181    Reserved.set(FramePtr);
182  // Some targets reserve R9.
183  if (STI.isR9Reserved())
184    Reserved.set(ARM::R9);
185  return Reserved;
186}
187
188bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
189                                        unsigned Reg) const {
190  switch (Reg) {
191  default: break;
192  case ARM::SP:
193  case ARM::PC:
194    return true;
195  case ARM::R7:
196  case ARM::R11:
197    if (FramePtr == Reg && hasFP(MF))
198      return true;
199    break;
200  case ARM::R9:
201    return STI.isR9Reserved();
202  }
203
204  return false;
205}
206
207const TargetRegisterClass *
208ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
209                                              const TargetRegisterClass *B,
210                                              unsigned SubIdx) const {
211  switch (SubIdx) {
212  default: return 0;
213  case ARM::ssub_0:
214  case ARM::ssub_1:
215  case ARM::ssub_2:
216  case ARM::ssub_3: {
217    // S sub-registers.
218    if (A->getSize() == 8) {
219      if (B == &ARM::SPR_8RegClass)
220        return &ARM::DPR_8RegClass;
221      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
222      if (A == &ARM::DPR_8RegClass)
223        return A;
224      return &ARM::DPR_VFP2RegClass;
225    }
226
227    if (A->getSize() == 16) {
228      if (B == &ARM::SPR_8RegClass)
229        return &ARM::QPR_8RegClass;
230      return &ARM::QPR_VFP2RegClass;
231    }
232
233    if (A->getSize() == 32) {
234      if (B == &ARM::SPR_8RegClass)
235        return 0;  // Do not allow coalescing!
236      return &ARM::QQPR_VFP2RegClass;
237    }
238
239    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
240    return 0;  // Do not allow coalescing!
241  }
242  case ARM::dsub_0:
243  case ARM::dsub_1:
244  case ARM::dsub_2:
245  case ARM::dsub_3: {
246    // D sub-registers.
247    if (A->getSize() == 16) {
248      if (B == &ARM::DPR_VFP2RegClass)
249        return &ARM::QPR_VFP2RegClass;
250      if (B == &ARM::DPR_8RegClass)
251        return 0;  // Do not allow coalescing!
252      return A;
253    }
254
255    if (A->getSize() == 32) {
256      if (B == &ARM::DPR_VFP2RegClass)
257        return &ARM::QQPR_VFP2RegClass;
258      if (B == &ARM::DPR_8RegClass)
259        return 0;  // Do not allow coalescing!
260      return A;
261    }
262
263    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
264    if (B != &ARM::DPRRegClass)
265      return 0;  // Do not allow coalescing!
266    return A;
267  }
268  case ARM::dsub_4:
269  case ARM::dsub_5:
270  case ARM::dsub_6:
271  case ARM::dsub_7: {
272    // D sub-registers of QQQQ registers.
273    if (A->getSize() == 64 && B == &ARM::DPRRegClass)
274      return A;
275    return 0;  // Do not allow coalescing!
276  }
277
278  case ARM::qsub_0:
279  case ARM::qsub_1: {
280    // Q sub-registers.
281    if (A->getSize() == 32) {
282      if (B == &ARM::QPR_VFP2RegClass)
283        return &ARM::QQPR_VFP2RegClass;
284      if (B == &ARM::QPR_8RegClass)
285        return 0;  // Do not allow coalescing!
286      return A;
287    }
288
289    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
290    if (B == &ARM::QPRRegClass)
291      return A;
292    return 0;  // Do not allow coalescing!
293  }
294  case ARM::qsub_2:
295  case ARM::qsub_3: {
296    // Q sub-registers of QQQQ registers.
297    if (A->getSize() == 64 && B == &ARM::QPRRegClass)
298      return A;
299    return 0;  // Do not allow coalescing!
300  }
301  }
302  return 0;
303}
304
305bool
306ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
307                                          SmallVectorImpl<unsigned> &SubIndices,
308                                          unsigned &NewSubIdx) const {
309
310  unsigned Size = RC->getSize() * 8;
311  if (Size < 6)
312    return 0;
313
314  NewSubIdx = 0;  // Whole register.
315  unsigned NumRegs = SubIndices.size();
316  if (NumRegs == 8) {
317    // 8 D registers -> 1 QQQQ register.
318    return (Size == 512 &&
319            SubIndices[0] == ARM::dsub_0 &&
320            SubIndices[1] == ARM::dsub_1 &&
321            SubIndices[2] == ARM::dsub_2 &&
322            SubIndices[3] == ARM::dsub_3 &&
323            SubIndices[4] == ARM::dsub_4 &&
324            SubIndices[5] == ARM::dsub_5 &&
325            SubIndices[6] == ARM::dsub_6 &&
326            SubIndices[7] == ARM::dsub_7);
327  } else if (NumRegs == 4) {
328    if (SubIndices[0] == ARM::qsub_0) {
329      // 4 Q registers -> 1 QQQQ register.
330      return (Size == 512 &&
331              SubIndices[1] == ARM::qsub_1 &&
332              SubIndices[2] == ARM::qsub_2 &&
333              SubIndices[3] == ARM::qsub_3);
334    } else if (SubIndices[0] == ARM::dsub_0) {
335      // 4 D registers -> 1 QQ register.
336      if (Size >= 256 &&
337          SubIndices[1] == ARM::dsub_1 &&
338          SubIndices[2] == ARM::dsub_2 &&
339          SubIndices[3] == ARM::dsub_3) {
340        if (Size == 512)
341          NewSubIdx = ARM::qqsub_0;
342        return true;
343      }
344    } else if (SubIndices[0] == ARM::dsub_4) {
345      // 4 D registers -> 1 QQ register (2nd).
346      if (Size == 512 &&
347          SubIndices[1] == ARM::dsub_5 &&
348          SubIndices[2] == ARM::dsub_6 &&
349          SubIndices[3] == ARM::dsub_7) {
350        NewSubIdx = ARM::qqsub_1;
351        return true;
352      }
353    } else if (SubIndices[0] == ARM::ssub_0) {
354      // 4 S registers -> 1 Q register.
355      if (Size >= 128 &&
356          SubIndices[1] == ARM::ssub_1 &&
357          SubIndices[2] == ARM::ssub_2 &&
358          SubIndices[3] == ARM::ssub_3) {
359        if (Size >= 256)
360          NewSubIdx = ARM::qsub_0;
361        return true;
362      }
363    }
364  } else if (NumRegs == 2) {
365    if (SubIndices[0] == ARM::qsub_0) {
366      // 2 Q registers -> 1 QQ register.
367      if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
368        if (Size == 512)
369          NewSubIdx = ARM::qqsub_0;
370        return true;
371      }
372    } else if (SubIndices[0] == ARM::qsub_2) {
373      // 2 Q registers -> 1 QQ register (2nd).
374      if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
375        NewSubIdx = ARM::qqsub_1;
376        return true;
377      }
378    } else if (SubIndices[0] == ARM::dsub_0) {
379      // 2 D registers -> 1 Q register.
380      if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
381        if (Size >= 256)
382          NewSubIdx = ARM::qsub_0;
383        return true;
384      }
385    } else if (SubIndices[0] == ARM::dsub_2) {
386      // 2 D registers -> 1 Q register (2nd).
387      if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
388        NewSubIdx = ARM::qsub_1;
389        return true;
390      }
391    } else if (SubIndices[0] == ARM::dsub_4) {
392      // 2 D registers -> 1 Q register (3rd).
393      if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
394        NewSubIdx = ARM::qsub_2;
395        return true;
396      }
397    } else if (SubIndices[0] == ARM::dsub_6) {
398      // 2 D registers -> 1 Q register (3rd).
399      if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
400        NewSubIdx = ARM::qsub_3;
401        return true;
402      }
403    } else if (SubIndices[0] == ARM::ssub_0) {
404      // 2 S registers -> 1 D register.
405      if (SubIndices[1] == ARM::ssub_1) {
406        if (Size >= 128)
407          NewSubIdx = ARM::dsub_0;
408        return true;
409      }
410    } else if (SubIndices[0] == ARM::ssub_2) {
411      // 2 S registers -> 1 D register (2nd).
412      if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
413        NewSubIdx = ARM::dsub_1;
414        return true;
415      }
416    }
417  }
418  return false;
419}
420
421
422const TargetRegisterClass *
423ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
424  return ARM::GPRRegisterClass;
425}
426
427/// getAllocationOrder - Returns the register allocation order for a specified
428/// register class in the form of a pair of TargetRegisterClass iterators.
429std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
430ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
431                                        unsigned HintType, unsigned HintReg,
432                                        const MachineFunction &MF) const {
433  // Alternative register allocation orders when favoring even / odd registers
434  // of register pairs.
435
436  // No FP, R9 is available.
437  static const unsigned GPREven1[] = {
438    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
439    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
440    ARM::R9, ARM::R11
441  };
442  static const unsigned GPROdd1[] = {
443    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
444    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
445    ARM::R8, ARM::R10
446  };
447
448  // FP is R7, R9 is available.
449  static const unsigned GPREven2[] = {
450    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
451    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
452    ARM::R9, ARM::R11
453  };
454  static const unsigned GPROdd2[] = {
455    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
456    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
457    ARM::R8, ARM::R10
458  };
459
460  // FP is R11, R9 is available.
461  static const unsigned GPREven3[] = {
462    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
463    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
464    ARM::R9
465  };
466  static const unsigned GPROdd3[] = {
467    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
468    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
469    ARM::R8
470  };
471
472  // No FP, R9 is not available.
473  static const unsigned GPREven4[] = {
474    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
475    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
476    ARM::R11
477  };
478  static const unsigned GPROdd4[] = {
479    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
480    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
481    ARM::R10
482  };
483
484  // FP is R7, R9 is not available.
485  static const unsigned GPREven5[] = {
486    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
487    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
488    ARM::R11
489  };
490  static const unsigned GPROdd5[] = {
491    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
492    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
493    ARM::R10
494  };
495
496  // FP is R11, R9 is not available.
497  static const unsigned GPREven6[] = {
498    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
499    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
500  };
501  static const unsigned GPROdd6[] = {
502    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
503    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
504  };
505
506
507  if (HintType == ARMRI::RegPairEven) {
508    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
509      // It's no longer possible to fulfill this hint. Return the default
510      // allocation order.
511      return std::make_pair(RC->allocation_order_begin(MF),
512                            RC->allocation_order_end(MF));
513
514    if (!hasFP(MF)) {
515      if (!STI.isR9Reserved())
516        return std::make_pair(GPREven1,
517                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
518      else
519        return std::make_pair(GPREven4,
520                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
521    } else if (FramePtr == ARM::R7) {
522      if (!STI.isR9Reserved())
523        return std::make_pair(GPREven2,
524                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
525      else
526        return std::make_pair(GPREven5,
527                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
528    } else { // FramePtr == ARM::R11
529      if (!STI.isR9Reserved())
530        return std::make_pair(GPREven3,
531                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
532      else
533        return std::make_pair(GPREven6,
534                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
535    }
536  } else if (HintType == ARMRI::RegPairOdd) {
537    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
538      // It's no longer possible to fulfill this hint. Return the default
539      // allocation order.
540      return std::make_pair(RC->allocation_order_begin(MF),
541                            RC->allocation_order_end(MF));
542
543    if (!hasFP(MF)) {
544      if (!STI.isR9Reserved())
545        return std::make_pair(GPROdd1,
546                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
547      else
548        return std::make_pair(GPROdd4,
549                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
550    } else if (FramePtr == ARM::R7) {
551      if (!STI.isR9Reserved())
552        return std::make_pair(GPROdd2,
553                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
554      else
555        return std::make_pair(GPROdd5,
556                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
557    } else { // FramePtr == ARM::R11
558      if (!STI.isR9Reserved())
559        return std::make_pair(GPROdd3,
560                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
561      else
562        return std::make_pair(GPROdd6,
563                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
564    }
565  }
566  return std::make_pair(RC->allocation_order_begin(MF),
567                        RC->allocation_order_end(MF));
568}
569
570/// ResolveRegAllocHint - Resolves the specified register allocation hint
571/// to a physical register. Returns the physical register if it is successful.
572unsigned
573ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
574                                         const MachineFunction &MF) const {
575  if (Reg == 0 || !isPhysicalRegister(Reg))
576    return 0;
577  if (Type == 0)
578    return Reg;
579  else if (Type == (unsigned)ARMRI::RegPairOdd)
580    // Odd register.
581    return getRegisterPairOdd(Reg, MF);
582  else if (Type == (unsigned)ARMRI::RegPairEven)
583    // Even register.
584    return getRegisterPairEven(Reg, MF);
585  return 0;
586}
587
588void
589ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
590                                        MachineFunction &MF) const {
591  MachineRegisterInfo *MRI = &MF.getRegInfo();
592  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
593  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
594       Hint.first == (unsigned)ARMRI::RegPairEven) &&
595      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
596    // If 'Reg' is one of the even / odd register pair and it's now changed
597    // (e.g. coalesced) into a different register. The other register of the
598    // pair allocation hint must be updated to reflect the relationship
599    // change.
600    unsigned OtherReg = Hint.second;
601    Hint = MRI->getRegAllocationHint(OtherReg);
602    if (Hint.second == Reg)
603      // Make sure the pair has not already divorced.
604      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
605  }
606}
607
608/// hasFP - Return true if the specified function should have a dedicated frame
609/// pointer register.  This is true if the function has variable sized allocas
610/// or if frame pointer elimination is disabled.
611///
612bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
613  // Mac OS X requires FP not to be clobbered for backtracing purpose.
614  if (STI.isTargetDarwin())
615    return true;
616
617  const MachineFrameInfo *MFI = MF.getFrameInfo();
618  // Always eliminate non-leaf frame pointers.
619  return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
620          needsStackRealignment(MF) ||
621          MFI->hasVarSizedObjects() ||
622          MFI->isFrameAddressTaken());
623}
624
625bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
626  const MachineFrameInfo *MFI = MF.getFrameInfo();
627  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
628  return (RealignStack &&
629          !AFI->isThumb1OnlyFunction() &&
630          !MFI->hasVarSizedObjects());
631}
632
633bool ARMBaseRegisterInfo::
634needsStackRealignment(const MachineFunction &MF) const {
635  const MachineFrameInfo *MFI = MF.getFrameInfo();
636  const Function *F = MF.getFunction();
637  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
638  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
639  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
640                               F->hasFnAttr(Attribute::StackAlignment));
641
642  // FIXME: Currently we don't support stack realignment for functions with
643  //        variable-sized allocas.
644  // FIXME: It's more complicated than this...
645  if (0 && requiresRealignment && MFI->hasVarSizedObjects())
646    report_fatal_error(
647      "Stack realignment in presense of dynamic allocas is not supported");
648
649  // FIXME: This probably isn't the right place for this.
650  if (0 && requiresRealignment && AFI->isThumb1OnlyFunction())
651    report_fatal_error(
652      "Stack realignment in thumb1 functions is not supported");
653
654  return requiresRealignment && canRealignStack(MF);
655}
656
657bool ARMBaseRegisterInfo::
658cannotEliminateFrame(const MachineFunction &MF) const {
659  const MachineFrameInfo *MFI = MF.getFrameInfo();
660  if (DisableFramePointerElim(MF) && MFI->adjustsStack())
661    return true;
662  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
663    || needsStackRealignment(MF);
664}
665
666/// estimateStackSize - Estimate and return the size of the frame.
667static unsigned estimateStackSize(MachineFunction &MF) {
668  const MachineFrameInfo *FFI = MF.getFrameInfo();
669  int Offset = 0;
670  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
671    int FixedOff = -FFI->getObjectOffset(i);
672    if (FixedOff > Offset) Offset = FixedOff;
673  }
674  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
675    if (FFI->isDeadObjectIndex(i))
676      continue;
677    Offset += FFI->getObjectSize(i);
678    unsigned Align = FFI->getObjectAlignment(i);
679    // Adjust to alignment boundary
680    Offset = (Offset+Align-1)/Align*Align;
681  }
682  return (unsigned)Offset;
683}
684
685/// estimateRSStackSizeLimit - Look at each instruction that references stack
686/// frames and return the stack size limit beyond which some of these
687/// instructions will require a scratch register during their expansion later.
688unsigned
689ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
690  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
691  unsigned Limit = (1 << 12) - 1;
692  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
693    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
694         I != E; ++I) {
695      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
696        if (!I->getOperand(i).isFI()) continue;
697
698        // When using ADDri to get the address of a stack object, 255 is the
699        // largest offset guaranteed to fit in the immediate offset.
700        if (I->getOpcode() == ARM::ADDri) {
701          Limit = std::min(Limit, (1U << 8) - 1);
702          break;
703        }
704
705        // Otherwise check the addressing mode.
706        switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
707        case ARMII::AddrMode3:
708        case ARMII::AddrModeT2_i8:
709          Limit = std::min(Limit, (1U << 8) - 1);
710          break;
711        case ARMII::AddrMode5:
712        case ARMII::AddrModeT2_i8s4:
713          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
714          break;
715        case ARMII::AddrModeT2_i12:
716          // i12 supports only positive offset so these will be converted to
717          // i8 opcodes. See llvm::rewriteT2FrameIndex.
718          if (hasFP(MF) && AFI->hasStackFrame())
719            Limit = std::min(Limit, (1U << 8) - 1);
720          break;
721        case ARMII::AddrMode6:
722          // Addressing mode 6 (load/store) instructions can't encode an
723          // immediate offset for stack references.
724          return 0;
725        default:
726          break;
727        }
728        break; // At most one FI per instruction
729      }
730    }
731  }
732
733  return Limit;
734}
735
736static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
737                                       const ARMBaseInstrInfo &TII) {
738  unsigned FnSize = 0;
739  for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
740       MBBI != E; ++MBBI) {
741    const MachineBasicBlock &MBB = *MBBI;
742    for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
743         I != E; ++I)
744      FnSize += TII.GetInstSizeInBytes(I);
745  }
746  return FnSize;
747}
748
749void
750ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
751                                                       RegScavenger *RS) const {
752  // This tells PEI to spill the FP as if it is any other callee-save register
753  // to take advantage the eliminateFrameIndex machinery. This also ensures it
754  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
755  // to combine multiple loads / stores.
756  bool CanEliminateFrame = true;
757  bool CS1Spilled = false;
758  bool LRSpilled = false;
759  unsigned NumGPRSpills = 0;
760  SmallVector<unsigned, 4> UnspilledCS1GPRs;
761  SmallVector<unsigned, 4> UnspilledCS2GPRs;
762  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
763  MachineFrameInfo *MFI = MF.getFrameInfo();
764
765  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
766  // scratch register.
767  // FIXME: It will be better just to find spare register here.
768  if (needsStackRealignment(MF) &&
769      AFI->isThumb2Function())
770    MF.getRegInfo().setPhysRegUsed(ARM::R4);
771
772  // Spill LR if Thumb1 function uses variable length argument lists.
773  if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
774    MF.getRegInfo().setPhysRegUsed(ARM::LR);
775
776  // Don't spill FP if the frame can be eliminated. This is determined
777  // by scanning the callee-save registers to see if any is used.
778  const unsigned *CSRegs = getCalleeSavedRegs();
779  for (unsigned i = 0; CSRegs[i]; ++i) {
780    unsigned Reg = CSRegs[i];
781    bool Spilled = false;
782    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
783      AFI->setCSRegisterIsSpilled(Reg);
784      Spilled = true;
785      CanEliminateFrame = false;
786    } else {
787      // Check alias registers too.
788      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
789        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
790          Spilled = true;
791          CanEliminateFrame = false;
792        }
793      }
794    }
795
796    if (!ARM::GPRRegisterClass->contains(Reg))
797      continue;
798
799    if (Spilled) {
800      NumGPRSpills++;
801
802      if (!STI.isTargetDarwin()) {
803        if (Reg == ARM::LR)
804          LRSpilled = true;
805        CS1Spilled = true;
806        continue;
807      }
808
809      // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
810      switch (Reg) {
811      case ARM::LR:
812        LRSpilled = true;
813        // Fallthrough
814      case ARM::R4:
815      case ARM::R5:
816      case ARM::R6:
817      case ARM::R7:
818        CS1Spilled = true;
819        break;
820      default:
821        break;
822      }
823    } else {
824      if (!STI.isTargetDarwin()) {
825        UnspilledCS1GPRs.push_back(Reg);
826        continue;
827      }
828
829      switch (Reg) {
830      case ARM::R4:
831      case ARM::R5:
832      case ARM::R6:
833      case ARM::R7:
834      case ARM::LR:
835        UnspilledCS1GPRs.push_back(Reg);
836        break;
837      default:
838        UnspilledCS2GPRs.push_back(Reg);
839        break;
840      }
841    }
842  }
843
844  bool ForceLRSpill = false;
845  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
846    unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
847    // Force LR to be spilled if the Thumb function size is > 2048. This enables
848    // use of BL to implement far jump. If it turns out that it's not needed
849    // then the branch fix up path will undo it.
850    if (FnSize >= (1 << 11)) {
851      CanEliminateFrame = false;
852      ForceLRSpill = true;
853    }
854  }
855
856  // If any of the stack slot references may be out of range of an immediate
857  // offset, make sure a register (or a spill slot) is available for the
858  // register scavenger. Note that if we're indexing off the frame pointer, the
859  // effective stack size is 4 bytes larger since the FP points to the stack
860  // slot of the previous FP. Also, if we have variable sized objects in the
861  // function, stack slot references will often be negative, and some of
862  // our instructions are positive-offset only, so conservatively consider
863  // that case to want a spill slot (or register) as well. Similarly, if
864  // the function adjusts the stack pointer during execution and the
865  // adjustments aren't already part of our stack size estimate, our offset
866  // calculations may be off, so be conservative.
867  // FIXME: We could add logic to be more precise about negative offsets
868  //        and which instructions will need a scratch register for them. Is it
869  //        worth the effort and added fragility?
870  bool BigStack =
871    (RS &&
872     (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
873      estimateRSStackSizeLimit(MF)))
874    || MFI->hasVarSizedObjects()
875    || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
876
877  bool ExtraCSSpill = false;
878  if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
879    AFI->setHasStackFrame(true);
880
881    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
882    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
883    if (!LRSpilled && CS1Spilled) {
884      MF.getRegInfo().setPhysRegUsed(ARM::LR);
885      AFI->setCSRegisterIsSpilled(ARM::LR);
886      NumGPRSpills++;
887      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
888                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
889      ForceLRSpill = false;
890      ExtraCSSpill = true;
891    }
892
893    if (hasFP(MF)) {
894      MF.getRegInfo().setPhysRegUsed(FramePtr);
895      NumGPRSpills++;
896    }
897
898    // If stack and double are 8-byte aligned and we are spilling an odd number
899    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
900    // the integer and double callee save areas.
901    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
902    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
903      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
904        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
905          unsigned Reg = UnspilledCS1GPRs[i];
906          // Don't spill high register if the function is thumb1
907          if (!AFI->isThumb1OnlyFunction() ||
908              isARMLowRegister(Reg) || Reg == ARM::LR) {
909            MF.getRegInfo().setPhysRegUsed(Reg);
910            AFI->setCSRegisterIsSpilled(Reg);
911            if (!isReservedReg(MF, Reg))
912              ExtraCSSpill = true;
913            break;
914          }
915        }
916      } else if (!UnspilledCS2GPRs.empty() &&
917                 !AFI->isThumb1OnlyFunction()) {
918        unsigned Reg = UnspilledCS2GPRs.front();
919        MF.getRegInfo().setPhysRegUsed(Reg);
920        AFI->setCSRegisterIsSpilled(Reg);
921        if (!isReservedReg(MF, Reg))
922          ExtraCSSpill = true;
923      }
924    }
925
926    // Estimate if we might need to scavenge a register at some point in order
927    // to materialize a stack offset. If so, either spill one additional
928    // callee-saved register or reserve a special spill slot to facilitate
929    // register scavenging. Thumb1 needs a spill slot for stack pointer
930    // adjustments also, even when the frame itself is small.
931    if (BigStack && !ExtraCSSpill) {
932      // If any non-reserved CS register isn't spilled, just spill one or two
933      // extra. That should take care of it!
934      unsigned NumExtras = TargetAlign / 4;
935      SmallVector<unsigned, 2> Extras;
936      while (NumExtras && !UnspilledCS1GPRs.empty()) {
937        unsigned Reg = UnspilledCS1GPRs.back();
938        UnspilledCS1GPRs.pop_back();
939        if (!isReservedReg(MF, Reg) &&
940            (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
941             Reg == ARM::LR)) {
942          Extras.push_back(Reg);
943          NumExtras--;
944        }
945      }
946      // For non-Thumb1 functions, also check for hi-reg CS registers
947      if (!AFI->isThumb1OnlyFunction()) {
948        while (NumExtras && !UnspilledCS2GPRs.empty()) {
949          unsigned Reg = UnspilledCS2GPRs.back();
950          UnspilledCS2GPRs.pop_back();
951          if (!isReservedReg(MF, Reg)) {
952            Extras.push_back(Reg);
953            NumExtras--;
954          }
955        }
956      }
957      if (Extras.size() && NumExtras == 0) {
958        for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
959          MF.getRegInfo().setPhysRegUsed(Extras[i]);
960          AFI->setCSRegisterIsSpilled(Extras[i]);
961        }
962      } else if (!AFI->isThumb1OnlyFunction()) {
963        // note: Thumb1 functions spill to R12, not the stack.  Reserve a slot
964        // closest to SP or frame pointer.
965        const TargetRegisterClass *RC = ARM::GPRRegisterClass;
966        RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
967                                                           RC->getAlignment(),
968                                                           false));
969      }
970    }
971  }
972
973  if (ForceLRSpill) {
974    MF.getRegInfo().setPhysRegUsed(ARM::LR);
975    AFI->setCSRegisterIsSpilled(ARM::LR);
976    AFI->setLRIsSpilledForFarJump(true);
977  }
978}
979
980unsigned ARMBaseRegisterInfo::getRARegister() const {
981  return ARM::LR;
982}
983
984unsigned
985ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
986  if (hasFP(MF))
987    return FramePtr;
988  return ARM::SP;
989}
990
991// Provide a base+offset reference to an FI slot for debug info. It's the
992// same as what we use for resolving the code-gen references for now.
993// FIXME: This can go wrong when references are SP-relative and simple call
994//        frames aren't used.
995int
996ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
997                                            unsigned &FrameReg) const {
998  return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
999}
1000
1001int
1002ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
1003                                                int FI,
1004                                                unsigned &FrameReg,
1005                                                int SPAdj) const {
1006  const MachineFrameInfo *MFI = MF.getFrameInfo();
1007  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1008  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
1009  int FPOffset = Offset - AFI->getFramePtrSpillOffset();
1010  bool isFixed = MFI->isFixedObjectIndex(FI);
1011
1012  FrameReg = ARM::SP;
1013  Offset += SPAdj;
1014  if (AFI->isGPRCalleeSavedArea1Frame(FI))
1015    return Offset - AFI->getGPRCalleeSavedArea1Offset();
1016  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
1017    return Offset - AFI->getGPRCalleeSavedArea2Offset();
1018  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
1019    return Offset - AFI->getDPRCalleeSavedAreaOffset();
1020
1021  // When dynamically realigning the stack, use the frame pointer for
1022  // parameters, and the stack pointer for locals.
1023  if (needsStackRealignment(MF)) {
1024    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
1025    if (isFixed) {
1026      FrameReg = getFrameRegister(MF);
1027      Offset = FPOffset;
1028    }
1029    return Offset;
1030  }
1031
1032  // If there is a frame pointer, use it when we can.
1033  if (hasFP(MF) && AFI->hasStackFrame()) {
1034    // Use frame pointer to reference fixed objects. Use it for locals if
1035    // there are VLAs (and thus the SP isn't reliable as a base).
1036    if (isFixed || MFI->hasVarSizedObjects()) {
1037      FrameReg = getFrameRegister(MF);
1038      Offset = FPOffset;
1039    } else if (AFI->isThumb2Function()) {
1040      // In Thumb2 mode, the negative offset is very limited. Try to avoid
1041      // out of range references.
1042      if (FPOffset >= -255 && FPOffset < 0) {
1043        FrameReg = getFrameRegister(MF);
1044        Offset = FPOffset;
1045      }
1046    } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1047      // Otherwise, use SP or FP, whichever is closer to the stack slot.
1048      FrameReg = getFrameRegister(MF);
1049      Offset = FPOffset;
1050    }
1051  }
1052  return Offset;
1053}
1054
1055int
1056ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1057                                         int FI) const {
1058  unsigned FrameReg;
1059  return getFrameIndexReference(MF, FI, FrameReg);
1060}
1061
1062unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1063  llvm_unreachable("What is the exception register");
1064  return 0;
1065}
1066
1067unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1068  llvm_unreachable("What is the exception handler register");
1069  return 0;
1070}
1071
1072int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1073  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1074}
1075
1076unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1077                                              const MachineFunction &MF) const {
1078  switch (Reg) {
1079  default: break;
1080  // Return 0 if either register of the pair is a special register.
1081  // So no R12, etc.
1082  case ARM::R1:
1083    return ARM::R0;
1084  case ARM::R3:
1085    return ARM::R2;
1086  case ARM::R5:
1087    return ARM::R4;
1088  case ARM::R7:
1089    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
1090  case ARM::R9:
1091    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
1092  case ARM::R11:
1093    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1094
1095  case ARM::S1:
1096    return ARM::S0;
1097  case ARM::S3:
1098    return ARM::S2;
1099  case ARM::S5:
1100    return ARM::S4;
1101  case ARM::S7:
1102    return ARM::S6;
1103  case ARM::S9:
1104    return ARM::S8;
1105  case ARM::S11:
1106    return ARM::S10;
1107  case ARM::S13:
1108    return ARM::S12;
1109  case ARM::S15:
1110    return ARM::S14;
1111  case ARM::S17:
1112    return ARM::S16;
1113  case ARM::S19:
1114    return ARM::S18;
1115  case ARM::S21:
1116    return ARM::S20;
1117  case ARM::S23:
1118    return ARM::S22;
1119  case ARM::S25:
1120    return ARM::S24;
1121  case ARM::S27:
1122    return ARM::S26;
1123  case ARM::S29:
1124    return ARM::S28;
1125  case ARM::S31:
1126    return ARM::S30;
1127
1128  case ARM::D1:
1129    return ARM::D0;
1130  case ARM::D3:
1131    return ARM::D2;
1132  case ARM::D5:
1133    return ARM::D4;
1134  case ARM::D7:
1135    return ARM::D6;
1136  case ARM::D9:
1137    return ARM::D8;
1138  case ARM::D11:
1139    return ARM::D10;
1140  case ARM::D13:
1141    return ARM::D12;
1142  case ARM::D15:
1143    return ARM::D14;
1144  case ARM::D17:
1145    return ARM::D16;
1146  case ARM::D19:
1147    return ARM::D18;
1148  case ARM::D21:
1149    return ARM::D20;
1150  case ARM::D23:
1151    return ARM::D22;
1152  case ARM::D25:
1153    return ARM::D24;
1154  case ARM::D27:
1155    return ARM::D26;
1156  case ARM::D29:
1157    return ARM::D28;
1158  case ARM::D31:
1159    return ARM::D30;
1160  }
1161
1162  return 0;
1163}
1164
1165unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1166                                             const MachineFunction &MF) const {
1167  switch (Reg) {
1168  default: break;
1169  // Return 0 if either register of the pair is a special register.
1170  // So no R12, etc.
1171  case ARM::R0:
1172    return ARM::R1;
1173  case ARM::R2:
1174    return ARM::R3;
1175  case ARM::R4:
1176    return ARM::R5;
1177  case ARM::R6:
1178    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
1179  case ARM::R8:
1180    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
1181  case ARM::R10:
1182    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1183
1184  case ARM::S0:
1185    return ARM::S1;
1186  case ARM::S2:
1187    return ARM::S3;
1188  case ARM::S4:
1189    return ARM::S5;
1190  case ARM::S6:
1191    return ARM::S7;
1192  case ARM::S8:
1193    return ARM::S9;
1194  case ARM::S10:
1195    return ARM::S11;
1196  case ARM::S12:
1197    return ARM::S13;
1198  case ARM::S14:
1199    return ARM::S15;
1200  case ARM::S16:
1201    return ARM::S17;
1202  case ARM::S18:
1203    return ARM::S19;
1204  case ARM::S20:
1205    return ARM::S21;
1206  case ARM::S22:
1207    return ARM::S23;
1208  case ARM::S24:
1209    return ARM::S25;
1210  case ARM::S26:
1211    return ARM::S27;
1212  case ARM::S28:
1213    return ARM::S29;
1214  case ARM::S30:
1215    return ARM::S31;
1216
1217  case ARM::D0:
1218    return ARM::D1;
1219  case ARM::D2:
1220    return ARM::D3;
1221  case ARM::D4:
1222    return ARM::D5;
1223  case ARM::D6:
1224    return ARM::D7;
1225  case ARM::D8:
1226    return ARM::D9;
1227  case ARM::D10:
1228    return ARM::D11;
1229  case ARM::D12:
1230    return ARM::D13;
1231  case ARM::D14:
1232    return ARM::D15;
1233  case ARM::D16:
1234    return ARM::D17;
1235  case ARM::D18:
1236    return ARM::D19;
1237  case ARM::D20:
1238    return ARM::D21;
1239  case ARM::D22:
1240    return ARM::D23;
1241  case ARM::D24:
1242    return ARM::D25;
1243  case ARM::D26:
1244    return ARM::D27;
1245  case ARM::D28:
1246    return ARM::D29;
1247  case ARM::D30:
1248    return ARM::D31;
1249  }
1250
1251  return 0;
1252}
1253
1254/// emitLoadConstPool - Emits a load from constpool to materialize the
1255/// specified immediate.
1256void ARMBaseRegisterInfo::
1257emitLoadConstPool(MachineBasicBlock &MBB,
1258                  MachineBasicBlock::iterator &MBBI,
1259                  DebugLoc dl,
1260                  unsigned DestReg, unsigned SubIdx, int Val,
1261                  ARMCC::CondCodes Pred,
1262                  unsigned PredReg) const {
1263  MachineFunction &MF = *MBB.getParent();
1264  MachineConstantPool *ConstantPool = MF.getConstantPool();
1265  const Constant *C =
1266        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1267  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1268
1269  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1270    .addReg(DestReg, getDefRegState(true), SubIdx)
1271    .addConstantPoolIndex(Idx)
1272    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1273}
1274
1275bool ARMBaseRegisterInfo::
1276requiresRegisterScavenging(const MachineFunction &MF) const {
1277  return true;
1278}
1279
1280bool ARMBaseRegisterInfo::
1281requiresFrameIndexScavenging(const MachineFunction &MF) const {
1282  return true;
1283}
1284
1285// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1286// not required, we reserve argument space for call sites in the function
1287// immediately on entry to the current function. This eliminates the need for
1288// add/sub sp brackets around call sites. Returns true if the call frame is
1289// included as part of the stack frame.
1290bool ARMBaseRegisterInfo::
1291hasReservedCallFrame(const MachineFunction &MF) const {
1292  const MachineFrameInfo *FFI = MF.getFrameInfo();
1293  unsigned CFSize = FFI->getMaxCallFrameSize();
1294  // It's not always a good idea to include the call frame as part of the
1295  // stack frame. ARM (especially Thumb) has small immediate offset to
1296  // address the stack frame. So a large call frame can cause poor codegen
1297  // and may even makes it impossible to scavenge a register.
1298  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1299    return false;
1300
1301  return !MF.getFrameInfo()->hasVarSizedObjects();
1302}
1303
1304// canSimplifyCallFramePseudos - If there is a reserved call frame, the
1305// call frame pseudos can be simplified. Unlike most targets, having a FP
1306// is not sufficient here since we still may reference some objects via SP
1307// even when FP is available in Thumb2 mode.
1308bool ARMBaseRegisterInfo::
1309canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1310  return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1311}
1312
1313static void
1314emitSPUpdate(bool isARM,
1315             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1316             DebugLoc dl, const ARMBaseInstrInfo &TII,
1317             int NumBytes,
1318             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1319  if (isARM)
1320    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1321                            Pred, PredReg, TII);
1322  else
1323    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1324                           Pred, PredReg, TII);
1325}
1326
1327
1328void ARMBaseRegisterInfo::
1329eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1330                              MachineBasicBlock::iterator I) const {
1331  if (!hasReservedCallFrame(MF)) {
1332    // If we have alloca, convert as follows:
1333    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1334    // ADJCALLSTACKUP   -> add, sp, sp, amount
1335    MachineInstr *Old = I;
1336    DebugLoc dl = Old->getDebugLoc();
1337    unsigned Amount = Old->getOperand(0).getImm();
1338    if (Amount != 0) {
1339      // We need to keep the stack aligned properly.  To do this, we round the
1340      // amount of space needed for the outgoing arguments up to the next
1341      // alignment boundary.
1342      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1343      Amount = (Amount+Align-1)/Align*Align;
1344
1345      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1346      assert(!AFI->isThumb1OnlyFunction() &&
1347             "This eliminateCallFramePseudoInstr does not support Thumb1!");
1348      bool isARM = !AFI->isThumbFunction();
1349
1350      // Replace the pseudo instruction with a new instruction...
1351      unsigned Opc = Old->getOpcode();
1352      int PIdx = Old->findFirstPredOperandIdx();
1353      ARMCC::CondCodes Pred = (PIdx == -1)
1354        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1355      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1356        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1357        unsigned PredReg = Old->getOperand(2).getReg();
1358        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1359      } else {
1360        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1361        unsigned PredReg = Old->getOperand(3).getReg();
1362        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1363        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1364      }
1365    }
1366  }
1367  MBB.erase(I);
1368}
1369
1370/// needsFrameBaseReg - Returns true if the instruction's frame index
1371/// reference would be better served by a base register other than FP
1372/// or SP. Used by LocalStackFrameAllocation to determine which frame index
1373/// references it should create new base registers for.
1374bool ARMBaseRegisterInfo::
1375needsFrameBaseReg(MachineInstr *MI, unsigned operand) const {
1376  assert (MI->getOperand(operand).isFI() &&
1377          "needsFrameBaseReg() called on non Frame Index operand!");
1378
1379  // It's the load/store FI references that cause issues, as it can be difficult
1380  // to materialize the offset if it won't fit in the literal field. Estimate
1381  // based on the size of the local frame and some conservative assumptions
1382  // about the rest of the stack frame (note, this is pre-regalloc, so
1383  // we don't know everything for certain yet) whether this offset is likely
1384  // to be out of range of the immediate. Return true if so.
1385
1386  // FIXME: For testing, return true for all loads/stores and false for
1387  // everything else. We want to create lots of base regs to shake out bugs.
1388  //
1389  // FIXME: This is Thumb2/ARM only for now to keep it simpler.
1390  ARMFunctionInfo *AFI =
1391    MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1392  if (AFI->isThumb1OnlyFunction())
1393    return false;
1394
1395  unsigned Opc = MI->getOpcode();
1396
1397  switch (Opc) {
1398  case ARM::LDR: case ARM::LDRH: case ARM::LDRB:
1399  case ARM::STR: case ARM::STRH: case ARM::STRB:
1400  case ARM::t2LDRi12: case ARM::t2LDRi8:
1401  case ARM::t2STRi12: case ARM::t2STRi8:
1402  case ARM::VLDRS: case ARM::VLDRD:
1403  case ARM::VSTRS: case ARM::VSTRD:
1404    return true;
1405  default:
1406    return false;
1407  }
1408}
1409
1410/// materializeFrameBaseRegister - Insert defining instruction(s) for
1411/// BaseReg to be a pointer to FrameIdx before insertion point I.
1412void ARMBaseRegisterInfo::
1413materializeFrameBaseRegister(MachineBasicBlock::iterator I,
1414                             unsigned BaseReg, int FrameIdx) const {
1415  ARMFunctionInfo *AFI =
1416    I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1417  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1418  assert(!AFI->isThumb1OnlyFunction() &&
1419         "This materializeFrameBaseRegister does not support Thumb1!");
1420
1421  MachineInstrBuilder MIB =
1422    BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1423    .addFrameIndex(FrameIdx).addImm(0);
1424  AddDefaultCC(AddDefaultPred(MIB));
1425}
1426
1427void
1428ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1429                                       unsigned BaseReg, int64_t Offset) const {
1430  MachineInstr &MI = *I;
1431  MachineBasicBlock &MBB = *MI.getParent();
1432  MachineFunction &MF = *MBB.getParent();
1433  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1434  int Off = Offset; // ARM doesn't need the general 64-bit offsets
1435  unsigned i = 0;
1436
1437  assert(!AFI->isThumb1OnlyFunction() &&
1438         "This resolveFrameIndex does not support Thumb1!");
1439
1440  while (!MI.getOperand(i).isFI()) {
1441    ++i;
1442    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1443  }
1444  bool Done = false;
1445  if (!AFI->isThumbFunction())
1446    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1447  else {
1448    assert(AFI->isThumb2Function());
1449    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1450  }
1451  assert (Done && "Unable to resolve frame index!");
1452}
1453
1454unsigned
1455ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1456                                         int SPAdj, FrameIndexValue *Value,
1457                                         RegScavenger *RS) const {
1458  unsigned i = 0;
1459  MachineInstr &MI = *II;
1460  MachineBasicBlock &MBB = *MI.getParent();
1461  MachineFunction &MF = *MBB.getParent();
1462  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1463  assert(!AFI->isThumb1OnlyFunction() &&
1464         "This eliminateFrameIndex does not support Thumb1!");
1465
1466  while (!MI.getOperand(i).isFI()) {
1467    ++i;
1468    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1469  }
1470
1471  int FrameIndex = MI.getOperand(i).getIndex();
1472  unsigned FrameReg;
1473
1474  int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1475
1476  // Special handling of dbg_value instructions.
1477  if (MI.isDebugValue()) {
1478    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1479    MI.getOperand(i+1).ChangeToImmediate(Offset);
1480    return 0;
1481  }
1482
1483  // Modify MI as necessary to handle as much of 'Offset' as possible
1484  bool Done = false;
1485  if (!AFI->isThumbFunction())
1486    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1487  else {
1488    assert(AFI->isThumb2Function());
1489    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1490  }
1491  if (Done)
1492    return 0;
1493
1494  // If we get here, the immediate doesn't fit into the instruction.  We folded
1495  // as much as possible above, handle the rest, providing a register that is
1496  // SP+LargeImm.
1497  assert((Offset ||
1498          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1499          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1500         "This code isn't needed if offset already handled!");
1501
1502  unsigned ScratchReg = 0;
1503  int PIdx = MI.findFirstPredOperandIdx();
1504  ARMCC::CondCodes Pred = (PIdx == -1)
1505    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1506  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1507  if (Offset == 0)
1508    // Must be addrmode4/6.
1509    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1510  else {
1511    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1512    if (Value) {
1513      Value->first = FrameReg; // use the frame register as a kind indicator
1514      Value->second = Offset;
1515    }
1516    if (!AFI->isThumbFunction())
1517      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1518                              Offset, Pred, PredReg, TII);
1519    else {
1520      assert(AFI->isThumb2Function());
1521      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1522                             Offset, Pred, PredReg, TII);
1523    }
1524    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1525    if (!ReuseFrameIndexVals)
1526      ScratchReg = 0;
1527  }
1528  return ScratchReg;
1529}
1530
1531/// Move iterator past the next bunch of callee save load / store ops for
1532/// the particular spill area (1: integer area 1, 2: integer area 2,
1533/// 3: fp area, 0: don't care).
1534static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1535                                   MachineBasicBlock::iterator &MBBI,
1536                                   int Opc1, int Opc2, unsigned Area,
1537                                   const ARMSubtarget &STI) {
1538  while (MBBI != MBB.end() &&
1539         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1540         MBBI->getOperand(1).isFI()) {
1541    if (Area != 0) {
1542      bool Done = false;
1543      unsigned Category = 0;
1544      switch (MBBI->getOperand(0).getReg()) {
1545      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1546      case ARM::LR:
1547        Category = 1;
1548        break;
1549      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1550        Category = STI.isTargetDarwin() ? 2 : 1;
1551        break;
1552      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1553      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1554        Category = 3;
1555        break;
1556      default:
1557        Done = true;
1558        break;
1559      }
1560      if (Done || Category != Area)
1561        break;
1562    }
1563
1564    ++MBBI;
1565  }
1566}
1567
1568void ARMBaseRegisterInfo::
1569emitPrologue(MachineFunction &MF) const {
1570  MachineBasicBlock &MBB = MF.front();
1571  MachineBasicBlock::iterator MBBI = MBB.begin();
1572  MachineFrameInfo  *MFI = MF.getFrameInfo();
1573  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1574  assert(!AFI->isThumb1OnlyFunction() &&
1575         "This emitPrologue does not support Thumb1!");
1576  bool isARM = !AFI->isThumbFunction();
1577  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1578  unsigned NumBytes = MFI->getStackSize();
1579  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1580  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1581
1582  // Determine the sizes of each callee-save spill areas and record which frame
1583  // belongs to which callee-save spill areas.
1584  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1585  int FramePtrSpillFI = 0;
1586
1587  // Allocate the vararg register save area. This is not counted in NumBytes.
1588  if (VARegSaveSize)
1589    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1590
1591  if (!AFI->hasStackFrame()) {
1592    if (NumBytes != 0)
1593      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1594    return;
1595  }
1596
1597  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1598    unsigned Reg = CSI[i].getReg();
1599    int FI = CSI[i].getFrameIdx();
1600    switch (Reg) {
1601    case ARM::R4:
1602    case ARM::R5:
1603    case ARM::R6:
1604    case ARM::R7:
1605    case ARM::LR:
1606      if (Reg == FramePtr)
1607        FramePtrSpillFI = FI;
1608      AFI->addGPRCalleeSavedArea1Frame(FI);
1609      GPRCS1Size += 4;
1610      break;
1611    case ARM::R8:
1612    case ARM::R9:
1613    case ARM::R10:
1614    case ARM::R11:
1615      if (Reg == FramePtr)
1616        FramePtrSpillFI = FI;
1617      if (STI.isTargetDarwin()) {
1618        AFI->addGPRCalleeSavedArea2Frame(FI);
1619        GPRCS2Size += 4;
1620      } else {
1621        AFI->addGPRCalleeSavedArea1Frame(FI);
1622        GPRCS1Size += 4;
1623      }
1624      break;
1625    default:
1626      AFI->addDPRCalleeSavedAreaFrame(FI);
1627      DPRCSSize += 8;
1628    }
1629  }
1630
1631  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1632  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1633  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1634
1635  // Set FP to point to the stack slot that contains the previous FP.
1636  // For Darwin, FP is R7, which has now been stored in spill area 1.
1637  // Otherwise, if this is not Darwin, all the callee-saved registers go
1638  // into spill area 1, including the FP in R11.  In either case, it is
1639  // now safe to emit this assignment.
1640  bool HasFP = hasFP(MF);
1641  if (HasFP) {
1642    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1643    MachineInstrBuilder MIB =
1644      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1645      .addFrameIndex(FramePtrSpillFI).addImm(0);
1646    AddDefaultCC(AddDefaultPred(MIB));
1647  }
1648
1649  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1650  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1651
1652  // Build the new SUBri to adjust SP for FP callee-save spill area.
1653  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1654  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1655
1656  // Determine starting offsets of spill areas.
1657  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1658  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1659  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1660  if (HasFP)
1661    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1662                                NumBytes);
1663  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1664  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1665  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1666
1667  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1668  NumBytes = DPRCSOffset;
1669  if (NumBytes) {
1670    // Adjust SP after all the callee-save spills.
1671    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1672    if (HasFP)
1673      AFI->setShouldRestoreSPFromFP(true);
1674  }
1675
1676  if (STI.isTargetELF() && hasFP(MF)) {
1677    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1678                             AFI->getFramePtrSpillOffset());
1679    AFI->setShouldRestoreSPFromFP(true);
1680  }
1681
1682  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1683  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1684  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1685
1686  // If we need dynamic stack realignment, do it here.
1687  if (needsStackRealignment(MF)) {
1688    unsigned MaxAlign = MFI->getMaxAlignment();
1689    assert (!AFI->isThumb1OnlyFunction());
1690    if (!AFI->isThumbFunction()) {
1691      // Emit bic sp, sp, MaxAlign
1692      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1693                                          TII.get(ARM::BICri), ARM::SP)
1694                                  .addReg(ARM::SP, RegState::Kill)
1695                                  .addImm(MaxAlign-1)));
1696    } else {
1697      // We cannot use sp as source/dest register here, thus we're emitting the
1698      // following sequence:
1699      // mov r4, sp
1700      // bic r4, r4, MaxAlign
1701      // mov sp, r4
1702      // FIXME: It will be better just to find spare register here.
1703      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1704        .addReg(ARM::SP, RegState::Kill);
1705      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1706                                          TII.get(ARM::t2BICri), ARM::R4)
1707                                  .addReg(ARM::R4, RegState::Kill)
1708                                  .addImm(MaxAlign-1)));
1709      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1710        .addReg(ARM::R4, RegState::Kill);
1711    }
1712
1713    AFI->setShouldRestoreSPFromFP(true);
1714  }
1715
1716  // If the frame has variable sized objects then the epilogue must restore
1717  // the sp from fp.
1718  if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
1719    AFI->setShouldRestoreSPFromFP(true);
1720}
1721
1722static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1723  for (unsigned i = 0; CSRegs[i]; ++i)
1724    if (Reg == CSRegs[i])
1725      return true;
1726  return false;
1727}
1728
1729static bool isCSRestore(MachineInstr *MI,
1730                        const ARMBaseInstrInfo &TII,
1731                        const unsigned *CSRegs) {
1732  return ((MI->getOpcode() == (int)ARM::VLDRD ||
1733           MI->getOpcode() == (int)ARM::LDR ||
1734           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1735          MI->getOperand(1).isFI() &&
1736          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1737}
1738
1739void ARMBaseRegisterInfo::
1740emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1741  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1742  assert(MBBI->getDesc().isReturn() &&
1743         "Can only insert epilog into returning blocks");
1744  unsigned RetOpcode = MBBI->getOpcode();
1745  DebugLoc dl = MBBI->getDebugLoc();
1746  MachineFrameInfo *MFI = MF.getFrameInfo();
1747  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1748  assert(!AFI->isThumb1OnlyFunction() &&
1749         "This emitEpilogue does not support Thumb1!");
1750  bool isARM = !AFI->isThumbFunction();
1751
1752  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1753  int NumBytes = (int)MFI->getStackSize();
1754
1755  if (!AFI->hasStackFrame()) {
1756    if (NumBytes != 0)
1757      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1758  } else {
1759    // Unwind MBBI to point to first LDR / VLDRD.
1760    const unsigned *CSRegs = getCalleeSavedRegs();
1761    if (MBBI != MBB.begin()) {
1762      do
1763        --MBBI;
1764      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1765      if (!isCSRestore(MBBI, TII, CSRegs))
1766        ++MBBI;
1767    }
1768
1769    // Move SP to start of FP callee save spill area.
1770    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1771                 AFI->getGPRCalleeSavedArea2Size() +
1772                 AFI->getDPRCalleeSavedAreaSize());
1773
1774    // Reset SP based on frame pointer only if the stack frame extends beyond
1775    // frame pointer stack slot or target is ELF and the function has FP.
1776    if (AFI->shouldRestoreSPFromFP()) {
1777      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1778      if (NumBytes) {
1779        if (isARM)
1780          emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1781                                  ARMCC::AL, 0, TII);
1782        else
1783          emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1784                                 ARMCC::AL, 0, TII);
1785      } else {
1786        // Thumb2 or ARM.
1787        if (isARM)
1788          BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1789            .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1790        else
1791          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1792            .addReg(FramePtr);
1793      }
1794    } else if (NumBytes)
1795      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1796
1797    // Move SP to start of integer callee save spill area 2.
1798    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1799    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1800
1801    // Move SP to start of integer callee save spill area 1.
1802    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1803    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1804
1805    // Move SP to SP upon entry to the function.
1806    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1807    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1808  }
1809
1810  if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1811      RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1812    // Tail call return: adjust the stack pointer and jump to callee.
1813    MBBI = prior(MBB.end());
1814    MachineOperand &JumpTarget = MBBI->getOperand(0);
1815
1816    // Jump to label or value in register.
1817    if (RetOpcode == ARM::TCRETURNdi) {
1818      BuildMI(MBB, MBBI, dl,
1819            TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
1820        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1821                         JumpTarget.getTargetFlags());
1822    } else if (RetOpcode == ARM::TCRETURNdiND) {
1823      BuildMI(MBB, MBBI, dl,
1824            TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
1825        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1826                         JumpTarget.getTargetFlags());
1827    } else if (RetOpcode == ARM::TCRETURNri) {
1828      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
1829        addReg(JumpTarget.getReg(), RegState::Kill);
1830    } else if (RetOpcode == ARM::TCRETURNriND) {
1831      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
1832        addReg(JumpTarget.getReg(), RegState::Kill);
1833    }
1834
1835    MachineInstr *NewMI = prior(MBBI);
1836    for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1837      NewMI->addOperand(MBBI->getOperand(i));
1838
1839    // Delete the pseudo instruction TCRETURN.
1840    MBB.erase(MBBI);
1841  }
1842
1843  if (VARegSaveSize)
1844    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1845}
1846
1847#include "ARMGenRegisterInfo.inc"
1848