ARMBaseRegisterInfo.cpp revision e038a206df7df6f799be8e3a308101b77a3414ce 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42namespace llvm {
43static cl::opt<bool>
44ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
45          cl::desc("Force use of virtual base registers for stack load/store"));
46static cl::opt<bool>
47EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
48          cl::desc("Enable pre-regalloc stack frame index allocation"));
49}
50
51using namespace llvm;
52
53static cl::opt<bool>
54EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
55          cl::desc("Enable use of a base pointer for complex stack frames"));
56
57
58ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
59                                         const ARMSubtarget &sti)
60  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
61    TII(tii), STI(sti),
62    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
63    BasePtr(ARM::R6) {
64}
65
66const unsigned*
67ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
68  static const unsigned CalleeSavedRegs[] = {
69    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
70    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
71
72    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
73    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
74    0
75  };
76
77  static const unsigned DarwinCalleeSavedRegs[] = {
78    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
79    // register.
80    ARM::LR, ARM::R11, ARM::R10, ARM::R8,
81    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
82
83    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
84    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
85    0
86  };
87  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
88}
89
90BitVector ARMBaseRegisterInfo::
91getReservedRegs(const MachineFunction &MF) const {
92  // FIXME: avoid re-calculating this everytime.
93  BitVector Reserved(getNumRegs());
94  Reserved.set(ARM::SP);
95  Reserved.set(ARM::PC);
96  Reserved.set(ARM::FPSCR);
97  if (hasFP(MF))
98    Reserved.set(FramePtr);
99  if (hasBasePointer(MF))
100    Reserved.set(BasePtr);
101  // Some targets reserve R9.
102  if (STI.isR9Reserved())
103    Reserved.set(ARM::R9);
104  return Reserved;
105}
106
107bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
108                                        unsigned Reg) const {
109  switch (Reg) {
110  default: break;
111  case ARM::SP:
112  case ARM::PC:
113    return true;
114  case ARM::R6:
115    if (hasBasePointer(MF))
116      return true;
117    break;
118  case ARM::R7:
119  case ARM::R11:
120    if (FramePtr == Reg && hasFP(MF))
121      return true;
122    break;
123  case ARM::R9:
124    return STI.isR9Reserved();
125  }
126
127  return false;
128}
129
130const TargetRegisterClass *
131ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
132                                              const TargetRegisterClass *B,
133                                              unsigned SubIdx) const {
134  switch (SubIdx) {
135  default: return 0;
136  case ARM::ssub_0:
137  case ARM::ssub_1:
138  case ARM::ssub_2:
139  case ARM::ssub_3: {
140    // S sub-registers.
141    if (A->getSize() == 8) {
142      if (B == &ARM::SPR_8RegClass)
143        return &ARM::DPR_8RegClass;
144      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
145      if (A == &ARM::DPR_8RegClass)
146        return A;
147      return &ARM::DPR_VFP2RegClass;
148    }
149
150    if (A->getSize() == 16) {
151      if (B == &ARM::SPR_8RegClass)
152        return &ARM::QPR_8RegClass;
153      return &ARM::QPR_VFP2RegClass;
154    }
155
156    if (A->getSize() == 32) {
157      if (B == &ARM::SPR_8RegClass)
158        return 0;  // Do not allow coalescing!
159      return &ARM::QQPR_VFP2RegClass;
160    }
161
162    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
163    return 0;  // Do not allow coalescing!
164  }
165  case ARM::dsub_0:
166  case ARM::dsub_1:
167  case ARM::dsub_2:
168  case ARM::dsub_3: {
169    // D sub-registers.
170    if (A->getSize() == 16) {
171      if (B == &ARM::DPR_VFP2RegClass)
172        return &ARM::QPR_VFP2RegClass;
173      if (B == &ARM::DPR_8RegClass)
174        return 0;  // Do not allow coalescing!
175      return A;
176    }
177
178    if (A->getSize() == 32) {
179      if (B == &ARM::DPR_VFP2RegClass)
180        return &ARM::QQPR_VFP2RegClass;
181      if (B == &ARM::DPR_8RegClass)
182        return 0;  // Do not allow coalescing!
183      return A;
184    }
185
186    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
187    if (B != &ARM::DPRRegClass)
188      return 0;  // Do not allow coalescing!
189    return A;
190  }
191  case ARM::dsub_4:
192  case ARM::dsub_5:
193  case ARM::dsub_6:
194  case ARM::dsub_7: {
195    // D sub-registers of QQQQ registers.
196    if (A->getSize() == 64 && B == &ARM::DPRRegClass)
197      return A;
198    return 0;  // Do not allow coalescing!
199  }
200
201  case ARM::qsub_0:
202  case ARM::qsub_1: {
203    // Q sub-registers.
204    if (A->getSize() == 32) {
205      if (B == &ARM::QPR_VFP2RegClass)
206        return &ARM::QQPR_VFP2RegClass;
207      if (B == &ARM::QPR_8RegClass)
208        return 0;  // Do not allow coalescing!
209      return A;
210    }
211
212    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
213    if (B == &ARM::QPRRegClass)
214      return A;
215    return 0;  // Do not allow coalescing!
216  }
217  case ARM::qsub_2:
218  case ARM::qsub_3: {
219    // Q sub-registers of QQQQ registers.
220    if (A->getSize() == 64 && B == &ARM::QPRRegClass)
221      return A;
222    return 0;  // Do not allow coalescing!
223  }
224  }
225  return 0;
226}
227
228bool
229ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
230                                          SmallVectorImpl<unsigned> &SubIndices,
231                                          unsigned &NewSubIdx) const {
232
233  unsigned Size = RC->getSize() * 8;
234  if (Size < 6)
235    return 0;
236
237  NewSubIdx = 0;  // Whole register.
238  unsigned NumRegs = SubIndices.size();
239  if (NumRegs == 8) {
240    // 8 D registers -> 1 QQQQ register.
241    return (Size == 512 &&
242            SubIndices[0] == ARM::dsub_0 &&
243            SubIndices[1] == ARM::dsub_1 &&
244            SubIndices[2] == ARM::dsub_2 &&
245            SubIndices[3] == ARM::dsub_3 &&
246            SubIndices[4] == ARM::dsub_4 &&
247            SubIndices[5] == ARM::dsub_5 &&
248            SubIndices[6] == ARM::dsub_6 &&
249            SubIndices[7] == ARM::dsub_7);
250  } else if (NumRegs == 4) {
251    if (SubIndices[0] == ARM::qsub_0) {
252      // 4 Q registers -> 1 QQQQ register.
253      return (Size == 512 &&
254              SubIndices[1] == ARM::qsub_1 &&
255              SubIndices[2] == ARM::qsub_2 &&
256              SubIndices[3] == ARM::qsub_3);
257    } else if (SubIndices[0] == ARM::dsub_0) {
258      // 4 D registers -> 1 QQ register.
259      if (Size >= 256 &&
260          SubIndices[1] == ARM::dsub_1 &&
261          SubIndices[2] == ARM::dsub_2 &&
262          SubIndices[3] == ARM::dsub_3) {
263        if (Size == 512)
264          NewSubIdx = ARM::qqsub_0;
265        return true;
266      }
267    } else if (SubIndices[0] == ARM::dsub_4) {
268      // 4 D registers -> 1 QQ register (2nd).
269      if (Size == 512 &&
270          SubIndices[1] == ARM::dsub_5 &&
271          SubIndices[2] == ARM::dsub_6 &&
272          SubIndices[3] == ARM::dsub_7) {
273        NewSubIdx = ARM::qqsub_1;
274        return true;
275      }
276    } else if (SubIndices[0] == ARM::ssub_0) {
277      // 4 S registers -> 1 Q register.
278      if (Size >= 128 &&
279          SubIndices[1] == ARM::ssub_1 &&
280          SubIndices[2] == ARM::ssub_2 &&
281          SubIndices[3] == ARM::ssub_3) {
282        if (Size >= 256)
283          NewSubIdx = ARM::qsub_0;
284        return true;
285      }
286    }
287  } else if (NumRegs == 2) {
288    if (SubIndices[0] == ARM::qsub_0) {
289      // 2 Q registers -> 1 QQ register.
290      if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
291        if (Size == 512)
292          NewSubIdx = ARM::qqsub_0;
293        return true;
294      }
295    } else if (SubIndices[0] == ARM::qsub_2) {
296      // 2 Q registers -> 1 QQ register (2nd).
297      if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
298        NewSubIdx = ARM::qqsub_1;
299        return true;
300      }
301    } else if (SubIndices[0] == ARM::dsub_0) {
302      // 2 D registers -> 1 Q register.
303      if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
304        if (Size >= 256)
305          NewSubIdx = ARM::qsub_0;
306        return true;
307      }
308    } else if (SubIndices[0] == ARM::dsub_2) {
309      // 2 D registers -> 1 Q register (2nd).
310      if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
311        NewSubIdx = ARM::qsub_1;
312        return true;
313      }
314    } else if (SubIndices[0] == ARM::dsub_4) {
315      // 2 D registers -> 1 Q register (3rd).
316      if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
317        NewSubIdx = ARM::qsub_2;
318        return true;
319      }
320    } else if (SubIndices[0] == ARM::dsub_6) {
321      // 2 D registers -> 1 Q register (3rd).
322      if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
323        NewSubIdx = ARM::qsub_3;
324        return true;
325      }
326    } else if (SubIndices[0] == ARM::ssub_0) {
327      // 2 S registers -> 1 D register.
328      if (SubIndices[1] == ARM::ssub_1) {
329        if (Size >= 128)
330          NewSubIdx = ARM::dsub_0;
331        return true;
332      }
333    } else if (SubIndices[0] == ARM::ssub_2) {
334      // 2 S registers -> 1 D register (2nd).
335      if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
336        NewSubIdx = ARM::dsub_1;
337        return true;
338      }
339    }
340  }
341  return false;
342}
343
344
345const TargetRegisterClass *
346ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
347  return ARM::GPRRegisterClass;
348}
349
350/// getAllocationOrder - Returns the register allocation order for a specified
351/// register class in the form of a pair of TargetRegisterClass iterators.
352std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
353ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
354                                        unsigned HintType, unsigned HintReg,
355                                        const MachineFunction &MF) const {
356  // Alternative register allocation orders when favoring even / odd registers
357  // of register pairs.
358
359  // No FP, R9 is available.
360  static const unsigned GPREven1[] = {
361    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
362    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
363    ARM::R9, ARM::R11
364  };
365  static const unsigned GPROdd1[] = {
366    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
367    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
368    ARM::R8, ARM::R10
369  };
370
371  // FP is R7, R9 is available.
372  static const unsigned GPREven2[] = {
373    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
374    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
375    ARM::R9, ARM::R11
376  };
377  static const unsigned GPROdd2[] = {
378    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
379    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
380    ARM::R8, ARM::R10
381  };
382
383  // FP is R11, R9 is available.
384  static const unsigned GPREven3[] = {
385    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
386    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
387    ARM::R9
388  };
389  static const unsigned GPROdd3[] = {
390    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
391    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
392    ARM::R8
393  };
394
395  // No FP, R9 is not available.
396  static const unsigned GPREven4[] = {
397    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
398    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
399    ARM::R11
400  };
401  static const unsigned GPROdd4[] = {
402    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
403    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
404    ARM::R10
405  };
406
407  // FP is R7, R9 is not available.
408  static const unsigned GPREven5[] = {
409    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
410    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
411    ARM::R11
412  };
413  static const unsigned GPROdd5[] = {
414    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
415    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
416    ARM::R10
417  };
418
419  // FP is R11, R9 is not available.
420  static const unsigned GPREven6[] = {
421    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
422    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
423  };
424  static const unsigned GPROdd6[] = {
425    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
426    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
427  };
428
429
430  if (HintType == ARMRI::RegPairEven) {
431    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
432      // It's no longer possible to fulfill this hint. Return the default
433      // allocation order.
434      return std::make_pair(RC->allocation_order_begin(MF),
435                            RC->allocation_order_end(MF));
436
437    if (!hasFP(MF)) {
438      if (!STI.isR9Reserved())
439        return std::make_pair(GPREven1,
440                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
441      else
442        return std::make_pair(GPREven4,
443                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
444    } else if (FramePtr == ARM::R7) {
445      if (!STI.isR9Reserved())
446        return std::make_pair(GPREven2,
447                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
448      else
449        return std::make_pair(GPREven5,
450                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
451    } else { // FramePtr == ARM::R11
452      if (!STI.isR9Reserved())
453        return std::make_pair(GPREven3,
454                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
455      else
456        return std::make_pair(GPREven6,
457                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
458    }
459  } else if (HintType == ARMRI::RegPairOdd) {
460    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
461      // It's no longer possible to fulfill this hint. Return the default
462      // allocation order.
463      return std::make_pair(RC->allocation_order_begin(MF),
464                            RC->allocation_order_end(MF));
465
466    if (!hasFP(MF)) {
467      if (!STI.isR9Reserved())
468        return std::make_pair(GPROdd1,
469                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
470      else
471        return std::make_pair(GPROdd4,
472                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
473    } else if (FramePtr == ARM::R7) {
474      if (!STI.isR9Reserved())
475        return std::make_pair(GPROdd2,
476                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
477      else
478        return std::make_pair(GPROdd5,
479                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
480    } else { // FramePtr == ARM::R11
481      if (!STI.isR9Reserved())
482        return std::make_pair(GPROdd3,
483                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
484      else
485        return std::make_pair(GPROdd6,
486                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
487    }
488  }
489  return std::make_pair(RC->allocation_order_begin(MF),
490                        RC->allocation_order_end(MF));
491}
492
493/// ResolveRegAllocHint - Resolves the specified register allocation hint
494/// to a physical register. Returns the physical register if it is successful.
495unsigned
496ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
497                                         const MachineFunction &MF) const {
498  if (Reg == 0 || !isPhysicalRegister(Reg))
499    return 0;
500  if (Type == 0)
501    return Reg;
502  else if (Type == (unsigned)ARMRI::RegPairOdd)
503    // Odd register.
504    return getRegisterPairOdd(Reg, MF);
505  else if (Type == (unsigned)ARMRI::RegPairEven)
506    // Even register.
507    return getRegisterPairEven(Reg, MF);
508  return 0;
509}
510
511void
512ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
513                                        MachineFunction &MF) const {
514  MachineRegisterInfo *MRI = &MF.getRegInfo();
515  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
516  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
517       Hint.first == (unsigned)ARMRI::RegPairEven) &&
518      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
519    // If 'Reg' is one of the even / odd register pair and it's now changed
520    // (e.g. coalesced) into a different register. The other register of the
521    // pair allocation hint must be updated to reflect the relationship
522    // change.
523    unsigned OtherReg = Hint.second;
524    Hint = MRI->getRegAllocationHint(OtherReg);
525    if (Hint.second == Reg)
526      // Make sure the pair has not already divorced.
527      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
528  }
529}
530
531/// hasFP - Return true if the specified function should have a dedicated frame
532/// pointer register.  This is true if the function has variable sized allocas
533/// or if frame pointer elimination is disabled.
534///
535bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
536  // Mac OS X requires FP not to be clobbered for backtracing purpose.
537  if (STI.isTargetDarwin())
538    return true;
539
540  const MachineFrameInfo *MFI = MF.getFrameInfo();
541  // Always eliminate non-leaf frame pointers.
542  return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
543          needsStackRealignment(MF) ||
544          MFI->hasVarSizedObjects() ||
545          MFI->isFrameAddressTaken());
546}
547
548bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
549  const MachineFrameInfo *MFI = MF.getFrameInfo();
550  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
551
552  if (!EnableBasePointer)
553    return false;
554
555  if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
556    return true;
557
558  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
559  // negative range for ldr/str (255), and thumb1 is positive offsets only.
560  // It's going to be better to use the SP or Base Pointer instead. When there
561  // are variable sized objects, we can't reference off of the SP, so we
562  // reserve a Base Pointer.
563  if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
564    // Conservatively estimate whether the negative offset from the frame
565    // pointer will be sufficient to reach. If a function has a smallish
566    // frame, it's less likely to have lots of spills and callee saved
567    // space, so it's all more likely to be within range of the frame pointer.
568    // If it's wrong, the scavenger will still enable access to work, it just
569    // won't be optimal.
570    if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
571      return false;
572    return true;
573  }
574
575  return false;
576}
577
578bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
579  const MachineFrameInfo *MFI = MF.getFrameInfo();
580  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
581  // We can't realign the stack if:
582  // 1. Dynamic stack realignment is explicitly disabled,
583  // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
584  // 3. There are VLAs in the function and the base pointer is disabled.
585  return (RealignStack && !AFI->isThumb1OnlyFunction() &&
586          (!MFI->hasVarSizedObjects() || EnableBasePointer));
587}
588
589bool ARMBaseRegisterInfo::
590needsStackRealignment(const MachineFunction &MF) const {
591  const MachineFrameInfo *MFI = MF.getFrameInfo();
592  const Function *F = MF.getFunction();
593  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
594  bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
595                               F->hasFnAttr(Attribute::StackAlignment));
596
597  return requiresRealignment && canRealignStack(MF);
598}
599
600bool ARMBaseRegisterInfo::
601cannotEliminateFrame(const MachineFunction &MF) const {
602  const MachineFrameInfo *MFI = MF.getFrameInfo();
603  if (DisableFramePointerElim(MF) && MFI->adjustsStack())
604    return true;
605  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
606    || needsStackRealignment(MF);
607}
608
609/// estimateStackSize - Estimate and return the size of the frame.
610static unsigned estimateStackSize(MachineFunction &MF) {
611  const MachineFrameInfo *FFI = MF.getFrameInfo();
612  int Offset = 0;
613  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
614    int FixedOff = -FFI->getObjectOffset(i);
615    if (FixedOff > Offset) Offset = FixedOff;
616  }
617  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
618    if (FFI->isDeadObjectIndex(i))
619      continue;
620    Offset += FFI->getObjectSize(i);
621    unsigned Align = FFI->getObjectAlignment(i);
622    // Adjust to alignment boundary
623    Offset = (Offset+Align-1)/Align*Align;
624  }
625  return (unsigned)Offset;
626}
627
628/// estimateRSStackSizeLimit - Look at each instruction that references stack
629/// frames and return the stack size limit beyond which some of these
630/// instructions will require a scratch register during their expansion later.
631unsigned
632ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
633  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
634  unsigned Limit = (1 << 12) - 1;
635  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
636    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
637         I != E; ++I) {
638      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
639        if (!I->getOperand(i).isFI()) continue;
640
641        // When using ADDri to get the address of a stack object, 255 is the
642        // largest offset guaranteed to fit in the immediate offset.
643        if (I->getOpcode() == ARM::ADDri) {
644          Limit = std::min(Limit, (1U << 8) - 1);
645          break;
646        }
647
648        // Otherwise check the addressing mode.
649        switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
650        case ARMII::AddrMode3:
651        case ARMII::AddrModeT2_i8:
652          Limit = std::min(Limit, (1U << 8) - 1);
653          break;
654        case ARMII::AddrMode5:
655        case ARMII::AddrModeT2_i8s4:
656          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
657          break;
658        case ARMII::AddrModeT2_i12:
659          // i12 supports only positive offset so these will be converted to
660          // i8 opcodes. See llvm::rewriteT2FrameIndex.
661          if (hasFP(MF) && AFI->hasStackFrame())
662            Limit = std::min(Limit, (1U << 8) - 1);
663          break;
664        case ARMII::AddrMode6:
665          // Addressing mode 6 (load/store) instructions can't encode an
666          // immediate offset for stack references.
667          return 0;
668        default:
669          break;
670        }
671        break; // At most one FI per instruction
672      }
673    }
674  }
675
676  return Limit;
677}
678
679static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
680                                       const ARMBaseInstrInfo &TII) {
681  unsigned FnSize = 0;
682  for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
683       MBBI != E; ++MBBI) {
684    const MachineBasicBlock &MBB = *MBBI;
685    for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
686         I != E; ++I)
687      FnSize += TII.GetInstSizeInBytes(I);
688  }
689  return FnSize;
690}
691
692void
693ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
694                                                       RegScavenger *RS) const {
695  // This tells PEI to spill the FP as if it is any other callee-save register
696  // to take advantage the eliminateFrameIndex machinery. This also ensures it
697  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
698  // to combine multiple loads / stores.
699  bool CanEliminateFrame = true;
700  bool CS1Spilled = false;
701  bool LRSpilled = false;
702  unsigned NumGPRSpills = 0;
703  SmallVector<unsigned, 4> UnspilledCS1GPRs;
704  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
705  MachineFrameInfo *MFI = MF.getFrameInfo();
706
707  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
708  // scratch register.
709  // FIXME: It will be better just to find spare register here.
710  if (needsStackRealignment(MF) &&
711      AFI->isThumb2Function())
712    MF.getRegInfo().setPhysRegUsed(ARM::R4);
713
714  // Spill LR if Thumb1 function uses variable length argument lists.
715  if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
716    MF.getRegInfo().setPhysRegUsed(ARM::LR);
717
718  // Spill the BasePtr if it's used.
719  if (hasBasePointer(MF))
720    MF.getRegInfo().setPhysRegUsed(BasePtr);
721
722  // Don't spill FP if the frame can be eliminated. This is determined
723  // by scanning the callee-save registers to see if any is used.
724  const unsigned *CSRegs = getCalleeSavedRegs();
725  for (unsigned i = 0; CSRegs[i]; ++i) {
726    unsigned Reg = CSRegs[i];
727    bool Spilled = false;
728    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
729      AFI->setCSRegisterIsSpilled(Reg);
730      Spilled = true;
731      CanEliminateFrame = false;
732    } else {
733      // Check alias registers too.
734      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
735        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
736          Spilled = true;
737          CanEliminateFrame = false;
738        }
739      }
740    }
741
742    if (!ARM::GPRRegisterClass->contains(Reg))
743      continue;
744
745    if (Spilled) {
746      NumGPRSpills++;
747
748      if (!STI.isTargetDarwin()) {
749        if (Reg == ARM::LR)
750          LRSpilled = true;
751        CS1Spilled = true;
752        continue;
753      }
754
755      // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
756      switch (Reg) {
757      case ARM::LR:
758        LRSpilled = true;
759        // Fallthrough
760      case ARM::R4:
761      case ARM::R5:
762      case ARM::R6:
763      case ARM::R7:
764        CS1Spilled = true;
765        break;
766      default:
767        break;
768      }
769    } else {
770      UnspilledCS1GPRs.push_back(Reg);
771    }
772  }
773
774  bool ForceLRSpill = false;
775  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
776    unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
777    // Force LR to be spilled if the Thumb function size is > 2048. This enables
778    // use of BL to implement far jump. If it turns out that it's not needed
779    // then the branch fix up path will undo it.
780    if (FnSize >= (1 << 11)) {
781      CanEliminateFrame = false;
782      ForceLRSpill = true;
783    }
784  }
785
786  // If any of the stack slot references may be out of range of an immediate
787  // offset, make sure a register (or a spill slot) is available for the
788  // register scavenger. Note that if we're indexing off the frame pointer, the
789  // effective stack size is 4 bytes larger since the FP points to the stack
790  // slot of the previous FP. Also, if we have variable sized objects in the
791  // function, stack slot references will often be negative, and some of
792  // our instructions are positive-offset only, so conservatively consider
793  // that case to want a spill slot (or register) as well. Similarly, if
794  // the function adjusts the stack pointer during execution and the
795  // adjustments aren't already part of our stack size estimate, our offset
796  // calculations may be off, so be conservative.
797  // FIXME: We could add logic to be more precise about negative offsets
798  //        and which instructions will need a scratch register for them. Is it
799  //        worth the effort and added fragility?
800  bool BigStack =
801    (RS &&
802     (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
803      estimateRSStackSizeLimit(MF)))
804    || MFI->hasVarSizedObjects()
805    || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
806
807  bool ExtraCSSpill = false;
808  if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
809    AFI->setHasStackFrame(true);
810
811    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
812    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
813    if (!LRSpilled && CS1Spilled) {
814      MF.getRegInfo().setPhysRegUsed(ARM::LR);
815      AFI->setCSRegisterIsSpilled(ARM::LR);
816      NumGPRSpills++;
817      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
818                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
819      ForceLRSpill = false;
820      ExtraCSSpill = true;
821    }
822
823    if (hasFP(MF)) {
824      MF.getRegInfo().setPhysRegUsed(FramePtr);
825      NumGPRSpills++;
826    }
827
828    // If stack and double are 8-byte aligned and we are spilling an odd number
829    // of GPRs, spill one extra callee save GPR so we won't have to pad between
830    // the integer and double callee save areas.
831    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
832    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
833      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
834        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
835          unsigned Reg = UnspilledCS1GPRs[i];
836          // Don't spill high register if the function is thumb1
837          if (!AFI->isThumb1OnlyFunction() ||
838              isARMLowRegister(Reg) || Reg == ARM::LR) {
839            MF.getRegInfo().setPhysRegUsed(Reg);
840            AFI->setCSRegisterIsSpilled(Reg);
841            if (!isReservedReg(MF, Reg))
842              ExtraCSSpill = true;
843            break;
844          }
845        }
846      }
847    }
848
849    // Estimate if we might need to scavenge a register at some point in order
850    // to materialize a stack offset. If so, either spill one additional
851    // callee-saved register or reserve a special spill slot to facilitate
852    // register scavenging. Thumb1 needs a spill slot for stack pointer
853    // adjustments also, even when the frame itself is small.
854    if (BigStack && !ExtraCSSpill) {
855      // If any non-reserved CS register isn't spilled, just spill one or two
856      // extra. That should take care of it!
857      unsigned NumExtras = TargetAlign / 4;
858      SmallVector<unsigned, 2> Extras;
859      while (NumExtras && !UnspilledCS1GPRs.empty()) {
860        unsigned Reg = UnspilledCS1GPRs.back();
861        UnspilledCS1GPRs.pop_back();
862        if (!isReservedReg(MF, Reg) &&
863            (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
864             Reg == ARM::LR)) {
865          Extras.push_back(Reg);
866          NumExtras--;
867        }
868      }
869      if (Extras.size() && NumExtras == 0) {
870        for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
871          MF.getRegInfo().setPhysRegUsed(Extras[i]);
872          AFI->setCSRegisterIsSpilled(Extras[i]);
873        }
874      } else if (!AFI->isThumb1OnlyFunction()) {
875        // note: Thumb1 functions spill to R12, not the stack.  Reserve a slot
876        // closest to SP or frame pointer.
877        const TargetRegisterClass *RC = ARM::GPRRegisterClass;
878        RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
879                                                           RC->getAlignment(),
880                                                           false));
881      }
882    }
883  }
884
885  if (ForceLRSpill) {
886    MF.getRegInfo().setPhysRegUsed(ARM::LR);
887    AFI->setCSRegisterIsSpilled(ARM::LR);
888    AFI->setLRIsSpilledForFarJump(true);
889  }
890}
891
892unsigned ARMBaseRegisterInfo::getRARegister() const {
893  return ARM::LR;
894}
895
896unsigned
897ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
898  if (hasFP(MF))
899    return FramePtr;
900  return ARM::SP;
901}
902
903// Provide a base+offset reference to an FI slot for debug info. It's the
904// same as what we use for resolving the code-gen references for now.
905// FIXME: This can go wrong when references are SP-relative and simple call
906//        frames aren't used.
907int
908ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
909                                            unsigned &FrameReg) const {
910  return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
911}
912
913int
914ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
915                                                int FI,
916                                                unsigned &FrameReg,
917                                                int SPAdj) const {
918  const MachineFrameInfo *MFI = MF.getFrameInfo();
919  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
920  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
921  int FPOffset = Offset - AFI->getFramePtrSpillOffset();
922  bool isFixed = MFI->isFixedObjectIndex(FI);
923
924  FrameReg = ARM::SP;
925  Offset += SPAdj;
926  if (AFI->isGPRCalleeSavedAreaFrame(FI))
927    return Offset - AFI->getGPRCalleeSavedAreaOffset();
928  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
929    return Offset - AFI->getDPRCalleeSavedAreaOffset();
930
931  // When dynamically realigning the stack, use the frame pointer for
932  // parameters, and the stack/base pointer for locals.
933  if (needsStackRealignment(MF)) {
934    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
935    if (isFixed) {
936      FrameReg = getFrameRegister(MF);
937      Offset = FPOffset;
938    } else if (MFI->hasVarSizedObjects()) {
939      assert(hasBasePointer(MF) &&
940             "VLAs and dynamic stack alignment, but missing base pointer!");
941      FrameReg = BasePtr;
942    }
943    return Offset;
944  }
945
946  // If there is a frame pointer, use it when we can.
947  if (hasFP(MF) && AFI->hasStackFrame()) {
948    // Use frame pointer to reference fixed objects. Use it for locals if
949    // there are VLAs (and thus the SP isn't reliable as a base).
950    if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
951      FrameReg = getFrameRegister(MF);
952      return FPOffset;
953    } else if (MFI->hasVarSizedObjects()) {
954      assert(hasBasePointer(MF) && "missing base pointer!");
955      // Use the base register since we have it.
956      FrameReg = BasePtr;
957    } else if (AFI->isThumb2Function()) {
958      // In Thumb2 mode, the negative offset is very limited. Try to avoid
959      // out of range references.
960      if (FPOffset >= -255 && FPOffset < 0) {
961        FrameReg = getFrameRegister(MF);
962        return FPOffset;
963      }
964    } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
965      // Otherwise, use SP or FP, whichever is closer to the stack slot.
966      FrameReg = getFrameRegister(MF);
967      return FPOffset;
968    }
969  }
970  // Use the base pointer if we have one.
971  if (hasBasePointer(MF))
972    FrameReg = BasePtr;
973  return Offset;
974}
975
976int
977ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
978                                         int FI) const {
979  unsigned FrameReg;
980  return getFrameIndexReference(MF, FI, FrameReg);
981}
982
983unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
984  llvm_unreachable("What is the exception register");
985  return 0;
986}
987
988unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
989  llvm_unreachable("What is the exception handler register");
990  return 0;
991}
992
993int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
994  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
995}
996
997unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
998                                              const MachineFunction &MF) const {
999  switch (Reg) {
1000  default: break;
1001  // Return 0 if either register of the pair is a special register.
1002  // So no R12, etc.
1003  case ARM::R1:
1004    return ARM::R0;
1005  case ARM::R3:
1006    return ARM::R2;
1007  case ARM::R5:
1008    return ARM::R4;
1009  case ARM::R7:
1010    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1011      ? 0 : ARM::R6;
1012  case ARM::R9:
1013    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
1014  case ARM::R11:
1015    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1016
1017  case ARM::S1:
1018    return ARM::S0;
1019  case ARM::S3:
1020    return ARM::S2;
1021  case ARM::S5:
1022    return ARM::S4;
1023  case ARM::S7:
1024    return ARM::S6;
1025  case ARM::S9:
1026    return ARM::S8;
1027  case ARM::S11:
1028    return ARM::S10;
1029  case ARM::S13:
1030    return ARM::S12;
1031  case ARM::S15:
1032    return ARM::S14;
1033  case ARM::S17:
1034    return ARM::S16;
1035  case ARM::S19:
1036    return ARM::S18;
1037  case ARM::S21:
1038    return ARM::S20;
1039  case ARM::S23:
1040    return ARM::S22;
1041  case ARM::S25:
1042    return ARM::S24;
1043  case ARM::S27:
1044    return ARM::S26;
1045  case ARM::S29:
1046    return ARM::S28;
1047  case ARM::S31:
1048    return ARM::S30;
1049
1050  case ARM::D1:
1051    return ARM::D0;
1052  case ARM::D3:
1053    return ARM::D2;
1054  case ARM::D5:
1055    return ARM::D4;
1056  case ARM::D7:
1057    return ARM::D6;
1058  case ARM::D9:
1059    return ARM::D8;
1060  case ARM::D11:
1061    return ARM::D10;
1062  case ARM::D13:
1063    return ARM::D12;
1064  case ARM::D15:
1065    return ARM::D14;
1066  case ARM::D17:
1067    return ARM::D16;
1068  case ARM::D19:
1069    return ARM::D18;
1070  case ARM::D21:
1071    return ARM::D20;
1072  case ARM::D23:
1073    return ARM::D22;
1074  case ARM::D25:
1075    return ARM::D24;
1076  case ARM::D27:
1077    return ARM::D26;
1078  case ARM::D29:
1079    return ARM::D28;
1080  case ARM::D31:
1081    return ARM::D30;
1082  }
1083
1084  return 0;
1085}
1086
1087unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1088                                             const MachineFunction &MF) const {
1089  switch (Reg) {
1090  default: break;
1091  // Return 0 if either register of the pair is a special register.
1092  // So no R12, etc.
1093  case ARM::R0:
1094    return ARM::R1;
1095  case ARM::R2:
1096    return ARM::R3;
1097  case ARM::R4:
1098    return ARM::R5;
1099  case ARM::R6:
1100    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1101      ? 0 : ARM::R7;
1102  case ARM::R8:
1103    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
1104  case ARM::R10:
1105    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1106
1107  case ARM::S0:
1108    return ARM::S1;
1109  case ARM::S2:
1110    return ARM::S3;
1111  case ARM::S4:
1112    return ARM::S5;
1113  case ARM::S6:
1114    return ARM::S7;
1115  case ARM::S8:
1116    return ARM::S9;
1117  case ARM::S10:
1118    return ARM::S11;
1119  case ARM::S12:
1120    return ARM::S13;
1121  case ARM::S14:
1122    return ARM::S15;
1123  case ARM::S16:
1124    return ARM::S17;
1125  case ARM::S18:
1126    return ARM::S19;
1127  case ARM::S20:
1128    return ARM::S21;
1129  case ARM::S22:
1130    return ARM::S23;
1131  case ARM::S24:
1132    return ARM::S25;
1133  case ARM::S26:
1134    return ARM::S27;
1135  case ARM::S28:
1136    return ARM::S29;
1137  case ARM::S30:
1138    return ARM::S31;
1139
1140  case ARM::D0:
1141    return ARM::D1;
1142  case ARM::D2:
1143    return ARM::D3;
1144  case ARM::D4:
1145    return ARM::D5;
1146  case ARM::D6:
1147    return ARM::D7;
1148  case ARM::D8:
1149    return ARM::D9;
1150  case ARM::D10:
1151    return ARM::D11;
1152  case ARM::D12:
1153    return ARM::D13;
1154  case ARM::D14:
1155    return ARM::D15;
1156  case ARM::D16:
1157    return ARM::D17;
1158  case ARM::D18:
1159    return ARM::D19;
1160  case ARM::D20:
1161    return ARM::D21;
1162  case ARM::D22:
1163    return ARM::D23;
1164  case ARM::D24:
1165    return ARM::D25;
1166  case ARM::D26:
1167    return ARM::D27;
1168  case ARM::D28:
1169    return ARM::D29;
1170  case ARM::D30:
1171    return ARM::D31;
1172  }
1173
1174  return 0;
1175}
1176
1177/// emitLoadConstPool - Emits a load from constpool to materialize the
1178/// specified immediate.
1179void ARMBaseRegisterInfo::
1180emitLoadConstPool(MachineBasicBlock &MBB,
1181                  MachineBasicBlock::iterator &MBBI,
1182                  DebugLoc dl,
1183                  unsigned DestReg, unsigned SubIdx, int Val,
1184                  ARMCC::CondCodes Pred,
1185                  unsigned PredReg) const {
1186  MachineFunction &MF = *MBB.getParent();
1187  MachineConstantPool *ConstantPool = MF.getConstantPool();
1188  const Constant *C =
1189        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1190  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1191
1192  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1193    .addReg(DestReg, getDefRegState(true), SubIdx)
1194    .addConstantPoolIndex(Idx)
1195    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1196}
1197
1198bool ARMBaseRegisterInfo::
1199requiresRegisterScavenging(const MachineFunction &MF) const {
1200  return true;
1201}
1202
1203bool ARMBaseRegisterInfo::
1204requiresFrameIndexScavenging(const MachineFunction &MF) const {
1205  return true;
1206}
1207
1208bool ARMBaseRegisterInfo::
1209requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1210  return EnableLocalStackAlloc;
1211}
1212
1213// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1214// not required, we reserve argument space for call sites in the function
1215// immediately on entry to the current function. This eliminates the need for
1216// add/sub sp brackets around call sites. Returns true if the call frame is
1217// included as part of the stack frame.
1218bool ARMBaseRegisterInfo::
1219hasReservedCallFrame(const MachineFunction &MF) const {
1220  const MachineFrameInfo *FFI = MF.getFrameInfo();
1221  unsigned CFSize = FFI->getMaxCallFrameSize();
1222  // It's not always a good idea to include the call frame as part of the
1223  // stack frame. ARM (especially Thumb) has small immediate offset to
1224  // address the stack frame. So a large call frame can cause poor codegen
1225  // and may even makes it impossible to scavenge a register.
1226  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1227    return false;
1228
1229  return !MF.getFrameInfo()->hasVarSizedObjects();
1230}
1231
1232// canSimplifyCallFramePseudos - If there is a reserved call frame, the
1233// call frame pseudos can be simplified. Unlike most targets, having a FP
1234// is not sufficient here since we still may reference some objects via SP
1235// even when FP is available in Thumb2 mode.
1236bool ARMBaseRegisterInfo::
1237canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1238  return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1239}
1240
1241static void
1242emitSPUpdate(bool isARM,
1243             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1244             DebugLoc dl, const ARMBaseInstrInfo &TII,
1245             int NumBytes,
1246             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1247  if (isARM)
1248    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1249                            Pred, PredReg, TII);
1250  else
1251    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1252                           Pred, PredReg, TII);
1253}
1254
1255
1256void ARMBaseRegisterInfo::
1257eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1258                              MachineBasicBlock::iterator I) const {
1259  if (!hasReservedCallFrame(MF)) {
1260    // If we have alloca, convert as follows:
1261    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1262    // ADJCALLSTACKUP   -> add, sp, sp, amount
1263    MachineInstr *Old = I;
1264    DebugLoc dl = Old->getDebugLoc();
1265    unsigned Amount = Old->getOperand(0).getImm();
1266    if (Amount != 0) {
1267      // We need to keep the stack aligned properly.  To do this, we round the
1268      // amount of space needed for the outgoing arguments up to the next
1269      // alignment boundary.
1270      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1271      Amount = (Amount+Align-1)/Align*Align;
1272
1273      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1274      assert(!AFI->isThumb1OnlyFunction() &&
1275             "This eliminateCallFramePseudoInstr does not support Thumb1!");
1276      bool isARM = !AFI->isThumbFunction();
1277
1278      // Replace the pseudo instruction with a new instruction...
1279      unsigned Opc = Old->getOpcode();
1280      int PIdx = Old->findFirstPredOperandIdx();
1281      ARMCC::CondCodes Pred = (PIdx == -1)
1282        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1283      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1284        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1285        unsigned PredReg = Old->getOperand(2).getReg();
1286        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1287      } else {
1288        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1289        unsigned PredReg = Old->getOperand(3).getReg();
1290        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1291        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1292      }
1293    }
1294  }
1295  MBB.erase(I);
1296}
1297
1298int64_t ARMBaseRegisterInfo::
1299getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
1300  const TargetInstrDesc &Desc = MI->getDesc();
1301  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1302  int64_t InstrOffs = 0;;
1303  int Scale = 1;
1304  unsigned ImmIdx = 0;
1305  switch (AddrMode) {
1306  case ARMII::AddrModeT2_i8:
1307  case ARMII::AddrModeT2_i12:
1308    // i8 supports only negative, and i12 supports only positive, so
1309    // based on Offset sign, consider the appropriate instruction
1310    InstrOffs = MI->getOperand(Idx+1).getImm();
1311    Scale = 1;
1312    break;
1313  case ARMII::AddrMode5: {
1314    // VFP address mode.
1315    const MachineOperand &OffOp = MI->getOperand(Idx+1);
1316    InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1317    if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1318      InstrOffs = -InstrOffs;
1319    Scale = 4;
1320    break;
1321  }
1322  case ARMII::AddrMode2: {
1323    ImmIdx = Idx+2;
1324    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1325    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1326      InstrOffs = -InstrOffs;
1327    break;
1328  }
1329  case ARMII::AddrMode3: {
1330    ImmIdx = Idx+2;
1331    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1332    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1333      InstrOffs = -InstrOffs;
1334    break;
1335  }
1336  case ARMII::AddrModeT1_s: {
1337    ImmIdx = Idx+1;
1338    InstrOffs = MI->getOperand(ImmIdx).getImm();
1339    Scale = 4;
1340    break;
1341  }
1342  default:
1343    llvm_unreachable("Unsupported addressing mode!");
1344    break;
1345  }
1346
1347  return InstrOffs * Scale;
1348}
1349
1350/// needsFrameBaseReg - Returns true if the instruction's frame index
1351/// reference would be better served by a base register other than FP
1352/// or SP. Used by LocalStackFrameAllocation to determine which frame index
1353/// references it should create new base registers for.
1354bool ARMBaseRegisterInfo::
1355needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1356  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1357    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1358  }
1359
1360  // It's the load/store FI references that cause issues, as it can be difficult
1361  // to materialize the offset if it won't fit in the literal field. Estimate
1362  // based on the size of the local frame and some conservative assumptions
1363  // about the rest of the stack frame (note, this is pre-regalloc, so
1364  // we don't know everything for certain yet) whether this offset is likely
1365  // to be out of range of the immediate. Return true if so.
1366
1367  // We only generate virtual base registers for loads and stores, so
1368  // return false for everything else.
1369  unsigned Opc = MI->getOpcode();
1370  switch (Opc) {
1371  case ARM::LDR: case ARM::LDRH: case ARM::LDRB:
1372  case ARM::STR: case ARM::STRH: case ARM::STRB:
1373  case ARM::t2LDRi12: case ARM::t2LDRi8:
1374  case ARM::t2STRi12: case ARM::t2STRi8:
1375  case ARM::VLDRS: case ARM::VLDRD:
1376  case ARM::VSTRS: case ARM::VSTRD:
1377  case ARM::tSTRspi: case ARM::tLDRspi:
1378    if (ForceAllBaseRegAlloc)
1379      return true;
1380    break;
1381  default:
1382    return false;
1383  }
1384
1385  // Without a virtual base register, if the function has variable sized
1386  // objects, all fixed-size local references will be via the frame pointer,
1387  // Approximate the offset and see if it's legal for the instruction.
1388  // Note that the incoming offset is based on the SP value at function entry,
1389  // so it'll be negative.
1390  MachineFunction &MF = *MI->getParent()->getParent();
1391  MachineFrameInfo *MFI = MF.getFrameInfo();
1392  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1393
1394  // Estimate an offset from the frame pointer.
1395  // Conservatively assume all callee-saved registers get pushed. R4-R6
1396  // will be earlier than the FP, so we ignore those.
1397  // R7, LR
1398  int64_t FPOffset = Offset - 8;
1399  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1400  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1401    FPOffset -= 80;
1402  // Estimate an offset from the stack pointer.
1403  // The incoming offset is relating to the SP at the start of the function,
1404  // but when we access the local it'll be relative to the SP after local
1405  // allocation, so adjust our SP-relative offset by that allocation size.
1406  Offset = -Offset;
1407  Offset += MFI->getLocalFrameSize();
1408  // Assume that we'll have at least some spill slots allocated.
1409  // FIXME: This is a total SWAG number. We should run some statistics
1410  //        and pick a real one.
1411  Offset += 128; // 128 bytes of spill slots
1412
1413  // If there is a frame pointer, try using it.
1414  // The FP is only available if there is no dynamic realignment. We
1415  // don't know for sure yet whether we'll need that, so we guess based
1416  // on whether there are any local variables that would trigger it.
1417  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1418  if (hasFP(MF) &&
1419      !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1420    if (isFrameOffsetLegal(MI, FPOffset))
1421      return false;
1422  }
1423  // If we can reference via the stack pointer, try that.
1424  // FIXME: This (and the code that resolves the references) can be improved
1425  //        to only disallow SP relative references in the live range of
1426  //        the VLA(s). In practice, it's unclear how much difference that
1427  //        would make, but it may be worth doing.
1428  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1429    return false;
1430
1431  // The offset likely isn't legal, we want to allocate a virtual base register.
1432  return true;
1433}
1434
1435/// materializeFrameBaseRegister - Insert defining instruction(s) for
1436/// BaseReg to be a pointer to FrameIdx before insertion point I.
1437void ARMBaseRegisterInfo::
1438materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1439                             int FrameIdx, int64_t Offset) const {
1440  ARMFunctionInfo *AFI =
1441    I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1442  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1443    (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1444
1445  MachineInstrBuilder MIB =
1446    BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1447    .addFrameIndex(FrameIdx).addImm(Offset);
1448  if (!AFI->isThumb1OnlyFunction())
1449    AddDefaultCC(AddDefaultPred(MIB));
1450}
1451
1452void
1453ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1454                                       unsigned BaseReg, int64_t Offset) const {
1455  MachineInstr &MI = *I;
1456  MachineBasicBlock &MBB = *MI.getParent();
1457  MachineFunction &MF = *MBB.getParent();
1458  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1459  int Off = Offset; // ARM doesn't need the general 64-bit offsets
1460  unsigned i = 0;
1461
1462  assert(!AFI->isThumb1OnlyFunction() &&
1463         "This resolveFrameIndex does not support Thumb1!");
1464
1465  while (!MI.getOperand(i).isFI()) {
1466    ++i;
1467    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1468  }
1469  bool Done = false;
1470  if (!AFI->isThumbFunction())
1471    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1472  else {
1473    assert(AFI->isThumb2Function());
1474    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1475  }
1476  assert (Done && "Unable to resolve frame index!");
1477}
1478
1479bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1480                                             int64_t Offset) const {
1481  const TargetInstrDesc &Desc = MI->getDesc();
1482  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1483  unsigned i = 0;
1484
1485  while (!MI->getOperand(i).isFI()) {
1486    ++i;
1487    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1488  }
1489
1490  // AddrMode4 and AddrMode6 cannot handle any offset.
1491  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1492    return Offset == 0;
1493
1494  unsigned NumBits = 0;
1495  unsigned Scale = 1;
1496  bool isSigned = true;
1497  switch (AddrMode) {
1498  case ARMII::AddrModeT2_i8:
1499  case ARMII::AddrModeT2_i12:
1500    // i8 supports only negative, and i12 supports only positive, so
1501    // based on Offset sign, consider the appropriate instruction
1502    Scale = 1;
1503    if (Offset < 0) {
1504      NumBits = 8;
1505      Offset = -Offset;
1506    } else {
1507      NumBits = 12;
1508    }
1509    break;
1510  case ARMII::AddrMode5:
1511    // VFP address mode.
1512    NumBits = 8;
1513    Scale = 4;
1514    break;
1515  case ARMII::AddrMode2:
1516    NumBits = 12;
1517    break;
1518  case ARMII::AddrMode3:
1519    NumBits = 8;
1520    break;
1521  case ARMII::AddrModeT1_s:
1522    NumBits = 5;
1523    Scale = 4;
1524    isSigned = false;
1525    break;
1526  default:
1527    llvm_unreachable("Unsupported addressing mode!");
1528    break;
1529  }
1530
1531  Offset += getFrameIndexInstrOffset(MI, i);
1532  // Make sure the offset is encodable for instructions that scale the
1533  // immediate.
1534  if ((Offset & (Scale-1)) != 0)
1535    return false;
1536
1537  if (isSigned && Offset < 0)
1538    Offset = -Offset;
1539
1540  unsigned Mask = (1 << NumBits) - 1;
1541  if ((unsigned)Offset <= Mask * Scale)
1542    return true;
1543
1544  return false;
1545}
1546
1547void
1548ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1549                                         int SPAdj, RegScavenger *RS) const {
1550  unsigned i = 0;
1551  MachineInstr &MI = *II;
1552  MachineBasicBlock &MBB = *MI.getParent();
1553  MachineFunction &MF = *MBB.getParent();
1554  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1555  assert(!AFI->isThumb1OnlyFunction() &&
1556         "This eliminateFrameIndex does not support Thumb1!");
1557
1558  while (!MI.getOperand(i).isFI()) {
1559    ++i;
1560    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1561  }
1562
1563  int FrameIndex = MI.getOperand(i).getIndex();
1564  unsigned FrameReg;
1565
1566  int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1567
1568  // Special handling of dbg_value instructions.
1569  if (MI.isDebugValue()) {
1570    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1571    MI.getOperand(i+1).ChangeToImmediate(Offset);
1572    return;
1573  }
1574
1575  // Modify MI as necessary to handle as much of 'Offset' as possible
1576  bool Done = false;
1577  if (!AFI->isThumbFunction())
1578    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1579  else {
1580    assert(AFI->isThumb2Function());
1581    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1582  }
1583  if (Done)
1584    return;
1585
1586  // If we get here, the immediate doesn't fit into the instruction.  We folded
1587  // as much as possible above, handle the rest, providing a register that is
1588  // SP+LargeImm.
1589  assert((Offset ||
1590          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1591          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1592         "This code isn't needed if offset already handled!");
1593
1594  unsigned ScratchReg = 0;
1595  int PIdx = MI.findFirstPredOperandIdx();
1596  ARMCC::CondCodes Pred = (PIdx == -1)
1597    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1598  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1599  if (Offset == 0)
1600    // Must be addrmode4/6.
1601    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1602  else {
1603    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1604    if (!AFI->isThumbFunction())
1605      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1606                              Offset, Pred, PredReg, TII);
1607    else {
1608      assert(AFI->isThumb2Function());
1609      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1610                             Offset, Pred, PredReg, TII);
1611    }
1612    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1613  }
1614}
1615
1616/// Move iterator past the next bunch of callee save load / store ops for
1617/// the particular spill area (1: integer area 1, 2: fp area, 0: don't care).
1618static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1619                                   MachineBasicBlock::iterator &MBBI,
1620                                   int Opc1, int Opc2, unsigned Area,
1621                                   const ARMSubtarget &STI) {
1622  while (MBBI != MBB.end() &&
1623         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1624         MBBI->getOperand(1).isFI()) {
1625    if (Area != 0) {
1626      bool Done = false;
1627      unsigned Category = 0;
1628      switch (MBBI->getOperand(0).getReg()) {
1629      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1630      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1631      case ARM::LR:
1632        Category = 1;
1633        break;
1634      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1635      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1636        Category = 2;
1637        break;
1638      default:
1639        Done = true;
1640        break;
1641      }
1642      if (Done || Category != Area)
1643        break;
1644    }
1645
1646    ++MBBI;
1647  }
1648}
1649
1650void ARMBaseRegisterInfo::
1651emitPrologue(MachineFunction &MF) const {
1652  MachineBasicBlock &MBB = MF.front();
1653  MachineBasicBlock::iterator MBBI = MBB.begin();
1654  MachineFrameInfo  *MFI = MF.getFrameInfo();
1655  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1656  assert(!AFI->isThumb1OnlyFunction() &&
1657         "This emitPrologue does not support Thumb1!");
1658  bool isARM = !AFI->isThumbFunction();
1659  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1660  unsigned NumBytes = MFI->getStackSize();
1661  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1662  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1663
1664  // Determine the sizes of each callee-save spill areas and record which frame
1665  // belongs to which callee-save spill areas.
1666  unsigned GPRCSSize = 0/*, GPRCS2Size = 0*/, DPRCSSize = 0;
1667  int FramePtrSpillFI = 0;
1668
1669  // Allocate the vararg register save area. This is not counted in NumBytes.
1670  if (VARegSaveSize)
1671    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1672
1673  if (!AFI->hasStackFrame()) {
1674    if (NumBytes != 0)
1675      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1676    return;
1677  }
1678
1679  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1680    unsigned Reg = CSI[i].getReg();
1681    int FI = CSI[i].getFrameIdx();
1682    switch (Reg) {
1683    case ARM::R4:
1684    case ARM::R5:
1685    case ARM::R6:
1686    case ARM::R7:
1687    case ARM::R8:
1688    case ARM::R9:
1689    case ARM::R10:
1690    case ARM::R11:
1691    case ARM::LR:
1692      if (Reg == FramePtr)
1693        FramePtrSpillFI = FI;
1694      AFI->addGPRCalleeSavedAreaFrame(FI);
1695      GPRCSSize += 4;
1696      break;
1697    default:
1698      AFI->addDPRCalleeSavedAreaFrame(FI);
1699      DPRCSSize += 8;
1700    }
1701  }
1702
1703  // Build the new SUBri to adjust SP for integer callee-save spill area.
1704  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCSSize);
1705  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1706
1707  // Set FP to point to the stack slot that contains the previous FP.
1708  bool HasFP = hasFP(MF);
1709  if (HasFP) {
1710    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1711    MachineInstrBuilder MIB =
1712      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1713      .addFrameIndex(FramePtrSpillFI).addImm(0);
1714    AddDefaultCC(AddDefaultPred(MIB));
1715  }
1716
1717  // Build the new SUBri to adjust SP for FP callee-save spill area.
1718  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1719
1720  // Determine starting offsets of spill areas.
1721  unsigned DPRCSOffset  = NumBytes - (GPRCSSize + DPRCSSize);
1722  unsigned GPRCSOffset = DPRCSOffset + DPRCSSize;
1723  if (HasFP)
1724    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1725                                NumBytes);
1726  AFI->setGPRCalleeSavedAreaOffset(GPRCSOffset);
1727  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1728
1729  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 2, STI);
1730  NumBytes = DPRCSOffset;
1731  if (NumBytes) {
1732    // Adjust SP after all the callee-save spills.
1733    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1734    if (HasFP)
1735      AFI->setShouldRestoreSPFromFP(true);
1736  }
1737
1738  if (STI.isTargetELF() && hasFP(MF)) {
1739    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1740                             AFI->getFramePtrSpillOffset());
1741    AFI->setShouldRestoreSPFromFP(true);
1742  }
1743
1744  AFI->setGPRCalleeSavedAreaSize(GPRCSSize);
1745  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1746
1747  // If we need dynamic stack realignment, do it here. Be paranoid and make
1748  // sure if we also have VLAs, we have a base pointer for frame access.
1749  if (needsStackRealignment(MF)) {
1750    unsigned MaxAlign = MFI->getMaxAlignment();
1751    assert (!AFI->isThumb1OnlyFunction());
1752    if (!AFI->isThumbFunction()) {
1753      // Emit bic sp, sp, MaxAlign
1754      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1755                                          TII.get(ARM::BICri), ARM::SP)
1756                                  .addReg(ARM::SP, RegState::Kill)
1757                                  .addImm(MaxAlign-1)));
1758    } else {
1759      // We cannot use sp as source/dest register here, thus we're emitting the
1760      // following sequence:
1761      // mov r4, sp
1762      // bic r4, r4, MaxAlign
1763      // mov sp, r4
1764      // FIXME: It will be better just to find spare register here.
1765      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1766        .addReg(ARM::SP, RegState::Kill);
1767      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1768                                          TII.get(ARM::t2BICri), ARM::R4)
1769                                  .addReg(ARM::R4, RegState::Kill)
1770                                  .addImm(MaxAlign-1)));
1771      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1772        .addReg(ARM::R4, RegState::Kill);
1773    }
1774
1775    AFI->setShouldRestoreSPFromFP(true);
1776  }
1777
1778  // If we need a base pointer, set it up here. It's whatever the value
1779  // of the stack pointer is at this point. Any variable size objects
1780  // will be allocated after this, so we can still use the base pointer
1781  // to reference locals.
1782  if (hasBasePointer(MF)) {
1783    if (isARM)
1784      BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), BasePtr)
1785        .addReg(ARM::SP)
1786        .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1787    else
1788      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
1789        .addReg(ARM::SP);
1790  }
1791
1792  // If the frame has variable sized objects then the epilogue must restore
1793  // the sp from fp.
1794  if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
1795    AFI->setShouldRestoreSPFromFP(true);
1796}
1797
1798static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1799  for (unsigned i = 0; CSRegs[i]; ++i)
1800    if (Reg == CSRegs[i])
1801      return true;
1802  return false;
1803}
1804
1805static bool isCSRestore(MachineInstr *MI,
1806                        const ARMBaseInstrInfo &TII,
1807                        const unsigned *CSRegs) {
1808  return ((MI->getOpcode() == (int)ARM::VLDRD ||
1809           MI->getOpcode() == (int)ARM::LDR ||
1810           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1811          MI->getOperand(1).isFI() &&
1812          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1813}
1814
1815void ARMBaseRegisterInfo::
1816emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1817  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1818  assert(MBBI->getDesc().isReturn() &&
1819         "Can only insert epilog into returning blocks");
1820  unsigned RetOpcode = MBBI->getOpcode();
1821  DebugLoc dl = MBBI->getDebugLoc();
1822  MachineFrameInfo *MFI = MF.getFrameInfo();
1823  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1824  assert(!AFI->isThumb1OnlyFunction() &&
1825         "This emitEpilogue does not support Thumb1!");
1826  bool isARM = !AFI->isThumbFunction();
1827
1828  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1829  int NumBytes = (int)MFI->getStackSize();
1830
1831  if (!AFI->hasStackFrame()) {
1832    if (NumBytes != 0)
1833      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1834  } else {
1835    // Unwind MBBI to point to first LDR / VLDRD.
1836    const unsigned *CSRegs = getCalleeSavedRegs();
1837    if (MBBI != MBB.begin()) {
1838      do
1839        --MBBI;
1840      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1841      if (!isCSRestore(MBBI, TII, CSRegs))
1842        ++MBBI;
1843    }
1844
1845    // Move SP to start of FP callee save spill area.
1846    NumBytes -= (AFI->getGPRCalleeSavedAreaSize() +
1847                 AFI->getDPRCalleeSavedAreaSize());
1848
1849    // Reset SP based on frame pointer only if the stack frame extends beyond
1850    // frame pointer stack slot or target is ELF and the function has FP.
1851    if (AFI->shouldRestoreSPFromFP()) {
1852      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1853      if (NumBytes) {
1854        if (isARM)
1855          emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1856                                  ARMCC::AL, 0, TII);
1857        else
1858          emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1859                                 ARMCC::AL, 0, TII);
1860      } else {
1861        // Thumb2 or ARM.
1862        if (isARM)
1863          BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1864            .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1865        else
1866          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1867            .addReg(FramePtr);
1868      }
1869    } else if (NumBytes)
1870      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1871
1872    // Move SP to start of integer callee save spill area.
1873    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 2, STI);
1874    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1875
1876    // Move SP to SP upon entry to the function.
1877    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1878    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedAreaSize());
1879  }
1880
1881  if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1882      RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1883    // Tail call return: adjust the stack pointer and jump to callee.
1884    MBBI = prior(MBB.end());
1885    MachineOperand &JumpTarget = MBBI->getOperand(0);
1886
1887    // Jump to label or value in register.
1888    if (RetOpcode == ARM::TCRETURNdi) {
1889      BuildMI(MBB, MBBI, dl,
1890            TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
1891        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1892                         JumpTarget.getTargetFlags());
1893    } else if (RetOpcode == ARM::TCRETURNdiND) {
1894      BuildMI(MBB, MBBI, dl,
1895            TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
1896        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1897                         JumpTarget.getTargetFlags());
1898    } else if (RetOpcode == ARM::TCRETURNri) {
1899      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
1900        addReg(JumpTarget.getReg(), RegState::Kill);
1901    } else if (RetOpcode == ARM::TCRETURNriND) {
1902      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
1903        addReg(JumpTarget.getReg(), RegState::Kill);
1904    }
1905
1906    MachineInstr *NewMI = prior(MBBI);
1907    for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1908      NewMI->addOperand(MBBI->getOperand(i));
1909
1910    // Delete the pseudo instruction TCRETURN.
1911    MBB.erase(MBBI);
1912  }
1913
1914  if (VARegSaveSize)
1915    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
1916}
1917
1918#include "ARMGenRegisterInfo.inc"
1919