ARMBaseRegisterInfo.cpp revision e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARM.h" 15#include "ARMAddressingModes.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMBaseRegisterInfo.h" 18#include "ARMInstrInfo.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMSubtarget.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/LLVMContext.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineLocation.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/RegisterScavenging.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetFrameInfo.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/BitVector.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/Support/CommandLine.h" 41 42namespace llvm { 43cl::opt<bool> 44ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true), 45 cl::desc("Reuse repeated frame index values")); 46} 47 48using namespace llvm; 49 50unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, 51 bool *isSPVFP) { 52 if (isSPVFP) 53 *isSPVFP = false; 54 55 using namespace ARM; 56 switch (RegEnum) { 57 default: 58 llvm_unreachable("Unknown ARM register!"); 59 case R0: case D0: case Q0: return 0; 60 case R1: case D1: case Q1: return 1; 61 case R2: case D2: case Q2: return 2; 62 case R3: case D3: case Q3: return 3; 63 case R4: case D4: case Q4: return 4; 64 case R5: case D5: case Q5: return 5; 65 case R6: case D6: case Q6: return 6; 66 case R7: case D7: case Q7: return 7; 67 case R8: case D8: case Q8: return 8; 68 case R9: case D9: case Q9: return 9; 69 case R10: case D10: case Q10: return 10; 70 case R11: case D11: case Q11: return 11; 71 case R12: case D12: case Q12: return 12; 72 case SP: case D13: case Q13: return 13; 73 case LR: case D14: case Q14: return 14; 74 case PC: case D15: case Q15: return 15; 75 76 case D16: return 16; 77 case D17: return 17; 78 case D18: return 18; 79 case D19: return 19; 80 case D20: return 20; 81 case D21: return 21; 82 case D22: return 22; 83 case D23: return 23; 84 case D24: return 24; 85 case D25: return 25; 86 case D26: return 26; 87 case D27: return 27; 88 case D28: return 28; 89 case D29: return 29; 90 case D30: return 30; 91 case D31: return 31; 92 93 case S0: case S1: case S2: case S3: 94 case S4: case S5: case S6: case S7: 95 case S8: case S9: case S10: case S11: 96 case S12: case S13: case S14: case S15: 97 case S16: case S17: case S18: case S19: 98 case S20: case S21: case S22: case S23: 99 case S24: case S25: case S26: case S27: 100 case S28: case S29: case S30: case S31: { 101 if (isSPVFP) 102 *isSPVFP = true; 103 switch (RegEnum) { 104 default: return 0; // Avoid compile time warning. 105 case S0: return 0; 106 case S1: return 1; 107 case S2: return 2; 108 case S3: return 3; 109 case S4: return 4; 110 case S5: return 5; 111 case S6: return 6; 112 case S7: return 7; 113 case S8: return 8; 114 case S9: return 9; 115 case S10: return 10; 116 case S11: return 11; 117 case S12: return 12; 118 case S13: return 13; 119 case S14: return 14; 120 case S15: return 15; 121 case S16: return 16; 122 case S17: return 17; 123 case S18: return 18; 124 case S19: return 19; 125 case S20: return 20; 126 case S21: return 21; 127 case S22: return 22; 128 case S23: return 23; 129 case S24: return 24; 130 case S25: return 25; 131 case S26: return 26; 132 case S27: return 27; 133 case S28: return 28; 134 case S29: return 29; 135 case S30: return 30; 136 case S31: return 31; 137 } 138 } 139 } 140} 141 142ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 143 const ARMSubtarget &sti) 144 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 145 TII(tii), STI(sti), 146 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 147} 148 149const unsigned* 150ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 151 static const unsigned CalleeSavedRegs[] = { 152 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 153 ARM::R7, ARM::R6, ARM::R5, ARM::R4, 154 155 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 156 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 157 0 158 }; 159 160 static const unsigned DarwinCalleeSavedRegs[] = { 161 // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 162 // register. 163 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 164 ARM::R11, ARM::R10, ARM::R8, 165 166 ARM::D15, ARM::D14, ARM::D13, ARM::D12, 167 ARM::D11, ARM::D10, ARM::D9, ARM::D8, 168 0 169 }; 170 return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 171} 172 173BitVector ARMBaseRegisterInfo:: 174getReservedRegs(const MachineFunction &MF) const { 175 // FIXME: avoid re-calculating this everytime. 176 BitVector Reserved(getNumRegs()); 177 Reserved.set(ARM::SP); 178 Reserved.set(ARM::PC); 179 Reserved.set(ARM::FPSCR); 180 if (STI.isTargetDarwin() || hasFP(MF)) 181 Reserved.set(FramePtr); 182 // Some targets reserve R9. 183 if (STI.isR9Reserved()) 184 Reserved.set(ARM::R9); 185 return Reserved; 186} 187 188bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 189 unsigned Reg) const { 190 switch (Reg) { 191 default: break; 192 case ARM::SP: 193 case ARM::PC: 194 return true; 195 case ARM::R7: 196 case ARM::R11: 197 if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 198 return true; 199 break; 200 case ARM::R9: 201 return STI.isR9Reserved(); 202 } 203 204 return false; 205} 206 207const TargetRegisterClass * 208ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 209 const TargetRegisterClass *B, 210 unsigned SubIdx) const { 211 switch (SubIdx) { 212 default: return 0; 213 case ARM::ssub_0: 214 case ARM::ssub_1: 215 case ARM::ssub_2: 216 case ARM::ssub_3: { 217 // S sub-registers. 218 if (A->getSize() == 8) { 219 if (B == &ARM::SPR_8RegClass) 220 return &ARM::DPR_8RegClass; 221 assert(B == &ARM::SPRRegClass && "Expecting SPR register class!"); 222 if (A == &ARM::DPR_8RegClass) 223 return A; 224 return &ARM::DPR_VFP2RegClass; 225 } 226 227 if (A->getSize() == 16) { 228 if (B == &ARM::SPR_8RegClass) 229 return &ARM::QPR_8RegClass; 230 return &ARM::QPR_VFP2RegClass; 231 } 232 233 if (A->getSize() == 32) { 234 if (B == &ARM::SPR_8RegClass) 235 return 0; // Do not allow coalescing! 236 return &ARM::QQPR_VFP2RegClass; 237 } 238 239 assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 240 return 0; // Do not allow coalescing! 241 } 242 case ARM::dsub_0: 243 case ARM::dsub_1: 244 case ARM::dsub_2: 245 case ARM::dsub_3: { 246 // D sub-registers. 247 if (A->getSize() == 16) { 248 if (B == &ARM::DPR_VFP2RegClass) 249 return &ARM::QPR_VFP2RegClass; 250 if (B == &ARM::DPR_8RegClass) 251 return 0; // Do not allow coalescing! 252 return A; 253 } 254 255 if (A->getSize() == 32) { 256 if (B == &ARM::DPR_VFP2RegClass) 257 return &ARM::QQPR_VFP2RegClass; 258 if (B == &ARM::DPR_8RegClass) 259 return 0; // Do not allow coalescing! 260 return A; 261 } 262 263 assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 264 if (B != &ARM::DPRRegClass) 265 return 0; // Do not allow coalescing! 266 return A; 267 } 268 case ARM::dsub_4: 269 case ARM::dsub_5: 270 case ARM::dsub_6: 271 case ARM::dsub_7: { 272 // D sub-registers of QQQQ registers. 273 if (A->getSize() == 64 && B == &ARM::DPRRegClass) 274 return A; 275 return 0; // Do not allow coalescing! 276 } 277 278 case ARM::qsub_0: 279 case ARM::qsub_1: { 280 // Q sub-registers. 281 if (A->getSize() == 32) { 282 if (B == &ARM::QPR_VFP2RegClass) 283 return &ARM::QQPR_VFP2RegClass; 284 if (B == &ARM::QPR_8RegClass) 285 return 0; // Do not allow coalescing! 286 return A; 287 } 288 289 assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 290 if (B == &ARM::QPRRegClass) 291 return A; 292 return 0; // Do not allow coalescing! 293 } 294 case ARM::qsub_2: 295 case ARM::qsub_3: { 296 // Q sub-registers of QQQQ registers. 297 if (A->getSize() == 64 && B == &ARM::QPRRegClass) 298 return A; 299 return 0; // Do not allow coalescing! 300 } 301 } 302 return 0; 303} 304 305bool 306ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC, 307 SmallVectorImpl<unsigned> &SubIndices, 308 unsigned &NewSubIdx) const { 309 310 unsigned Size = RC->getSize() * 8; 311 if (Size < 6) 312 return 0; 313 314 NewSubIdx = 0; // Whole register. 315 unsigned NumRegs = SubIndices.size(); 316 if (NumRegs == 8) { 317 // 8 D registers -> 1 QQQQ register. 318 return (Size == 512 && 319 SubIndices[0] == ARM::dsub_0 && 320 SubIndices[1] == ARM::dsub_1 && 321 SubIndices[2] == ARM::dsub_2 && 322 SubIndices[3] == ARM::dsub_3 && 323 SubIndices[4] == ARM::dsub_4 && 324 SubIndices[5] == ARM::dsub_5 && 325 SubIndices[6] == ARM::dsub_6 && 326 SubIndices[7] == ARM::dsub_7); 327 } else if (NumRegs == 4) { 328 if (SubIndices[0] == ARM::qsub_0) { 329 // 4 Q registers -> 1 QQQQ register. 330 return (Size == 512 && 331 SubIndices[1] == ARM::qsub_1 && 332 SubIndices[2] == ARM::qsub_2 && 333 SubIndices[3] == ARM::qsub_3); 334 } else if (SubIndices[0] == ARM::dsub_0) { 335 // 4 D registers -> 1 QQ register. 336 if (Size >= 256 && 337 SubIndices[1] == ARM::dsub_1 && 338 SubIndices[2] == ARM::dsub_2 && 339 SubIndices[3] == ARM::dsub_3) { 340 if (Size == 512) 341 NewSubIdx = ARM::qqsub_0; 342 return true; 343 } 344 } else if (SubIndices[0] == ARM::dsub_4) { 345 // 4 D registers -> 1 QQ register (2nd). 346 if (Size == 512 && 347 SubIndices[1] == ARM::dsub_5 && 348 SubIndices[2] == ARM::dsub_6 && 349 SubIndices[3] == ARM::dsub_7) { 350 NewSubIdx = ARM::qqsub_1; 351 return true; 352 } 353 } else if (SubIndices[0] == ARM::ssub_0) { 354 // 4 S registers -> 1 Q register. 355 if (Size >= 128 && 356 SubIndices[1] == ARM::ssub_1 && 357 SubIndices[2] == ARM::ssub_2 && 358 SubIndices[3] == ARM::ssub_3) { 359 if (Size >= 256) 360 NewSubIdx = ARM::qsub_0; 361 return true; 362 } 363 } 364 } else if (NumRegs == 2) { 365 if (SubIndices[0] == ARM::qsub_0) { 366 // 2 Q registers -> 1 QQ register. 367 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) { 368 if (Size == 512) 369 NewSubIdx = ARM::qqsub_0; 370 return true; 371 } 372 } else if (SubIndices[0] == ARM::qsub_2) { 373 // 2 Q registers -> 1 QQ register (2nd). 374 if (Size == 512 && SubIndices[1] == ARM::qsub_3) { 375 NewSubIdx = ARM::qqsub_1; 376 return true; 377 } 378 } else if (SubIndices[0] == ARM::dsub_0) { 379 // 2 D registers -> 1 Q register. 380 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) { 381 if (Size >= 256) 382 NewSubIdx = ARM::qsub_0; 383 return true; 384 } 385 } else if (SubIndices[0] == ARM::dsub_2) { 386 // 2 D registers -> 1 Q register (2nd). 387 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) { 388 NewSubIdx = ARM::qsub_1; 389 return true; 390 } 391 } else if (SubIndices[0] == ARM::dsub_4) { 392 // 2 D registers -> 1 Q register (3rd). 393 if (Size == 512 && SubIndices[1] == ARM::dsub_5) { 394 NewSubIdx = ARM::qsub_2; 395 return true; 396 } 397 } else if (SubIndices[0] == ARM::dsub_6) { 398 // 2 D registers -> 1 Q register (3rd). 399 if (Size == 512 && SubIndices[1] == ARM::dsub_7) { 400 NewSubIdx = ARM::qsub_3; 401 return true; 402 } 403 } else if (SubIndices[0] == ARM::ssub_0) { 404 // 2 S registers -> 1 D register. 405 if (SubIndices[1] == ARM::ssub_1) { 406 if (Size >= 128) 407 NewSubIdx = ARM::dsub_0; 408 return true; 409 } 410 } else if (SubIndices[0] == ARM::ssub_2) { 411 // 2 S registers -> 1 D register (2nd). 412 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) { 413 NewSubIdx = ARM::dsub_1; 414 return true; 415 } 416 } 417 } 418 return false; 419} 420 421 422const TargetRegisterClass * 423ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { 424 return ARM::GPRRegisterClass; 425} 426 427/// getAllocationOrder - Returns the register allocation order for a specified 428/// register class in the form of a pair of TargetRegisterClass iterators. 429std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 430ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, 431 unsigned HintType, unsigned HintReg, 432 const MachineFunction &MF) const { 433 // Alternative register allocation orders when favoring even / odd registers 434 // of register pairs. 435 436 // No FP, R9 is available. 437 static const unsigned GPREven1[] = { 438 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 439 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 440 ARM::R9, ARM::R11 441 }; 442 static const unsigned GPROdd1[] = { 443 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 444 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 445 ARM::R8, ARM::R10 446 }; 447 448 // FP is R7, R9 is available. 449 static const unsigned GPREven2[] = { 450 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 451 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 452 ARM::R9, ARM::R11 453 }; 454 static const unsigned GPROdd2[] = { 455 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 456 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 457 ARM::R8, ARM::R10 458 }; 459 460 // FP is R11, R9 is available. 461 static const unsigned GPREven3[] = { 462 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 463 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 464 ARM::R9 465 }; 466 static const unsigned GPROdd3[] = { 467 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 468 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 469 ARM::R8 470 }; 471 472 // No FP, R9 is not available. 473 static const unsigned GPREven4[] = { 474 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 475 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 476 ARM::R11 477 }; 478 static const unsigned GPROdd4[] = { 479 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 480 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 481 ARM::R10 482 }; 483 484 // FP is R7, R9 is not available. 485 static const unsigned GPREven5[] = { 486 ARM::R0, ARM::R2, ARM::R4, ARM::R10, 487 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 488 ARM::R11 489 }; 490 static const unsigned GPROdd5[] = { 491 ARM::R1, ARM::R3, ARM::R5, ARM::R11, 492 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 493 ARM::R10 494 }; 495 496 // FP is R11, R9 is not available. 497 static const unsigned GPREven6[] = { 498 ARM::R0, ARM::R2, ARM::R4, ARM::R6, 499 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 500 }; 501 static const unsigned GPROdd6[] = { 502 ARM::R1, ARM::R3, ARM::R5, ARM::R7, 503 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 504 }; 505 506 507 if (HintType == ARMRI::RegPairEven) { 508 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 509 // It's no longer possible to fulfill this hint. Return the default 510 // allocation order. 511 return std::make_pair(RC->allocation_order_begin(MF), 512 RC->allocation_order_end(MF)); 513 514 if (!STI.isTargetDarwin() && !hasFP(MF)) { 515 if (!STI.isR9Reserved()) 516 return std::make_pair(GPREven1, 517 GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); 518 else 519 return std::make_pair(GPREven4, 520 GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); 521 } else if (FramePtr == ARM::R7) { 522 if (!STI.isR9Reserved()) 523 return std::make_pair(GPREven2, 524 GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); 525 else 526 return std::make_pair(GPREven5, 527 GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); 528 } else { // FramePtr == ARM::R11 529 if (!STI.isR9Reserved()) 530 return std::make_pair(GPREven3, 531 GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); 532 else 533 return std::make_pair(GPREven6, 534 GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); 535 } 536 } else if (HintType == ARMRI::RegPairOdd) { 537 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 538 // It's no longer possible to fulfill this hint. Return the default 539 // allocation order. 540 return std::make_pair(RC->allocation_order_begin(MF), 541 RC->allocation_order_end(MF)); 542 543 if (!STI.isTargetDarwin() && !hasFP(MF)) { 544 if (!STI.isR9Reserved()) 545 return std::make_pair(GPROdd1, 546 GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); 547 else 548 return std::make_pair(GPROdd4, 549 GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); 550 } else if (FramePtr == ARM::R7) { 551 if (!STI.isR9Reserved()) 552 return std::make_pair(GPROdd2, 553 GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); 554 else 555 return std::make_pair(GPROdd5, 556 GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); 557 } else { // FramePtr == ARM::R11 558 if (!STI.isR9Reserved()) 559 return std::make_pair(GPROdd3, 560 GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); 561 else 562 return std::make_pair(GPROdd6, 563 GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); 564 } 565 } 566 return std::make_pair(RC->allocation_order_begin(MF), 567 RC->allocation_order_end(MF)); 568} 569 570/// ResolveRegAllocHint - Resolves the specified register allocation hint 571/// to a physical register. Returns the physical register if it is successful. 572unsigned 573ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 574 const MachineFunction &MF) const { 575 if (Reg == 0 || !isPhysicalRegister(Reg)) 576 return 0; 577 if (Type == 0) 578 return Reg; 579 else if (Type == (unsigned)ARMRI::RegPairOdd) 580 // Odd register. 581 return getRegisterPairOdd(Reg, MF); 582 else if (Type == (unsigned)ARMRI::RegPairEven) 583 // Even register. 584 return getRegisterPairEven(Reg, MF); 585 return 0; 586} 587 588void 589ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 590 MachineFunction &MF) const { 591 MachineRegisterInfo *MRI = &MF.getRegInfo(); 592 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 593 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 594 Hint.first == (unsigned)ARMRI::RegPairEven) && 595 Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { 596 // If 'Reg' is one of the even / odd register pair and it's now changed 597 // (e.g. coalesced) into a different register. The other register of the 598 // pair allocation hint must be updated to reflect the relationship 599 // change. 600 unsigned OtherReg = Hint.second; 601 Hint = MRI->getRegAllocationHint(OtherReg); 602 if (Hint.second == Reg) 603 // Make sure the pair has not already divorced. 604 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 605 } 606} 607 608/// hasFP - Return true if the specified function should have a dedicated frame 609/// pointer register. This is true if the function has variable sized allocas 610/// or if frame pointer elimination is disabled. 611/// 612bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { 613 const MachineFrameInfo *MFI = MF.getFrameInfo(); 614 return ((DisableFramePointerElim(MF) && MFI->adjustsStack())|| 615 needsStackRealignment(MF) || 616 MFI->hasVarSizedObjects() || 617 MFI->isFrameAddressTaken()); 618} 619 620bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 621 const MachineFrameInfo *MFI = MF.getFrameInfo(); 622 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 623 return (RealignStack && 624 !AFI->isThumb1OnlyFunction() && 625 !MFI->hasVarSizedObjects()); 626} 627 628bool ARMBaseRegisterInfo:: 629needsStackRealignment(const MachineFunction &MF) const { 630 const MachineFrameInfo *MFI = MF.getFrameInfo(); 631 const Function *F = MF.getFunction(); 632 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 633 unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 634 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 635 F->hasFnAttr(Attribute::StackAlignment)); 636 637 // FIXME: Currently we don't support stack realignment for functions with 638 // variable-sized allocas. 639 // FIXME: It's more complicated than this... 640 if (0 && requiresRealignment && MFI->hasVarSizedObjects()) 641 report_fatal_error( 642 "Stack realignment in presense of dynamic allocas is not supported"); 643 644 // FIXME: This probably isn't the right place for this. 645 if (0 && requiresRealignment && AFI->isThumb1OnlyFunction()) 646 report_fatal_error( 647 "Stack realignment in thumb1 functions is not supported"); 648 649 return requiresRealignment && canRealignStack(MF); 650} 651 652bool ARMBaseRegisterInfo:: 653cannotEliminateFrame(const MachineFunction &MF) const { 654 const MachineFrameInfo *MFI = MF.getFrameInfo(); 655 if (DisableFramePointerElim(MF) && MFI->adjustsStack()) 656 return true; 657 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 658 || needsStackRealignment(MF); 659} 660 661/// estimateStackSize - Estimate and return the size of the frame. 662static unsigned estimateStackSize(MachineFunction &MF) { 663 const MachineFrameInfo *FFI = MF.getFrameInfo(); 664 int Offset = 0; 665 for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 666 int FixedOff = -FFI->getObjectOffset(i); 667 if (FixedOff > Offset) Offset = FixedOff; 668 } 669 for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 670 if (FFI->isDeadObjectIndex(i)) 671 continue; 672 Offset += FFI->getObjectSize(i); 673 unsigned Align = FFI->getObjectAlignment(i); 674 // Adjust to alignment boundary 675 Offset = (Offset+Align-1)/Align*Align; 676 } 677 return (unsigned)Offset; 678} 679 680/// estimateRSStackSizeLimit - Look at each instruction that references stack 681/// frames and return the stack size limit beyond which some of these 682/// instructions will require a scratch register during their expansion later. 683unsigned 684ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const { 685 unsigned Limit = (1 << 12) - 1; 686 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 687 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 688 I != E; ++I) { 689 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 690 if (!I->getOperand(i).isFI()) continue; 691 692 // When using ADDri to get the address of a stack object, 255 is the 693 // largest offset guaranteed to fit in the immediate offset. 694 if (I->getOpcode() == ARM::ADDri) { 695 Limit = std::min(Limit, (1U << 8) - 1); 696 break; 697 } 698 699 // Otherwise check the addressing mode. 700 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) { 701 case ARMII::AddrMode3: 702 case ARMII::AddrModeT2_i8: 703 Limit = std::min(Limit, (1U << 8) - 1); 704 break; 705 case ARMII::AddrMode5: 706 case ARMII::AddrModeT2_i8s4: 707 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 708 break; 709 case ARMII::AddrModeT2_i12: 710 if (hasFP(MF)) Limit = std::min(Limit, (1U << 8) - 1); 711 break; 712 case ARMII::AddrMode6: 713 // Addressing mode 6 (load/store) instructions can't encode an 714 // immediate offset for stack references. 715 return 0; 716 default: 717 break; 718 } 719 break; // At most one FI per instruction 720 } 721 } 722 } 723 724 return Limit; 725} 726 727static unsigned GetFunctionSizeInBytes(const MachineFunction &MF, 728 const ARMBaseInstrInfo &TII) { 729 unsigned FnSize = 0; 730 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); 731 MBBI != E; ++MBBI) { 732 const MachineBasicBlock &MBB = *MBBI; 733 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); 734 I != E; ++I) 735 FnSize += TII.GetInstSizeInBytes(I); 736 } 737 return FnSize; 738} 739 740void 741ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 742 RegScavenger *RS) const { 743 // This tells PEI to spill the FP as if it is any other callee-save register 744 // to take advantage the eliminateFrameIndex machinery. This also ensures it 745 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 746 // to combine multiple loads / stores. 747 bool CanEliminateFrame = true; 748 bool CS1Spilled = false; 749 bool LRSpilled = false; 750 unsigned NumGPRSpills = 0; 751 SmallVector<unsigned, 4> UnspilledCS1GPRs; 752 SmallVector<unsigned, 4> UnspilledCS2GPRs; 753 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 754 MachineFrameInfo *MFI = MF.getFrameInfo(); 755 756 // Spill R4 if Thumb2 function requires stack realignment - it will be used as 757 // scratch register. 758 // FIXME: It will be better just to find spare register here. 759 if (needsStackRealignment(MF) && 760 AFI->isThumb2Function()) 761 MF.getRegInfo().setPhysRegUsed(ARM::R4); 762 763 // Spill LR if Thumb1 function uses variable length argument lists. 764 if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0) 765 MF.getRegInfo().setPhysRegUsed(ARM::LR); 766 767 // Don't spill FP if the frame can be eliminated. This is determined 768 // by scanning the callee-save registers to see if any is used. 769 const unsigned *CSRegs = getCalleeSavedRegs(); 770 for (unsigned i = 0; CSRegs[i]; ++i) { 771 unsigned Reg = CSRegs[i]; 772 bool Spilled = false; 773 if (MF.getRegInfo().isPhysRegUsed(Reg)) { 774 AFI->setCSRegisterIsSpilled(Reg); 775 Spilled = true; 776 CanEliminateFrame = false; 777 } else { 778 // Check alias registers too. 779 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 780 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 781 Spilled = true; 782 CanEliminateFrame = false; 783 } 784 } 785 } 786 787 if (!ARM::GPRRegisterClass->contains(Reg)) 788 continue; 789 790 if (Spilled) { 791 NumGPRSpills++; 792 793 if (!STI.isTargetDarwin()) { 794 if (Reg == ARM::LR) 795 LRSpilled = true; 796 CS1Spilled = true; 797 continue; 798 } 799 800 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 801 switch (Reg) { 802 case ARM::LR: 803 LRSpilled = true; 804 // Fallthrough 805 case ARM::R4: 806 case ARM::R5: 807 case ARM::R6: 808 case ARM::R7: 809 CS1Spilled = true; 810 break; 811 default: 812 break; 813 } 814 } else { 815 if (!STI.isTargetDarwin()) { 816 UnspilledCS1GPRs.push_back(Reg); 817 continue; 818 } 819 820 switch (Reg) { 821 case ARM::R4: 822 case ARM::R5: 823 case ARM::R6: 824 case ARM::R7: 825 case ARM::LR: 826 UnspilledCS1GPRs.push_back(Reg); 827 break; 828 default: 829 UnspilledCS2GPRs.push_back(Reg); 830 break; 831 } 832 } 833 } 834 835 bool ForceLRSpill = false; 836 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 837 unsigned FnSize = GetFunctionSizeInBytes(MF, TII); 838 // Force LR to be spilled if the Thumb function size is > 2048. This enables 839 // use of BL to implement far jump. If it turns out that it's not needed 840 // then the branch fix up path will undo it. 841 if (FnSize >= (1 << 11)) { 842 CanEliminateFrame = false; 843 ForceLRSpill = true; 844 } 845 } 846 847 // If any of the stack slot references may be out of range of an immediate 848 // offset, make sure a register (or a spill slot) is available for the 849 // register scavenger. Note that if we're indexing off the frame pointer, the 850 // effective stack size is 4 bytes larger since the FP points to the stack 851 // slot of the previous FP. Also, if we have variable sized objects in the 852 // function, stack slot references will often be negative, and some of 853 // our instructions are positive-offset only, so conservatively consider 854 // that case to want a spill slot (or register) as well. Similarly, if 855 // the function adjusts the stack pointer during execution and the 856 // adjustments aren't already part of our stack size estimate, our offset 857 // calculations may be off, so be conservative. 858 // FIXME: We could add logic to be more precise about negative offsets 859 // and which instructions will need a scratch register for them. Is it 860 // worth the effort and added fragility? 861 bool BigStack = 862 (RS && (estimateStackSize(MF) + (hasFP(MF) ? 4:0) >= 863 estimateRSStackSizeLimit(MF))) 864 || MFI->hasVarSizedObjects() 865 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); 866 867 bool ExtraCSSpill = false; 868 if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) { 869 AFI->setHasStackFrame(true); 870 871 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 872 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 873 if (!LRSpilled && CS1Spilled) { 874 MF.getRegInfo().setPhysRegUsed(ARM::LR); 875 AFI->setCSRegisterIsSpilled(ARM::LR); 876 NumGPRSpills++; 877 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 878 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 879 ForceLRSpill = false; 880 ExtraCSSpill = true; 881 } 882 883 // Darwin ABI requires FP to point to the stack slot that contains the 884 // previous FP. 885 if (STI.isTargetDarwin() || hasFP(MF)) { 886 MF.getRegInfo().setPhysRegUsed(FramePtr); 887 NumGPRSpills++; 888 } 889 890 // If stack and double are 8-byte aligned and we are spilling an odd number 891 // of GPRs. Spill one extra callee save GPR so we won't have to pad between 892 // the integer and double callee save areas. 893 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 894 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 895 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 896 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 897 unsigned Reg = UnspilledCS1GPRs[i]; 898 // Don't spill high register if the function is thumb1 899 if (!AFI->isThumb1OnlyFunction() || 900 isARMLowRegister(Reg) || Reg == ARM::LR) { 901 MF.getRegInfo().setPhysRegUsed(Reg); 902 AFI->setCSRegisterIsSpilled(Reg); 903 if (!isReservedReg(MF, Reg)) 904 ExtraCSSpill = true; 905 break; 906 } 907 } 908 } else if (!UnspilledCS2GPRs.empty() && 909 !AFI->isThumb1OnlyFunction()) { 910 unsigned Reg = UnspilledCS2GPRs.front(); 911 MF.getRegInfo().setPhysRegUsed(Reg); 912 AFI->setCSRegisterIsSpilled(Reg); 913 if (!isReservedReg(MF, Reg)) 914 ExtraCSSpill = true; 915 } 916 } 917 918 // Estimate if we might need to scavenge a register at some point in order 919 // to materialize a stack offset. If so, either spill one additional 920 // callee-saved register or reserve a special spill slot to facilitate 921 // register scavenging. Thumb1 needs a spill slot for stack pointer 922 // adjustments also, even when the frame itself is small. 923 if (BigStack && !ExtraCSSpill) { 924 // If any non-reserved CS register isn't spilled, just spill one or two 925 // extra. That should take care of it! 926 unsigned NumExtras = TargetAlign / 4; 927 SmallVector<unsigned, 2> Extras; 928 while (NumExtras && !UnspilledCS1GPRs.empty()) { 929 unsigned Reg = UnspilledCS1GPRs.back(); 930 UnspilledCS1GPRs.pop_back(); 931 if (!isReservedReg(MF, Reg) && 932 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || 933 Reg == ARM::LR)) { 934 Extras.push_back(Reg); 935 NumExtras--; 936 } 937 } 938 // For non-Thumb1 functions, also check for hi-reg CS registers 939 if (!AFI->isThumb1OnlyFunction()) { 940 while (NumExtras && !UnspilledCS2GPRs.empty()) { 941 unsigned Reg = UnspilledCS2GPRs.back(); 942 UnspilledCS2GPRs.pop_back(); 943 if (!isReservedReg(MF, Reg)) { 944 Extras.push_back(Reg); 945 NumExtras--; 946 } 947 } 948 } 949 if (Extras.size() && NumExtras == 0) { 950 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 951 MF.getRegInfo().setPhysRegUsed(Extras[i]); 952 AFI->setCSRegisterIsSpilled(Extras[i]); 953 } 954 } else if (!AFI->isThumb1OnlyFunction()) { 955 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot 956 // closest to SP or frame pointer. 957 const TargetRegisterClass *RC = ARM::GPRRegisterClass; 958 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 959 RC->getAlignment(), 960 false)); 961 } 962 } 963 } 964 965 if (ForceLRSpill) { 966 MF.getRegInfo().setPhysRegUsed(ARM::LR); 967 AFI->setCSRegisterIsSpilled(ARM::LR); 968 AFI->setLRIsSpilledForFarJump(true); 969 } 970} 971 972unsigned ARMBaseRegisterInfo::getRARegister() const { 973 return ARM::LR; 974} 975 976unsigned 977ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 978 if (STI.isTargetDarwin() || hasFP(MF)) 979 return FramePtr; 980 return ARM::SP; 981} 982 983// Provide a base+offset reference to an FI slot for debug info. It's the 984// same as what we use for resolving the code-gen references for now. 985// FIXME: This can go wrong when references are SP-relative and simple call 986// frames aren't used. 987int 988ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI, 989 unsigned &FrameReg) const { 990 return ResolveFrameIndexReference(MF, FI, FrameReg, 0); 991} 992 993int 994ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF, 995 int FI, 996 unsigned &FrameReg, 997 int SPAdj) const { 998 const MachineFrameInfo *MFI = MF.getFrameInfo(); 999 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1000 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 1001 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 1002 bool isFixed = MFI->isFixedObjectIndex(FI); 1003 1004 FrameReg = ARM::SP; 1005 Offset += SPAdj; 1006 if (AFI->isGPRCalleeSavedArea1Frame(FI)) 1007 return Offset - AFI->getGPRCalleeSavedArea1Offset(); 1008 else if (AFI->isGPRCalleeSavedArea2Frame(FI)) 1009 return Offset - AFI->getGPRCalleeSavedArea2Offset(); 1010 else if (AFI->isDPRCalleeSavedAreaFrame(FI)) 1011 return Offset - AFI->getDPRCalleeSavedAreaOffset(); 1012 1013 // When dynamically realigning the stack, use the frame pointer for 1014 // parameters, and the stack pointer for locals. 1015 if (needsStackRealignment(MF)) { 1016 assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 1017 if (isFixed) { 1018 FrameReg = getFrameRegister(MF); 1019 Offset = FPOffset; 1020 } 1021 return Offset; 1022 } 1023 1024 // If there is a frame pointer, use it when we can. 1025 if (hasFP(MF) && AFI->hasStackFrame()) { 1026 // Use frame pointer to reference fixed objects. Use it for locals if 1027 // there are VLAs (and thus the SP isn't reliable as a base). 1028 if (isFixed || MFI->hasVarSizedObjects()) { 1029 FrameReg = getFrameRegister(MF); 1030 Offset = FPOffset; 1031 } else if (AFI->isThumb2Function()) { 1032 // In Thumb2 mode, the negative offset is very limited. Try to avoid 1033 // out of range references. 1034 if (FPOffset >= -255 && FPOffset < 0) { 1035 FrameReg = getFrameRegister(MF); 1036 Offset = FPOffset; 1037 } 1038 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { 1039 // Otherwise, use SP or FP, whichever is closer to the stack slot. 1040 FrameReg = getFrameRegister(MF); 1041 Offset = FPOffset; 1042 } 1043 } 1044 return Offset; 1045} 1046 1047int 1048ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF, 1049 int FI) const { 1050 unsigned FrameReg; 1051 return getFrameIndexReference(MF, FI, FrameReg); 1052} 1053 1054unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 1055 llvm_unreachable("What is the exception register"); 1056 return 0; 1057} 1058 1059unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 1060 llvm_unreachable("What is the exception handler register"); 1061 return 0; 1062} 1063 1064int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1065 return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1066} 1067 1068unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 1069 const MachineFunction &MF) const { 1070 switch (Reg) { 1071 default: break; 1072 // Return 0 if either register of the pair is a special register. 1073 // So no R12, etc. 1074 case ARM::R1: 1075 return ARM::R0; 1076 case ARM::R3: 1077 return ARM::R2; 1078 case ARM::R5: 1079 return ARM::R4; 1080 case ARM::R7: 1081 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; 1082 case ARM::R9: 1083 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 1084 case ARM::R11: 1085 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 1086 1087 case ARM::S1: 1088 return ARM::S0; 1089 case ARM::S3: 1090 return ARM::S2; 1091 case ARM::S5: 1092 return ARM::S4; 1093 case ARM::S7: 1094 return ARM::S6; 1095 case ARM::S9: 1096 return ARM::S8; 1097 case ARM::S11: 1098 return ARM::S10; 1099 case ARM::S13: 1100 return ARM::S12; 1101 case ARM::S15: 1102 return ARM::S14; 1103 case ARM::S17: 1104 return ARM::S16; 1105 case ARM::S19: 1106 return ARM::S18; 1107 case ARM::S21: 1108 return ARM::S20; 1109 case ARM::S23: 1110 return ARM::S22; 1111 case ARM::S25: 1112 return ARM::S24; 1113 case ARM::S27: 1114 return ARM::S26; 1115 case ARM::S29: 1116 return ARM::S28; 1117 case ARM::S31: 1118 return ARM::S30; 1119 1120 case ARM::D1: 1121 return ARM::D0; 1122 case ARM::D3: 1123 return ARM::D2; 1124 case ARM::D5: 1125 return ARM::D4; 1126 case ARM::D7: 1127 return ARM::D6; 1128 case ARM::D9: 1129 return ARM::D8; 1130 case ARM::D11: 1131 return ARM::D10; 1132 case ARM::D13: 1133 return ARM::D12; 1134 case ARM::D15: 1135 return ARM::D14; 1136 case ARM::D17: 1137 return ARM::D16; 1138 case ARM::D19: 1139 return ARM::D18; 1140 case ARM::D21: 1141 return ARM::D20; 1142 case ARM::D23: 1143 return ARM::D22; 1144 case ARM::D25: 1145 return ARM::D24; 1146 case ARM::D27: 1147 return ARM::D26; 1148 case ARM::D29: 1149 return ARM::D28; 1150 case ARM::D31: 1151 return ARM::D30; 1152 } 1153 1154 return 0; 1155} 1156 1157unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 1158 const MachineFunction &MF) const { 1159 switch (Reg) { 1160 default: break; 1161 // Return 0 if either register of the pair is a special register. 1162 // So no R12, etc. 1163 case ARM::R0: 1164 return ARM::R1; 1165 case ARM::R2: 1166 return ARM::R3; 1167 case ARM::R4: 1168 return ARM::R5; 1169 case ARM::R6: 1170 return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; 1171 case ARM::R8: 1172 return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 1173 case ARM::R10: 1174 return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 1175 1176 case ARM::S0: 1177 return ARM::S1; 1178 case ARM::S2: 1179 return ARM::S3; 1180 case ARM::S4: 1181 return ARM::S5; 1182 case ARM::S6: 1183 return ARM::S7; 1184 case ARM::S8: 1185 return ARM::S9; 1186 case ARM::S10: 1187 return ARM::S11; 1188 case ARM::S12: 1189 return ARM::S13; 1190 case ARM::S14: 1191 return ARM::S15; 1192 case ARM::S16: 1193 return ARM::S17; 1194 case ARM::S18: 1195 return ARM::S19; 1196 case ARM::S20: 1197 return ARM::S21; 1198 case ARM::S22: 1199 return ARM::S23; 1200 case ARM::S24: 1201 return ARM::S25; 1202 case ARM::S26: 1203 return ARM::S27; 1204 case ARM::S28: 1205 return ARM::S29; 1206 case ARM::S30: 1207 return ARM::S31; 1208 1209 case ARM::D0: 1210 return ARM::D1; 1211 case ARM::D2: 1212 return ARM::D3; 1213 case ARM::D4: 1214 return ARM::D5; 1215 case ARM::D6: 1216 return ARM::D7; 1217 case ARM::D8: 1218 return ARM::D9; 1219 case ARM::D10: 1220 return ARM::D11; 1221 case ARM::D12: 1222 return ARM::D13; 1223 case ARM::D14: 1224 return ARM::D15; 1225 case ARM::D16: 1226 return ARM::D17; 1227 case ARM::D18: 1228 return ARM::D19; 1229 case ARM::D20: 1230 return ARM::D21; 1231 case ARM::D22: 1232 return ARM::D23; 1233 case ARM::D24: 1234 return ARM::D25; 1235 case ARM::D26: 1236 return ARM::D27; 1237 case ARM::D28: 1238 return ARM::D29; 1239 case ARM::D30: 1240 return ARM::D31; 1241 } 1242 1243 return 0; 1244} 1245 1246/// emitLoadConstPool - Emits a load from constpool to materialize the 1247/// specified immediate. 1248void ARMBaseRegisterInfo:: 1249emitLoadConstPool(MachineBasicBlock &MBB, 1250 MachineBasicBlock::iterator &MBBI, 1251 DebugLoc dl, 1252 unsigned DestReg, unsigned SubIdx, int Val, 1253 ARMCC::CondCodes Pred, 1254 unsigned PredReg) const { 1255 MachineFunction &MF = *MBB.getParent(); 1256 MachineConstantPool *ConstantPool = MF.getConstantPool(); 1257 const Constant *C = 1258 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 1259 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 1260 1261 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 1262 .addReg(DestReg, getDefRegState(true), SubIdx) 1263 .addConstantPoolIndex(Idx) 1264 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 1265} 1266 1267bool ARMBaseRegisterInfo:: 1268requiresRegisterScavenging(const MachineFunction &MF) const { 1269 return true; 1270} 1271 1272bool ARMBaseRegisterInfo:: 1273requiresFrameIndexScavenging(const MachineFunction &MF) const { 1274 return true; 1275} 1276 1277// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 1278// not required, we reserve argument space for call sites in the function 1279// immediately on entry to the current function. This eliminates the need for 1280// add/sub sp brackets around call sites. Returns true if the call frame is 1281// included as part of the stack frame. 1282bool ARMBaseRegisterInfo:: 1283hasReservedCallFrame(const MachineFunction &MF) const { 1284 const MachineFrameInfo *FFI = MF.getFrameInfo(); 1285 unsigned CFSize = FFI->getMaxCallFrameSize(); 1286 // It's not always a good idea to include the call frame as part of the 1287 // stack frame. ARM (especially Thumb) has small immediate offset to 1288 // address the stack frame. So a large call frame can cause poor codegen 1289 // and may even makes it impossible to scavenge a register. 1290 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 1291 return false; 1292 1293 return !MF.getFrameInfo()->hasVarSizedObjects(); 1294} 1295 1296// canSimplifyCallFramePseudos - If there is a reserved call frame, the 1297// call frame pseudos can be simplified. Unlike most targets, having a FP 1298// is not sufficient here since we still may reference some objects via SP 1299// even when FP is available in Thumb2 mode. 1300bool ARMBaseRegisterInfo:: 1301canSimplifyCallFramePseudos(const MachineFunction &MF) const { 1302 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); 1303} 1304 1305static void 1306emitSPUpdate(bool isARM, 1307 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 1308 DebugLoc dl, const ARMBaseInstrInfo &TII, 1309 int NumBytes, 1310 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 1311 if (isARM) 1312 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 1313 Pred, PredReg, TII); 1314 else 1315 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 1316 Pred, PredReg, TII); 1317} 1318 1319 1320void ARMBaseRegisterInfo:: 1321eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1322 MachineBasicBlock::iterator I) const { 1323 if (!hasReservedCallFrame(MF)) { 1324 // If we have alloca, convert as follows: 1325 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 1326 // ADJCALLSTACKUP -> add, sp, sp, amount 1327 MachineInstr *Old = I; 1328 DebugLoc dl = Old->getDebugLoc(); 1329 unsigned Amount = Old->getOperand(0).getImm(); 1330 if (Amount != 0) { 1331 // We need to keep the stack aligned properly. To do this, we round the 1332 // amount of space needed for the outgoing arguments up to the next 1333 // alignment boundary. 1334 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1335 Amount = (Amount+Align-1)/Align*Align; 1336 1337 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1338 assert(!AFI->isThumb1OnlyFunction() && 1339 "This eliminateCallFramePseudoInstr does not support Thumb1!"); 1340 bool isARM = !AFI->isThumbFunction(); 1341 1342 // Replace the pseudo instruction with a new instruction... 1343 unsigned Opc = Old->getOpcode(); 1344 int PIdx = Old->findFirstPredOperandIdx(); 1345 ARMCC::CondCodes Pred = (PIdx == -1) 1346 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 1347 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 1348 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1349 unsigned PredReg = Old->getOperand(2).getReg(); 1350 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 1351 } else { 1352 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1353 unsigned PredReg = Old->getOperand(3).getReg(); 1354 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 1355 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 1356 } 1357 } 1358 } 1359 MBB.erase(I); 1360} 1361 1362unsigned 1363ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1364 int SPAdj, FrameIndexValue *Value, 1365 RegScavenger *RS) const { 1366 unsigned i = 0; 1367 MachineInstr &MI = *II; 1368 MachineBasicBlock &MBB = *MI.getParent(); 1369 MachineFunction &MF = *MBB.getParent(); 1370 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1371 assert(!AFI->isThumb1OnlyFunction() && 1372 "This eliminateFrameIndex does not support Thumb1!"); 1373 1374 while (!MI.getOperand(i).isFI()) { 1375 ++i; 1376 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 1377 } 1378 1379 int FrameIndex = MI.getOperand(i).getIndex(); 1380 unsigned FrameReg; 1381 1382 int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 1383 1384 // Special handling of dbg_value instructions. 1385 if (MI.isDebugValue()) { 1386 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); 1387 MI.getOperand(i+1).ChangeToImmediate(Offset); 1388 return 0; 1389 } 1390 1391 // Modify MI as necessary to handle as much of 'Offset' as possible 1392 bool Done = false; 1393 if (!AFI->isThumbFunction()) 1394 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 1395 else { 1396 assert(AFI->isThumb2Function()); 1397 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 1398 } 1399 if (Done) 1400 return 0; 1401 1402 // If we get here, the immediate doesn't fit into the instruction. We folded 1403 // as much as possible above, handle the rest, providing a register that is 1404 // SP+LargeImm. 1405 assert((Offset || 1406 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 1407 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 1408 "This code isn't needed if offset already handled!"); 1409 1410 unsigned ScratchReg = 0; 1411 int PIdx = MI.findFirstPredOperandIdx(); 1412 ARMCC::CondCodes Pred = (PIdx == -1) 1413 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1414 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1415 if (Offset == 0) 1416 // Must be addrmode4/6. 1417 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 1418 else { 1419 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); 1420 if (Value) { 1421 Value->first = FrameReg; // use the frame register as a kind indicator 1422 Value->second = Offset; 1423 } 1424 if (!AFI->isThumbFunction()) 1425 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1426 Offset, Pred, PredReg, TII); 1427 else { 1428 assert(AFI->isThumb2Function()); 1429 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1430 Offset, Pred, PredReg, TII); 1431 } 1432 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1433 if (!ReuseFrameIndexVals) 1434 ScratchReg = 0; 1435 } 1436 return ScratchReg; 1437} 1438 1439/// Move iterator past the next bunch of callee save load / store ops for 1440/// the particular spill area (1: integer area 1, 2: integer area 2, 1441/// 3: fp area, 0: don't care). 1442static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1443 MachineBasicBlock::iterator &MBBI, 1444 int Opc1, int Opc2, unsigned Area, 1445 const ARMSubtarget &STI) { 1446 while (MBBI != MBB.end() && 1447 ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && 1448 MBBI->getOperand(1).isFI()) { 1449 if (Area != 0) { 1450 bool Done = false; 1451 unsigned Category = 0; 1452 switch (MBBI->getOperand(0).getReg()) { 1453 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1454 case ARM::LR: 1455 Category = 1; 1456 break; 1457 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1458 Category = STI.isTargetDarwin() ? 2 : 1; 1459 break; 1460 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1461 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1462 Category = 3; 1463 break; 1464 default: 1465 Done = true; 1466 break; 1467 } 1468 if (Done || Category != Area) 1469 break; 1470 } 1471 1472 ++MBBI; 1473 } 1474} 1475 1476void ARMBaseRegisterInfo:: 1477emitPrologue(MachineFunction &MF) const { 1478 MachineBasicBlock &MBB = MF.front(); 1479 MachineBasicBlock::iterator MBBI = MBB.begin(); 1480 MachineFrameInfo *MFI = MF.getFrameInfo(); 1481 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1482 assert(!AFI->isThumb1OnlyFunction() && 1483 "This emitPrologue does not support Thumb1!"); 1484 bool isARM = !AFI->isThumbFunction(); 1485 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1486 unsigned NumBytes = MFI->getStackSize(); 1487 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1488 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 1489 1490 // Determine the sizes of each callee-save spill areas and record which frame 1491 // belongs to which callee-save spill areas. 1492 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1493 int FramePtrSpillFI = 0; 1494 1495 // Allocate the vararg register save area. This is not counted in NumBytes. 1496 if (VARegSaveSize) 1497 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); 1498 1499 if (!AFI->hasStackFrame()) { 1500 if (NumBytes != 0) 1501 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1502 return; 1503 } 1504 1505 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1506 unsigned Reg = CSI[i].getReg(); 1507 int FI = CSI[i].getFrameIdx(); 1508 switch (Reg) { 1509 case ARM::R4: 1510 case ARM::R5: 1511 case ARM::R6: 1512 case ARM::R7: 1513 case ARM::LR: 1514 if (Reg == FramePtr) 1515 FramePtrSpillFI = FI; 1516 AFI->addGPRCalleeSavedArea1Frame(FI); 1517 GPRCS1Size += 4; 1518 break; 1519 case ARM::R8: 1520 case ARM::R9: 1521 case ARM::R10: 1522 case ARM::R11: 1523 if (Reg == FramePtr) 1524 FramePtrSpillFI = FI; 1525 if (STI.isTargetDarwin()) { 1526 AFI->addGPRCalleeSavedArea2Frame(FI); 1527 GPRCS2Size += 4; 1528 } else { 1529 AFI->addGPRCalleeSavedArea1Frame(FI); 1530 GPRCS1Size += 4; 1531 } 1532 break; 1533 default: 1534 AFI->addDPRCalleeSavedAreaFrame(FI); 1535 DPRCSSize += 8; 1536 } 1537 } 1538 1539 // Build the new SUBri to adjust SP for integer callee-save spill area 1. 1540 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); 1541 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); 1542 1543 // Set FP to point to the stack slot that contains the previous FP. 1544 // For Darwin, FP is R7, which has now been stored in spill area 1. 1545 // Otherwise, if this is not Darwin, all the callee-saved registers go 1546 // into spill area 1, including the FP in R11. In either case, it is 1547 // now safe to emit this assignment. 1548 if (STI.isTargetDarwin() || hasFP(MF)) { 1549 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 1550 MachineInstrBuilder MIB = 1551 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 1552 .addFrameIndex(FramePtrSpillFI).addImm(0); 1553 AddDefaultCC(AddDefaultPred(MIB)); 1554 } 1555 1556 // Build the new SUBri to adjust SP for integer callee-save spill area 2. 1557 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); 1558 1559 // Build the new SUBri to adjust SP for FP callee-save spill area. 1560 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); 1561 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); 1562 1563 // Determine starting offsets of spill areas. 1564 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1565 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1566 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1567 if (STI.isTargetDarwin() || hasFP(MF)) 1568 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 1569 NumBytes); 1570 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1571 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1572 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1573 1574 movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI); 1575 NumBytes = DPRCSOffset; 1576 if (NumBytes) { 1577 // Adjust SP after all the callee-save spills. 1578 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1579 } 1580 1581 if (STI.isTargetELF() && hasFP(MF)) { 1582 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1583 AFI->getFramePtrSpillOffset()); 1584 } 1585 1586 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1587 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1588 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1589 1590 // If we need dynamic stack realignment, do it here. 1591 if (needsStackRealignment(MF)) { 1592 unsigned MaxAlign = MFI->getMaxAlignment(); 1593 assert (!AFI->isThumb1OnlyFunction()); 1594 if (!AFI->isThumbFunction()) { 1595 // Emit bic sp, sp, MaxAlign 1596 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 1597 TII.get(ARM::BICri), ARM::SP) 1598 .addReg(ARM::SP, RegState::Kill) 1599 .addImm(MaxAlign-1))); 1600 } else { 1601 // We cannot use sp as source/dest register here, thus we're emitting the 1602 // following sequence: 1603 // mov r4, sp 1604 // bic r4, r4, MaxAlign 1605 // mov sp, r4 1606 // FIXME: It will be better just to find spare register here. 1607 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4) 1608 .addReg(ARM::SP, RegState::Kill); 1609 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 1610 TII.get(ARM::t2BICri), ARM::R4) 1611 .addReg(ARM::R4, RegState::Kill) 1612 .addImm(MaxAlign-1))); 1613 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP) 1614 .addReg(ARM::R4, RegState::Kill); 1615 } 1616 } 1617} 1618 1619static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1620 for (unsigned i = 0; CSRegs[i]; ++i) 1621 if (Reg == CSRegs[i]) 1622 return true; 1623 return false; 1624} 1625 1626static bool isCSRestore(MachineInstr *MI, 1627 const ARMBaseInstrInfo &TII, 1628 const unsigned *CSRegs) { 1629 return ((MI->getOpcode() == (int)ARM::VLDRD || 1630 MI->getOpcode() == (int)ARM::LDR || 1631 MI->getOpcode() == (int)ARM::t2LDRi12) && 1632 MI->getOperand(1).isFI() && 1633 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1634} 1635 1636void ARMBaseRegisterInfo:: 1637emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { 1638 MachineBasicBlock::iterator MBBI = prior(MBB.end()); 1639 assert(MBBI->getDesc().isReturn() && 1640 "Can only insert epilog into returning blocks"); 1641 unsigned RetOpcode = MBBI->getOpcode(); 1642 DebugLoc dl = MBBI->getDebugLoc(); 1643 MachineFrameInfo *MFI = MF.getFrameInfo(); 1644 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1645 assert(!AFI->isThumb1OnlyFunction() && 1646 "This emitEpilogue does not support Thumb1!"); 1647 bool isARM = !AFI->isThumbFunction(); 1648 1649 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1650 int NumBytes = (int)MFI->getStackSize(); 1651 1652 if (!AFI->hasStackFrame()) { 1653 if (NumBytes != 0) 1654 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1655 } else { 1656 // Unwind MBBI to point to first LDR / VLDRD. 1657 const unsigned *CSRegs = getCalleeSavedRegs(); 1658 if (MBBI != MBB.begin()) { 1659 do 1660 --MBBI; 1661 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 1662 if (!isCSRestore(MBBI, TII, CSRegs)) 1663 ++MBBI; 1664 } 1665 1666 // Move SP to start of FP callee save spill area. 1667 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1668 AFI->getGPRCalleeSavedArea2Size() + 1669 AFI->getDPRCalleeSavedAreaSize()); 1670 1671 // Darwin ABI requires FP to point to the stack slot that contains the 1672 // previous FP. 1673 bool HasFP = hasFP(MF); 1674 if ((STI.isTargetDarwin() && NumBytes) || HasFP) { 1675 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1676 // Reset SP based on frame pointer only if the stack frame extends beyond 1677 // frame pointer stack slot or target is ELF and the function has FP. 1678 if (HasFP || 1679 AFI->getGPRCalleeSavedArea2Size() || 1680 AFI->getDPRCalleeSavedAreaSize() || 1681 AFI->getDPRCalleeSavedAreaOffset()) { 1682 if (NumBytes) { 1683 if (isARM) 1684 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1685 ARMCC::AL, 0, TII); 1686 else 1687 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1688 ARMCC::AL, 0, TII); 1689 } else { 1690 // Thumb2 or ARM. 1691 if (isARM) 1692 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 1693 .addReg(FramePtr) 1694 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1695 else 1696 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) 1697 .addReg(FramePtr); 1698 } 1699 } 1700 } else if (NumBytes) 1701 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1702 1703 // Move SP to start of integer callee save spill area 2. 1704 movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI); 1705 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); 1706 1707 // Move SP to start of integer callee save spill area 1. 1708 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); 1709 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); 1710 1711 // Move SP to SP upon entry to the function. 1712 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); 1713 emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); 1714 } 1715 1716 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || 1717 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) { 1718 // Tail call return: adjust the stack pointer and jump to callee. 1719 MBBI = prior(MBB.end()); 1720 MachineOperand &JumpTarget = MBBI->getOperand(0); 1721 1722 // Jump to label or value in register. 1723 if (RetOpcode == ARM::TCRETURNdi) { 1724 BuildMI(MBB, MBBI, dl, 1725 TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)). 1726 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 1727 JumpTarget.getTargetFlags()); 1728 } else if (RetOpcode == ARM::TCRETURNdiND) { 1729 BuildMI(MBB, MBBI, dl, 1730 TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)). 1731 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 1732 JumpTarget.getTargetFlags()); 1733 } else if (RetOpcode == ARM::TCRETURNri) { 1734 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)). 1735 addReg(JumpTarget.getReg(), RegState::Kill); 1736 } else if (RetOpcode == ARM::TCRETURNriND) { 1737 BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)). 1738 addReg(JumpTarget.getReg(), RegState::Kill); 1739 } 1740 1741 MachineInstr *NewMI = prior(MBBI); 1742 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 1743 NewMI->addOperand(MBBI->getOperand(i)); 1744 1745 // Delete the pseudo instruction TCRETURN. 1746 MBB.erase(MBBI); 1747 } 1748 1749 if (VARegSaveSize) 1750 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 1751} 1752 1753#include "ARMGenRegisterInfo.inc" 1754